Duty cycle corrector circuit and related apparatus and methods

Abstract

This application relates to duty cycle corrector circuits and related devices and methods. One device includes an integrator circuit, an amplifier circuit, and an electrically controllable switch. The integrator circuit is configured to provide an integrator signal that substantially indicates the integration of a corrected clock signal. The amplifier circuit is configured to deactivate in response to detecting that an input clock signal has been deactivated. The amplifier circuit includes a first amplifier input terminal and a second amplifier input terminal. The electrically controllable switch is configured to selectively electrically connect the first amplifier input terminal to the second amplifier input terminal in response to detecting that the input clock signal has been deactivated. A method for correcting the duty cycle of an input clock signal includes adjusting the corrected duty cycle of the corrected clock signal in response to a first error signal and a second error signal from the amplifier circuit.

Description

[0001] Citation of relevant applications

[0002] This application claims the benefit of U.S. Patent Application No. 17 / 366,655, filed July 2, 2021, entitled “Duty-Cycle Corrector Circuits and Related Apparatuses and Methods,” the disclosure of which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to duty cycle corrector circuitry, and more specifically, to a clock detector that disables duty cycle correction in response to the deactivation of an input clock signal. Background Technology

[0004] Many electronic devices use clock signals to control the timing of operation. Examples of devices that can be used to generate clock signals include crystal (e.g., quartz) oscillators and oscillator circuits (e.g., voltage-controlled oscillators or VCOs). The duty cycle of the clock signal provided by these devices may not be perfect in electronic devices thus manufactured and can vary during device operation. For example, it may be necessary to operate the electronic device using a clock signal with a 50% duty cycle. Deviations from the desired duty cycle in the clock signal can be problematic for the operation of some electronic devices. Summary of the Invention

[0005] In some embodiments, a device includes an integrator circuit, an amplifier circuit, and an electrically controllable switch. The integrator circuit is configured to receive a calibrated clock signal and a complementary calibrated clock signal. The complementary calibrated clock signal is complementary to the calibrated clock signal. The integrator circuit is configured to provide an integrator signal that substantially indicates the integration of the calibrated clock signal and a complementary integrator signal that substantially indicates the integration of the complementary calibrated clock signal. The amplifier circuit is configured to control the correction made to the duty cycle of the calibrated clock signal. The amplifier circuit is configured to deactivate in response to detecting that an input clock signal is deactivated. The amplifier circuit includes a first amplifier input terminal configured to receive the integrator signal and a second amplifier input terminal configured to receive the complementary integrator signal. The electrically controllable switch is configured to selectively connect the first amplifier input terminal to the second amplifier input terminal in response to detecting that the input clock signal is deactivated.

[0006] In some embodiments, a device includes a duty cycle regulator, an integrator circuit, an amplifier circuit, and a clock detector. The duty cycle regulator is configured to receive an input clock signal and correct the duty cycle of a corrected clock signal relative to an input duty cycle of the input clock signal. The integrator circuit is configured to generate an integrator signal in response to the corrected clock signal. The integrator signal substantially indicates the integration of the corrected clock signal over time. The amplifier circuit is configured to control the correction of the duty cycle of the corrected clock signal made by the duty cycle regulator in response to the integrator signal. The clock detector is configured to deactivate the correction of the duty cycle of the corrected clock signal in response to detecting that the input clock signal has been deactivated.

[0007] In some embodiments, a method for correcting the duty cycle of an input clock signal includes: generating an intermediate corrected clock signal in response to the input clock signal; splitting the intermediate corrected clock signal into a corrected clock signal and a complementary corrected clock signal; integrating the corrected clock signal to generate an integrator signal; integrating the complementary corrected clock signal to generate a complementary integrator signal; generating a first error signal and a second error signal using the amplifier circuit in response to the integrator signal provided to a first amplifier input terminal of the amplifier circuit and the complementary integrator signal provided to a second amplifier input terminal of the amplifier circuit; adjusting the corrected duty cycle of the intermediate corrected clock signal relative to the input duty cycle of the input clock signal in response to the first error signal and the second error signal; and electrically connecting the first amplifier input terminal to the second amplifier input terminal in response to detecting that the input clock signal is not activated. Attached Figure Description

[0008] Although this disclosure is summarized by means of claims that precisely point out and clearly assert particular embodiments, various features and advantages of embodiments within the scope of this disclosure may be more readily apparent from the following description when read in conjunction with the accompanying drawings, in which:

[0009] Figure 1 A block diagram of an electronic device according to some embodiments;

[0010] Figure 2 This is a block diagram of a memory device according to some embodiments;

[0011] Figure 3 This is a schematic circuit diagram of a duty cycle corrector according to some embodiments;

[0012] Figure 4 For use according to some embodiments Figure 3A schematic diagram of the amplifier circuit.

[0013] Figure 5 for Figure 3 The signal timing diagram of an example of a duty cycle corrector, wherein the duty cycle of the input clock signal is approximately 50%;

[0014] Figure 6 for Figure 3 The signal timing diagram of an example of a duty cycle corrector, wherein the duty cycle of the input clock signal is approximately 30%;

[0015] Figure 7 A flowchart illustrating a method for correcting the duty cycle of an input clock signal according to some embodiments; and

[0016] Figure 8 This is a block diagram of a computing system according to some embodiments. Detailed Implementation

[0017] In the following detailed description, reference is made to the accompanying drawings, which form a part of this disclosure, and specific examples of embodiments in which the disclosure may be practiced are illustrated by means of the figures. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure. However, other embodiments implemented herein may be utilized, and changes in structure, materials, and processes may be made without departing from the scope of the disclosure.

[0018] The illustrations presented herein are not intended to be actual views of any particular method, system, apparatus, or structure, but are merely idealized representations for describing embodiments of this disclosure. In some cases, similar structures or components in the figures may be numbered the same or similarly for the reader's convenience; however, similarity in numbering does not necessarily imply that the size, composition, configuration, or any other property of the structures or components are identical.

[0019] The following description may include examples to help enable those skilled in the art to practice the disclosed embodiments. The use of the terms “exemplary,” “for example,” and “e.g.” means that the description is explanatory, and while the scope of this disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of this disclosure to the specified components, steps, features, functions, etc.

[0020] It will be readily understood that the components of the embodiments generally described herein and illustrated in the accompanying drawings can be arranged and designed in a wide variety of different configurations. Therefore, the following description of various embodiments is not intended to limit the scope of this disclosure, but merely to illustrate various embodiments. Although various aspects of the embodiments may be presented in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0021] Furthermore, unless otherwise specified herein, the specific embodiments shown and described are merely examples and should not be construed as the only ways of implementing this disclosure. Components, circuits, and functions may be shown in block diagram form to avoid obscuring this disclosure with unnecessary detail. Conversely, unless otherwise specified herein, the specific embodiments shown and described are merely exemplary and should not be construed as the only ways of implementing this disclosure. Additionally, the block definitions and logical divisions between various blocks are examples of specific embodiments. It will be apparent to those skilled in the art that this disclosure can be practiced through many other partitioning solutions. Details regarding timing considerations, etc., have been largely omitted, as such details are unnecessary for a full understanding of this disclosure and are within the capabilities of those skilled in the art.

[0022] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and skills. Some diagrams may show a signal as a single signal for clarity of presentation and description. Those skilled in the art will understand that a signal may represent a bus of signals, wherein the bus may have a variety of bit widths, and this disclosure may be implemented on any number of data signals comprising a single data signal.

[0023] Implementations can be described based on processes depicted as flowcharts, flow diagrams, or block diagrams. While flowcharts may describe actions as a sequential process, many of these actions can be performed in another order, in parallel, or substantially simultaneously. Furthermore, the order of actions can be rearranged.

[0024] The use of designations such as "first," "second," etc., to refer to elements herein does not limit the number or order of those elements unless such limitation is explicitly stated. In fact, these designations serve as a convenient way to distinguish two or more elements or instances of elements. Therefore, references to first and second elements do not imply that only two elements may be used herein, or that the first element must somehow precede the second element. Furthermore, unless otherwise stated, a group of elements may contain one or more elements.

[0025] As used herein, the term "generally" with respect to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition conforms to variance (e.g., within acceptable tolerances) as would be understood by one of ordinary skill in the art. By way of example, depending on the particular parameter, property, or condition that is generally satisfied, it may be satisfied at least 90%, at least 95%, or even at least 99%.

[0026] As used herein, the term “electrical connection” refers to both direct electrical connection (i.e., electrical connection without any intervening object) and indirect electrical connection (i.e., electrical connection between one or more intervening objects).

[0027] As used herein, when used to indicate the state of an electrical signal, the term "assert" and other forms of the term "assert" (e.g., "asserted," "asserting," "assertion") refer to the state of a circuit system that transitions and / or maintains an electrical signal to trigger the receipt of electrical signals to perform a predetermined function. For example, an operational amplifier may have an enable input terminal and may be activated in response to an assertion (e.g., a transition from a logic low voltage potential to a logic high voltage potential) provided to the enable input terminal. It will be apparent to those skilled in the art that an assertion of an electrical signal may include a transition from a logic low voltage potential to a logic high voltage potential, a transition from a logic high voltage potential to a logic low voltage potential, a maintenance of a logic high voltage potential, a maintenance of a logic low voltage potential, a transition from a first logic voltage potential to a second logic voltage potential (e.g., in a system containing three or more logic voltage potentials), or combinations thereof. Furthermore, as used herein, the term “de-assert” and other forms of the term “de-assert” (e.g., “de-asserted”, “de-asserting”, “de-assertion”) refer to the state in which an electrical signal is switched to and / or maintained as a state in which a circuit system that receives electrical signals from performing a predetermined function is deactivated.

[0028] As used herein, the term "active material" refers to a semiconductor material that has been doped to serve as the channel material in a metal-oxide-semiconductor (MOS) field-effect transistor (FET) (MOSFET). A MOSFET transistor having a channel material that is predominantly doped with donor impurities is referred to herein as an N-type MOS (NMOS) transistor because the active material serving as the channel material for an NMOS transistor comprises an N-type semiconductor material. Similarly, a MOSFET transistor having a channel material that is predominantly doped with trivalent or acceptor impurities is referred to herein as a P-type MOS (PMOS) transistor because the active material serving as the channel material for a PMOS transistor comprises a P-type semiconductor material.

[0029] The quality of clock signals in electronic devices (e.g., memory devices) (e.g., clock duty cycle and clock jitter) is related to high-frequency data transmission. Some systems using complementary metal-oxide-semiconductor (CMOS) signaling can benefit from duty cycle fine-tuning. One way to perform duty cycle fine-tuning of a clock signal is to use a string of inverters having at least one inverter with a variable-intensity PMOS field-effect transistor (PFET) and an NMOS field-effect transistor (NFET). The transistors used to drive the signal (e.g., the clock signal) can be controlled by switching the transistors on and off. The rise and fall times can be adjusted based on the switching of the transistors, and the duty cycle adjusted accordingly.

[0030] Another way to fine-tune the duty cycle of the clock signal is to use pull-up and pull-down resistors that are selectively electrically connected to the input of the inverter. By connecting or disconnecting the additional pull-up or pull-down resistors toward the positive or negative power supply (e.g., ground), the operating point (e.g., voltage potential) at the input of the inverter can be adjusted, which in turn adjusts the duty cycle of the inverter's output.

[0031] These methods for fine-tuning the duty cycle may be applicable to one-time adjustments (e.g., during the manufacture of an electronic device, or when the electronic device is powered on), but may not be able to compensate for duty cycle errors (e.g., due to temperature variations) during operation. Furthermore, if such switching operations are performed on the running clock, then operation of the switches in the duty cycle fine-tuner may disrupt one of the clock cycles at the output of the duty cycle fine-tuner.

[0032] In some embodiments, the duty cycle of a signal (e.g., a clock signal) can be tracked "in operation." In other words, the duty cycle of a signal can be measured and adjusted on a running clock signal during operation of an electronic device using a clock signal. By means of a non-limiting example, an integrating resistor-capacitor (RC) circuit can be used to measure the duty cycle. Assuming a 50% duty cycle is required, the integrating RC circuit electrically connected to the output of the duty cycle trimmer can be charged to a voltage potential halfway between logic level voltage potentials (e.g., halfway between a logic high voltage potential and a logic low voltage potential). The circuit system can compare the output of the duty cycle trimmer with a reference voltage potential (e.g., using a comparator or operational amplifier, but not limited to). By means of a non-limiting example, the reference voltage potential can be generated using a simple resistive voltage divider circuit (e.g., to provide a reference voltage potential halfway between logic level voltage potentials). The operational amplifier can derive an error signal, amplify the error signal, and feed the error signal back to the midpoint between two inverters to correct any duty cycle distortion. As a result, the duty cycle of the clock signal provided by the duty cycle trimmer can be maintained at close to 50%, despite changes in power supply voltage potential, logic level voltage potential, temperature, and transistor degradation over time.

[0033] Many electronic devices, including some that are sensitive to the duty cycle of a clock signal, may sometimes operate in a low-power mode and / or be shut off to conserve power. During low-power and / or shutdown modes, the input clock signal may be maintained at one logic level voltage potential instead of continuing to oscillate between two logic levels. As a result, the error signal provided by the integrating RC circuit may saturate to the logic level voltage potential at which the input clock signal is held. When the input clock signal is later activated, the error signal may take many clock cycles to deviate from the saturation at the logic level voltage potential held by the input clock signal during the low-power and / or shutdown modes. Consequently, the calibrated clock signal provided by the duty cycle trimmer may be distorted over many clock cycles, and some clock cycles of the calibrated clock signal may even disappear completely. By way of a non-limiting example, the error signal may take ten to twenty clock cycles to sufficiently deviate from the logic level voltage potential for the duty cycle trimmer to operate correctly.

[0034] Although data transfer in some electronic devices, such as memory devices, may not begin at the first timing edge after transitioning from a low-power or deactivated state, proper operation may require some no-operation (NOP) edges. In other words, for some electronic devices, such as memory devices, operational problems can arise if the clock signal output by the duty cycle trimmer does not resolve within approximately one clock cycle of activation.

[0035] Furthermore, at high frequencies, the rising and falling edges of the clock signal may not be linear, and the integrator receiving the clock signal may not be at exactly halfway between logic level voltage potentials, even if the duty cycle is at the desired level. One way to address this problem is to store the value of the voltage potential indicating the error signal at the integrator when transitioning to a low-power mode or deactivation mode. When the clock signal is reactivated, a voltage potential substantially at the stored value can be provided to the integrator. Disadvantageously, the digitization of the error signal during deactivation (e.g., using an analog-to-digital converter) and the storage of the digitized value (e.g., using a dedicated register) can increase the complexity of the electronics. Also, system parameters (e.g., power rail voltage potential, temperature) can fluctuate during downtime, which can invalidate the stored values ​​for said parameters upon reactivation.

[0036] This document discloses duty cycle correctors that measure and adjust the duty cycle of a clock signal during operation of an electronic device using a clock signal. These duty cycle correctors can disable duty cycle correction using a clock detector in response to detecting that the input clock signal supplied to them has been deactivated. Therefore, when the input clock signal is deactivated, the error signal indicating an error in the duty cycle of the corrected clock signal provided by these correctors may not be saturated. As a result, the error signal may be at an appropriate level upon reactivation of the input clock signal, and the corrected clock signal can be modulated for one or more clock cycles after reactivation.

[0037] In some embodiments, a device includes an integrator circuit, an amplifier circuit, and an electrically controllable switch. The integrator circuit is configured to receive a calibrated clock signal and a complementary calibrated clock signal. The complementary calibrated clock signal is complementary to the calibrated clock signal. The integrator circuit is configured to provide an integrator signal that substantially indicates the integration of the calibrated clock signal. The integrator is also configured to provide a complementary integrator signal that substantially indicates the integration of the complementary calibrated clock signal. The amplifier circuit is configured to control the correction made to the duty cycle of the calibrated clock signal. The amplifier circuit is configured to deactivate in response to detecting that the input clock signal is deactivated. The amplifier circuit includes a first amplifier input terminal configured to receive the integrator signal. The amplifier also includes a second amplifier input terminal configured to receive the complementary integrator signal. The electrically controllable switch is configured to selectively electrically connect the first amplifier input terminal to the second amplifier input terminal in response to detecting that the input clock signal is deactivated.

[0038] In some embodiments, a device includes a duty cycle regulator, an integrator circuit, an amplifier circuit, and a clock detector. The duty cycle regulator is configured to receive an input clock signal and correct the duty cycle of a corrected clock signal relative to an input duty cycle of the input clock signal. The integrator circuit is configured to generate an integrator signal in response to the corrected clock signal. The integrator signal substantially indicates the integration of the corrected clock signal over time. The amplifier circuit is configured to control the correction of the duty cycle of the corrected clock signal made by the duty cycle regulator in response to the integrator signal. The clock detector is configured to deactivate the correction of the duty cycle of the corrected clock signal in response to detecting that the input clock signal has been deactivated.

[0039] In some embodiments, a method for correcting the duty cycle of an input clock signal includes: generating an intermediate corrected clock signal in response to the input clock signal; splitting the intermediate corrected clock signal into a corrected clock signal and a complementary corrected clock signal; integrating the corrected clock signal to generate an integrator signal; and integrating the complementary corrected clock signal to generate a complementary integrator signal. The method further includes using the amplifier circuit to generate a first error signal and a second error signal in response to the integrator signal provided to a first amplifier input terminal of the amplifier circuit and the complementary integrator signal provided to a second amplifier input terminal of the amplifier circuit. The method further includes adjusting the corrected duty cycle of the intermediate corrected clock signal relative to the duty cycle of the input clock signal in response to the first error signal and the second error signal, and electrically connecting the first amplifier input terminal to the second amplifier input terminal in response to detecting that the input clock signal is not activated.

[0040] Figure 1 This is a block diagram of an electronic device 100 according to some embodiments. The electronic device 100 includes an oscillator 102, a duty cycle corrector 104, and a clock utilization circuit system 106. The oscillator 102 is configured to generate an input clock signal CLK_IN. The duty cycle corrector 104 is configured to correct the duty cycle of the input clock signal CLK_IN and provide a corrected clock signal CLK_OUT_T to the clock utilization circuit system 106.

[0041] The clock utilization circuitry 106 is configured to use a calibrated clock signal CLK_OUT_T for its operation. By way of a non-limiting example, the clock utilization circuitry 106 may include a synchronous digital circuitry system timed by the calibrated clock signal CLK_OUT_T. As a specific non-limiting example, the clock utilization circuitry 106 may include a memory circuitry system.

[0042] Duty cycle corrector 104 is configured to measure and adjust the corrected duty cycle of the corrected clock signal CLK_OUT_T during operation of the clock utilization circuit system 106. Duty cycle corrector 104 is also configured to deactivate in response to detecting that the input clock signal CLK_IN is deactivated.

[0043] In some embodiments, the duty cycle corrector 104 is configured to provide a complementary corrected clock signal CLK_OUT_C ​​to the clock utilization circuitry 106. The complementary corrected clock signal CLK_OUT_C ​​may be complementary to the corrected clock signal CLK_OUT_T. For example, the complementary corrected clock signal CLK_OUT_C ​​may be at a logic level voltage potential complementary to the logic level voltage potential of the corrected clock signal CLK_OUT_T. As a particular non-limiting example, when the corrected clock signal CLK_OUT_T oscillates from 1 to 0 to 1 to 0, the complementary corrected clock signal may oscillate from 0 to 1 to 0 to 1.

[0044] Figure 2 This is a block diagram of a memory device 200 according to some embodiments. The memory device 200 includes references to... Figure 1 The oscillator 102 and duty cycle corrector 104 discussed are similar to oscillator 202 and duty cycle corrector 204. Similar to oscillator 102, oscillator 202 provides the input clock signal CLK_IN to duty cycle corrector 204, and duty cycle corrector 204 provides a corrected clock signal (i.e., a corrected clock signal CLK_OUT_T and a complementary corrected clock signal CLK_OUT_C) in response to the input clock signal CLK_IN.

[0045] The memory device 200 also includes a memory circuitry 206 that uses a calibrated clock signal in its operation. By way of a non-limiting example, the calibrated clock signal provided by the duty cycle corrector 204 can be used to time high-speed data transfers (e.g., read operations, write operations).

[0046] Figure 3 This is a schematic circuit diagram of a duty cycle corrector 300 according to some embodiments. The duty cycle corrector 300 may be... Figure 1 Duty cycle corrector 104 and Figure 2 An example of a duty cycle corrector 204. Duty cycle corrector 300 includes a duty cycle adjuster 310, a clock splitter 312, an integrator circuit 326, a clock detector 328, an amplifier circuit 378, and an electrically controllable switch 358.

[0047] Duty cycle adjuster 310 is configured to receive an input clock signal CLK_IN and correct the corrected duty cycle of a corrected clock signal CLK_OUT_T relative to the input duty cycle of the input clock signal CLK_IN. Duty cycle adjuster 310 includes inverters 302 and 304, resistors 340 and 342, and controllable current sources 306 and 308. The output terminals of inverters 302 and 304 are electrically connected to resistors 340 and 342, respectively. The input terminal of inverter 302 is electrically connected to the input terminal 366 of duty cycle corrector 300. Therefore, the input terminal of inverter 302 is configured to receive the input clock signal CLK_IN. Resistor 340 is electrically connected from the output terminal of inverter 302 to the first node 360 ​​of duty cycle corrector 300. A first voltage potential RC1 can be observed at the first node 360. The input terminal of inverter 304 is electrically connected to the first node 360. Resistor 342 is electrically connected from the output terminal of inverter 304 to the second node 362. A second voltage potential RC2 can be observed at the second node 362. A controllable current source 306 is electrically connected from the first node 360 ​​to a low-voltage potential power node 368 (e.g., a ground node). A controllable current source 308 is electrically connected from the second node 362 to the low-voltage potential power node 368.

[0048] Controllable current sources 306 and 308 provide bidirectional current that can shift the common mode of the first voltage potential RC1 and the second voltage potential RC2 vertically from halfway between the logic high and low voltage potentials. In the case of zero current at controllable current sources 306 and 308, input terminal 366 propagates through duty cycle regulator 310 without changing the duty cycle. If a non-zero current is applied by controllable current sources 306 and 308, the corrected duty cycle of the second voltage potential RC2 and the correspondingly corrected clock signal CLK_OUT_T can be proportionally changed to the magnitude and sign (e.g., negative, positive) of the current relative to the input duty cycle of the input clock signal CLK_IN. Applying current at two nodes (i.e., the first node 360 ​​and the second node 362) achieves a wider duty cycle correction range and more linear operation compared to applying current to only one node. The relatively large common-mode offset relative to the threshold voltage potentials of inverters 302 and 304 can generate a relatively large reverse current.

[0049] In response to a second voltage potential RC2 provided by the duty cycle regulator 310, the clock splitter 312 generates two differential clock signals comprising a calibrated clock signal CLK_OUT_T and a complementary clock signal CLK_OUT_C. Therefore, the second voltage potential RC2 can serve as an intermediate calibrated clock signal, and the clock splitter 312 can be configured to receive the intermediate calibrated clock signal and, in response to the intermediate calibrated clock signal, generate a calibrated clock signal CLK_OUT_T and a complementary calibrated clock signal. The complementary calibrated clock signal CLK_OUT_C ​​is complementary to the calibrated clock signal CLK_OUT_T.

[0050] Clock splitter 312 includes inverters 314, 316, 318, 320, 322, and 324, and resistor 344. The input terminal of inverter 314 is electrically connected to the second node 362 of duty cycle regulator 310 and is configured to receive a second voltage potential RC2 (intermediate corrected clock signal) from duty cycle regulator 310. Resistor 344 is electrically connected from the output terminal of inverter 314 to the input terminal of inverter 318. The output terminal of inverter 318 is electrically connected to the integrator output terminal 374 of integrator circuit 326. The input terminal of inverter 316 is electrically connected to the output terminal of inverter 314. The output terminal of inverter 316 is electrically connected to the input terminal of inverter 320. The output terminal of inverter 320 is electrically connected to the complementary integrator output terminal 376 of integrator circuit 326. The input terminal of inverter 322 is electrically connected to the complementary integrator output terminal 376. The output terminal of inverter 322 is electrically connected to the output terminal of integrator 374. The input terminal of inverter 324 is electrically connected to the output terminal of integrator 374. The output terminal of inverter 324 is electrically connected to the output terminal of complementary integrator 376.

[0051] Resistor 344 can be selected to simulate the delay of inverter 316 so that the calibrated clock signal CLK_OUT_T and the complementary calibrated clock signal CLK_OUT_C ​​switch substantially simultaneously, although in opposite directions (i.e., the rising edge of the complementary calibrated clock signal CLK_OUT_C ​​may occur substantially simultaneously with the falling edge of the calibrated clock signal CLK_OUT_T, and vice versa). Inverters 322 and 324 can be aligned with the rising and falling edges (e.g., via phase interpolation between the rising and falling edges). The use of differential signaling at integrator circuit 326 allows duty cycle sensing and correction to be substantially independent of distortion caused by the different shapes of the rising and falling edges of the calibrated clock signal CLK_OUT_T and the complementary calibrated clock signal CLK_OUT_C. Clock splitter 312 is configured to provide the calibrated clock signal CLK_OUT_T and the complementary calibrated clock signal CLK_OUT_C ​​to integrator circuit 326.

[0052] Integrator circuit 326 is configured to receive a calibrated clock signal CLK_OUT_T and a complementary calibrated clock signal CLK_OUT_C ​​from clock splitter 312. Integrator circuit 326 is configured to generate integrator signals (e.g., integrator signal INTEGR_T and complementary integrator signal INTEGR_C) in response to the calibrated clock signal CLK_OUT_T and the complementary calibrated clock signal CLK_OUT_C. The integrator signals substantially indicate the integration of the calibrated clock signal CLK_OUT_T and the complementary calibrated clock signal CLK_OUT_C ​​over time. Integrator signal INTEGR_T substantially indicates the integration of the calibrated clock signal CLK_OUT_T. Complementary integrator signal INTEGR_C substantially indicates the integration of the complementary calibrated clock signal CLK_OUT_C.

[0053] Integrator circuit 326 includes a first RC circuit, which includes a resistor 346 and a capacitor 350. Resistor 346 is electrically connected from integrator output terminal 374 of integrator circuit 326 to capacitor 350. Capacitor 350 is electrically connected from resistor 346 to low-voltage potential power node 368. The first RC circuit is configured to provide an integrator signal INTEGR_T in response to a calibrated clock signal CLK_OUT_T.

[0054] The integrator circuit 326 also includes a second RC circuit, which includes a resistor 348 and a capacitor 352. Resistor 348 is electrically connected from the complementary integrator output terminal 376 to capacitor 352. Capacitor 352 is electrically connected from resistor 348 to a low-voltage potential power node 368. The second RC circuit is configured to provide a complementary integrator signal INTEGR_C in response to a complementary, calibrated clock signal CLK_OUT_C.

[0055] The first RC circuit (containing resistor 348 and capacitor 352) and the second RC circuit (containing resistor 346 and capacitor 350) can act as integrators for determining the calibrated duty cycle of the calibrated clock signal CLK_OUT_T and the complementary calibrated clock signal CLK_OUT_C. If the calibrated duty cycle is exactly 50%, then the voltage potentials of the integrator signals INTEGR_T and INTEGR_C can be substantially equal to each other and substantially equal to half the logic high voltage potential and logic low voltage potential of the calibrated clock signal CLK_OUT_T and the complementary calibrated clock signal CLK_OUT_C. However, if the calibrated duty cycle is not 50%, then the voltage potentials of the integrator signals INTEGR_T and INTEGR_C can be different from half the voltage potential. By way of a non-limiting example, for a calibrated duty cycle of 40% for the calibrated clock signal CLK_OUT_T, the voltage potential of the integrator signal INTEGR_T can be substantially at 40% of the logic low to logic high voltage potential (e.g., 40% of VDD). Furthermore, the voltage potential of the complementary integrator signal INTEGR_C can be substantially at 60% of the logic low to logic high voltage potential (e.g., 60% of VDD). Integrator circuit 326 is configured to provide the integrator signal INTEGR_T and the complementary integrator signal INTEGR_C to amplifier circuit 378.

[0056] Amplifier circuit 378 is configured to control the correction of the corrected duty cycle of the corrected clock signal CLK_OUT_T in response to integrator signals (integrator signal INTEGR_T and complementary integrator signal INTEGR_C). For example, amplifier circuit 378 compares integrator signal INTEGR_T with complementary integrator signal INTEGR_C and generates a first error signal 370 and a second error signal 372, which are used to control the controllable current source 306 and controllable current source 308 of duty cycle regulator 310, respectively.

[0057] In some embodiments, amplifier circuit 378 includes a differential amplifier. Amplifier circuit 378 includes a first amplifier output terminal electrically connected to a controllable current source 306 to pass a first error signal 370 to the controllable current source 306. Amplifier circuit 378 also includes a second amplifier output terminal electrically connected to a controllable current source 308 to pass a second error signal 372 to the controllable current source 306. Amplifier circuit 378 further includes a first amplifier input terminal (e.g., an inverting input terminal) configured to receive an integrator signal INTEGR_T. Amplifier circuit 378 also includes a second amplifier input terminal (e.g., a non-inverting input terminal) configured to receive a complementary integrator signal INTEGR_C.

[0058] In response to error signals (first error signal 370 and second error signal 372) provided by amplifier circuit 378, duty cycle regulator 310 is configured to receive input clock signal CLK_IN and adjust the corrected duty cycle of the second voltage potential RC2 (intermediate corrected clock signal), and consequently adjust the corrected clock signal CLK_OUT_T. The feedback loop (e.g., a complete negative feedback loop) maintains the voltage potential difference between integrator signal INTEGR_T and complementary integrator signal INTEGR_C at approximately zero volts. As a result, the corrected duty cycle can be maintained at approximately 50%. Compensation circuitry can be used for feedback loop stability, but is not included for simplicity. Figure 3 The example is shown in [the image]. Detailed examples of amplifier circuit 400, which can be used with amplifier circuit 378, are shown in [the image]. Figure 4 It is displayed in the middle.

[0059] Clock detector 328 is configured to disable the correction of the corrected duty cycle of the corrected clock signal CLK_OUT_T in response to detecting that the input clock signal CLK_IN is disabled. By means of a non-limiting example, clock detector 328 may be configured to deactivate amplifier circuit 378 in response to detecting that the input clock signal CLK_IN is disabled or deactivated. In other words, amplifier circuit 378 is configured to deactivate in response to detecting that the input clock signal CLK_IN is disabled or deactivated.

[0060] Clock detector 328 is configured to provide an enable signal ENABLE to amplifier circuit 378. The enable signal ENABLE is configured to control the enabling and disabling of the amplifier circuit. Clock detector 328 is configured to assert the enable signal ENABLE for at least a portion of each clock cycle of the input signal in response to the input clock signal CLK_IN being enabled. Clock detector 328 is also configured to maintain the enable signal ENABLE as an unasserted signal in response to the input clock signal CLK_IN being deactivated.

[0061] Clock detector 328 includes a series of inverters 330, 332, and 334 configured to receive an input clock signal CLK_IN (e.g., at the input terminal of inverter 330) and provide an inverted input clock signal. Clock detector 328 also includes a NAND gate 336 configured to provide a short-time pulse interference signal GLITCH in response to the input clock signal CLK_IN and the inverted clock signal from the series of inverters 330, 332, and 334. Clock detector 328 further includes an RC circuit comprising a resistor 356 and a capacitor 354, the resistor and capacitor being electrically connected in parallel to each other from a third node 364 to a low-voltage potential power node 368. Clock detector 328 also includes a transistor 380 (e.g., a PMOS transistor) electrically connected from a power node VDD to the RC circuit (i.e., to the third node 364). Transistor 380 is configured to electrically connect third node 364 (i.e., the RC circuit) to power node VDD (e.g., a logic low voltage potential in the case of transistor 380 being a PMOS transistor) in response to an assertion of a short-time pulse interference signal GLITCH. Clock detector 328 further includes a Schmitt trigger inverter 338 electrically connected from the RC circuit (i.e., third node 364) to amplifier circuit 378. Schmitt trigger inverter 338 is configured to provide an enable signal ENABLE to amplifier circuit 378.

[0062] A short-time pulse interference (e.g., an assertion of the short-time pulse interference signal GLITCH) on the gate terminal of transistor 380 can charge capacitor 354. Capacitor 354 can then be slowly discharged via resistor 356, which defines the lowest detectable frequency. The third voltage potential RC3 at the third node 364 is gated by Schmitt trigger inverter 338 to improve noise immunity and define the lowest frequency for duty cycle adjustment. As a result, duty cycle adjustment may not be enabled by each rising edge of the input clock signal CLK_IN, but only once per clock cycle.

[0063] A controllable switch 358 is configured to electrically connect a first amplifier input terminal (e.g., the inverting input terminal of amplifier circuit 378) to a second amplifier input terminal (e.g., the non-inverting input terminal of amplifier circuit 378) in response to detecting that the input clock signal CLK_IN is deactivated or deactivated. A clock detector 328 is configured to provide an enable signal ENABLE to the controllable switch 358. The enable signal ENABLE is configured to control the opening and closing of the controllable switch 358. By means of a non-limiting example, the controllable switch 358 may close in response to an assertion of the enable signal ENABLE, electrically connecting the first amplifier input terminal to the second amplifier input terminal. A Schmitt trigger inverter 338 is electrically connected from an RC circuit (i.e., the third node 364) to the controllable switch 358. The Schmitt trigger inverter 338 is configured to provide the enable signal ENABLE to the controllable switch 358.

[0064] Clock detector 328 can only enable duty cycle correction when the input clock signal CLK_IN is activated or enabled. As discussed above, when the input clock signal CLK_IN is not actively oscillating, it can be maintained at a logic low voltage potential (e.g., "0") or a logic high voltage potential (e.g., "1"). In response to the input clock signal CLK_IN without the amplifier circuit 378 being deactivated and the controllable switch 358 being closed, the integrator signal INTEGR_T and the complementary integrator signal INTEGR_C will saturate to a logic level voltage potential (e.g., the power rail voltage potential). In this state, if the input clock signal begins to oscillate, the duty cycle regulator 310 will begin to operate from the maximum possible duty cycle distortion, and therefore the first few cycles of the output clock signal CLK_OUT will have a very low or very high corrected duty cycle or may disappear completely.

[0065] The use of the clock detector 328 via amplifier circuit 378 and controllable switch 358 keeps the error signals 370 and 372 supplied to the current source equal and / or zero by electrically connecting the first amplifier input terminal and the second amplifier input terminal. As a result, both the integrator signal INTEGR_T and the complementary integrator signal INTEGR_C can be maintained at approximately halfway between the logic low and logic high voltage potentials, and amplifier circuit 378 can be deactivated. In this case, the first few clock cycles of the calibrated clock signal CLK_OUT_T can be provided by a duty cycle corrector 300 without duty cycle correction (e.g., a duty cycle approximately equal to 1). The duty cycle corrector 300 can later begin duty cycle correction, and the calibrated duty cycle of the calibrated clock signal CLK_OUT_T can later stabilize to approximately 50% for several (e.g., 20 to 30) clock cycles.

[0066] Figure 4 For use according to some embodiments Figure 3 A schematic circuit diagram of amplifier circuit 400 of amplifier circuit 378. Amplifier circuit 400 includes a first amplifier input terminal 432, a second amplifier input terminal 434, a first amplifier output terminal 436, a second amplifier output terminal 438, a low-voltage potential power node 428 (e.g., GND, VSS), a high-voltage potential power node 430 (e.g., VDD), a fourth node 440, a fifth node 442, a sixth node 444, a seventh node 446, and an eighth node 448. Amplifier circuit 400 also includes a current source 402, PMOS transistors 404, 406, 408, 410, 412, and 414, and NMOS transistors 416, 418, 420, 422, 424, and 426.

[0067] NMOS transistors 416 and 418 act as a differential stage receiving integrator signals INTEGR_T and INTEGR_C. NMOS transistor 416 is electrically connected from the fourth node 440 to the eighth node 448. The gate terminal of NMOS transistor 416 is electrically connected to the second amplifier input terminal 434. Therefore, the gate terminal of NMOS transistor 416 is configured to receive the complementary integrator signal INTEGR_C. NMOS transistor 418 is electrically connected from the fifth node 442 to the eighth node 448. The gate terminal of NMOS transistor 418 is electrically connected to the first amplifier input terminal 432. Therefore, the gate terminal of NMOS transistor 418 is configured to receive the integrator signal INTEGR_T.

[0068] PMOS transistor 404 is electrically connected from high-voltage power node 430 to the first amplifier output terminal 436. PMOS transistor 406 is electrically connected from high-voltage power node 430 to the sixth node 444. PMOS transistor 408 is electrically connected from high-voltage power node 430 to the fourth node 440. The gate terminals of PMOS transistors 404, 406, and 408 are electrically connected to the fourth node 440.

[0069] PMOS transistor 414 is electrically connected from high-voltage power node 430 to the second amplifier output terminal 438. PMOS transistor 412 is electrically connected from high-voltage power node 430 to the seventh node 446. PMOS transistor 410 is electrically connected from high-voltage power node 430 to the fifth node 442. The gate terminals of PMOS transistors 410, 412, and 414 are electrically connected to the fifth node 442.

[0070] NMOS transistor 420 is electrically connected from the first amplifier output terminal 436 to the low-voltage potential power node 428. The gate terminal of NMOS transistor 420 is electrically connected to the seventh node 446. NMOS transistor 422 is electrically connected from the sixth node 444 to the low-voltage potential power node 428. The gate terminal of NMOS transistor 422 is electrically connected to the sixth node 444.

[0071] NMOS transistor 424 is electrically connected from node 7 446 to low-voltage potential power node 428. The gate terminal of NMOS transistor 424 is electrically connected to node 7 446. NMOS transistor 426 is electrically connected from the second amplifier output terminal 438 to low-voltage potential power node 428. The gate terminal of NMOS transistor 426 is electrically connected to node 6 444. Current source 402 is electrically connected from node 8 448 to low-voltage potential power node 428.

[0072] PMOS transistors 404 and 408 may be cross-connected current mirrors for pull-up current (considering only one side), and NMOS transistors 420 and 424 may be cross-connected current mirrors for pull-down current.

[0073] If the input signals at the first amplifier input terminal 432 and the second amplifier input terminal 434, the integrator signals INTEGR_T and INTEGR_C are at the same voltage potential, then the pull-up and pull-down currents can have the same magnitude but opposite directions. As a result, the current supplied to the first amplifier output terminal 436 (first error signal 370) is zero. If the op-amp differential input signal (the difference between the integrator signals INTEGR_T and INTEGR_C) is not zero, then one of the pull-up or pull-down currents will dominate, and additional current will be added to or subtracted from the first amplifier output terminal 436 and the second amplifier output terminal 438 (at the first error signal 370 and the second error signal 372), thereby causing duty cycle correction (e.g., using...). Figure 3 Duty cycle corrector 300).

[0074] Figure 5 for Figure 3The following is a signal timing diagram of an example of signal 500 for a duty cycle corrector 300, where the duty cycle of the input clock signal CLK_IN is approximately 50%. Signal 500 includes the input clock signal CLK_IN, a short-time pulse interference signal GLITCH, a third voltage potential RC3, an enable signal ENABLE, a first voltage potential RC1, a second voltage potential RC2, a corrected clock signal CLK_OUT_T, a complementary corrected clock signal CLK_OUT_C, and an integrator signal INTEGR_T / C. The integrator signal INTEGR_T is shown using a solid line, and the complementary integrator signal INTEGR_C is shown using a dashed line.

[0075] Figure 5 Signal 500 is shown during the input clock deactivation period 502 and the input clock activation period 504. During the input clock deactivation period 502, the input clock signal CLK_IN is maintained at a logic low voltage level, the short-time pulse interference signal GLITCH is maintained at a logic high voltage level, the third voltage level RC3 is maintained at a logic low voltage level, the enable signal ENABLE is maintained at a logic low voltage level, the first voltage level RC1 is maintained at a logic high voltage level, the second voltage level is maintained at a logic low voltage level, the calibrated clock signal CLK_OUT_T is maintained at a logic low voltage level, and the complementary calibrated clock signal CLK_OUT_C ​​is maintained at a logic high voltage level. As previously discussed, during the input clock deactivation period 502, the integrator signal INTEGR_T / C is maintained at approximately halfway between the logic high and logic low voltage levels.

[0076] At input clock enable time 506, the input clock signal CLK_IN is enabled. As a result, during the input clock enable period 504 following input clock enable time 506, the input clock signal CLK_IN oscillates between logic high and logic low voltage levels. As can be seen by observing the input clock signal CLK_IN during input clock enable period 504, the input duty cycle of the input clock signal CLK_IN is approximately 50%.

[0077] At the positive edge of the input clock signal CLK_IN, a short-time pulse interference signal GLITCH briefly pulses to a logic level low voltage potential. This is because, for a brief moment, the NAND gate 336 ( Figure 3 The input is attributed to inverters 330, 332, and 334. Figure 3The added delay is the same. In response to each pulse of the short-time pulse wave interference signal GLITCH to the logic level low voltage potential, transistor 380 transitions from an electrically insulating state to a conductive state, which electrically connects the power node VDD to capacitor 354. Figure 3 As a result, capacitor 354 is charged, and the third voltage potential RC3 increases at each pulse of the short-time pulse wave interference signal GLITCH.

[0078] At duty cycle correction enable time 508, the third voltage potential RC3 reaches the switching threshold voltage potential of the Schmitt trigger inverter 338. As a result, the enable signal ENABLE (switching from logic low voltage potential to logic high voltage potential) can be asserted at duty cycle correction enable time 508. The enable signal ENABLE can remain asserted for the remainder of the input clock enable period 504 because the third voltage potential RC3 continues to increase with each pulse of the short pulse wave interference signal GLITCH during the input clock enable period 504 until the third voltage potential RC3 reaches and remains at the logic high voltage potential.

[0079] At input clock enable time 506, the first voltage potential RC1 and the second voltage potential RC2 begin to oscillate. The second voltage potential RC2 is substantially opposite to or complementary to the first voltage potential RC1, except that the second voltage potential is delayed relative to the first voltage potential (e.g., due to...). Figure 3 (The delay of inverter 304 and resistor 342). Since the duty cycle of the input clock signal CLK_IN is approximately 50%, the duty cycles of the first voltage potential RC1 and the second voltage potential RC2 are also approximately 50% even before the duty cycle correction enable time 508.

[0080] In response to the oscillation of the second voltage potential RC2 during the input clock enable period 504, the clock splitter 312 ( Figure 3 It provides a calibrated clock signal CLK_OUT_T and a complementary calibrated clock signal CLK_OUT_C. Since the duty cycle of the second voltage potential RC2 is approximately 50%, the calibrated duty cycle of the calibrated clock signal CLK_OUT_T is 50% even before the duty cycle calibration enable time 508, and so is the complementary calibrated duty cycle of the calibrated complementary clock signal CLK_OUT_C.

[0081] After duty cycle correction is enabled at time 508, the integrator signal INTEGR_T / C exhibits a small oscillation as integrator circuit 326 ( Figure 3The RC circuit responds to the calibrated clock signal CLK_OUT_T and the complementary calibrated clock signal CLK_OUT_C ​​for charging and discharging. However, since the input cycle of the input clock signal CLK_IN is approximately 50%, the error signal generated by the oscillation in the integrator signal INTEGR_T / C ( Figure 3 The second error signal 372 and the integrator output terminal 374) can be relatively small, and the duty cycle regulator 310 ( Figure 3 No significant correction is made to the calibrated duty cycle of the calibrated clock signal CLK_OUT_T.

[0082] Figure 6 for Figure 3 The following is a signal timing diagram of an example of signal 600 of duty cycle corrector 300, where the duty cycle of input clock signal CLK_IN is approximately 30%. Signal 600 includes input clock signal CLK_IN, short-time pulse interference signal GLITCH, third voltage potential RC3, enable signal ENABLE, first voltage potential RC1, second voltage potential RC2, corrected clock signal CLK_OUT_T, complementary corrected clock signal CLK_OUT_C, and integrator signal INTEGR_T / C. Integrator signal INTEGR_T is shown using solid lines, and complementary integrator signal INTEGR_C is shown using dashed lines.

[0083] Figure 6 Signal 600 is shown during input clock deactivation period 602 and input clock activation period 604. Similarly, as referenced above... Figure 5 As discussed earlier, during the input clock deactivation period 602, the input clock signal CLK_IN is maintained at a logic low voltage level, the short-time pulse interference signal GLITCH is maintained at a logic high voltage level, the third voltage level RC3 is maintained at a logic low voltage level, the enable signal ENABLE is maintained at a logic low voltage level, the first voltage level RC1 is maintained at a logic high voltage level, the second voltage level RC2 is maintained at a logic low voltage level, the calibrated clock signal CLK_OUT_T is maintained at a logic low voltage level, and the complementary calibrated clock signal CLK_OUT_C ​​is maintained at a logic high voltage level. Also as previously discussed, during the input clock deactivation period 602, the integrator signal INTEGR_T / C is maintained at approximately halfway between the logic high and low voltage levels.

[0084] At input clock enable time 606, the input clock signal CLK_IN is enabled. As a result, during the input clock enable period 604 following input clock enable time 606, the input clock signal CLK_IN oscillates between logic high and logic low voltage levels. As can be seen by observing the input clock signal CLK_IN during input clock enable period 604, the input duty cycle of the input clock signal CLK_IN is approximately 30%. Consequently, the input clock signal CLK_IN is severely distorted at a 30% duty cycle.

[0085] As discussed above, at the positive edge of the input clock signal CLK_IN, the short-time pulse interference signal GLITCH briefly pulses to the logic level low voltage potential. In response to each pulse of the short-time pulse interference signal GLITCH to the logic level low voltage potential, the third voltage potential RC3 increases.

[0086] At duty cycle correction enable time 608, the third voltage potential RC3 reaches the switching threshold voltage potential of the Schmitt trigger inverter 338. As a result, the enable signal ENABLE can be asserted at duty cycle correction enable time 608. The enable signal ENABLE can remain asserted for the remainder of the input clock enable period 604 because the third voltage potential RC3 continues to increase with each pulse of the short-time pulse wave interference signal GLITCH during the input clock enable period 604 until the third voltage potential RC3 reaches and remains at a logic high voltage potential.

[0087] At input clock enable time 606, the first voltage potential RC1 and the second voltage potential RC2 begin to oscillate. The second voltage potential RC2 is substantially opposite to or complementary to the first voltage potential RC1, except that the second voltage potential is delayed compared to the first voltage potential. Since the duty cycle of the input clock signal CLK_IN is substantially 30%, the duty cycle of the second voltage potential RC2 is also substantially 30% before the duty cycle correction enable time 608.

[0088] In response to the oscillation of the second voltage potential RC2 during the input clock enable period 604, the clock splitter 312 ( Figure 3 This provides a calibrated clock signal CLK_OUT_T and a complementary calibrated clock signal CLK_OUT_C. Since the duty cycle of the second voltage potential RC2 is approximately 30%, the calibrated duty cycle of the calibrated clock signal CLK_OUT_T is also approximately 30%. The complementary calibrated duty cycle of the calibrated complementary clock signal CLK_OUT_C ​​can be approximately 70% before the duty cycle calibration enable time 608.

[0089] After duty cycle correction is enabled at time 608, the integrator signal INTEGR_T / C is displayed in relation to... Figure 5 The oscillations shown are stronger than the oscillations because the corrected duty cycle is not 50%, which makes the integrator circuit 326 ( Figure 3 The RC circuit of the integrator is charged and discharged in response to the calibrated clock signal CLK_OUT_T and the complementary calibrated clock signal CLK_OUT_C. As a result, the error signal generated by the oscillation in the integrator signal INTEGR_T / C ( Figure 3 The second error signal 372 and the integrator output terminal 374) can be relatively large, and the duty cycle regulator 310 ( Figure 3 It can significantly correct the corrected duty cycle of the corrected clock signal CLK_OUT_T.

[0090] It can be observed that the calibrated duty cycle of the calibrated clock signal CLK_OUT_T approaches 50% with each clock cycle after the duty cycle calibration enable time 608, until the calibrated duty cycle of the calibrated clock signal CLK_OUT_T is approximately 50% after only a few clock cycles. Furthermore, it should be noted that the calibrated clock signal CLK_OUT_T and the complementary calibrated clock signal are provided before the duty cycle calibration enable time 608, but with a distorted duty cycle.

[0091] Figure 7 The following is a flowchart illustrating a method 700 for correcting the duty cycle of an input clock signal according to some embodiments. At operation 702, method 700 includes receiving an input clock signal. At operation 704, method 700 includes generating an intermediate corrected clock signal in response to the input clock signal. At operation 706, method 700 includes splitting the intermediate corrected clock signal into a corrected clock signal and a complementary corrected clock signal.

[0092] At operation 708, method 700 includes integrating the calibrated clock signal to generate an integrator signal. In some embodiments, integrating the calibrated clock signal includes applying the calibrated clock signal to a first RC circuit. At operation 710, method 700 includes integrating a complementary calibrated clock signal to generate a complementary integrator signal. In some embodiments, integrating the complementary calibrated clock signal includes applying the complementary calibrated clock signal to a second RC circuit. At operation 712, method 700 includes using the amplifier circuit to generate a first error signal and a second error signal in response to the integrator signal provided to a first amplifier input terminal of the amplifier circuit and the complementary integrator signal provided to a second amplifier input terminal of the amplifier circuit.

[0093] At operation 714, method 700 includes adjusting the duty cycle of an intermediate calibrated clock signal relative to the duty cycle of an input clock signal in response to a first error signal and a second error signal. In some embodiments, adjusting the duty cycle of the intermediate calibrated clock signal includes providing the first error signal to a first controllable current source electrically connected to a first node of the duty cycle regulator. In some embodiments, adjusting the duty cycle of the intermediate calibrated clock signal includes providing the second error signal to a second controllable current source electrically connected to a second node of the duty cycle regulator.

[0094] At operation 716, method 700 includes detecting whether the input clock signal is activated. At operation 718, method 700 includes disabling the amplifier circuit in response to detecting that the input clock signal is not activated. At operation 720, method 700 includes electrically connecting the first amplifier input terminal to the second amplifier input terminal in response to detecting that the input clock signal is not activated.

[0095] Figure 8 This is a block diagram of a computing system 800 according to some embodiments. The computing system 800 includes one or more processors 804 operatively coupled to one or more memory devices 802, one or more non-volatile data storage devices 810, one or more input devices 806, and one or more output devices 808. In some embodiments, the computing system 800 includes a personal computer (PC), such as a desktop computer, laptop computer, tablet computer, mobile computer (e.g., smartphone, personal digital assistant (PDA), etc.), web server, or other computer device.

[0096] In some embodiments, one or more processors 804 may include a central processing unit (CPU) or other processors configured to control the computing system 800. In some embodiments, one or more memory devices 802 include random access memory (RAM), such as volatile data storage devices (e.g., dynamic RAM (DRAM), static RAM (SRAM), etc.). In some embodiments, one or more non-volatile data storage devices 810 include hard disk drives, solid-state drives, flash memory, erasable programmable read-only memory (EPROM), other non-volatile data storage devices, or any combination thereof. In some embodiments, one or more input devices 806 include a keyboard 814, pointing devices 818 (e.g., mouse, tracking pad, etc.), a microphone 812, a keypad 816, a scanner 820, a camera 828, other input devices, or any combination thereof. In some embodiments, an output device 808 includes an electronic display 822, a speaker 826, a printer 824, other output devices, or any combination thereof.

[0097] In some embodiments, one or more memory devices 802 include Figure 2 The memory device 200. In such embodiments, the memory device 802 may include a duty cycle corrector, for example... Figure 3 Duty cycle corrector 300. Therefore, one or more memory devices 802 can correct the clock signal (e.g., ...) Figure 1 , Figure 2 , Figure 3 , Figure 5 or Figure 6 The calibrated clock signal CLK_OUT_T is operated, the calibrated clock signal having a calibrated duty cycle calibrated according to one or more embodiments discussed herein.

[0098] As used in this disclosure, the term "combination" referring to multiple elements can include a combination of all elements or any of a variety of different sub-combinations of some elements. For example, the phrase "A, B, C, D or a combination thereof" can refer to any of the following: A, B, C or D; a combination of each of A, B, C and D; and any sub-combination of A, B, C or D, such as A, B and C; A, B and D; A, C and D; B, C and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0099] The terms used in this disclosure and especially in the appended claims (e.g., the body of the appended claims) are generally intended to be “open-ended” terms (e.g., the term “including” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “having at least”, the term “includes” should be interpreted as “including but not limited to”, etc.).

[0100] Furthermore, if a specific number of introduced claim statements are anticipated, this intention will be explicitly stated in the claims, and if no such statements are present, this intention does not exist. For example, to aid understanding, the appended claims may contain introductory phrases such as "at least one" and "one or more" to introduce claim statements. However, the use of such phrases should not be construed as implying that introducing claim statements with the indefinite article "a (a / an)" limits any particular claim containing such introduced claim statements to embodiments containing only one such statement, even if the same claim contains the introductory phrases "one or more" or "at least one" and an indefinite article such as "a (a / an)" (e.g., "a (a and / or an)" should be interpreted as meaning "at least one" or "one or more"); the same applies to cases where definite articles are used to introduce claim statements.

[0101] Furthermore, even if a specific number of claims is explicitly stated, those skilled in the art will recognize that such a statement should be interpreted as meaning at least the number of claims (e.g., the unadorned statement "two statements" without other embellishments means at least two statements or two or more statements). Moreover, in cases where conventions such as "at least one of A, B, and C" or "one or more of A, B, and C" are used, such structures are generally intended to include only A, only B, only C, A and B, A and C, B and C, or A, B, and C, etc.

[0102] Furthermore, any transitional words or phrases presenting two or more alternative terms in the description, claims, or drawings should be understood to include the possibility of including one, any, or both of the stated terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0103] Example

[0104] The following is a non-exhaustive and non-limiting list of examples. Not every example listed below is explicitly and individually indicated to be combinable with all others listed below and discussed above. However, it is intended that these examples can be combined with all other examples unless it will be obvious to a person skilled in the art that the examples cannot be combined.

[0105] Example 1: An apparatus comprising: an integrator circuit configured to receive a calibrated clock signal and a complementary calibrated clock signal, the complementary calibrated clock signal being complementary to the calibrated clock signal, the integrator circuit being configured to provide: an integrator signal generally indicating the integration of the calibrated clock signal; and a complementary integrator signal generally indicating the integration of the complementary calibrated clock signal; an amplifier circuit configured to control a correction of the duty cycle of the calibrated clock signal, the amplifier circuit being configured to deactivate in response to detecting that an input clock signal is deactivated, the amplifier circuit including: a first amplifier input terminal configured to receive the integrator signal; and a second amplifier input terminal configured to receive the complementary integrator signal; and an electrically controllable switch configured to selectively electrically connect the first amplifier input terminal to the second amplifier input terminal in response to detecting that the input clock signal is deactivated.

[0106] Example 2: The device according to Example 1 further includes a clock detector configured to provide an enable signal to the amplifier circuit and the electrically controllable switch, the enable signal being configured to control the enabling and disabling of the amplifier circuit, and the enable signal being further configured to control the opening and closing of the electrically controllable switch.

[0107] Example 3: The device according to Example 2, wherein the clock detector is configured to: assert the enable signal during at least a portion of each clock cycle of the input clock signal in response to the input clock signal being enabled; and maintain the enable signal as a revoked assertion in response to the input clock signal being deactivated.

[0108] Example 4: The device according to Example 3, wherein the clock detector comprises: one or more inverters configured to receive the input clock signal and provide an inverted input clock signal; a NAND gate configured to provide a short-time pulse interference signal in response to the input clock signal and the inverted input clock signal; a resistor-capacitor (RC) circuit; a transistor electrically connected from a power node to the RC circuit, the transistor being configured to electrically connect the RC circuit to the power node in response to an assertion of the short-time pulse interference signal; and an inverter electrically connected from the RC circuit to the amplifier circuit and the electrically controllable switch, the inverter being configured to provide the enable signal to the amplifier circuit and the electrically controllable switch.

[0109] Example 5: The device according to any one of Examples 1 to 4 further includes a duty cycle adjuster configured to receive the input clock signal and adjust the duty cycle of the intermediate corrected clock signal in response to an error signal provided by the amplifier circuit.

[0110] Example 6: The device according to Example 5 further includes a clock splitter configured to receive the intermediate calibrated clock signal and generate the calibrated clock signal and the complementary calibrated clock signal in response to the intermediate calibrated clock signal.

[0111] Example 7: The device according to any one of Examples 1 to 6, wherein the amplifier circuit comprises a differential operational amplifier.

[0112] Example 8: The device according to any one of Examples 1 to 7, wherein the integrator circuit includes a first resistor-capacitor (RC) circuit and a second RC circuit, the first RC circuit being configured to provide the integrator signal in response to the calibrated clock signal, and the second RC circuit being configured to provide the complementary integrator signal in response to the complementary calibrated clock signal.

[0113] Example 9: An apparatus comprising: a duty cycle regulator configured to receive an input clock signal and correct the duty cycle of a corrected clock signal relative to an input duty cycle of the input clock signal; an integrator circuit configured to generate an integrator signal in response to the corrected clock signal, the integrator signal substantially indicating the integration of the corrected clock signal over time; an amplifier circuit configured to control the correction of the duty cycle of the corrected clock signal by the duty cycle regulator in response to the integrator signal; and a clock detector configured to disable the correction of the duty cycle of the corrected clock signal in response to detecting that the input clock signal has been deactivated.

[0114] Example 10: The device according to Example 9, wherein the clock detector is configured to deactivate the amplifier circuit in response to detecting that the input clock signal is deactivated.

[0115] Example 11: The device according to any one of Examples 9 and 10, wherein the duty cycle regulator comprises: a first inverter, a first input terminal of the first inverter being configured to receive an input clock signal; a first resistor electrically connected from a first output terminal of the first inverter to a first node; a second inverter, a second input terminal of the second inverter being electrically connected to the first node; a second resistor electrically connected from a second output terminal of the second inverter to a second node; a first controllable current source electrically connected from the first node to a power supply node; and a second controllable current source electrically connected from the second node to the power supply node.

[0116] Example 12: The device according to Example 11, wherein the amplifier circuit includes a differential amplifier, the differential amplifier including a first amplifier output terminal and a second amplifier output terminal, the first amplifier output terminal being electrically connected to a first controllable current source, and the second amplifier output terminal being electrically connected to a second controllable current source.

[0117] Example 13: The device according to Example 12 further includes an electrically controllable switch configured to electrically connect a first amplifier input terminal of the differential amplifier to a second amplifier input terminal of the differential amplifier in response to detecting that the input clock signal is deactivated.

[0118] Example 14: The device according to any one of Examples 9 to 13 further includes a clock splitter configured to receive an intermediate calibrated clock signal from the duty cycle regulator, the clock splitter being configured to provide the calibrated clock signal and a complementary calibrated clock signal to the integrator circuit, the complementary calibrated clock signal being complementary to the calibrated clock signal.

[0119] Example 15: A method for correcting the duty cycle of an input clock signal, the method comprising: generating an intermediate corrected clock signal in response to the input clock signal; splitting the intermediate corrected clock signal into a corrected clock signal and a complementary corrected clock signal; integrating the corrected clock signal to generate an integrator signal; integrating the complementary corrected clock signal to generate a complementary integrator signal; generating a first error signal and a second error signal using the amplifier circuit in response to the integrator signal provided to a first amplifier input terminal of the amplifier circuit and the complementary integrator signal provided to a second amplifier input terminal of the amplifier circuit; adjusting the corrected duty cycle of the intermediate corrected clock signal relative to an input duty cycle of the input clock signal in response to the first error signal and the second error signal; and electrically connecting the first amplifier input terminal to the second amplifier input terminal in response to detecting that the input clock signal is not activated.

[0120] Example 16: The method according to Example 15 further includes deactivating the amplifier circuit in response to detecting that the input clock signal is not activated.

[0121] Example 17: The method according to any one of Examples 15 and 16, wherein adjusting the calibrated duty cycle of the intermediate calibrated clock signal comprises: providing the first error signal to a first controllable current source electrically connected to a first node of the duty cycle regulator; and providing the second error signal to a second controllable current source electrically connected to a second node of the duty cycle regulator.

[0122] Example 18: The method according to any one of Examples 15 to 17, wherein: integrating the calibrated clock signal includes applying the calibrated clock signal to a first resistor-capacitor (RC) circuit; and integrating the complementary calibrated clock signal includes applying the complementary calibrated clock signal to a second RC circuit.

[0123] Example 19: The method according to any one of Examples 15 to 18 further includes providing the calibrated clock signal and the complementary calibrated clock signal to the clock utilization circuit system.

[0124] Example 20: According to the method of Example 19, providing the calibrated clock signal and the complementary calibrated clock signal to the clock utilization circuit system includes providing the calibrated clock signal and the complementary calibrated clock signal to the memory circuit system.

[0125] in conclusion

[0126] While this disclosure has been described herein with respect to certain illustrated embodiments, those skilled in the art will recognize and understand that the invention is not so limited. Rather, many additions, deletions, and modifications may be made to the illustrated and described embodiments without departing from the scope of the invention as claimed below and its legal equivalents. Furthermore, features from one embodiment may be combined with features from another embodiment while still being covered within the scope of the invention as contemplated by the inventors.

Claims

1. An apparatus comprising: An integrator circuit configured to receive a calibrated clock signal and a complementary calibrated clock signal, the complementary calibrated clock signal being complementary to the calibrated clock signal, the integrator circuit being configured to provide: Integrator signal, which indicates the integration of the calibrated clock signal; as well as The complementary integrator signal indicates the integration of the complementary calibrated clock signal; An amplifier circuit configured to control the correction of the duty cycle of the calibrated clock signal, the amplifier circuit being configured to deactivate in response to detecting that the input clock signal is deactivated, the amplifier circuit comprising: A first amplifier input terminal is configured to receive the integrator signal; as well as The second amplifier input terminal is configured to receive the complementary integrator signal; as well as An electrically controllable switch is configured to selectively connect the first amplifier input terminal to the second amplifier input terminal in response to detecting that the input clock signal is deactivated.

2. The device of claim 1, further comprising a clock detector configured to provide an enable signal to the amplifier circuit and the electrically controllable switch, the enable signal being configured to control the enabling and disabling of the amplifier circuit, and the enable signal being further configured to control the opening and closing of the electrically controllable switch.

3. The device of claim 2, wherein the clock detector is configured to: In response to the input clock signal being enabled, the enable signal is asserted during at least a portion of each clock cycle of the input clock signal; and The enable signal is maintained as a revocation assertion in response to the input clock signal being deactivated.

4. The device of claim 3, wherein the clock detector comprises: One or more inverters are configured to receive the input clock signal and provide an inverted input clock signal; A NAND gate is configured to provide a short-time pulse wave interference signal in response to the input clock signal and the inverted input clock signal; Resistor-capacitor RC circuit; A transistor electrically connected from a power node to the RC circuit, the transistor being configured to electrically connect the RC circuit to the power node in response to an assertion of the short-time pulse wave interference signal; as well as An inverter, electrically connected from the RC circuit to the amplifier circuit and the electrically controllable switch, is configured to provide the enable signal to the amplifier circuit and the electrically controllable switch.

5. The device according to any one of claims 1 to 4, further comprising a duty cycle adjuster configured to receive the input clock signal and adjust the duty cycle of the intermediate corrected clock signal in response to an error signal provided by the amplifier circuit.

6. The apparatus of claim 5, further comprising a clock splitter configured to receive the intermediate calibrated clock signal and, in response to the intermediate calibrated clock signal, generate the calibrated clock signal and the complementary calibrated clock signal.

7. The device according to any one of claims 1 to 4, wherein the amplifier circuit comprises a differential operational amplifier.

8. The device according to any one of claims 1 to 4, wherein the integrator circuit comprises a first RC circuit and a second RC circuit, the first RC circuit being configured to provide the integrator signal in response to the calibrated clock signal, and the second RC circuit being configured to provide the complementary integrator signal in response to the complementary calibrated clock signal.

9. An apparatus comprising: A duty cycle adjuster configured to receive an input clock signal and correct the duty cycle of the corrected clock signal relative to the input duty cycle of the input clock signal; An integrator circuit configured to generate an integrator signal in response to the calibrated clock signal, the integrator signal indicating the integration of the calibrated clock signal over time; An amplifier circuit configured to control the correction of the duty cycle of the corrected clock signal by the duty cycle regulator in response to the integrator signal; as well as A clock detector is configured to disable the correction of the duty cycle of the corrected clock signal in response to detecting that the input clock signal has been deactivated.

10. The device of claim 9, wherein the clock detector is configured to deactivate the amplifier circuit in response to detecting that the input clock signal is deactivated.

11. The device according to any one of claims 9 and 10, wherein the duty cycle regulator comprises: A first inverter, wherein the first input terminal of the first inverter is configured to receive an input clock signal; A first resistor is electrically connected from the first output terminal of the first inverter to the first node; The second inverter, the second input terminal of the second inverter is electrically connected to the first node; The second resistor is electrically connected from the second output terminal of the second inverter to the second node; A first controllable current source is electrically connected from the first node to the power supply node; as well as A second electrically controllable current source is electrically connected from the second node to the power supply node.

12. The device of claim 11, wherein the amplifier circuit comprises a differential amplifier, the differential amplifier including a first amplifier output terminal and a second amplifier output terminal, the first amplifier output terminal being electrically connected to a first controllable current source, and the second amplifier output terminal being electrically connected to a second controllable current source.

13. The device of claim 12, further comprising an electrically controllable switch configured to electrically connect a first amplifier input terminal of the differential amplifier to a second amplifier input terminal of the differential amplifier in response to detecting that the input clock signal is deactivated.

14. The device according to any one of claims 9 and 10, further comprising a clock splitter configured to receive an intermediate calibrated clock signal from the duty cycle regulator, the clock splitter being configured to provide the calibrated clock signal and a complementary calibrated clock signal to the integrator circuit, the complementary calibrated clock signal being complementary to the calibrated clock signal.

15. A method for correcting the duty cycle of an input clock signal, the method comprising: An intermediate corrected clock signal is generated in response to the input clock signal; The intermediate calibrated clock signal is split into a calibrated clock signal and a complementary calibrated clock signal; The calibrated clock signal is integrated to generate an integrator signal; The complementary, calibrated clock signal is integrated to generate a complementary integrator signal; The amplifier circuit generates a first error signal and a second error signal in response to the integrator signal provided to the first amplifier input terminal and the complementary integrator signal provided to the second amplifier input terminal. The calibrated duty cycle of the intermediate calibrated clock signal is adjusted relative to the input duty cycle of the input clock signal in response to the first error signal and the second error signal; as well as In response to detecting that the input clock signal is not activated, the first amplifier input terminal is electrically connected to the second amplifier input terminal.

16. The method of claim 15, further comprising deactivating the amplifier circuit in response to detecting that the input clock signal is not activated.

17. The method of claim 15, wherein adjusting the calibrated duty cycle of the intermediate calibrated clock signal comprises: The first error signal is provided to a first controllable current source electrically connected to a first node of the duty cycle regulator; and The second error signal is provided to a second controllable current source electrically connected to a second node of the duty cycle regulator.

18. The method of claim 15, wherein: Integrating the calibrated clock signal includes applying the calibrated clock signal to a first resistor-capacitor RC circuit; and Integrating the complementary calibrated clock signal includes applying the complementary calibrated clock signal to a second RC circuit.

19. The method according to any one of claims 15 to 18, further comprising providing the calibrated clock signal and the complementary calibrated clock signal to a clock utilization circuit system.

20. The method of claim 19, wherein providing the calibrated clock signal and the complementary calibrated clock signal to the clock utilization circuit system comprises providing the calibrated clock signal and the complementary calibrated clock signal to the memory circuit system.

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