An Improved SAR Analog-to-Digital Conversion Method and System

Abstract

This application provides an improved SAR analog-to-digital conversion method and system, belonging to the field of analog-to-digital conversion technology. The method includes: a successive approximation analog-to-digital converter, a multi-slope integrator, a time-to-digital converter, and a digital signal processor. The successive approximation analog-to-digital converter converts the input analog signal to obtain a first digital code and a residual voltage. The multi-slope integrator converts the residual voltage to obtain a time signal corresponding to the residual voltage. The time-to-digital converter counts the time signal to obtain a second digital code. The digital signal processor concatenates the first and second digital codes to obtain a digital signal corresponding to the analog signal. The improved SAR analog-to-digital conversion method and system provided by this application can meet the needs of high-precision measurement scenarios.

Description

Technical Field

[0001] This application belongs to the field of analog-to-digital conversion technology, and more specifically, relates to an improved SAR analog-to-digital conversion method and system. Background Technology

[0002] In the field of analog-to-digital conversion for high-precision scenarios such as power measurement, successive approximation register (SAR) ADCs are widely used due to their advantages of simple structure, low power consumption and fast conversion speed. Meanwhile, integral ADCs, with their good linearity, high sensitivity and theoretically infinitely achievable resolution, have become an important technical choice for high-precision scenarios. Together, they constitute the mainstream technical solutions in this field.

[0003] However, SARADCs are susceptible to factors such as capacitor mismatch, comparator offset voltage, and thermal noise in high-precision measurements of 12 bits or more, which limits the improvement of accuracy. Integrating ADCs have the inherent limitation of low conversion rate. Existing technologies have not fundamentally solved the problem of synergistic optimization of "accuracy and speed", which makes it difficult for existing analog-to-digital conversion systems to balance high-speed conversion and high-precision output, and thus cannot meet the needs of high-precision measurement scenarios. Summary of the Invention

[0004] The purpose of this application is to provide an improved SAR analog-to-digital conversion method and system to meet the needs of high-precision measurement scenarios.

[0005] A first aspect of this application provides an improved SAR analog-to-digital conversion system, comprising: a successive approximation analog-to-digital converter, a multi-slope integrator, a time-to-digital converter, and a digital signal processor; A successive approximation analog-to-digital converter is used to convert the input analog signal to obtain the first digital code and the residual voltage; A multi-slope integrator is used to convert the residual voltage to obtain the time signal corresponding to the residual voltage; A time-to-digital converter is used to count time signals to obtain a second digital code; A digital signal processor is used to concatenate a first digital code and a second digital code to obtain a digital signal corresponding to an analog signal.

[0006] A second aspect of this application provides an improved SAR analog-to-digital conversion method, comprising: The analog signal is converted using a successive approximation analog-to-digital converter to obtain the first digital code and the residual voltage; The residual voltage is converted using a multi-slope integrator to obtain the time signal corresponding to the residual voltage; The time-to-digital converter counts the time signal to obtain a second digital code; A digital signal processor concatenates the first digital code and the second digital code to obtain a digital signal corresponding to the analog signal.

[0007] A third aspect of this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the steps of the improved SAR analog-to-digital conversion method described above.

[0008] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the improved SAR analog-to-digital conversion method described above.

[0009] The beneficial effects of the improved SAR analog-to-digital conversion method and system provided in this application are as follows: This application uses a successive approximation analog-to-digital converter to convert the input analog signal, quickly outputting the first digital code and residual voltage, ensuring the conversion rate; a multi-slope integrator specifically processes the residual voltage, converting the voltage signal into a time signal, compensating for the shortcomings of traditional successive approximation ADCs in high-precision scenarios and improving conversion accuracy; a time-to-digital converter accurately counts the time signal to obtain the second digital code, providing reliable support for fine quantization; a digital signal processor concatenates the first and second digital codes, integrating the coarse and fine quantization results. Through the collaboration of various components, the high-speed advantage of the successive approximation analog-to-digital converter is utilized, while the high-precision characteristics of the multi-slope integrator are used to optimize the conversion quality, solving the problem of the difficulty in balancing "accuracy and speed" in traditional ADCs, and ultimately achieving high-speed, high-precision conversion of analog signals to digital signals, meeting the usage requirements of high-precision measurement scenarios. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A structural block diagram of an improved SAR analog-to-digital conversion system provided in one embodiment of this application; Figure 2 An overall architecture block diagram of an improved SAR analog-to-digital conversion system provided in one embodiment of this application; Figure 3A segmented capacitor DAC array circuit diagram provided in one embodiment of this application; Figure 4 A functional block diagram of a multi-slope integrator provided in an embodiment of this application; Figure 5 A timing diagram for conversion provided in an embodiment of this application; Figure 6 A flowchart of the adaptive ramp generator calibration provided in one embodiment of this application; Figure 7 A flowchart illustrating an improved SAR analog-to-digital conversion method provided in an embodiment of this application; Figure 8 This is a schematic block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0012] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, circuits, and methods are omitted so as not to obscure the description of this application with unnecessary detail.

[0013] To make the objectives, technical solutions, and advantages of this application clearer, the following description will be provided in conjunction with the accompanying drawings and specific embodiments.

[0014] Please refer to Figure 1 , Figure 1 The present application provides a structural block diagram of an improved SAR analog-to-digital conversion system 20, which includes: a successive approximation analog-to-digital converter 21, a multi-slope integrator 22, a time-to-digital converter 23, and a digital signal processor 24. A successive approximation analog-to-digital converter is used to convert the input analog signal to obtain the first digital code and the residual voltage; A multi-slope integrator is used to convert the residual voltage to obtain the time signal corresponding to the residual voltage; A time-to-digital converter is used to count time signals to obtain a second digital code; A digital signal processor is used to concatenate a first digital code and a second digital code to obtain a digital signal corresponding to an analog signal.

[0015] In this embodiment, the successive approximation analog-to-digital converter (ADC) is used to perform coarse quantization of the analog signal. The input analog signal range is 0~10V, which is suitable for the signal requirements of high-precision scenarios such as power measurement. Internally, it works in concert with components such as a segmented capacitor DAC array and comparators. The final output digital code is an 8-bit high-order digital code, and the amplitude of the residual voltage is controlled within 1mV, which reduces the processing difficulty for subsequent fine quantization.

[0016] Multi-slope integrators, employing a fully differential operational amplifier architecture, are components for achieving high-precision fine quantization. The residual voltage it receives is the error voltage signal from the successive approximation analog-to-digital converter. Through the forward-reverse integration process of its internal integrating capacitor network, the voltage signal is converted into a time signal. During the conversion process, techniques such as chopping stabilization and offset calibration are used to ensure conversion accuracy.

[0017] The Time to Digital Converter (TDC) can be designed based on a ring oscillator with a counting frequency of 200MHz, a counting range of 0~10μs, and a resolution of 5ns. It can accurately count the time signal output by the multi-slope integrator and output an 8-bit low-order digital code. Its resolution parameter ensures the accuracy of the time-to-digital conversion and matches the high-precision characteristics of the multi-slope integrator.

[0018] A Digital Signal Processor (DSP) can employ a lightweight hardware architecture design, integrating an FIR low-pass filter module, a nonlinear correction module, and a code concatenation module. The FIR low-pass filter module has a cutoff frequency of 10kHz and is used to eliminate high-frequency noise; the nonlinear correction module is used to compensate for non-ideal errors in various components of the system; the code concatenation module concatenates 8 high-order bits and 8 low-order bits into a 16-bit digital signal, and the final output digital signal can accurately reflect the true value of the input analog signal.

[0019] like Figure 2 As shown, in this embodiment, the input analog signal first enters a successive approximation analog-to-digital converter. After sampling and holding and successive approximation quantization, it outputs an 8-bit first digital code and a residual voltage of less than 1mV. The residual voltage is sent to a multi-slope integrator, which converts it into a corresponding time signal through cyclic processing of forward and reverse integration. The time-to-digital converter counts this time signal to generate an 8-bit second digital code. Finally, the digital signal processor receives the first and second digital codes, performs FIR filtering and nonlinear correction in sequence, and completes code value concatenation to output a 16-bit high-precision digital signal. The entire conversion process forms a closed-loop workflow of coarse quantization-fine quantization-signal synthesis.

[0020] like Figure 5As shown, the horizontal axis represents the time axis from 0 to 11 μs, and the vertical axis marks the working state of the module, which is divided into the following stages: sampling (0 to 5 μs), SRA quantization (5 to 9 μs), multi-slope integration (9 to 10 μs), TDC counting (10 to 10.5 μs), and result synthesis (10.5 to 11 μs). The timing of each stage is precisely coordinated to ensure that the single conversion cycle is 10 μs, providing timing support for the system's high-speed and high-precision analog-to-digital conversion.

[0021] As can be seen from the above, this embodiment uses a successive approximation analog-to-digital converter to convert the input analog signal, quickly outputting the first digital code and residual voltage, ensuring the conversion rate. The multi-slope integrator specifically processes the residual voltage, converting the voltage signal into a time signal, compensating for the shortcomings of traditional successive approximation ADCs in high-precision scenarios and improving conversion accuracy. The time-to-digital converter accurately counts the time signal to obtain the second digital code, providing reliable support for fine quantization. The digital signal processor concatenates the first and second digital codes, integrating the coarse and fine quantization results. Through the collaboration of these components, the high-speed advantage of the successive approximation analog-to-digital converter is leveraged, while the high-precision characteristics of the multi-slope integrator optimize the conversion quality, solving the problem of the traditional ADC's difficulty in balancing "accuracy and speed." Ultimately, it achieves high-speed, high-precision conversion of analog signals to digital signals, meeting the usage requirements of high-precision measurement scenarios.

[0022] In one embodiment of this application, the successive approximation analog-to-digital converter includes: a sample-and-hold circuit, a segmented capacitor DAC array, a comparator, and a successive approximation register; The sample-and-hold circuit is used to acquire the input analog signal and hold the analog signal. A segmented capacitor DAC array is used to generate the first reference voltage under the control of the successive approximation register; The comparator is used to compare the analog signal output by the sample-and-hold circuit with the first reference voltage generated by the segmented capacitor DAC array, and outputs the comparison result; The successive approximation register is used to control the segmented capacitor DAC array to adjust the first reference voltage based on the comparison result of the comparator, and to generate the first digital code and residual voltage through the successive approximation algorithm.

[0023] In this embodiment, the sample-and-hold circuit can adopt a fully differential structure design with a bandwidth of 1MHz, a sampling time ≤5μs, and a holding voltage fluctuation <0.1mV. The fully differential structure can effectively suppress common-mode noise, the 1MHz bandwidth ensures the ability to acquire mid-to-high frequency analog signals, the ≤5μs sampling time meets the system's 100kS / s conversion rate requirement, and the holding voltage fluctuation <0.1mV characteristic ensures the stability of the signal during subsequent quantization, avoiding additional errors introduced by signal fluctuations.

[0024] like Figure 3 As shown, the segmented capacitor DAC array can employ a combination of high-order 8-bit binary weighted capacitors (128C~1C) and low-order 8-bit unit capacitors (1C×8), while also incorporating a 0.5C redundant correction capacitor, supporting a configuration where 8 columns share one DAC. Under the control of the successive approximation register, the capacitor connection state is adjusted via the V_ref / GND switching control terminal to generate first reference voltages of different amplitudes. The accuracy of the reference voltage directly affects the accuracy of the comparison results.

[0025] The comparator employs an optimized Strong-arm structure with a built-in dynamic pre-amplifier module, exhibiting an offset voltage of <1mV, a bandwidth of 1MHz, and a latch time of <2ns. The optimized Strong-arm structure improves the comparator's response speed, the dynamic pre-amplifier module enhances the signal driving capability, the <1mV offset voltage reduces inherent errors during comparison, and the <2ns latch time ensures rapid output of the comparison result, adapting to the bit-by-bit judgment rhythm of the successive approximation algorithm.

[0026] The successive approximation register is based on finite state machine logic design, and its core function is to implement the control logic of the successive approximation algorithm. It receives the high-low level comparison result from the comparator output and, in order from the most significant bit to the least significant bit, sequentially controls the segmented capacitor DAC array to adjust the first reference voltage. After each adjustment, it receives the feedback result from the comparator to determine the code value of the current bit, until the generation of the 8-bit code value is completed. Finally, it outputs the 8-bit first digital code and calculates the difference between the input analog signal and the first reference voltage, i.e., the residual voltage.

[0027] In this embodiment, the sample-and-hold circuit, under the control of a control signal, acquires the input 0~10V analog signal for ≤5μs. After acquisition, it enters the holding phase to stably hold the acquired analog signal, avoiding signal attenuation or distortion. After the successive approximation register is initialized, the segmented capacitor DAC array is controlled to generate an initial first reference voltage (usually half of the full scale). The comparator compares the analog signal output from the sample-and-hold circuit with the first reference voltage. If the analog signal is greater than the first reference voltage, it outputs a high level; otherwise, it outputs a low level. The successive approximation register determines the highest bit value based on the comparison result, and then controls the segmented capacitor DAC array to adjust the first reference voltage, proceeding to the next bit value judgment. The above comparison and adjustment process is repeated until the generation of the 8-bit first digital code is completed. At the same time, the difference between the analog signal and the final first reference voltage is calculated to obtain the residual voltage and output it.

[0028] As can be seen from the above, the fully differential structure and low-ripple hold characteristics of the sample-and-hold circuit in this embodiment ensure the fidelity of the signal before quantization and reduce errors in the signal acquisition stage; the combined structure of the segmented capacitor DAC array and the multi-column shared design reduce hardware area and cost while ensuring the accuracy of reference voltage generation; the optimized strong-arm comparator improves comparison speed and accuracy; the finite state machine logic of the successive approximation register ensures the efficient execution of the successive approximation algorithm. The coarse quantization process of the entire successive approximation analog-to-digital converter only takes 4μs, achieving a high conversion rate of 100kS / s, and the residual voltage is controlled within 1mV, providing a good foundation for the subsequent fine quantization of the multi-slope integrator, effectively improving the coarse quantization accuracy and working efficiency of the entire system.

[0029] In one embodiment of this application, the multi-slope integrator includes: an input buffer, an operational amplifier, an integrating capacitor network, and an output comparator; The input terminal of the input buffer receives the residual voltage; The input terminal of the operational amplifier is connected to the output terminal of the input buffer to amplify the residual voltage and obtain the amplified signal. An integrating capacitor network is connected between the input and output terminals of an operational amplifier to integrate the amplified signal and generate an integrated signal at the output terminal of the operational amplifier. The input of the output comparator is connected to the output of the operational amplifier to compare the integrated signal with the second reference voltage and output a time signal.

[0030] In this embodiment, the input buffer adopts a complementary symmetric transistor structure design with an input impedance ≥1MΩ, an output impedance ≤100Ω, and a bandwidth of 100kHz. The high input impedance avoids the load effect on the residual voltage signal, preventing signal attenuation; the low output impedance enhances the driving capability of subsequent operational amplifiers; and the 100kHz bandwidth matches the signal frequency of the residual voltage, ensuring distortion-free signal transmission. Its input terminal directly receives the residual voltage output from the successive approximation analog-to-digital converter, providing a stable input signal for the multi-slope integrator.

[0031] The operational amplifier employs a fully differential architecture with an open-loop gain >100dB, a bandwidth of 100kHz, and a slew rate ≥1V / μs. The fully differential architecture effectively suppresses common-mode noise and enhances anti-interference capabilities; the high open-loop gain ensures the accuracy of signal amplification and reduces errors during the amplification process; the 100kHz bandwidth and ≥1V / μs slew rate meet the dynamic requirements of residual voltage amplification.

[0032] The integrating capacitor network can be composed of two 1pF high-precision ceramic capacitors connected in parallel. The ceramic capacitors have a dielectric loss ≤0.01% and a temperature coefficient ≤±5ppm / ℃. The parallel design of the two capacitors improves the capacitance stability of the network, while the low dielectric loss and low temperature coefficient of the high-precision ceramic capacitors ensure the linearity of the integration process. This network is directly connected between the inverting input and output of the operational amplifier, forming a negative feedback loop to achieve the integration of the amplified residual voltage.

[0033] The output comparator can employ a high-speed comparator structure. Its fast response time ensures real-time capture of the integral signal, low offset voltage improves comparison accuracy, and a wide power supply voltage range enhances environmental adaptability. The second reference voltage is a standard ramp signal generated by an adaptive ramp generator. Its output is directly connected to the input of the time-to-digital converter. The output timing signal is a digital timing signal that switches between high and low levels. The width of the timing signal is positively correlated with the amplitude of the residual voltage. The second reference voltage can be set empirically.

[0034] like Figure 4 As shown, in this embodiment, the input buffer receives the residual voltage output from the successive approximation analog-to-digital converter, amplifies it through buffering, and then transmits it to the input of the operational amplifier. The operational amplifier amplifies the residual voltage with high gain, and the amplified signal enters the integrating capacitor network. Under the negative feedback of the operational amplifier, the integrating capacitor network performs positive integration on the amplified signal, with the integration time being an integer part of the power frequency period (50 / 60Hz). Then, it performs reverse integration, forming a "positive integration-reverse integration" cycle, generating a continuously changing integrated signal at the output of the operational amplifier. The output comparator compares the integrated signal with the second reference voltage (standard ramp signal) in real time. When the integrated signal reaches the threshold of the second reference voltage, the output level of the output comparator flips. The time from the start of integration to the level flip is the time signal corresponding to the residual voltage, and this time signal is transmitted to the time-to-digital converter.

[0035] As can be seen from the above, the high input impedance and low output impedance design of the input buffer in this embodiment ensures the distortion-free transmission of the residual voltage signal, providing an accurate original signal for subsequent integration operations; the fully differential architecture and high open-loop gain characteristics of the operational amplifier improve the accuracy of signal amplification and anti-interference capability; the integration capacitor network uses high-precision ceramic capacitors, combined with the power frequency synchronous integration time design, which effectively suppresses power frequency noise; the fast response and low offset voltage characteristics of the output comparator ensure the accurate generation of the time signal, ultimately reducing the conversion error from residual voltage to time signal, significantly improving the fine quantization accuracy, and providing a guarantee for the 16-bit high-precision output of the entire system.

[0036] In one embodiment of this application, the multi-slope integrator further includes: a chopper control circuit, an offset calibration circuit, and a common-mode feedback circuit; The chopper control circuit is connected to the integrating capacitor network and is used to control the chopper stability of the integrating capacitor network. The offset calibration circuit is connected to the integrating capacitor network and is used to calibrate the offset voltage of the operational amplifier by adjusting the operating parameters of the integrating capacitor network. The common-mode feedback circuit is connected to the operational amplifier and is used to stabilize the common-mode operating point of the operational amplifier.

[0037] In this embodiment, the chopper control circuit is a hardware circuit, consisting of an analog switch array and a clock generator. The analog switch array is connected to both ends of the integrating capacitor network. The 200kHz clock signal generated by the clock generator controls the periodic switching of the analog switch array, realizing the polarity switching of the input and output signals, thereby modulating the DC offset voltage of the operational amplifier to a high frequency band of 200kHz, which is convenient for subsequent filtering by the low-pass characteristics of the integrating capacitor network.

[0038] The offset calibration circuit is an automatic calibration circuit, which can be composed of a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), and a calibration logic module.

[0039] The common-mode feedback circuit (CMFB) employs a resistor-divided sampling + operational amplifier feedback structure. The sampling resistor is a high-precision metal film resistor with a resistance error ≤ ±0.1%, and the feedback operational amplifier is a low-noise operational amplifier with an input offset voltage <0.1mV. The sampling resistor is connected between the two differential outputs of the operational amplifier to sample the common-mode voltage. After the sampled signal is amplified by the feedback operational amplifier, a feedback control signal is output to the common-mode control terminal of the operational amplifier to adjust the tail current source current, thereby stabilizing the common-mode operating point of the operational amplifier.

[0040] like Figure 4As shown, in this embodiment, the chopper control circuit, driven by a 200kHz clock signal, indirectly switches the polarity of the operational amplifier's input and output signals by periodically switching the analog switch array across the integrating capacitor network. This modulates the operational amplifier's DC offset voltage from the DC band to the 200kHz high-frequency band. Due to the low-pass filtering characteristics of the integrating capacitor network, the offset voltage component in the high-frequency band is filtered out, thereby suppressing the influence of the offset voltage on the integrated signal. The offset calibration circuit collects the operational amplifier's output offset voltage in real time, calculates the calibration compensation value through the calibration logic module, controls the digital-to-analog converter to output the corresponding calibration voltage, and adjusts the operating parameters of the integrating capacitor network (such as the equivalent capacitance value) to indirectly offset the operational amplifier's inherent offset voltage, achieving automatic calibration of the offset voltage. The common-mode feedback circuit collects the operational amplifier's differential output common-mode voltage in real time through a sampling resistor, compares it with the preset target common-mode voltage, and generates a feedback control signal to adjust the operational amplifier's tail current source, stabilizing the common-mode operating point near the target value and avoiding distortion of the integrated signal caused by common-mode voltage fluctuations.

[0041] As can be seen from the above, the chopper control circuit and the integrating capacitor network in this embodiment work together to effectively suppress the DC offset voltage of the operational amplifier, reducing the impact of the offset voltage on the conversion accuracy by an order of magnitude; the offset calibration circuit reduces inherent errors through the automatic calibration mechanism of adjusting the parameters of the integrating capacitor network; and the common-mode feedback circuit ensures the stability of the common-mode operating point of the operational amplifier and improves the anti-interference capability of the multi-slope integrator.

[0042] In one embodiment of this application, it further includes: an adaptive ramp generator; An adaptive ramp generator is used to generate a calibration signal; The output terminals of the adaptive ramp generator include a first calibration output terminal, a second calibration output terminal, and a third calibration output terminal; The first calibration output is connected to the segmented capacitor DAC array and is used to provide a calibration signal to the segmented capacitor DAC array to calibrate its capacitor mismatch error. The second calibration output is connected to the comparator and is used to provide a calibration signal to the comparator to calibrate its offset voltage. The third calibration output is connected to the multi-slope integrator to provide a calibration signal to the multi-slope integrator for calibrating its gain and offset errors.

[0043] In this embodiment, the adaptive ramp generator can adopt a hybrid architecture design of resistive + current-mode DAC. It integrates a calibration control module, which is based on finite state machine logic design. It can control the timing, step size and calibration cycle of the calibration signal generation. The calibration cycle is set to once every 100 conversion cycles, and the time taken for a single calibration is ≤1.143ms. The calibration is completed by utilizing the idle time of the ADC when it is not working, without affecting the normal conversion process.

[0044] The calibration signal is a standard ramp signal with a linearity ≥0.01%. The signal step size can be adjusted via the calibration control module, with a coarse adjustment step size of 0.05V and a fine adjustment accuracy of 8 bits, which can meet the calibration accuracy requirements of different components. This signal simultaneously generates three identical signals, which are output through the first, second, and third calibration output terminals respectively. The output terminals adopt a metal pin design and are soldered to the corresponding calibration object pins via wires to ensure signal transmission stability.

[0045] The first calibration output is connected to the calibration control pin of the segmented capacitor DAC array, and the calibration signal is input through the self-calibration logic interface of the DAC array; the second calibration output is connected to the offset calibration pin of the comparator, directly providing a calibration reference signal to the comparator; the third calibration output is connected to the input buffer of the multi-slope integrator, serving as a standard signal input to the multi-slope integrator for gain and offset calibration.

[0046] like Figure 6 As shown, in this embodiment, the adaptive ramp generator initiates the calibration process during the idle time when the ADC is not in operation: First, a fixed-step coarse adjustment is performed through a resistive DAC to generate a ramp signal with a step size of 0.05V, so that the upper limit of the ramp falls within the target value of ±0.5V; then, a successive approximation fine adjustment is performed through a current-type DAC to search for the midpoint of the ramp until the linearity of the ramp signal is ≤±0.01%; after the calibration signal is generated, the three identical calibration signals are transmitted to the segmented capacitor DAC array, comparator, and multi-ramp integrator through their respective output terminals. After receiving the calibration signal, the segmented capacitor DAC array adjusts the capacitor weight coefficient through self-calibration logic to compensate for capacitor mismatch error; the comparator adjusts the internal bias voltage based on the calibration signal to cancel the offset voltage; the multi-ramp integrator uses the calibration signal as the standard input signal and adjusts the gain and offset of the operational amplifier through internal calibration logic to compensate for gain offset error. The entire calibration process is repeated every 100 conversion cycles to continuously compensate for the error caused by PVT changes.

[0047] As can be seen from the above, the adaptive ramp generator in this embodiment generates a calibration signal, which provides calibration for the segmented capacitor DAC array, comparator and multi-slope integrator through three output terminals, respectively. It specifically compensates for capacitor mismatch, offset voltage and gain and offset errors, reduces the impact of non-ideal characteristics of components, and ultimately significantly improves the accuracy and working stability of the analog-to-digital conversion system, making it suitable for high-precision measurement scenarios.

[0048] An improved SAR analog-to-digital conversion system corresponding to the above embodiment, Figure 7 This is a structural block diagram of an improved SAR analog-to-digital conversion method according to an embodiment of this application. For ease of explanation, only the parts relevant to the embodiment of this application are shown. References Figure 7 , Figure 7 This application provides a flowchart illustrating an improved SAR analog-to-digital conversion method according to an embodiment of the present application. The method may include: S101: The analog signal is converted based on the successive approximation analog-to-digital converter to obtain the first digital code and residual voltage.

[0049] S102: The residual voltage is converted based on the multi-slope integrator to obtain the time signal corresponding to the residual voltage.

[0050] S103: Counts the time signal based on the time-to-digital converter to obtain the second digital code.

[0051] S104: The first digital code and the second digital code are concatenated by a digital signal processor to obtain a digital signal corresponding to the analog signal.

[0052] In one embodiment of this application, the multi-slope integrator includes: an input buffer, an operational amplifier, an integrating capacitor network, and an output comparator; The residual voltage is converted using a multi-slope integrator to obtain the corresponding time-varying signal, including: The residual voltage is received through the input buffer and then transmitted to the operational amplifier. Operational amplifiers are used to amplify residual voltages to obtain amplified signals; The amplified signal is integrated by integrating the signal through an integrating capacitor network to generate an integrated signal. The integrated signal is compared with the second reference voltage by the output comparator to obtain the time signal.

[0053] In one embodiment of this application, the multi-slope integrator further includes: a chopper control circuit, an offset calibration circuit, and a common-mode feedback circuit; An improved SAR analog-to-digital conversion method also includes: The operational amplifier is controlled by a chopper control circuit to stabilize the chopper of the operational amplifier. The offset voltage of the operational amplifier is calibrated based on the offset calibration circuit; The common-mode operating point of the operational amplifier is stabilized based on the common-mode feedback circuit.

[0054] See Figure 8 , Figure 8 This is a schematic block diagram of an electronic device provided according to an embodiment of this application. Figure 8 The electronic device 300 in this embodiment may include one or more processors 301, one or more input devices 302, one or more output devices 303, and one or more memories 304. The processors 301, input devices 302, output devices 303, and memories 304 communicate with each other via a communication bus 305. The memories 304 store computer programs, including program instructions. The processors 301 execute the program instructions stored in the memories 304. Specifically, the processors 301 are configured to invoke the program instructions to perform the functions of the modules in the aforementioned system embodiments, for example... Figure 1 The functions of the successive approximation analog-to-digital converter 21, the multi-slope integrator 22, the time-to-digital converter 23, and the digital signal processor 24 are shown.

[0055] It should be understood that, in the embodiments of this application, the processor 301 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0056] Input device 302 may include a touchpad, a fingerprint sensor (for collecting the user's fingerprint information and fingerprint orientation information), a microphone, etc., and output device 303 may include a display (LCD, etc.), a speaker, etc.

[0057] The memory 304 may include read-only memory and random access memory, and provides instructions and data to the processor 301. A portion of the memory 304 may also include non-volatile random access memory. For example, the memory 304 may also store device type information.

[0058] In specific implementations, the processor 301, input device 302, and output device 303 described in the embodiments of this application can execute the implementation method described in the improved SAR analog-to-digital conversion method provided in the embodiments of this application, or they can execute the implementation method of the electronic device described in the embodiments of this application, which will not be repeated here.

[0059] In another embodiment of this application, a computer-readable storage medium is provided. This computer-readable storage medium stores a computer program, which includes program instructions. When executed by a processor, the program instructions implement all or part of the processes in the methods described above. Alternatively, the computer program can instruct related hardware to implement these processes. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include any entity or system capable of carrying computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.

[0060] The computer-readable storage medium can be an internal storage unit of the electronic device in any of the foregoing embodiments, such as a hard disk or memory of the electronic device. The computer-readable storage medium can also be an external storage device of the electronic device, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the electronic device. Furthermore, the computer-readable storage medium can include both internal and external storage units of the electronic device. The computer-readable storage medium is used to store computer programs and other programs and data required by the electronic device. The computer-readable storage medium can also be used to temporarily store data that has been output or will be output.

[0061] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0062] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the electronic devices and units described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0063] In the several embodiments provided in this application, it should be understood that the disclosed electronic devices and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connections shown or discussed may be indirect coupling or communication connections through some interfaces or units, or they may be electrical, mechanical, or other forms of connection.

[0064] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of this application, depending on actual needs.

[0065] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0066] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An improved SAR analog-to-digital conversion system, characterized in that, include: Successive approximation analog-to-digital converters, multi-slope integrators, time-to-digital converters, and digital signal processors; The successive approximation analog-to-digital converter is used to convert the input analog signal to obtain a first digital code and a residual voltage. The multi-slope integrator is used to convert the residual voltage to obtain the time signal corresponding to the residual voltage; The time-to-digital converter is used to count the time signal to obtain a second digital code; The digital signal processor is used to concatenate the first digital code and the second digital code to obtain a digital signal corresponding to the analog signal.

2. The improved SAR analog-to-digital conversion system as described in claim 1, characterized in that, The successive approximation analog-to-digital converter includes: a sample-and-hold circuit, a segmented capacitor DAC array, a comparator, and a successive approximation register; The sample-and-hold circuit is used to acquire the input analog signal and hold the analog signal. The segmented capacitor DAC array is used to generate a first reference voltage under the control of the successive approximation register; The comparator is used to compare the analog signal output by the sample-and-hold circuit with the first reference voltage generated by the segmented capacitor DAC array, and output the comparison result. The successive approximation register is used to control the segmented capacitor DAC array to adjust the first reference voltage according to the comparison result of the comparator, and to generate the first digital code and the residual voltage through the successive approximation algorithm.

3. An improved SAR analog-to-digital conversion system as described in claim 1, characterized in that, The multi-slope integrator includes: an input buffer, an operational amplifier, an integrating capacitor network, and an output comparator; The input terminal of the input buffer receives the residual voltage; The input terminal of the operational amplifier is connected to the output terminal of the input buffer to amplify the residual voltage and obtain an amplified signal. The integrating capacitor network is connected between the input and output terminals of the operational amplifier and is used to integrate the amplified signal to generate an integrated signal at the output terminal of the operational amplifier. The input terminal of the output comparator is connected to the output terminal of the operational amplifier, and is used to compare the integral signal with the second reference voltage and output the time signal.

4. An improved SAR analog-to-digital conversion system as described in claim 3, characterized in that, The multi-slope integrator also includes: a chopper control circuit, an offset calibration circuit, and a common-mode feedback circuit; The chopper control circuit is connected to the integrating capacitor network and is used to control the chopper stability of the integrating capacitor network. The offset calibration circuit is connected to the integrating capacitor network and is used to calibrate the offset voltage of the operational amplifier by adjusting the operating parameters of the integrating capacitor network. The common-mode feedback circuit is connected to the operational amplifier and is used to stabilize the common-mode operating point of the operational amplifier.

5. An improved SAR analog-to-digital conversion system as described in claim 2, characterized in that, Also includes: Adaptive ramp generator; The adaptive ramp generator is used to generate a calibration signal; The output terminals of the adaptive ramp generator include a first calibration output terminal, a second calibration output terminal, and a third calibration output terminal; The first calibration output terminal is connected to the segmented capacitor DAC array and is used to provide the calibration signal to the segmented capacitor DAC array to calibrate its capacitor mismatch error; The second calibration output is connected to the comparator and is used to provide the comparator with the calibration signal to calibrate its offset voltage; The third calibration output terminal is connected to the multi-slope integrator and is used to provide the calibration signal to the multi-slope integrator to calibrate its gain and offset error.

6. An improved SAR analog-to-digital conversion method, characterized in that, include: The analog signal is converted using a successive approximation analog-to-digital converter to obtain the first digital code and the residual voltage; The residual voltage is converted using a multi-slope integrator to obtain the time signal corresponding to the residual voltage; The time signal is counted using a time-to-digital converter to obtain a second digital code; The first digital code and the second digital code are concatenated by a digital signal processor to obtain a digital signal corresponding to the analog signal.

7. An improved SAR analog-to-digital conversion method as described in claim 6, characterized in that, The multi-slope integrator includes: an input buffer, an operational amplifier, an integrating capacitor network, and an output comparator; The process of converting the residual voltage using a multi-slope integrator to obtain the time signal corresponding to the residual voltage includes: The residual voltage is received through the input buffer and transmitted to the operational amplifier; The operational amplifier is used to amplify the residual voltage to obtain an amplified signal; The amplified signal is integrated through the integrating capacitor network to generate an integrated signal. The integrated signal is compared with the second reference voltage by the output comparator to obtain the time signal.

8. An improved SAR analog-to-digital conversion method as described in claim 7, characterized in that, The multi-slope integrator also includes: a chopper control circuit, an offset calibration circuit, and a common-mode feedback circuit; Also includes: The operational amplifier is controlled based on the chopper control circuit to stabilize the chopper of the operational amplifier. The offset voltage of the operational amplifier is calibrated based on the offset calibration circuit. The common-mode operating point of the operational amplifier is stabilized based on the common-mode feedback circuit.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 6 to 8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 6 to 8.

Images