Multi-bit quantization discrete sigma-delta modulator and method based on capacitive multiplexing

Abstract

The application discloses a multi-bit quantization discrete sigma-delta modulator and method based on capacitor multiplexing, and belongs to the field of analog-to-digital conversion in analog integrated circuits. The multi-bit quantization discrete sigma-delta modulator based on capacitor multiplexing comprises an integrator module, a P-terminal comparator module, an N-terminal comparator module, a SAR logic module, a P-terminal capacitor array module, an N-terminal capacitor array module, a P-terminal switch array module and an N-terminal switch array module. The application forms a full-differential quantizer by connecting two single-ended successive approximation ADCs in parallel, multiplexes the capacitive DAC of the single-ended successive approximation ADC, realizes the quantization function and the feedback function in the sigma-delta modulator, and improves the modulation precision of the modulator. The application can reduce the number of capacitors required by the multi-bit quantization discrete sigma-delta modulator, thereby reducing the power consumption of the switched capacitor network and the layout area of the modulator.

Description

Technical Field

[0001] This invention belongs to the field of analog-to-digital conversion in analog integrated circuits, and relates to a multi-bit quantization Sigma-Delta modulator and modulation method based on capacitor reuse principle. Background Technology

[0002] With the rapid development of science and technology, digital signal processing technology has become increasingly mature. The accuracy of analog-to-digital converters (ADCs) has become a bottleneck in signal processing. Sigma-Delta ADCs are an ADC structure that is gaining increasing importance in high-precision applications. The Sigma-Delta modulator in the internal analog circuitry is the core of the entire Sigma-Delta ADC, largely determining its accuracy, power consumption, and other performance characteristics. For multi-bit quantization Sigma-Delta modulators, the accuracy of the ADC can be significantly improved by reducing the quantization noise of the quantizer. Common multi-bit quantizers use SAR ADCs; however, SAR ADCs require four sets of capacitor arrays and frequently switch the charging state of the capacitors according to the principle of bit-by-bit approximation, resulting in high power consumption and the large capacitor array occupying a large portion of the SAR ADC's area. A traditional first-order multi-bit quantization Sigma-Delta modulator block diagram is shown below. Figure 1 As shown.

[0003] Therefore, there is an urgent need to invent a multi-bit quantization Sigma-Delta modulator and modulation method to reduce its power consumption and area. Summary of the Invention

[0004] To address the shortcomings of existing multi-bit quantization Sigma-Delta modulators, this invention aims to provide a multi-bit quantization discrete Sigma-Delta modulator and method based on capacitor reuse. This is achieved by connecting two single-ended successive approximation ADCs in parallel to form a fully differential quantizer, and reusing the capacitor-based DAC of the single-ended successive approximation ADCs to realize the quantization and feedback functions of the Sigma-Delta modulator, thereby improving the modulation accuracy. This invention reduces the number of capacitors required for the multi-bit quantization discrete Sigma-Delta modulator, using only two sets of capacitor arrays, thus reducing the power consumption of the switched capacitor network and the layout area of ​​the modulator.

[0005] The objective of this invention is achieved through the following technical solution: The present invention discloses a multi-bit quantization discrete Sigma-Delta modulator based on capacitor multiplexing, comprising an integrator module, a P-terminal comparator module, an N-terminal comparator module, a SAR logic module, a P-terminal capacitor array module, an N-terminal capacitor array module, a P-terminal switch array module, and an N-terminal switch array module.

[0006] The integrator module includes an integrator P terminal and an integrator N terminal. The integrator P terminal includes the input terminal VIP, switches SW1, SW3, SW5, and SW7, and a sampling capacitor. Integrating capacitor The output terminal is VOP; the integrator's N-terminal includes the input terminal VIN, and switches SW2, SW4, SW6, SW8, and the sampling capacitor. Integrating capacitor And the output VOP.

[0007] The P-terminal comparator module includes a positive input terminal, a negative input terminal, and an output terminal.

[0008] The N-terminal comparator module includes a positive input, a negative input, and an output.

[0009] The SAR logic module is a SAR logic control module, consisting of a P input terminal, an N input terminal, a P output terminal, and an N output terminal. The SAR logic module determines the switch corresponding to the capacitor that needs to be turned on or off at the current moment based on the output signals of the P-terminal comparator module and the N-terminal comparator module, and outputs a signal to control the P-terminal capacitor array and the N-terminal capacitor array module to open or close the switch corresponding to the capacitor at that position.

[0010] The P-terminal capacitor array consists of N DAC capacitors. composition.

[0011] Furthermore, the first capacitor in the P-terminal capacitor array has a capacitance of 1C, the second capacitor has a capacitance of 2C, and the third capacitor has a capacitance of... C, the Nth position is C, where C is the capacitance value of a unit capacitor. The upper plates of N capacitors are connected together to form the upper plate of the capacitor array of the P-terminal circuit, and the lower plates of the N capacitors are independent of each other.

[0012] The N-terminal capacitor array consists of N DAC capacitors. composition.

[0013] Furthermore, the first capacitor in the N-terminal capacitor array has a capacitance of 1C, the second capacitor has a capacitance of 2C, and the third capacitor has a capacitance of... C, the Nth position is C, where C is the capacitance value of a unit capacitor. The upper plates of N capacitors are connected together to form the upper plate of an N-terminal circuit capacitor array, and the lower plates of the N capacitors are independent of each other.

[0014] The P-end switch array module includes N switches: SWP1, SWP2, SWP3...SWPN.

[0015] Furthermore, each switch in the P-terminal switch array module consists of a positive reference voltage VREFP port, a negative reference voltage VREFN port, a common-mode voltage VCM port, and an output port. The output ports of the N switches are independent of each other.

[0016] The N-terminal switch array module includes N switches: SWN1, SWN2, SWN3...SWNN.

[0017] Furthermore, each switch in the N-terminal switch array module consists of a positive reference voltage VREFP port, a negative reference voltage VREFN port, a common-mode voltage VCM port, and an output port. The output ports of the N switches are independent of each other.

[0018] A P-terminal capacitor array module, a P-terminal switch array module, and a P-terminal comparator module constitute a P-terminal single-ended SAR ADC, while an N-terminal capacitor array module, an N-terminal switch array module, and an N-terminal comparator module constitute an N-terminal single-ended SAR ADC.

[0019] Furthermore, the P-terminal single-ended SAR ADC and the N-terminal single-ended SAR ADC are differential structures to form a fully differential dual-ended SAR ADC, which is used to convert two differential feedback voltages VtransP and VtransN.

[0020] The input signal is a differential signal, with the positive and negative terminals input from the P and N terminals, respectively.

[0021] The signal at terminal P is connected to the sampling capacitor via switch SW1. The feedback voltage VtransP at the P terminal of the lower electrode is connected to the sampling capacitor via switch SW3. Lower electrode. Sampling capacitor. The upper plate is connected to the common-mode voltage VCM via switch SW5, and the sampling capacitor... The upper plate is connected to the positive input terminal of the fully differential op-amp via switch SW7, and the integrating capacitor... The lower plate is connected to the positive input terminal of the fully differential op-amp, and the integrating capacitor... The upper plate is connected to the negative output terminal of the fully differential op-amp. The negative output terminal of the fully differential op-amp is connected to the positive input terminal of the P-terminal comparator module through SW13. The common-mode voltage VCM is connected to the sampling capacitor through SW11. The lower-level board, sampling capacitor The lower plate is connected to the positive input terminal of the P-type comparator, and the sampling capacitor... The upper plate is connected to the common-mode voltage VCM, and the P-terminal output VOP of the integrator module is connected to the upper plate of the P-terminal capacitor array module.

[0022] Furthermore, the feedback voltage VtransP is connected to the lower plate of the P-terminal capacitor array module via switch SW9 and the negative input terminal of the P-terminal comparator.

[0023] Furthermore, the switch SW9 controls the lower plate of the P-terminal capacitor array module to be connected to the common-mode voltage VCM, which is used to clear the charge in the capacitors of the P-terminal capacitor array module.

[0024] The output of the P-terminal comparator module is connected to the P-terminal input of the SAR logic module. The P-terminal output of the SAR logic module controls the P-terminal switch array module. The negative reference voltage VREFN, the positive reference voltage VREFP, and the common-mode voltage VCM are connected to the capacitors of the P-terminal capacitor array module through the switches SWP1, SWP2, SWP3…SWPN of the P-terminal switch array module. The lower electrode plate.

[0025] The N-terminal signal is connected to the sampling capacitor via switch SW2. The feedback voltage VtransN at the N-terminal of the lower electrode is connected to the sampling capacitor via switch SW4. Lower electrode. Sampling capacitor. The upper plate is connected to the common-mode voltage VCM via switch SW6, and the sampling capacitor... The upper plate is connected to the negative input terminal of the fully differential op-amp via switch SW8, and the integrating capacitor... The lower plate is connected to the negative input terminal of the fully differential op-amp, and the integrating capacitor... The upper plate is connected to the positive output of the fully differential op-amp, and the positive output of the fully differential op-amp is connected to the positive input of the N-terminal comparator module via SW14. The sampling capacitor... The lower plate is connected to the positive input of the N-terminal comparator, and the common-mode voltage VCM is connected to the sampling capacitor via SW12. The lower electrode, sampling capacitor The upper plate is connected to the common-mode voltage VCM, and the N-terminal output VON of the integrator module is connected to the upper plate of the N-terminal capacitor array module.

[0026] Furthermore, the feedback voltage VtransN is connected to the lower plate of the N-terminal capacitor array module via switch SW10 and the negative input terminal of the N-terminal comparator.

[0027] Furthermore, the switch SW10 controls the lower plate of the N-terminal capacitor array module to be connected to the common-mode voltage VCM, which is used to clear the charge in the capacitors of the N-terminal capacitor array module.

[0028] The output of the N-terminal comparator module is connected to the N-input of the SAR logic module. The N-output of the SAR logic module controls the N-terminal switch array module. The negative reference voltage VREFN, the positive reference voltage VREFP, and the common-mode voltage VCM are connected to the capacitors of the N-terminal capacitor array module through the switches SWN1, SWN2, SWN3…SWNN of the N-terminal switch array module. The lower electrode plate.

[0029] The integrator module in the front part of the modulator has two main operating states: sampling state and integration state.

[0030] This invention discloses a discrete Sigma-Delta modulation method based on capacitor multiplexing and multi-bit quantization, used in a discrete Sigma-Delta modulator based on capacitor multiplexing and multi-bit quantization. The discrete Sigma-Delta modulation method based on capacitor multiplexing and multi-bit quantization includes the following steps: Step 1: The integrator module uses the sampling capacitor... The input signals VIP and VIN are acquired.

[0031] In this step, the Sigma-Delta modulator is in sampling mode, with ports P1 and SW5 closed and W3 and SW7 open, and the input signal VIP is acquired. In the middle; with ports N closed (SW2 and SW6) and ports W4 and SW8 open, the input signal VIN is acquired. middle.

[0032] Step 2 is performed simultaneously with step 1: clear the residual charge of the capacitors in the capacitor array, improve the accuracy of the quantizer, quantize the output voltage of the integrator module at the previous moment through two differential single-ended SAR ADCs, and simultaneously convert two feedback voltages VtransP and VtransN.

[0033] SW11 and SW12 are on, SW13 and SW14 are off, SWP1, SWP2, SWP3…SWPN are connected to VCM, and SWN1, SWN2, SWN3…SWNN are connected to VCM. This clears the charge from the P-terminal and N-terminal capacitor array modules. After a time delay, switch SW11 on the P-terminal opens, switch SW13 closes, and the VOP node voltage is sampled onto the capacitor. During this process, when switch SW9 is closed, the capacitor... The upper plate is connected to the common-mode voltage VCM; switch SW12 at the N terminal is open, switch SW14 is closed, and the voltage at node VON is sampled onto the capacitor. In this process, SW10 closes the capacitor. The upper plate is connected to the common-mode voltage VCM; then the SAR logic module turns on the capacitor array switches sequentially from low bit to high bit according to the comparator output. When the SAR logic performs its first quantization, if the P port comparator output is high, the SAR logic module controls switch SWP3 to connect to the positive reference voltage VREFP and switch SWN3 to connect to the negative reference voltage VREFN. Then, for the second quantization, if the P port comparator output is low, the SAR logic module controls switch SWP2 to connect to the negative reference voltage VREFP and switch SWN2 to connect to the positive reference voltage VREFP, until the Nth quantization ends.

[0034] After quantization is completed, the entire sampling process also ends, and we proceed to step three.

[0035] Step 3: Feed back the feedback voltages VtransP and VtransN to the integrator module, and the integrator module performs mathematical operations on the voltages of the input signals VIP and VIN and the feedback voltages VtransP and VtransN. The voltages of nodes VOP and VON at this time are obtained by the law of charge conservation.

[0036] In this step, the Sigma-Delta modulator is in integration mode, switches SW3 and SW7 on the P-side are closed, switches SW1 and SW5 are open, and the sampling capacitor... Part of the charge is transferred to the integral. In this process, switches SW4 and SW8 at the N terminal are closed, while switches SW2 and SW6 are open, and the sampling capacitor... Some of the charge is transferred to the integrating capacitor. In this case, according to charge conservation, the node voltages VOP and VON are: Steps one through three are single modulation cycles of a discrete Sigma-Delta modulator.

[0037] Step 4: Based on the preset modulation requirements, iterate through steps 1 to 3 to achieve discrete Sigma-Delta modulation with multi-bit quantization based on capacitor multiplexing.

[0038] Beneficial effects: 1. The present invention discloses a multi-bit quantization discrete Sigma-Delta modulator and method based on capacitor reuse. By adding a path from the capacitor array to the integrator module, the feedback path of the Sigma-Delta modulator is modified. The capacitor DAC of the single-ended successive approximation ADC is reused to realize the quantization and feedback functions in the Sigma-Delta modulator, thereby reducing the modulator layout area and the power consumption when switching capacitors.

[0039] 2. The multi-bit quantization discrete Sigma-Delta modulator and method based on capacitor reuse disclosed in this invention adopts a structure that adds a switch to connect the common-mode voltage in the feedback path of the Sigma-Delta modulator, so as to clear the residual charge in the capacitor array module in a timely manner, increase the accuracy of the Sigma-Delta modulator in the quantization and feedback process, and thus improve the modulation accuracy of the modulator.

[0040] 3. The multi-bit quantization discrete Sigma-Delta modulator and method based on capacitor multiplexing disclosed in this invention replaces the comparator in the traditional method with a structure of a fully differential SAR ADC composed of two single-ended SAR ADCs. This allows for the simultaneous conversion of two feedback voltages, VtransP and VtransN, which overcomes the deficiency of traditional SAR ADCs that can only obtain feedback voltages by successive approximation using a capacitor array at one end. Furthermore, compared to traditional comparators, this scheme uses a more refined quantizer, resulting in a more refined feedback voltage. This makes the quantization noise approximately white noise, significantly reducing the generation of idle tones and improving the accuracy of the modulator.

[0041] 4. For traditional multi-bit quantized Sigma-Delta modulators, the N-bit quantizer is mainly quantized by a SARADC. The SARADC consists of an N-bit capacitor DAC array and a comparator. For differential SAR ADCs, two DAC arrays and one comparator are required. The DAC arrays have the largest area and power consumption overhead. After the signal is quantized, two more DAC arrays are needed to convert the quantization result into an analog voltage and feed it back to the integrator front end. Therefore, traditional multi-bit quantized Sigma-Delta modulators require four DAC arrays, which increases the modulator's area and power consumption. The multi-bit quantized discrete Sigma-Delta modulator and method disclosed in this invention, based on capacitor multiplexing, uses switches SW9 and SW10 to connect the DAC in the SAR ADC to the modulator feedback port. This allows the analog voltage signal, obtained by the quantizer's successive approximation of the input signal, to be directly fed back to the modulator input, thereby saving two DACs, reducing the modulator layout area, and decreasing power consumption when switching capacitors. Attached Figure Description

[0042] Figure 1 This is a block diagram of a traditional first-order multi-bit quantization Sigma-Delta modulator. Figure 2 A block diagram of a first-order multi-bit quantization Sigma-Delta modulator provided in an embodiment of the present invention; Figure 3 The circuit diagram of the multi-bit quantization discrete Sigma-Delta modulator based on capacitor multiplexing disclosed in this invention is shown below. Figure 4 This is a circuit diagram of a multi-bit quantization discrete Sigma-Delta modulator based on capacitor multiplexing according to Embodiment 1 of the present invention; Among them: 1—Integrator module, 2—P-terminal comparator module, 3—N-terminal comparator module, 4—SAR logic module, 5—P-terminal capacitor array module, 6—N-terminal capacitor array module, 7—P-terminal switch array module, 8—N-terminal switch array module. Detailed Implementation

[0043] To better illustrate the purpose and advantages of the present invention, the invention will be further described below in conjunction with the accompanying drawings and examples.

[0044] Example 1: This embodiment discloses a capacitor-reused multi-dimensional discrete Sigma-Delta modulator that achieves both quantization and feedback functions in a Sigma-Delta modulator by multiplexing the capacitor DAC of a single-ended successive approximation ADC. It can perform the feedback function without an additional feedback DAC. Its block diagram is shown below. Figure 2 As shown, its circuit diagram is as follows: Figure 3 As shown. Taking a capacitor-multiplexed, multi-dimensional discrete Sigma-Delta modulator using a 3-bit quantizer as an example, its circuit diagram is as follows. Figure 4 As shown, its circuit includes an integrator module 1, a P-terminal comparator module 2, an N-terminal comparator module 3, a SAR logic module 4, a P-terminal capacitor array module 5, an N-terminal capacitor array module 6, a P-terminal switch array module 7, and an N-terminal switch array module 8.

[0045] Integrator module 1 includes an integrator P terminal and an integrator N terminal. The integrator P terminal includes the input terminal VIP, switch SW1, switch SW3, switch SW5, switch SW7, and sampling capacitor. Integrating capacitor The output terminal is VOP; the integrator's N-terminal includes the input terminal VIN, and switches SW2, SW4, SW6, SW8, and the sampling capacitor. Integrating capacitor And the output VOP.

[0046] The P-terminal comparator module 2 includes a positive input terminal, a negative input terminal, and an output terminal.

[0047] The N-terminal comparator module 3 includes a positive input terminal, a negative input terminal, and an output terminal.

[0048] SAR logic module 4 is a SAR logic control module, consisting of a P input terminal, an N input terminal, a P output terminal, and an N output terminal. SAR logic module 4 determines the switch corresponding to the capacitor that needs to be turned on or off at the current moment based on the output signals of the P-terminal comparator module and the N-terminal comparator module, and outputs a signal to control the P-terminal capacitor array and the N-terminal capacitor array module to open or close the switch corresponding to the capacitor at that position.

[0049] The P-terminal capacitor array consists of 3 DAC capacitors. composition.

[0050] The first capacitor in the P-terminal capacitor array has a capacitance of 1C, the second has 2C, and the third has... C, where C is the capacitance value of a unit capacitor. The upper plates of N capacitors are connected together to form the upper plate of the capacitor array of the P-terminal circuit, and the lower plates of the N capacitors are independent of each other.

[0051] The N-terminal capacitor array consists of N DAC capacitors. composition.

[0052] The first capacitor in the N-terminal capacitor array has a capacitance of 1C, the second has 2C, and the third has... C, where C is the capacitance value of a unit capacitor. The upper plates of N capacitors are connected together to form the upper plate of an N-terminal circuit capacitor array, and the lower plates of the N capacitors are independent of each other.

[0053] The P-end switch array module 5 includes three switches: SWP1, SWP2, and SWP3.

[0054] Each switch in the P-terminal switch array module 7 consists of a positive reference voltage VREFP port, a negative reference voltage VREFN port, a common mode voltage VCM port, and an output port. The output ports of the three switches are independent of each other.

[0055] The N-terminal switch array module 8 includes three switches: SWN1, SWN2, and SWN3.

[0056] Each switch in the N-terminal switch array module 8 consists of a positive reference voltage VREFP port, a negative reference voltage VREFN port, a common mode voltage VCM port, and an output port. The output ports of the three switches are independent of each other.

[0057] The P-end capacitor array module 5, the P-end switch array module 7, and the P-end comparator module 2 form a P-end single-ended SAR ADC, and the N-end capacitor array module 6, the N-end switch array module 7, and the N-end comparator module 3 form an N-end single-ended SAR ADC.

[0058] The P-terminal single-ended SAR ADC and the N-terminal single-ended SAR ADC are differential structures, forming a fully differential dual-ended SAR ADC, which is used to convert two differential feedback voltages VtransP and VtransN.

[0059] The input signal is a differential signal, with the positive and negative terminals input from the P and N terminals, respectively.

[0060] The signal at terminal P is connected to the sampling capacitor via switch SW1. The feedback voltage VtransP at the P terminal of the lower electrode is connected to the sampling capacitor via switch SW3. Lower electrode. Sampling capacitor. The upper plate is connected to the common-mode voltage VCM via switch SW5, and the sampling capacitor... The upper plate is connected to the positive input terminal of the fully differential op-amp via switch SW7, and the integrating capacitor... The lower plate is connected to the positive input terminal of the fully differential op-amp, and the integrating capacitor... The upper plate is connected to the negative output terminal of the fully differential op-amp. The negative output terminal of the fully differential op-amp is connected to the positive input terminal of the P-terminal comparator module through SW13. The common-mode voltage VCM is connected to the sampling capacitor through SW11. The lower-level board, sampling capacitor The lower plate is connected to the positive input terminal of the P-type comparator, and the sampling capacitor... The upper plate is connected to the common-mode voltage VCM, and the P-terminal output VOP of the integrator module is connected to the upper plate of the P-terminal capacitor array module.

[0061] The feedback voltage VtransP is connected to the lower plate of the P-terminal capacitor array module through switch SW9 and the negative input terminal of the P-terminal comparator.

[0062] The switch SW9 controls the lower plate of the P-terminal capacitor array module to be connected to the common-mode voltage VCM, which is used to clear the charge in the capacitors of the P-terminal capacitor array module.

[0063] The output of comparator module 2 is connected to the P input of the SAR logic module. The P output of SAR logic module 4 controls the P-side switch array module 7. The negative reference voltage VREFN, positive reference voltage VREFP, and common-mode voltage VCM are connected to the capacitors of the P-side capacitor array module 5 through switches SWP1, SWP2, and SWP3 of the P-side switch array module 7. The lower electrode plate.

[0064] The N-terminal signal is connected to the sampling capacitor via switch SW2. The feedback voltage VtransN at the N-terminal of the lower electrode is connected to the sampling capacitor via switch SW4. Lower electrode. Sampling capacitor. The upper plate is connected to the common-mode voltage VCM via switch SW6, and the sampling capacitor... The upper plate is connected to the negative input terminal of the fully differential op-amp via switch SW8, and the integrating capacitor... The lower plate is connected to the negative input terminal of the fully differential op-amp, and the integrating capacitor... The upper plate is connected to the positive output of the fully differential op-amp, and the positive output of the fully differential op-amp is connected to the positive input of the N-terminal comparator module via SW14. The sampling capacitor... The lower plate is connected to the positive input of the N-terminal comparator, and the common-mode voltage VCM is connected to the sampling capacitor via SW12. The lower electrode, sampling capacitor The upper plate is connected to the common-mode voltage VCM, and the N-terminal output VON of the integrator module is connected to the upper plate of the N-terminal capacitor array module.

[0065] The feedback voltage VtransN is connected to the lower plate of the N-terminal capacitor array module via switch SW10 and the negative input terminal of the N-terminal comparator.

[0066] The switch SW10 controls the lower plate of the N-terminal capacitor array module to be connected to the common-mode voltage VCM, which is used to clear the charge in the capacitors of the N-terminal capacitor array module.

[0067] The output of N-terminal comparator module 3 is connected to the N-input of SAR logic module 4. The N-output of SAR logic module 4 controls N-terminal switch array module 8. The negative reference voltage VREFN, positive reference voltage VREFP, and common-mode voltage VCM are connected to the capacitors of N-terminal capacitor array module 6 through switches SWN1, SWN2, and SWN3 of N-terminal switch array module 8. The lower electrode plate.

[0068] The integrator module in the front part of the modulator has two main operating states: sampling state and integration state.

[0069] This embodiment discloses a discrete Sigma-Delta modulation method based on capacitor multiplexing and multi-bit quantization, used in the discrete Sigma-Delta modulator based on capacitor multiplexing and multi-bit quantization. The specific implementation steps of the discrete Sigma-Delta modulation method based on capacitor multiplexing and multi-bit quantization are as follows: Step 1: Integrator module 1 uses the sampling capacitor The input signals VIP and VIN are acquired.

[0070] In this step, the Sigma-Delta modulator is in sampling mode, with ports P1 and SW5 closed and W3 and SW7 open, and the input signal VIP is acquired. In the middle; with ports N closed (SW2 and SW6) and ports W4 and SW8 open, the input signal VIN is acquired. middle.

[0071] Step 2 is performed simultaneously with step 1: clear the residual charge of the capacitors in the capacitor array, improve the accuracy of the quantizer, quantize the output voltage of the integrator module at the previous moment through two differential single-ended SAR ADCs, and simultaneously convert two feedback voltages VtransP and VtransN.

[0072] SW11 and SW12 are on, SW13 and SW14 are off, SWP1, SWP2, and SWP3 are connected to VCM, and SWN1, SWN2, and SWN3 are also connected to VCM. This clears the charge in the P-end capacitor array module 5 and the N-end capacitor array module 6. After a time delay, switch SW11 on the P-end opens, switch SW13 closes, and the VOP node voltage is sampled onto the capacitor. During this process, when switch SW9 is closed, the capacitor... The upper plate is connected to the common-mode voltage VCM; switch SW12 at the N terminal is open, switch SW14 is closed, and the voltage at node VON is sampled onto the capacitor. In this process, SW10 closes the capacitor. The upper plate is connected to the common-mode voltage VCM; then the SAR logic module 4 turns on the capacitor array switches in order from low bit to high bit according to the comparator output.

[0073] During the first quantization of the SAR logic, if the P-side comparator outputs a high level and the N-side comparator outputs a low level, then SAR logic module 4 controls switch SWP3 to connect to the positive reference voltage VREFP and switch SWN3 to connect to the negative reference voltage VREFN. Subsequently, during the second quantization, if the P-side comparator outputs a low level and the N-side comparator outputs a high level, then SAR logic module 4 controls switch SWP2 to connect to the negative reference voltage VREFP and switch SWN2 to connect to the positive reference voltage VREFP. Then, during the third quantization, if the P-side comparator outputs a high level and the N-side comparator outputs a low level, then SAR logic module 4 controls switch SWP3 to connect to the positive reference voltage VREFP and switch SWN3 to connect to the negative reference voltage VREFN. At this point, the three quantizations are complete, and the historical output digital code of the P-side comparator is 1, 0, and 1. The voltage at node VtransP is: Because the N-terminal circuit and the P-terminal circuit are differential, the N-terminal comparator outputs digital codes 0, 1, and 0 sequentially; at this time, the VtransN node voltage is: After quantization is completed, the entire sampling process also ends, and we proceed to step three.

[0074] Step 3: Feed back the feedback voltages VtransP and VtransN to the integrator module, and the integrator module performs mathematical operations on the voltages of the input signals VIP and VIN and the feedback voltages VtransP and VtransN. The voltages of nodes VOP and VON at this time are obtained by the law of charge conservation.

[0075] In this step, the Sigma-Delta modulator is in integration mode, switches SW3 and SW7 on the P-side are closed, switches SW1 and SW5 are open, and the sampling capacitor... Part of the charge is transferred to the integral. In this process, switches SW4 and SW8 at the N terminal are closed, while switches SW2 and SW6 are open, and the sampling capacitor... Some of the charge is transferred to the integrating capacitor. In this case, according to the principle of charge conservation, the voltage at the VOP node is: Substitute the voltage VtransP: VON node voltage: Substitute the voltage VtransN: Step 3 ends. Steps 1 to 3 are single modulation cycles of a discrete Sigma-Delta modulator.

[0076] Step 4: Based on the preset modulation requirements, iterate through steps 1 to 3 to achieve discrete Sigma-Delta modulation with multi-bit quantization based on capacitor multiplexing.

[0077] In summary, the discrete Sigma-Delta modulator based on the principle of capacitor sharing disclosed in this embodiment uses the capacitor DAC of a single-ended successive approximation ADC to realize the quantization and feedback functions in the Sigma-Delta modulator. The feedback function can be completed without an additional feedback DAC, which improves the modulator accuracy while reducing the modulator layout area and power consumption when switching capacitors.

[0078] The above detailed description further illustrates the purpose, technical solution, and beneficial effects of the invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-bit quantization discrete Sigma-Delta modulator based on capacitor multiplexing, characterized in that: It includes an integrator module, a P-terminal comparator module, an N-terminal comparator module, a SAR logic module, a P-terminal capacitor array module, an N-terminal capacitor array module, a P-terminal switch array module, and an N-terminal switch array module. The integrator module includes an integrator P terminal and an integrator N terminal; the integrator P terminal includes the input terminal VIP, switch SW1, switch SW3, switch SW5, switch SW7, and sampling capacitor. Integrating capacitor The output terminal is VOP; the integrator's N-terminal includes the input terminal VIN, and switches SW2, SW4, SW6, SW8, and the sampling capacitor. Integrating capacitor and the output VOP; The P-terminal comparator module includes a positive input terminal, a negative input terminal, and an output terminal; An N-terminal comparator module includes a positive input, a negative input, and an output. The SAR logic module is a SAR logic control module, consisting of a P input terminal, an N input terminal, a P output terminal, and an N output terminal. The SAR logic module determines the switch corresponding to the capacitor that needs to be turned on or off at the current moment based on the output signals of the P-terminal comparator module and the N-terminal comparator module, and outputs a signal to control the P-terminal capacitor array and the N-terminal capacitor array module to open or close the switch corresponding to the capacitor at that position. The P-terminal capacitor array consists of N DAC capacitors. composition; The N-terminal capacitor array consists of N DAC capacitors. composition; The P-end switch array module includes N switches: SWP1, SWP2, SWP3...SWPN. The N-terminal switch array module includes N switches: SWN1, SWN2, SWN3...SWNN. A P-terminal capacitor array module, a P-terminal switch array module, and a P-terminal comparator module constitute a P-terminal single-ended SAR ADC; an N-terminal capacitor array module, an N-terminal switch array module, and an N-terminal comparator module constitute an N-terminal single-ended SAR ADC. The input signal is a differential signal, with the positive and negative terminals input from the P and N terminals, respectively. The signal at terminal P is connected to the sampling capacitor via switch SW1. The feedback voltage VtransP at the P terminal of the lower electrode is connected to the sampling capacitor via switch SW3. Lower electrode; sampling capacitor The upper plate is connected to the common-mode voltage VCM via switch SW5, and the sampling capacitor... The upper plate is connected to the positive input terminal of the fully differential op-amp via switch SW7, and the integrating capacitor... The lower plate is connected to the positive input terminal of the fully differential op-amp, and the integrating capacitor... The upper plate is connected to the negative output terminal of the fully differential op-amp. The negative output terminal of the fully differential op-amp is connected to the positive input terminal of the P-terminal comparator module through SW13. The common-mode voltage VCM is connected to the sampling capacitor through SW11. The lower-level board, sampling capacitor The lower plate is connected to the positive input terminal of the P-type comparator, and the sampling capacitor... The upper plate is connected to the common-mode voltage VCM, and the P-terminal output VOP of the integrator module is connected to the upper plate of the P-terminal capacitor array module. The N-terminal signal is connected to the sampling capacitor via switch SW2. The feedback voltage VtransN at the N-terminal of the lower electrode is connected to the sampling capacitor via switch SW4. Lower electrode; sampling capacitor The upper plate is connected to the common-mode voltage VCM via switch SW6, and the sampling capacitor... The upper plate is connected to the negative input terminal of the fully differential op-amp via switch SW8, and the integrating capacitor... The lower plate is connected to the negative input terminal of the fully differential op-amp, and the integrating capacitor... The upper plate is connected to the positive output of the fully differential op-amp, and the positive output of the fully differential op-amp is connected to the positive input of the N-terminal comparator module via SW14. The sampling capacitor... The lower plate is connected to the positive input of the N-terminal comparator, and the common-mode voltage VCM is connected to the sampling capacitor via SW12. The lower electrode, sampling capacitor The upper plate is connected to the common-mode voltage VCM, and the N-terminal output VON of the integrator module is connected to the upper plate of the N-terminal capacitor array module.

2. The multi-bit quantization discrete Sigma-Delta modulator based on capacitor multiplexing as described in claim 1, characterized in that: The first capacitor in the P-terminal capacitor array has a capacitance of 1C, the second has 2C, and the third has... C, the Nth position is C, where C is the capacitance value of a unit capacitor. The upper plates of N capacitors are connected together to form the upper plate of the capacitor array of the P-terminal circuit, and the lower plates of the N capacitors are independent of each other. The first capacitor in the N-terminal capacitor array has a capacitance of 1C, the second has 2C, and the third has... C, the Nth position is C, where C is the capacitance value of a unit capacitor. The upper plates of N capacitors are connected together to form the upper plate of an N-terminal circuit capacitor array, and the lower plates of the N capacitors are independent of each other.

3. The multi-bit quantization discrete Sigma-Delta modulator based on capacitor multiplexing as described in claim 2, characterized in that: Each switch in the P-terminal switch array module consists of a positive reference voltage VREFP port, a negative reference voltage VREFN port, a common mode voltage VCM port, and an output port. The output ports of the N switches are independent of each other. Each switch in the N-terminal switch array module consists of a positive reference voltage VREFP port, a negative reference voltage VREFN port, a common mode voltage VCM port, and an output port. The output ports of the N switches are independent of each other.

4. The multi-bit quantization discrete Sigma-Delta modulator based on capacitor multiplexing as described in claim 3, characterized in that: The P-terminal single-ended SAR ADC and the N-terminal single-ended SAR ADC are differential structures, forming a fully differential dual-ended SAR ADC, which is used to convert two differential feedback voltages VtransP and VtransN.

5. The multi-bit quantization discrete Sigma-Delta modulator based on capacitor multiplexing as described in claim 4, characterized in that: The feedback voltage VtransP is connected to the lower plate of the P-terminal capacitor array module through switch SW9 and the negative input terminal of the P-terminal comparator. The switch SW9 controls the lower plate of the P-terminal capacitor array module to be connected to the common-mode voltage VCM, which is used to clear the charge in the capacitors of the P-terminal capacitor array module. The output of the P-terminal comparator module is connected to the P-terminal input of the SAR logic module. The P-terminal output of the SAR logic module controls the P-terminal switch array module. The negative reference voltage VREFN, the positive reference voltage VREFP, and the common-mode voltage VCM are connected to the capacitors of the P-terminal capacitor array module through the switches SWP1, SWP2, SWP3…SWPN of the P-terminal switch array module. The lower electrode plate.

6. The multi-bit quantization discrete Sigma-Delta modulator based on capacitor multiplexing as described in claim 5, characterized in that: The feedback voltage VtransN is connected to the lower plate of the N-terminal capacitor array module through switch SW10 and the negative input terminal of the N-terminal comparator. The switch SW10 controls the lower plate of the N-terminal capacitor array module to be connected to the common-mode voltage VCM, which is used to clear the charge in the capacitors of the N-terminal capacitor array module. The output of the N-terminal comparator module is connected to the N-input of the SAR logic module. The N-output of the SAR logic module controls the N-terminal switch array module. The negative reference voltage VREFN, the positive reference voltage VREFP, and the common-mode voltage VCM are connected to the capacitors of the N-terminal capacitor array module through the switches SWN1, SWN2, SWN3…SWNN of the N-terminal switch array module. The lower electrode plate.

7. A discrete Sigma-Delta modulation method based on capacitor multiplexing multi-bit quantization, used in the capacitor multiplexing multi-bit quantization discrete Sigma-Delta modulator as described in claims 1, 2, 3, 4, 5, or 6, characterized in that: Includes the following steps: Step 1: The integrator module uses the sampling capacitor... Collect the input signals VIP and VIN; Step 2 is performed simultaneously with step 1: clear the residual charge of the capacitors in the capacitor array, improve the accuracy of the quantizer, quantize the output voltage of the integrator module at the previous moment through two differential single-ended SAR ADCs, and simultaneously convert two feedback voltages VtransP and VtransN. Step 3: Feed back the feedback voltages VtransP and VtransN to the integrator module, and the integrator module performs mathematical operations on the voltages of the input signals VIP and VIN and the feedback voltages VtransP and VtransN. The voltages of nodes VOP and VON at this time are obtained by the law of charge conservation. Steps one through three are single modulation cycles of a discrete Sigma-Delta modulator; Step 4: Based on the preset modulation requirements, iterate through steps 1 to 3 to achieve discrete Sigma-Delta modulation with multi-bit quantization based on capacitor multiplexing.

8. The discrete Sigma-Delta modulation method based on capacitor multiplexing multi-bit quantization as described in claim 7, characterized in that: The implementation method for step one is as follows: In this step, the Sigma-Delta modulator is in sampling mode, with ports P1 and SW5 closed and W3 and SW7 open, and the input signal VIP is acquired. In the middle; with ports N closed (SW2 and SW6) and ports W4 and SW8 open, the input signal VIN is acquired. middle.

9. The discrete Sigma-Delta modulation method based on capacitor multiplexing multi-bit quantization as described in claim 8, characterized in that: The second step is implemented as follows: SW11 and SW12 are on, SW13 and SW14 are off, SWP1, SWP2, SWP3…SWPN are connected to VCM, and SWN1, SWN2, SWN3…SWNN are connected to VCM. This clears the charge from the P-terminal and N-terminal capacitor array modules. After a time delay, switch SW11 on the P-terminal opens, switch SW13 closes, and the VOP node voltage is sampled onto the capacitor. During this process, when switch SW9 is closed, the capacitor... The upper plate is connected to the common-mode voltage VCM; switch SW12 at the N terminal is open, switch SW14 is closed, and the voltage at node VON is sampled onto the capacitor. In this process, SW10 closes the capacitor. The upper plate is connected to the common-mode voltage VCM; then the SAR logic module turns on the capacitor array switches sequentially from low bit to high bit according to the comparator output. When the SAR logic performs the first quantization, if the P port comparator output is high, the SAR logic module controls switch SWP1 to connect to the positive reference voltage VREFP and control switch SWN1 to connect to the negative reference voltage VREFN. Then, for the second quantization, if the P port comparator output is low, the SAR logic module controls switch SWP2 to connect to the negative reference voltage VREFP and control switch SWN2 to connect to the positive reference voltage VREFP, until the Nth quantization ends. After the quantization ends, the entire sampling state also ends, and the process proceeds to step three.

10. The discrete Sigma-Delta modulation method based on capacitor multiplexing multi-bit quantization as described in claim 9, characterized in that: The method for implementing step three is as follows: In this step, the Sigma-Delta modulator is in integration mode, switches SW3 and SW7 on the P-side are closed, switches SW1 and SW5 are open, and the sampling capacitor... Some of the charge in the integral is transferred to the integral. In this process, switches SW4 and SW8 at the N terminal are closed, while switches SW2 and SW6 are open, and the sampling capacitor... Some of the charge is transferred to the integrating capacitor. In this case, according to charge conservation, the node voltages VOP and VON are: 。

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