Switching drive integrated circuit and switching drive setting method

Abstract

The application provides a switch driving integrated circuit and a switch driving setting method, through enabling the first signal and the second signal at different time, so that the voltage control signal generating module or the current control signal generating module generates different voltage or different current under the action of different signals; the power tube driving current generating module can generate the pull-up driving current and the pull-down driving current of the power tube based on the different voltage or the different current. In the application, the different voltage or the different current is generated based on the external resistance network module, so that the resistance of the external resistance network module can be adjusted to adjust the size of the pull-up driving current and the pull-down driving current of the power tube, compared with the prior art, the application can adjust the pull-up driving current of the power tube and the pull-down driving current of the power tube through one pin, and the number of pins can be reduced.

Description

Technical Field

[0001] This invention relates to the field of switch driver technology, and more specifically to a switch driver integrated circuit and a switch driver setting method. Background Technology

[0002] Power transistors are widely used in various electronic products. A driver circuit drives the power transistor to turn it on or off, thereby outputting corresponding signals to control the electronic product. Because power transistors have parasitic capacitance, the on / off process typically involves charging or discharging this capacitance using a drive current. Therefore, the magnitude of the drive current determines the on / off speed of the power transistor. For example... Figure 1 The diagram shows a power transistor drive setting circuit in the prior art. Figure 1 In the diagram, M1 is the power transistor, and M2 and M3 are the pull-up and pull-down transistors, respectively. M2 and M3 are integrated into the chip, while M1 is located outside the chip. M2 and M3 are connected to the gate drive terminal of M1 through the PIN1 pin. The drive current of M1 is set through resistors R11, R12 and D11 between the PIN1 pin and the gate drive terminal of M1. Figure 1 In this configuration, M1 is located outside the chip IC, resulting in low integration density and requiring more area. Based on this, such as... Figure 2 The diagram shows another power transistor drive configuration circuit in the prior art, which integrates M1, M2, and M3 together in a single IC chip. The IC chip has PIN1 and PIN2 pins. Inside the IC chip, the common terminals of M2 and M3 are connected via PIN1 using wire bonding. PIN1 and PIN2 are connected through a network of resistors R11, R12, and D11. The gate drive terminal of M1 is connected to PIN2. Figure 2 While this method allows M1, M2, and M3 to be integrated into a single IC chip, increasing integration density, it is relatively... Figure 1 The current method requires an additional pin, increasing the number of pins. Furthermore, since two long wires are needed inside the IC chip to connect to pins PIN1 and PIN2 respectively, these long wires can affect the stability of the IC. Therefore, it is necessary to improve upon the shortcomings of the existing technology to enhance the performance of the power transistor driver circuit. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides a switch driver integrated circuit and a switch driver setting method.

[0004] According to a first aspect of the present invention, a switch driver integrated circuit is provided, comprising:

[0005] The power transistor is located inside the integrated circuit.

[0006] One pin PINK is used to connect the integrated circuit to an external resistor network module located outside the integrated circuit. The other end of the external resistor network module is connected to a low potential ground.

[0007] A control signal generation module is disposed inside the integrated circuit, and the control signal generation module is connected to the external resistor network module through the pin PINK.

[0008] A power transistor drive current generation module is disposed inside the integrated circuit and connected to the output terminal of the control signal generation module. The output terminal of the power transistor drive current generation module is connected to the gate drive terminal of the power transistor.

[0009] The control signal generation module is controlled by a first signal and a second signal to obtain a first control signal and a second control signal, wherein the first signal and the second signal are generated by the internal circuit of the integrated circuit.

[0010] Furthermore, the first signal and the second signal are valid at different times.

[0011] Furthermore, the external resistor network module is composed of resistors and diodes;

[0012] The diode has different conduction states when the first signal and the second signal are respectively valid.

[0013] Furthermore, the control signal generation module is a voltage control signal generation module.

[0014] When the first signal is valid, the voltage control signal generation module generates a first control voltage VK1.

[0015] When the second signal is valid, the voltage control signal generation module generates a second control voltage VK2;

[0016] The power transistor drive current generation module generates the pull-up drive current and pull-down drive current of the power transistor based on the first control voltage VK1 and the second control voltage VK2.

[0017] Furthermore, the control signal generation module is a current control signal generation module.

[0018] When the first signal is valid, the current control signal generation module generates a first control current IA;

[0019] When the second signal is valid, the current control signal generation module generates a second control current IB;

[0020] The power transistor drive current generation module generates the pull-up drive current and pull-down drive current of the power transistor based on the first control current IA and the second control current IB.

[0021] Furthermore, the voltage control signal generation module includes a first current source IK1, a second current source IK2, a first switch K1, and a second switch K2;

[0022] The first current source IK1 is connected in series with the first switch K1 between the power supply voltage VDD and the common node;

[0023] The common node is connected to the pin PINK;

[0024] The second current source IK2 and the second switch K2 are connected in series between the common node and the low potential ground; or, the second current source IK2 and the second switch K2 are connected in series between the power supply voltage VDD and the common node.

[0025] Furthermore, when the first signal is valid, the first switch K1 is closed, and the first current source IK1 acts on the external resistor network module to generate the first control voltage VK1 at the common node;

[0026] When the second signal is valid, the second switch K2 is closed, and the second current source IK2 acts on the external resistor network module to generate the second control voltage VK2 at the common node.

[0027] Furthermore, a rectifier module is also provided inside the voltage control signal generation module for rectifying the first control voltage VK1 and the second control voltage VK2;

[0028] The rectifier module rectifies the first control voltage VK1 and outputs a third voltage VK1'.

[0029] The rectifier module rectifies the second control voltage VK2 and outputs a fourth voltage VK2'.

[0030] Furthermore, the current control signal generation module includes a first voltage source V1, a second voltage source V2, a first switch K1, and a second switch K2;

[0031] The first switch K1 is connected between the first voltage source V1 and the common node, and the second switch K2 is connected between the common node and the second voltage source V2;

[0032] When the first signal is valid, the first switch K1 is closed, and the first voltage source V1 acts on the external resistor network module to generate the first control current IA;

[0033] When the second signal is valid, the second switch K2 is closed, and the second voltage source V2 acts on the external resistor network module to generate the second control current IB.

[0034] Furthermore, the power transistor drive current generation module includes an A / D conversion module, M drive upper transistors, N drive lower transistors, and gate drive signal generation modules for the upper and lower transistors;

[0035] The output terminal of the rectifier module is connected to the input terminal of the A / D conversion module;

[0036] The output of the A / D conversion module is connected to the input of the upper / lower MOSFET gate drive signal generation module;

[0037] The output terminal of the upper / lower MOSFET gate drive signal generation module is connected to the gate drive terminal of the upper MOSFET and the gate drive terminal of the lower MOSFET, respectively.

[0038] The M driving upper transistors are connected in parallel, the N driving lower transistors are connected in parallel, and the M driving upper transistors and the N driving lower transistors are connected in series at the gate driving terminal of the power transistor; where M and N are both positive integers greater than 1.

[0039] Furthermore, the A / D conversion module converts the third voltage VK1' into a digital signal with the first digit being A;

[0040] The A / D conversion module converts the fourth voltage VK2' into a digital signal with a second bit value of B; where A and B are both positive integers greater than 1.

[0041] Furthermore, the power transistor drive current generation module includes an A / D conversion module, M drive upper transistors, N drive lower transistors, and gate drive signal generation modules for the upper and lower transistors;

[0042] The first control voltage VK1 and the second control voltage VK2 are connected to the input terminal of the A / D conversion module;

[0043] The output of the A / D conversion module is connected to the input of the upper / lower MOSFET gate drive signal generation module;

[0044] The output terminal of the upper / lower MOSFET gate drive signal generation module is connected to the gate drive terminal of the upper MOSFET and the gate drive terminal of the lower MOSFET, respectively.

[0045] The M driving upper transistors are connected in parallel, the N driving lower transistors are connected in parallel, and the M driving upper transistors and the N driving lower transistors are connected in series at the gate driving terminal of the power transistor; where M and N are both positive integers greater than 1.

[0046] Furthermore, the A / D conversion module converts the first control voltage VK1 into a digital signal with the first digit being A;

[0047] The A / D conversion module converts the second control voltage VK2 into a second digital signal with a bit depth of B; where A and B are both positive integers greater than 1.

[0048] Furthermore, the M driving transistors are divided into A groups, and the gate driving terminals of the driving transistors in each group are connected together.

[0049] The N driving transistors are divided into B groups, and the gate driving terminals of the driving transistors in each group are connected together.

[0050] The upper transistor gate drive signal generation module generates A gate drive signals based on the first digital signal with a bit value of A and the first signal, respectively, to drive the gate drive terminals of the A groups of driving upper transistors.

[0051] The lower transistor gate drive signal generation module generates B gate drive signals based on the second B-bit digital signal and the second signal to drive the gate drive terminals of the B groups of lower transistors.

[0052] or,

[0053] The M driving transistors are divided into B groups, and the gate driving terminals of the driving transistors in each group are connected together.

[0054] The N driving transistors are divided into A groups, and the gate driving terminals of the driving transistors in each group are connected together.

[0055] The upper transistor gate drive signal generation module generates B gate drive signals based on the second B-bit digital signal and the second signal to drive the gate drive terminals of the B groups of upper transistors.

[0056] The lower transistor gate drive signal generation module generates A gate drive signals based on the first digital signal with a bit depth of A and the first signal, respectively, to drive the gate drive terminals of the A groups of lower transistors.

[0057] Furthermore, the A / D conversion module can be configured as one or two.

[0058] Furthermore, the first signal and the second signal are switch trigger signals generated internally by the integrated circuit before the generation of the power transistor gate drive terminal signal after the integrated circuit is powered on.

[0059] Furthermore, the power transistor drive current generation module includes a voltage-to-current conversion module and a current mirror module;

[0060] The output terminal of the rectifier module is connected to the input terminal of the voltage-to-current conversion module. The voltage-to-current conversion module converts the third voltage VK1' into the third current IC and the fourth voltage VK2' into the fourth current ID.

[0061] The input terminal of the current mirror module is connected to the output terminal of the voltage-to-current conversion module, and the output terminal of the current mirror module is connected to the gate drive terminal of the power transistor.

[0062] The third current IC outputs the pull-up drive current of the power transistor after passing through the current mirror module, and the fourth current ID outputs the pull-down drive current of the power transistor after passing through the current mirror module.

[0063] Alternatively, the third current IC outputs the pull-down drive current of the power transistor after passing through the current mirror module, and the fourth current ID outputs the pull-up drive current of the power transistor after passing through the current mirror module.

[0064] Furthermore, the power transistor drive current generation module includes a voltage-to-current conversion module and a current mirror module;

[0065] The first control voltage VK1 or the second control voltage VK2 is connected to the input terminal of the voltage-to-current conversion module. The voltage-to-current conversion module converts the first control voltage VK1 into a third current IC and the second control voltage VK2 into a fourth current ID.

[0066] The input terminal of the current mirror module is connected to the output terminal of the voltage-to-current conversion module, and the output terminal of the current mirror module is connected to the gate drive terminal of the power transistor.

[0067] The third current IC outputs the pull-up drive current of the power transistor after passing through the current mirror module, and the fourth current ID outputs the pull-down drive current of the power transistor after passing through the current mirror module.

[0068] Alternatively, the third current IC outputs the pull-down drive current of the power transistor after passing through the current mirror module, and the fourth current ID outputs the pull-up drive current of the power transistor after passing through the current mirror module.

[0069] Furthermore, a voltage-to-current conversion module is also provided inside the current control signal generation module;

[0070] The common node is connected to the input terminal of the voltage-to-current conversion module, and the voltage-to-current conversion module is connected to the external resistor network module through the pin PINK;

[0071] The voltage-to-current conversion module converts the first voltage source V1 into the first control current IA; the voltage-to-current conversion module converts the second voltage source V2 into the second control current IB.

[0072] Furthermore, the power transistor drive current generation module includes a current mirror module;

[0073] The first control current IA generates the pull-up drive current of the power transistor after passing through the current mirror module, and the second control current IB generates the pull-down drive current of the power transistor after passing through the current mirror module.

[0074] Alternatively, the first control current IA generates the pull-down drive current of the power transistor after passing through the current mirror module, and the second control current IB generates the pull-up drive current of the power transistor after passing through the current mirror module.

[0075] Furthermore, the first signal and the second signal are respectively signals that are the same as or opposite to the potential of the gate drive terminal of the power transistor.

[0076] The present invention also provides a switch drive setting method, characterized in that:

[0077] When the first signal is valid and the second signal is invalid, the voltage control signal generation module generates a first control voltage VK1; when the first signal is invalid and the second signal is valid, the voltage control signal generation module generates a second control voltage VK2; the power transistor drive current generation module generates the pull-up drive current and pull-down drive current of the power transistor based on the first control voltage VK1 and the second control voltage VK2.

[0078] Alternatively, when the first signal is valid and the second signal is invalid, the current control signal generation module generates a first control current IA; when the first signal is invalid and the second signal is valid, the current control signal generation module generates a second control current IB; the power transistor drive current generation module generates the pull-up drive current and pull-down drive current of the power transistor based on the first control current IA and the second control current IB.

[0079] The beneficial effects of the present invention include at least the following:

[0080] The switch-driven integrated circuit and switch-driven setting method provided by this invention can operate after the integrated circuit is powered on but before the power transistor gate drive terminal signal is generated, or can generate the power transistor's pull-up drive current and pull-down drive current in real time during the integrated circuit's operation. By enabling the first signal and the second signal at different times, the voltage control signal generation module or the current control signal generation module generates different voltages or different currents under the action of different signal enable. The power transistor drive current generation module can generate the power transistor's pull-up drive current and pull-down drive current based on the different voltages or different currents. In this invention, the different voltages or different currents are all generated based on the external resistor network module. Therefore, the magnitude of the power transistor's pull-up drive current and pull-down drive current can be adjusted by adjusting the resistance value of the external resistor network module. Compared with the prior art, this invention can adjust the power transistor's pull-up drive current and pull-down drive current through a single pin, which can reduce the number of pins in the integrated circuit and avoid circuit stability problems caused by excessively long wires.

[0081] It should be noted that the above general description and the following detailed description are exemplary and explanatory only, and do not limit the present invention. Attached Figure Description

[0082] Figure 1 A schematic diagram of a power transistor drive setup circuit in the prior art;

[0083] Figure 2 A schematic diagram of another power transistor drive circuit in the prior art;

[0084] Figure 3 A schematic diagram of the switch driver integrated circuit provided by the present invention;

[0085] Figure 4 A schematic diagram of an embodiment of the switch driver integrated circuit provided by the present invention;

[0086] Figure 5 A schematic diagram of an embodiment of the upper / lower transistor gate drive signal generation module provided by the present invention;

[0087] Figure 6 A schematic diagram of another embodiment of the upper / lower transistor gate drive signal generation module provided by the present invention;

[0088] Figure 7 A schematic diagram of another embodiment of the switch driver integrated circuit provided by the present invention;

[0089] Figure 8 A schematic diagram of another embodiment of the switch driver integrated circuit provided by the present invention;

[0090] Figure 9 A schematic diagram of another embodiment of the power transistor pull-up drive current generation module provided by the present invention;

[0091] Figure 10 A schematic diagram of another embodiment of the power transistor pull-down drive current generation module provided by the present invention;

[0092] Figure 11 A schematic diagram of another embodiment of the switch driver integrated circuit provided by the present invention;

[0093] Figure 12 A schematic diagram of another embodiment of the switch driver integrated circuit provided by the present invention;

[0094] Figure 13 A schematic diagram of another embodiment of the power transistor pull-up drive current generation module provided by the present invention;

[0095] Figure 14 A schematic diagram of another embodiment of the power transistor pull-down drive current generation module provided by the present invention;

[0096] Figure 15 A block diagram of an embodiment of the switch drive setting method provided by the present invention;

[0097] Figure 16 A block diagram of another embodiment of the switch drive setting method provided by the present invention; Detailed Implementation

[0098] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0099] like Figure 3The diagram shown is a schematic of a switch-driven integrated circuit provided by the present invention. It includes an integrated circuit 100, a power transistor MQ1, and a power transistor drive current generation module 20. The power transistor MQ1 and the power transistor drive current generation module 20 are disposed inside the integrated circuit 100. The integrated circuit 100 has a pin PINK. An external resistor network module 30 is connected to the integrated circuit 100 through the pin PINK. A control signal generation module 10 is also disposed inside the integrated circuit 100. The control signal generation module 10 is controlled by a first signal and a second signal to output a corresponding voltage or current signal. After outputting the corresponding voltage or current signal, the control signal generation module 10 is connected to the power transistor drive current generation module 20. The output terminal of the power transistor drive current generation module 20 is connected to the gate drive terminal GQ1 of the power transistor MQ1. The first and second signals are generated by the internal circuitry of the integrated circuit, and the first and second signals are valid at different times. That is, under the action of the first signal and the second signal, the control signal generation module 10 acts on the external resistor network module 30 to generate a corresponding voltage or current signal. The voltage or current signal acts on the power transistor drive current generation module 20, and the drive current of the power transistor MQ1 is set by the current output by the power transistor drive current generation module 20.

[0100] Further as Figure 4 The diagram illustrates an embodiment of the switch-driven integrated circuit provided by this invention. The external resistor network module 30 comprises resistors R1 and R2 and diode D1. The two ends of resistor R1 are connected in parallel with the series-connected resistor R2 and diode D1. One end of resistor R1 is connected to pin PINK of the integrated circuit 100, and the other end is connected to low-potential ground. Resistors R1 and R2 can be considered as an equivalent resistor, and the components of R1 and R2 can be configured by those skilled in the art according to actual conditions. In this embodiment, the control signal generation module 10 is a voltage control signal generation module, comprising a first switch K1, a first current source IK1, a second switch K2, and a second current source IK2. The first current source IK1 and the second current source IK2 are generated internally by the integrated circuit 100. The first current source IK1 and the first switch K1 are connected in series between the power supply voltage VDD and the common node N1. The second current source IK2 and the second switch K2 are connected in series between the common node N1 and low-potential ground. The common node N1 is connected to pin PINK. The first switch K1 is controlled by a first signal, which controls the opening or closing of the first switch K1 under the action of the first signal; the second switch K2 is controlled by a second signal, which controls the opening or closing of the second switch K2 under the action of the second signal. Furthermore, the voltage control signal generation module 10 also includes a rectifier module, the input terminal of which is connected to a common node N1. Figure 4The example shows that the voltage control signal generation module 10 is also provided with a rectification module. Whether or not a rectification module is provided, and whether the first control voltage VK1 and the second control voltage VK2 are rectified, can be selected by those skilled in the art according to the actual situation. The output terminal of the voltage control signal generation module 10 is connected to the power transistor drive current generation module 20. The power transistor drive current generation module 20 includes an A / D conversion module, an upper / lower transistor gate drive signal generation module 40, and a drive upper and lower transistor module 50. The output terminal of the A / D conversion module is connected to the upper / lower transistor gate drive signal generation module 40, and the output terminal of the upper / lower transistor gate drive signal generation module 40 is connected to the drive upper and lower transistor module 50, respectively. The drive upper transistor is composed of M upper transistors connected in parallel, and the gate drive terminals of the M drive upper transistors are respectively connected to GS1...GSM; the drive lower transistor is composed of N lower transistors connected in parallel, and the gate drive terminals of the N drive lower transistors are respectively connected to GK1...GKN; the specific number of M or N and the specific type of drive upper and lower transistors can be set by those skilled in the art according to the actual situation. The output terminal of the drive module 50 for the upper and lower transistors is connected to the gate drive terminal GQ1 of the power transistor MQ1.

[0101] The following reference Figure 4 and Figure 5 The working principle of the switch driver integrated circuit provided by the present invention will be explained, wherein... Figure 4 and Figure 5 The illustrated embodiment operates after the integrated circuit 100 is powered on, before the power transistor gate drive signal is generated. The first signal GK and the second signal GK' need to be valid at different times, both generated by the internal circuitry of the integrated circuit 100. When the first signal GK is valid, it acts on the first switch K1, causing the first switch K1 to close. At this time, the second signal GK' is invalid, acting on the second switch K2, causing the second switch K2 to open. The first current source IK1 flows through the external resistor network 30 to generate the first control voltage VK1. The first control voltage VK1 is rectified by the rectifier module to generate the third voltage VK1'. The third voltage VK1' acts on the input terminal of the A / D conversion module, and is converted by the A / D conversion module into a single-digit digital signal Q0……Qi……QA-1. When the second signal GK' is valid, it acts on the second switch K2, causing K2 to close. At this time, the first signal GK is invalid, acting on the first switch K1, causing K1 to open. The second current source IK2 flows through the external resistor network 30 to generate the second control voltage VK2. The second control voltage VK2 is rectified by the rectifier module to generate the fourth voltage VK2'. The fourth voltage VK2' acts on the input terminal of the A / D conversion module, and is converted into a B-bit digital signal Q0……Qi……QB-1 by the A / D conversion module. The specific number of bits A and B converted by the A / D conversion module can be set by those skilled in the art according to the actual situation. Based on the setting of A and B, such as... Figure 4 As shown, the M driving transistors can be divided into A groups, with the gate driving terminals of the driving transistors in each group connected together. The N driving transistors can be divided into B groups, with the gate driving terminals of the driving transistors in each group connected together. The upper transistor gate driving signal generation module 40 determines A gate driving signals based on digital signals Q0…Qi…QA-1 and a first signal GK, respectively, to be connected to the gate driving terminals of the driving transistors in the A groups. The lower transistor gate driving signal generation module 40 determines B gate driving signals based on digital signals Q0…Qi…QB-1 and a second signal GK', respectively, to be connected to the gate driving terminals of the driving transistors in the B groups. A and B can be set to be equal or unequal.

[0102] Specifically, when A and B are set to be equal, only one A / D conversion module can be used, responding to the first signal GK and the second signal GK' to perform analog-to-digital conversion on the third voltage VK1' and the fourth voltage VK2', respectively. When A and B are equal... Figure 5 The schematic diagrams of the i-th group of upper transistor gate drive signal generation module and the i-th group of lower transistor gate drive signal generation module are shown in the example, where 1≤i≤A; Figure 5The above corresponds to the case where the first signal GK is active high and the second signal GK' is active low. Each group of upper transistor gate drive signal generation modules and each group of lower transistor gate drive signal generation modules include an AND gate and an SR flip-flop. For the i-th group of upper transistor gate drive signal generation modules and the i-th group of lower transistor gate drive signal generation modules, one end of the AND gate in these two generation modules is connected to Qi-1. When the first signal GK is valid, the other end of the AND gate in the i-th group upper transistor gate drive signal generation module is connected to the first signal GK. The other end of the AND gate in the i-th group lower transistor gate drive signal generation module is connected to the signal obtained by inverting the level of the first signal GK. The output terminals of the AND gates in the i-th group upper transistor gate drive signal generation module and the i-th group lower transistor gate drive signal generation module are respectively connected to the set terminal S of the SR flip-flop. The two SR flip-flops output the gate drive signal of the i-th group upper transistor and the gate drive signal of the i-th group lower transistor, respectively. When the first signal GK is high, the SR flip-flop in the i-th group upper transistor gate drive signal generation module can latch the level corresponding to Qi-1 to provide the gate drive signal for the i-th group upper transistor. At this time, the i-th group lower transistor gate drive signal generation module always outputs a low level. When the second signal GK' is valid, the other end of the AND gate in the i-th group upper transistor gate drive signal generation module is connected to the second signal GK', and the other end of the AND gate in the i-th group lower transistor gate drive signal generation module is connected to the signal obtained by inverting the level of the second signal GK'. The output terminals of the AND gates in the i-th group upper transistor gate drive signal generation module and the i-th group lower transistor gate drive signal generation module are respectively connected to the set terminal S of the SR flip-flop. The two SR flip-flops output the gate drive signal for the i-th group upper transistor and the gate drive signal for the i-th group lower transistor, respectively. When the second signal GK' is low, the SR flip-flop in the i-th group lower transistor gate drive signal generation module can latch the level corresponding to Qi-1 to provide the gate drive signal for the i-th group lower transistor. At this time, the i-th group upper transistor gate drive signal generation module will maintain the level when the first signal GK is valid to provide the gate drive signal for the i-th group upper transistor. Similarly, the principles of the upper gate drive signal generation module and the lower gate drive signal generation module of the other groups besides the i-th group are the same as those of the upper gate drive signal generation module and the lower gate drive signal generation module of the i-th group.Therefore, the A upper transistor gate drive signal generation module and the A lower transistor gate drive signal generation module can provide signals to the gate drive terminals of the A groups of driving upper transistors and the A groups of driving lower transistors, respectively. The corresponding gate drive terminal signals can control the conduction or cutoff of each group of driving upper transistors or driving lower transistors. Since different numbers of driving upper transistors and driving lower transistors will generate different currents, the output terminals of the driving upper transistors and driving lower transistors act on the gate drive terminal of the power transistor MQ1, thereby realizing the control of the pull-up drive current and pull-down drive current of the power transistor MQ1.

[0103] When A and B are equal Figure 5 The diagram shows the schematic of the i-th group upper transistor gate drive signal generation module and the i-th group lower transistor gate drive signal generation module when the first signal GK is active high and the second signal GK' is active low. As another embodiment of the invention, the first signal GK can also be configured to be active low and the second signal GK' active high, in conjunction with... Figure 5 The difference lies in that, in the AND gate of the i-th group's upper transistor gate drive signal generation module, one end needs to invert the level of either the first signal GK or the second signal GK' before connection, while in the i-th group's lower transistor gate drive signal generation module, one end of the AND gate can be directly connected to either the first signal GK or the second signal GK'. Otherwise, its working principle is similar to [previous method / method]. Figure 4 and Figure 5 The description in the text.

[0104] In another embodiment of the present invention, when A and B are not equal, only one A / D conversion module may be provided. In this case, the conversion bit depth of the A / D conversion module adopts the maximum value of A and B, and performs analog-to-digital conversion on the third voltage VK1' and the fourth voltage VK2' respectively in response to the first signal GK and the second signal GK'. That is, the analog-to-digital conversion of the third voltage VK1' and the fourth voltage VK2' is realized through the time-division multiplexing function of the A / D conversion module. Its working principle is as follows. Figure 4 and Figure 5 The description in the text.

[0105] When A and B are not equal, as another embodiment of the present invention, such as Figure 6 As shown, two A / D conversion modules can be set up to perform analog-to-digital conversion on the third voltage VK1' and the fourth voltage VK2' respectively. A / D conversion module 1 converts the third voltage VK1' into an A-bit digital signal Q0……Qi……QA-1, and A / D conversion module 2 converts the fourth voltage VK2' into a B-bit digital signal Q0……Qi……QB-1. The schematic diagrams of the A-group upper transistor gate drive signal generation module and the B-group lower transistor gate drive signal generation module are shown below. Figure 7As shown, the two ends of the AND gate in each group of upper transistor gate drive signal generation modules and each group of lower transistor gate drive signal generation modules are independently connected. Figure 7 The example illustrates the scenario where the first signal GK is active high and the second signal GK' is active low. In the A-group upper transistor gate drive signal generation module, one end of the AND gate is connected to the first signal GK, and the other end is connected to the digital signal QA-1. In the B-group lower transistor gate drive signal generation module, one end of the AND gate is connected to the signal obtained by inverting the level of the second signal GK', and the other end is connected to the digital signal QB-1. Similarly, the principles of the upper transistor gate drive signal generation modules for groups other than A, and the lower transistor gate drive signal generation modules for groups other than B, are the same as those of the upper transistor gate drive signal generation modules for groups A and the lower transistor gate drive signal generation modules for groups B. Figure 6-7 The remaining working principles are as follows: Figure 4 and Figure 5 The description in the text.

[0106] In another embodiment of the present invention, when A and B are equal, two A / D conversion modules can be set to perform analog-to-digital conversion on the third voltage VK1' and the fourth voltage VK2' respectively. A / D conversion module 1 converts the third voltage VK1' into a single-digit digital signal Q0……Qi……QA-1 (A units), and A / D conversion module 2 converts the fourth voltage VK2' into a single-digit digital signal Q0……Qi……QA-1 (A=B). Its working principle is as follows: Figure 6 and Figure 7 The description in the text.

[0107] Figure 7 The diagram illustrates a scenario where the first signal GK is active high and the second signal GK' is active low. However, as other embodiments of the invention, the first signal GK being active high or low, and the second signal GK' being active high or low, can be configured by those skilled in the art according to actual circumstances, and are not limited to this specific configuration. Figure 7 The settings in [the system / mechanism].

[0108] Figure 4 , Figure 6 The composition of the external resistor network module 30 is only one embodiment of the present invention and is not limited to it. Figure 4 , Figure 6 The connection method in the external resistor network module 30 can be considered as having a resistor network section composed of resistors and diodes. This ensures that the connection method of the resistor network, where the diode's conduction state differs when the first signal is valid and the second signal is valid, is within the scope of protection claimed by this invention. Additionally, as another embodiment of this invention, it is also possible to... Figure 4 , Figure 6 The diode orientation is reversed by connecting the diode's cathode to pin PINK and the diode's anode to resistor R2. Its operating principle is as follows: Figure 4 , Figure 6 The working principle of [the system / mechanism].

[0109] in addition, Figure 5 , Figure 7 The R terminal of the SR flip-flop remains at a low level when the integrated circuit 100 is operating normally. When the integrated circuit 100 malfunctions, it outputs a high-level signal to turn off the driving upper and lower transistors. Additionally, other signals are connected to the gate drive terminals of the driving upper and lower transistors to achieve alternating conduction of the driving upper and lower transistors. The specific circuitry for achieving this alternating conduction is existing technology, and those skilled in the art can select and configure it according to actual needs.

[0110] In another embodiment of the present invention, when the first signal GK is valid, the digital signal of the third voltage VK1' after passing through the A / D conversion module can also be output to the lower transistor gate drive signal generation module to generate the gate drive signal for driving the lower transistor; when the second signal GK' is valid, the digital signal of the fourth voltage VK2' after passing through the A / D conversion module can be output to the upper transistor gate drive signal generation module to generate the gate drive signal for driving the upper transistor. Its working principle is as follows: Figure 4-7 As described in the text.

[0111] As described above, after the integrated chip is powered on but before the power transistor drive signal is generated, in response to the first and second signals, the voltage control signal generation module can generate different voltage signals. The power transistor drive current generation module generates the pull-up drive current and pull-down drive current of the power transistor based on these different voltage signals. These different voltage signals are generated using an external resistor network module. Therefore, when it is necessary to adjust the pull-up drive current and / or pull-down drive current of the power transistor, this can be achieved by adjusting the values ​​of resistors R1 and / or R2 in the external resistor network 30. That is, this invention can adjust both the pull-up drive current and the pull-down drive current of the power transistor using a single pin. Compared to existing technologies, this reduces the number of pins on the integrated circuit and avoids circuit stability issues caused by excessively long wires.

[0112] Furthermore, such as Figure 8As shown, this is another embodiment of the switch driver integrated circuit provided by the present invention. In this embodiment, the drive current of the power transistor can be adjusted in real time during the operation of the integrated circuit 100. The first switch K1 and the second switch K2 are respectively the same as or opposite to the gate drive terminal potential of the power transistor MQ1. For example, when the gate drive terminal potential of the power transistor MQ1 is high, the first switch K1 is closed and the second switch K2 is open; when the gate drive terminal potential of the power transistor MQ1 is low, the second switch K2 is closed and the first switch K1 is open. Figure 8 In the embodiment shown, the power transistor drive current generation module 20 includes a voltage-to-current conversion module and a current mirror module, and the output of the current mirror module is connected to the gate drive terminal of the power transistor.

[0113] The following is combined Figure 8-10 The working principle of this embodiment is explained as follows: When the gate drive terminal potential of power transistor MQ1 is high, the first switch K1 is closed and the second switch K2 is open. This can be understood as the first signal being valid and the second signal being invalid, causing the first current source IK1 to act on the external resistor network 30 to generate a first control voltage VK1. The first control voltage VK1 is rectified by the rectifier module to output a third voltage VK1'. The third voltage VK1' acts on the input terminal of the voltage-to-current conversion module, such as... Figure 9 The diagram shows the principle of the third voltage VK1' acting on the power transistor drive current generation module 20 to generate the pull-up drive current of power transistor MQ1. The third voltage VK1' acts on one end of the error amplifier EA. The other end of the error amplifier EA is connected to the end where MQ2 and resistor R3 are connected in series. The output of the error amplifier EA is connected to the gate drive terminal of MQ2. Because the error amplifier EA can make the voltages on its two ends equal, a third current IC will be generated in the branch containing resistors R3, MQ2, and MQ3. This third current IC is the ratio of the third voltage VK1' to the resistor R3. MQ3 and MQ4 form a current mirror structure. The third current IC flowing through MQ3, after being mirrored by MQ4, will generate a pull-up drive current IS in the branch containing MQ4. The ratio of the pull-up drive current IS to the third current IC depends on the size settings of MQ3 and MQ4, and the specific sizes of MQ3 and MQ4 can be set by those skilled in the art according to the actual situation. The pull-up drive current IS acts on the gate drive terminal of power transistor MQ1.

[0114] When the gate drive terminal potential of power transistor MQ1 is low, the second switch K2 is closed and the first switch K1 is open. This can be understood as the first signal being invalid and the second signal being valid, causing the second current source IK2 to act on the external resistor network 30 to generate a second control voltage VK2. The second control voltage VK2 is rectified by the rectifier module to output a fourth voltage VK2'. The fourth voltage VK2' acts on the input terminal of the voltage-to-current conversion module, such as... Figure 10The diagram shown illustrates the principle of the fourth voltage VK2' acting on the power transistor drive current generation module 20 to generate the pull-down drive current of power transistor MQ1. Figure 9 The difference is that a current mirror structure composed of MQ5 and MQ6 has been added, which is consistent with... Figure 9 The principle is the same. After passing through the error amplifier EA, a fourth current ID is generated in the branch containing resistors R4, MQ7, and MQ8. This fourth current ID is the ratio of the fourth voltage VK2' to the resistor R4. The fourth current ID flowing through MQ8 is mirrored by MQ9, generating a current I3 in the branch containing MQ9. The ratio of current I3 to the fourth current ID depends on the dimensions of MQ8 and MQ9. The current I3 flowing through MQ5 is mirrored by MQ6, generating a pull-down drive current IK on MQ6. The ratio of pull-down drive current IK to current I3 depends on the dimensions of MQ5 and MQ6. The specific dimensions of MQ8 and MQ9, and MQ5 and MQ6 can be set by those skilled in the art according to actual conditions. The pull-down drive current IK acts on the gate drive terminal of power transistor MQ1.

[0115] In another embodiment of the present invention, when the gate drive terminal potential of power transistor MQ1 is low, the first switch K1 is closed and the second switch K2 is open. The first current source IK1 acts on the external resistor network 30 to generate a first control voltage VK1. The first control voltage VK1 is rectified and outputs a third voltage VK1'. When the gate drive terminal potential of power transistor MQ1 is high, the first switch K1 is open and the second switch K2 is closed. The first current source IK2 acts on the external resistor network 30 to generate a second control voltage VK2. The second control voltage VK2 is rectified and outputs a fourth voltage VK2'. At this time, the pull-down drive current of power transistor MQ1 is determined by the third voltage VK1', and its generation principle is as follows. Figure 10 As shown in the figure; the pull-up drive current of power transistor MQ1 is determined by the fourth voltage VK2', and its generation principle is as follows. Figure 9 As shown in the image. Additionally... Figure 8-10 In the embodiment shown, the gate drive terminal of the power transistor MQ1 is also connected to other signals to enable the power transistor MQ1 to be turned on or off. The specific circuit for enabling the power transistor MQ1 to be turned on or off is already in the prior art, and those skilled in the art can select and set it according to actual needs.

[0116] As another embodiment of the present invention, it is also possible to... Figure 8 In the external resistor network 30, the diode orientation is reversed, i.e., the diode cathode is connected to pin PINK, and the diode anode is connected to resistor R2. Its working principle is as follows: Figure 8 The working principle of [the system / mechanism].

[0117] As described above, during the operation of integrated circuit 100, the pull-up drive current and pull-down drive current of power transistor MQ1 can be adjusted in real time based on the gate drive signal of power transistor MQ1. Based on the gate drive signal of power transistor MQ1, the voltage control signal generation module can generate different voltage signals, and the power transistor drive current generation module generates the pull-up drive current and pull-down drive current of the power transistor based on these different voltage signals. These different voltage signals are generated based on an external resistor network module. Therefore, when it is necessary to adjust the pull-up drive current and / or pull-down drive current of the power transistor, this can be achieved by adjusting the values ​​of resistors R1 and / or R2 in the external resistor network 30. That is, the present invention can achieve adjustment of both the pull-up drive current and the pull-down drive current of the power transistor using only one pin. Compared with existing technologies, this reduces the number of pins on the integrated circuit and avoids circuit stability problems caused by excessively long wires.

[0118] Furthermore, such as Figure 11 The image shows another embodiment of the switch driver integrated circuit provided by the present invention, relative to... Figure 4 In the embodiment shown, the second switch K2 and the second current source IK2 are connected in series between the power supply voltage VDD and the common node N1. When the second signal is valid, the second switch K2 is closed, and the second current source IK2 acts on the external resistor network module 30 to generate the second control voltage VK2. When the first signal is valid, the first switch K1 is closed, and the first current source IK1 acts on the external resistor network module 30 to generate the first control voltage VK1. The diode D1 has different conduction states when the first signal is valid and when the second signal is valid. The remaining operating principles of this embodiment are as described above. Figure 4 The working principle of [the system / mechanism]. Alternatively, [it can also be...] Figure 11 Medium voltage control signal generation module 10 is applied to Figure 6 , Figure 8 The illustrated embodiment.

[0119] Furthermore, such as Figure 12The diagram illustrates another embodiment of the switch-driven integrated circuit provided by the present invention. In this embodiment, the control signal generation module 10 is a current control signal generation module, comprising a first voltage source V1, a second voltage source V2, a first switch K1, a second switch K2, and a voltage-to-current conversion module. The first switch K1 is connected between the first voltage source V1 and a common node N2, and the second switch K2 is connected between the common node N2 and the second voltage source V2. The voltage-to-current conversion module converts the first voltage source V1 and the second voltage source V2 into a first control current IA and a second control current IB. The first control current IA and the second control current IB are applied to the gate drive terminal of the power transistor MQ1 through a current mirror module to provide pull-up and pull-down drive currents for the power transistor MQ1. The first voltage source V1 and the second voltage source V2 are generated by the internal circuitry of the integrated circuit IC. In this embodiment, the drive current of the power transistor can be adjusted in real time during the operation of the integrated circuit 100. The first switch K1 and the second switch K2 are respectively at the same potential or opposite potential to the gate drive terminal of the power transistor MQ1. For example, when the gate drive terminal potential of the power transistor MQ1 is high, the first switch K1 is closed and the second switch K2 is open; when the gate drive terminal potential of the power transistor MQ1 is low, the second switch K2 is closed and the first switch K1 is open. When the first switch K1 is closed, the first voltage source V1 can make the diode D1 conduct; when the second switch K2 is closed, the second voltage source V2 can make the diode D2 de-conduct.

[0120] The following is combined Figure 12-14 To explain its working principle, when the gate drive terminal potential of power transistor MQ1 is high, the first switch K1 is closed and the second switch K2 is open. This can be understood as the first signal being valid and the second signal being invalid. The first voltage source V1 acts on the voltage-to-current conversion module to generate the first control current IA. The first control current IA passes through the current mirror module to generate the pull-up drive current IS of power transistor MQ1. Figure 13As shown, the voltage acting on the external resistor network 30 is the first voltage source V1. The first voltage source V1 can turn on the diode D1 in the external resistor network 30. At this time, the external resistor network 30 can be considered as an equivalent resistance RA. The first control current IA is the ratio of the first voltage source V1 to RA. The first control current IA flowing through MQ3 is mirrored by MQ4 to generate the pull-up drive current IS acting on the power transistor MQ1. The ratio of the pull-up drive current IS to the first control current IA depends on the size settings of MQ3 and MQ4, and the specific sizes of MQ3 and MQ4 can be set by those skilled in the art according to actual conditions. When the gate drive terminal potential of the power transistor MQ1 is low, the second switch K2 is closed and the first switch K1 is open. At this time, it can be understood that the first signal is invalid and the second signal is valid. The second voltage source V2 acts on the voltage-to-current conversion module to generate the second control current IB. The second control current IB is mirrored by the current mirror module to generate the pull-down drive current IK of the power transistor MQ1, as shown. Figure 14 As shown, the voltage acting on the external resistor network 30 is the second voltage source V2. The second voltage source V2 makes the diode D1 in the external resistor network 30 non-conducting. At this time, the external resistor network 30 can be regarded as the equivalent resistance RB. The second control current IB is the ratio of the second voltage source V2 to RB. The second control current IB flowing through MQ8 passes through MQ9 and the mirror effect of MQ5 and MQ6 to generate the pull-down drive current IK on the power transistor MQ1. The ratio of the pull-down drive current IK to the second control current IB depends on the size of MQ8 and MQ9, as well as the size setting of MQ5 and MQ6. The specific size of MQ8 and MQ9, MQ5 and MQ6 can be set by those skilled in the art according to the actual situation.

[0121] In another embodiment of the present invention, it can also be configured such that when the gate drive terminal potential of power transistor MQ1 is low, the first switch K1 is closed and the second switch K2 is opened. At this time, the first voltage source V1 can be referenced in the appendix. Figure 14 The principle in the diagram determines the magnitude of the pull-down drive current of power transistor MQ1; when the gate drive terminal potential of power transistor MQ1 is high, the second switch K2 is closed and the first switch K1 is open. At this time, the second voltage source V2 can be referenced in the appendix. Figure 13 The principle in the circuit determines the magnitude of the pull-up drive current for power transistor MQ1. Additionally, Figure 12-14 In the embodiment shown, the gate drive terminal of the power transistor MQ1 is also connected to other signals to enable the power transistor MQ1 to be turned on or off. The specific circuit for enabling the power transistor MQ1 to be turned on or off is already in the prior art, and those skilled in the art can select and set it according to actual needs.

[0122] As another embodiment of the present invention, it is also possible to... Figure 12In the external resistor network 30, the diode orientation is reversed, that is, the diode cathode is connected to pin PINK, and the diode anode is connected to resistor R2.

[0123] As described above, in the operation of integrated circuit 100, the pull-up drive current and pull-down drive current of power transistor MQ1 can be adjusted in real time based on the gate drive signal of power transistor MQ1. Based on the gate drive signal of power transistor MQ1, the current control signal generation module can generate different currents in real time, and the power transistor drive current generation module generates the pull-up drive current and pull-down drive current of the power transistor based on these different currents. These different current signals are generated by an external resistor network module. Therefore, when it is necessary to adjust the pull-up drive current and / or pull-down drive current of the power transistor, this can be achieved by adjusting the values ​​of resistors R1 and / or R2 in the external resistor network 30. That is, the present invention can achieve adjustment of both the pull-up drive current and the pull-down drive current of the power transistor using only one pin. Compared with existing technologies, this reduces the number of pins on the integrated circuit and avoids circuit stability problems caused by excessively long wires.

[0124] This invention also provides a switch driver setting method, applied to the switch driver integrated circuit described above, such as... Figure 15 As shown, when the first signal is valid and the second signal is invalid, the voltage control signal generation module generates a first control voltage VK1; when the first signal is invalid and the second signal is valid, the voltage control signal generation module generates a second control voltage VK2; the power transistor drive current generation module generates the pull-up drive current and pull-down drive current of the power transistor based on the first control voltage VK1 and the second control voltage VK2; or, the power transistor drive current generation module generates the pull-down drive current and pull-up drive current of the power transistor based on the first control voltage VK1 and the second control voltage VK2.

[0125] As another embodiment of the switch driving setting method provided by the present invention, such as Figure 16 As shown, when the first signal is valid and the second signal is invalid, the current control signal generation module generates a first control current IA; when the first signal is invalid and the second signal is valid, the current control signal generation module generates a second control current IB; the power transistor drive current generation module generates the pull-up drive current and pull-down drive current of the power transistor based on the first control current IA and the second control current IB; or the power transistor drive current generation module generates the pull-down drive current and pull-up drive current of the power transistor based on the first control current IA and the second control current IB.

[0126] In summary, this invention can function after the integrated circuit is powered on but before the power transistor drive signal is generated, or it can generate the pull-up and pull-down drive currents of the power transistor in real time during the operation of the integrated circuit. By enabling the first and second signals at different times, the voltage control signal generation module or the current control signal generation module generates different voltages or different currents under the different signal enable actions; the power transistor drive current generation module can generate the pull-up and pull-down drive currents of the power transistor based on the different voltages or different currents. In this invention, the different voltages or different currents are all generated based on the external resistor network module. Therefore, the magnitude of the pull-up and pull-down drive currents of the power transistor can be adjusted by adjusting the resistance value of the external resistor network module. Compared with the prior art, this invention can adjust the pull-up and pull-down drive currents of the power transistor with a single pin; it can reduce the number of pins on the integrated circuit and avoid circuit stability problems caused by excessively long wires.

[0127] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating the present invention and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A switch driver integrated circuit, characterized in that: include: The power transistor is located inside the integrated circuit. One pin PINK is used to connect the integrated circuit to an external resistor network module located outside the integrated circuit. The other end of the external resistor network module is connected to a low potential ground. A control signal generation module is disposed inside the integrated circuit, and the control signal generation module is connected to the external resistor network module through the pin PINK. A power transistor drive current generation module is disposed inside the integrated circuit and connected to the output terminal of the control signal generation module. The output terminal of the power transistor drive current generation module is connected to the gate drive terminal of the power transistor. The control signal generation module is a voltage control signal generation module, which includes a first current source IK1, a second current source IK2, a first switch K1, and a second switch K2. The first current source IK1 and the first switch K1 are connected in series between the power supply voltage VDD and a common node. The common node is connected to the pin PINK. The second current source IK2 and the second switch K2 are connected in series between the common node and a low-potential ground. Alternatively, the second current source IK2 and the second switch K2 are connected in series between the power supply voltage VDD and the common node. When the first signal is valid, the voltage control signal generation module generates a first control voltage VK1. When the second signal is valid, the voltage control signal generation module generates a second control voltage VK2. The first signal and the second signal are generated by the internal circuitry of the integrated circuit.

2. The switch driver integrated circuit according to claim 1, characterized in that: The first signal and the second signal are valid at different times.

3. The switch driver integrated circuit according to claim 2, characterized in that: The external resistor network module consists of resistors and diodes; The diode has different conduction states when the first signal and the second signal are respectively valid.

4. The switch driver integrated circuit according to claim 3, characterized in that: The power transistor drive current generation module generates the pull-up drive current and pull-down drive current of the power transistor based on the first control voltage VK1 and the second control voltage VK2.

5. The switch driver integrated circuit according to claim 1, characterized in that: When the first signal is valid, the first switch K1 is closed, and the first current source IK1 acts on the external resistor network module to generate the first control voltage VK1 at the common node. When the second signal is valid, the second switch K2 is closed, and the second current source IK2 acts on the external resistor network module to generate the second control voltage VK2 at the common node.

6. The switch driver integrated circuit according to claim 5, characterized in that: The voltage control signal generation module is also equipped with a rectifier module for rectifying the first control voltage VK1 and the second control voltage VK2. The rectifier module rectifies the first control voltage VK1 and outputs a third voltage VK1'. The rectifier module rectifies the second control voltage VK2 and outputs a fourth voltage VK2'.

7. The switch driver integrated circuit according to claim 6, characterized in that: The power transistor drive current generation module includes an A / D conversion module, M drive upper transistors, N drive lower transistors, and gate drive signal generation modules for the upper and lower transistors. The output terminal of the rectifier module is connected to the input terminal of the A / D conversion module; The output of the A / D conversion module is connected to the input of the upper / lower MOSFET gate drive signal generation module; The output terminal of the upper / lower MOSFET gate drive signal generation module is connected to the gate drive terminal of the upper MOSFET and the gate drive terminal of the lower MOSFET, respectively. The M driving upper transistors are connected in parallel, the N driving lower transistors are connected in parallel, and the M driving upper transistors and the N driving lower transistors are connected in series at the gate driving terminal of the power transistor. in M and N are both positive integers greater than 1.

8. The switch driver integrated circuit according to claim 7, characterized in that: The A / D conversion module converts the third voltage VK1' into a digital signal with the first digit being A. The A / D conversion module converts the fourth voltage VK2' into a digital signal with a second bit value of B; where A and B are both positive integers greater than 1.

9. The switch driver integrated circuit according to claim 5, characterized in that: The power transistor drive current generation module includes an A / D conversion module, M drive upper transistors, N drive lower transistors, and gate drive signal generation modules for the upper and lower transistors. The first control voltage VK1 and the second control voltage VK2 are connected to the input terminal of the A / D conversion module; The output of the A / D conversion module is connected to the input of the upper / lower MOSFET gate drive signal generation module; The output terminal of the upper / lower MOSFET gate drive signal generation module is connected to the gate drive terminal of the upper MOSFET and the gate drive terminal of the lower MOSFET, respectively. The M driving upper transistors are connected in parallel, the N driving lower transistors are connected in parallel, and the M driving upper transistors and the N driving lower transistors are connected in series at the gate driving terminal of the power transistor. in M and N are both positive integers greater than 1.

10. The switch driver integrated circuit according to claim 9, characterized in that: The A / D conversion module converts the first control voltage VK1 into a digital signal with the first digit being A. The A / D conversion module converts the second control voltage VK2 into a second digital signal with a bit depth of B; where A and B are both positive integers greater than 1.

11. The switch driver integrated circuit according to claim 8 or 10, characterized in that: The M driving transistors are divided into A groups, and the gate driving terminals of the driving transistors in each group are connected together. The N driving transistors are divided into B groups, and the gate driving terminals of the driving transistors in each group are connected together. The upper transistor gate drive signal generation module generates A gate drive signals based on the first digital signal with a bit value of A and the first signal, respectively, to drive the gate drive terminals of the A groups of driving upper transistors. The lower transistor gate drive signal generation module generates B gate drive signals based on the second B-bit digital signal and the second signal to drive the gate drive terminals of the B groups of lower transistors. or, The M driving transistors are divided into B groups, and the gate driving terminals of the driving transistors in each group are connected together. The N driving transistors are divided into A groups, and the gate driving terminals of the driving transistors in each group are connected together. The upper transistor gate drive signal generation module generates B gate drive signals based on the second B-bit digital signal and the second signal to drive the gate drive terminals of the B groups of driving upper transistors. The lower transistor gate drive signal generation module generates A gate drive signals based on the first digital signal with a bit depth of A and the first signal, respectively, to drive the gate drive terminals of the A groups of lower transistors.

12. The switch driver integrated circuit according to claim 11, characterized in that: The A / D conversion module is configured to be one or two.

13. The switch driver integrated circuit according to any one of claims 7-10, 12, characterized in that: The first signal and the second signal are switch trigger signals generated inside the integrated circuit before the power transistor gate drive terminal signal is generated after the integrated circuit is powered on.

14. The switch driver integrated circuit according to claim 6, characterized in that: The power transistor drive current generation module includes a voltage-to-current conversion module and a current mirror module; The output terminal of the rectifier module is connected to the input terminal of the voltage-to-current conversion module. The voltage-to-current conversion module converts the third voltage VK1' into the third current IC and the fourth voltage VK2' into the fourth current ID. The input terminal of the current mirror module is connected to the output terminal of the voltage-to-current conversion module, and the output terminal of the current mirror module is connected to the gate drive terminal of the power transistor. The third current IC outputs the pull-up drive current of the power transistor after passing through the current mirror module, and the fourth current ID outputs the pull-down drive current of the power transistor after passing through the current mirror module. Alternatively, the third current IC outputs the pull-down drive current of the power transistor after passing through the current mirror module, and the fourth current ID outputs the pull-up drive current of the power transistor after passing through the current mirror module.

15. The switch driver integrated circuit according to claim 5, characterized in that: The power transistor drive current generation module includes a voltage-to-current conversion module and a current mirror module; The first control voltage VK1 or the second control voltage VK2 is connected to the input terminal of the voltage-to-current conversion module. The voltage-to-current conversion module converts the first control voltage VK1 into a third current IC and the second control voltage VK2 into a fourth current ID. The input terminal of the current mirror module is connected to the output terminal of the voltage-to-current conversion module, and the output terminal of the current mirror module is connected to the gate drive terminal of the power transistor. The third current IC outputs the pull-up drive current of the power transistor after passing through the current mirror module, and the fourth current ID outputs the pull-down drive current of the power transistor after passing through the current mirror module. Alternatively, the third current IC outputs the pull-down drive current of the power transistor after passing through the current mirror module, and the fourth current ID outputs the pull-up drive current of the power transistor after passing through the current mirror module.

16. The switch driver integrated circuit according to any one of claims 14-15, characterized in that: The first signal and the second signal are respectively signals that are the same as or opposite to the potential of the gate drive terminal of the power transistor.

17. A switch driving setting method, applied to the switch driving integrated circuit according to any one of claims 1-16, characterized in that: When the first signal is valid and the second signal is invalid, the voltage control signal generation module generates a first control voltage VK1; when the first signal is invalid and the second signal is valid, the voltage control signal generation module generates a second control voltage VK2; the power transistor drive current generation module generates the pull-up drive current and pull-down drive current of the power transistor based on the first control voltage VK1 and the second control voltage VK2.

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