Split input amplifier for protection against DC bias

Abstract

The present disclosure relates to a split input amplifier for protection from DC bias. Embodiments presented herein provide apparatuses and techniques to reduce direct current (DC) voltage bias between a transmitter and a receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver can include a first cell gain buffer that receives a reference voltage signal from the reference voltage source. The transmitter can be communicatively coupled to the receiver via one or more connections and can include a second cell gain buffer communicatively coupled to the first cell gain buffer via one of the connections. An amplifier (e.g., an operational amplifier) of the transmitter can include a plurality of positive inputs coupled to the second cell gain buffer and a bias tracker. The bias tracker can compensate for DC bias caused by at least power supply and / or ground bounce.

Description

Technical Field

[0001] This invention relates generally to wireless communication, and more specifically to communication between integrated circuits in electronic devices. Background Technology

[0002] Transceivers within electronic devices (e.g., intermediate frequency (IF) transceivers, baseband transceivers) can be coupled using a direct current (DC) link (e.g., a cable such as a flexible flat cable). DC links offer improvements over AC-coupled paths (e.g., alternating current or AC coupling), such as reduced cost, lower latency, reduced noise, and unsegmented DC / low-frequency information. However, DC links can be susceptible to DC bias, which can lead to poorer signal quality (e.g., in terms of signal eye diagram distortion, increased jitter, and bit error rate degradation). DC bias can be affected by reference voltage mismatch, supply fluctuations, ground bounce, etc. (e.g., caused or exacerbated by them). Summary of the Invention

[0003] The following outlines some of the embodiments disclosed herein. It should be understood that these aspects are presented merely to provide the reader with a concise overview of these particular embodiments, and are not intended to limit the scope of this disclosure. In fact, this disclosure may cover many aspects not set forth below.

[0004] In one embodiment, an electronic device is provided, comprising a receiver having a first unit gain buffer configured to receive a reference voltage signal. The electronic device also includes a transmitter having a second unit gain buffer coupled to the first unit gain buffer of the receiver. The transmitter further includes an amplifier having a first positive input configured to receive the reference voltage signal via the first and second unit gain buffers. The transmitter also includes a bias tracker coupled to a second positive input of the amplifier. The electronic device further includes a connector coupling the first unit gain buffer of the receiver to the second unit gain buffer of the transmitter.

[0005] In another embodiment, a transmitter is proposed that includes a first unit gain buffer coupled to a second unit gain buffer of a receiver via a coupler. The transmitter also includes a bias tracker that compensates for bias caused at least in part by variations in the power supply signal and ground bounce. The transmitter further includes an amplifier that includes a first input coupled to the second unit gain buffer and a second input coupled to the bias tracker.

[0006] In another embodiment, an electronic device is proposed, comprising a first integrated circuit having a receiver. The receiver includes a first unit gain buffer for receiving a reference voltage signal. The electronic device also includes a second integrated circuit having a transmitter having a power supply and a second unit gain buffer. The transmitter further includes an amplifier coupled to the second unit gain buffer and configured to receive a power supply signal from the power supply. The transmitter also includes a bias tracker coupled to the amplifier and configured to compensate for a DC voltage bias caused at least by variations in the power supply signal. The electronic device also includes a connector that couples the first integrated circuit to the second integrated circuit. The second unit gain buffer is configured to receive the reference voltage signal from the first integrated circuit via the connector.

[0007] Various modifications to the above-described features may exist with respect to various aspects of the invention. Other features may also be incorporated into these aspects. These modifications and additional features may exist individually or in any combination. For example, various features discussed below relating to one or more illustrated embodiments may be incorporated individually or in any combination into any of the above aspects of the invention. The brief summary presented above is intended only to familiarize the reader with specific aspects and context of the embodiments disclosed herein and does not limit the claimed subject matter. Attached Figure Description

[0008] Various aspects of this disclosure can be better understood by reading the following detailed description and referring to the accompanying drawings, wherein similar figures refer to similar parts.

[0009] Figure 1 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0010] Figure 2 An embodiment according to this disclosure includes multiple transceivers and connectors for communication between the transceivers. Figure 1 A block diagram of an electronic device.

[0011] Figure 3 It has Figure 2 A schematic diagram of a communication system of electronic devices with transceivers coupled via connectors.

[0012] Figure 4A This illustrates an embodiment of the present disclosure caused by reference voltage mismatch. Figure 3 Timing diagram of DC bias between transceivers.

[0013] Figure 4B This illustrates an embodiment of the present disclosure caused by power supply fluctuations. Figure 3 Timing diagram of DC bias between transceivers.

[0014] Figure 4C This illustrates the effect caused by ground bounce according to an embodiment of this disclosure. Figure 3 Timing diagram of DC bias between transceivers.

[0015] Figure 5 It is an embodiment of the present disclosure having a connector coupled to it. Figure 3 A schematic diagram of a communication system for a transceiver of an electronic device, showing a shared reference voltage signal, a multi-input amplifier, and a bias tracker.

[0016] Figure 6 According to the embodiments of this disclosure, both transceivers include a duplexer. Figure 5 A schematic diagram of the communication system.

[0017] Figure 7 It is based on the implementation scheme of this disclosure. Figure 5 and Figure 6 A schematic diagram of the amplifier.

[0018] Figure 8 It is shown Figure 3 , Figure 5 and Figure 6 The power suppression curve of the communication system.

[0019] Figure 9 It is shown Figure 3 , Figure 5 and Figure 6 The curve of ground bounce suppression in the communication system. Detailed Implementation

[0020] One or more specific implementations will be described below. To provide a brief description of these implementations, not all characteristics of the actual implementations are described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, decisions must be made specific to many implementations to achieve the developer's specific objectives, such as compliance with system-related and business-related constraints that may vary from one implementation to another. Furthermore, it should be understood that such development work can be complex and time-consuming, but will still be routine work of design, fabrication, and manufacturing for those skilled in the art who benefit from this disclosure.

[0021] When describing elements of various embodiments of this disclosure, the articles “an” and “the” are intended to refer to one or more of the elements present. The terms “comprising,” “including,” and “having” are intended to be included and to indicate the presence of additional elements besides those listed. Additionally, it should be understood that reference to “an embodiment” or “an embodiment” of this disclosure is not intended to be construed as excluding the existence of additional embodiments also incorporating the cited features. Furthermore, specific features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. The use of the terms “generally,” “approximately,” “about,” “close to,” and / or “substantially” should be understood to mean including close to the target (e.g., design, value, quantity), such as within limits of any suitable or conceivable error (e.g., within 0.1% of the target, within 1% of the target, within 5% of the target, within 10% of the target, within 25% of the target, etc.).

[0022] This disclosure relates to reducing or mitigating DC bias between transceivers (e.g., intermediate frequency (IF) transceivers, baseband transceivers) that may be affected (e.g., caused or exacerbated) by reference voltage mismatch, power supply fluctuations or transients, ground bounce, etc. Reference voltage mismatch can refer to the difference between reference voltages used by transceivers communicating within an electronic device. Deviations in the power supply output voltage due to variations in the power supply load can cause power supply fluctuations. Ground bounce (e.g., noise) can be caused by ground potential mismatch between transceivers due to large transient currents flowing through a cable with finite resistance.

[0023] The implementation includes a shared reference voltage signal generated by a reference voltage source. The reference voltage source may be located in a transmitter or receiver of an electronic device. The receiver may include a first unit gain buffer that receives the reference voltage signal via the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more intermediate frequency (IF) connectors (e.g., cables). The transmitter may include a second unit gain buffer that is communicatively coupled to the first unit gain buffer of the receiver via one of the IF cables. An amplifier (e.g., an operational amplifier) ​​of the transmitter may be coupled to the second unit gain buffer and a bias tracker. The bias tracker compensates for DC voltage bias caused at least by power supply and / or ground bounce.

[0024] Advantageously, the embodiments presented herein use a shared reference voltage between transceivers to reduce or mitigate reference voltage mismatch. Furthermore, the embodiments presented herein use a bias tracker that compensates for the corresponding DC bias to reduce or mitigate power supply fluctuations and / or ground bounce. Advantageously, the embodiments presented herein provide techniques and apparatus for reducing DC bias while maintaining low latency and low bit error rate (BER) without additional protocol complexity or hardware overhead.

[0025] Figure 1 This is a block diagram of an electronic device 10 according to an embodiment of the present disclosure. Among other things, the electronic device 10 may include one or more processors 12 (collectively referred to herein as a single processor, which may be implemented in any suitable form of processing circuitry), memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network interface (e.g., wireless interface) 25, and power supply 26. Figure 1 The various functional blocks shown may include hardware elements (including circuits), software elements (including machine-executable instructions), or combinations of hardware and software elements (which may be referred to as logic). Processor 12, memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network and / or wireless interface 25, and / or power supply 26 may each be communicatively coupled to each other directly or indirectly (e.g., via another component, communication bus, wireless connection, network) to transmit and / or receive data between them. It should be noted that... Figure 1 This is merely one example of a specific implementation and is intended to illustrate the types of components that may exist in electronic device 10.

[0026] For example, electronic device 10 may include any suitable computing device, including desktop computers or laptops (e.g., those available from Apple Inc., Cupertino, California). Pro, MacBook mini or Mac (in the form of) portable electronic devices or handheld electronic devices such as wireless electronic devices or smartphones (e.g., available from Apple Inc. in Cupertino, California). (Model form), tablet computers (for example, those available from Apple in Cupertino, California) (in the form of a model), wearable electronic devices (e.g., Apple products available from Apple Inc. in Cupertino, California) (in the form of) and other similar devices. In some cases, electronic device 10 may represent Network routers, terminal devices, and / or hibernating terminal devices (SEDs) are as discussed in this document.

[0027] It should be noted that Figure 1 The processor 12 and other related items herein may be generally referred to as "data processing circuitry". This data processing circuitry may be embodied wholly or partially in software, hardware, or both. Furthermore, the processor 12 and... Figure 1Other related items may be a single, independent processing module, or may be incorporated, wholly or partially, into any of the other elements within the electronic device 10. Processor 12 may be implemented using a combination of a general-purpose microprocessor, microcontroller, digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic device (PLD), controller, state machine, gated logic, discrete hardware components, dedicated hardware finite state machine, or any other suitable entity capable of performing computations or other manipulations of information. Processor 12 may perform the various functions described herein.

[0028] exist Figure 1 In the electronic device 10, a processor 12 may be operatively coupled to a memory 14 and a non-volatile storage device 16 to execute various algorithms. Such programs or instructions executed by the processor 12 may be stored in any suitable article of writing comprising one or more tangible computer-readable media. The tangible computer-readable media may include the memory 14 and / or the non-volatile storage device 16, individually or jointly, to store instructions or routines. The memory 14 and the non-volatile storage device 16 may include any suitable article of writing for storing data and executable instructions, such as random access memory, read-only memory, rewritable flash memory, hard disk drive, and optical disk. Furthermore, programs (e.g., operating systems) encoded on such computer program products may also include instructions executable by the processor 12 to enable the electronic device 10 to provide various functions.

[0029] In some embodiments, display 18 may facilitate a user's viewing of images generated on electronic device 10. In some embodiments, display 18 may include a touchscreen that facilitates user interaction with the user interface of electronic device 10. Furthermore, it should be understood that in some embodiments, display 18 may include one or more liquid crystal displays (LCDs), light-emitting diode (LED) displays, organic light-emitting diode (OLED) displays, active-matrix organic light-emitting diode (AMOLED) displays, or some combination of these and / or other display technologies.

[0030] The input structure 22 of the electronic device 10 allows a user to interact with the electronic device 10 (e.g., press a button to increase or decrease the volume level). Like the network and / or wireless interface 25, the I / O interface 24 allows the electronic device 10 to interact with a variety of other electronic devices. In some embodiments, the I / O interface 24 may include I / O ports for hardwired connections for charging and / or content manipulation using standard connectors and protocols such as the Lightning connector supplied by Apple Inc. of Cupertino, California, Universal Serial Bus (USB), or other similar connectors and protocols. The network and / or wireless interface 25 may include one or more interfaces, for example, for personal area networks (PANs) such as… Networks, local area networks (LANs), or wireless local area networks (WLANs) such as those employing a protocol from the IEEE 802.11x family of protocols (e.g., Networks such as low-speed wireless personal area networks (LR-WPANs) and low-speed wireless personal area networks (LSWPANs) using the IEEE 802.15.4 protocol (e.g., mesh networks) Networks) and / or wide area networks (WANs) such as any standards related to the 3rd Generation Partnership Project (3GPP), including, for example, third-generation (3G) cellular networks, Universal Mobile Telecommunications System (UMTS), fourth-generation (4G) cellular networks, Long Term Evolution (LTE) Cellular networks, Long Term Evolution License Assisted Access (LTE-LAA) cellular networks, fifth-generation (5G) cellular networks and / or new radio (NR) cellular networks, satellite networks, etc. Specifically, network interface 25 may include, for example, one or more interfaces for using Release-15 cellular communication standards that include millimeter-wave (mmWave) frequency ranges (e.g., 24.25-300 GHz). The network interface 25 of electronic device 10 may allow communication via the aforementioned networks (e.g., 5G, Wi-Fi, LTE-LAA, mesh networks, etc.). Communicating via networks, etc.

[0031] Network and / or wireless interface 25 may also include one or more interfaces for, for example, a broadband fixed wireless access network (e.g., Mobile broadband wireless network (mobile) Asynchronous digital subscriber lines (e.g., ADSL, VDSL), digital video terrestrial broadcasting (DVB-) Network and its extension DVB handheld (DVB- Networks, ultra-broadband (UWB) networks, alternating current (AC) power lines, etc.

[0032] As shown, network interface 25 may include transceiver 27. In some embodiments, all or part of transceiver 27 may be located within processor 12. Transceiver 27 may support the transmission and reception of various wireless signals via one or more antennas, and therefore may include transmitters and receivers. In some embodiments, transceiver 27 may include a 5G mmWave transceiver supporting the transmission and reception of 5G wireless signals. Such transceiver 27 may include intermediate frequency (IF) transceiver 28 and one or more mmWave front-ends 29. IF transceiver 28 may modulate an input baseband signal having a baseband frequency to an intermediate frequency (e.g., transmitted from processor 12 including a baseband processor) to one or more mmWave front-ends 29 (e.g., via connectors, couplers, or cables). One or more mmWave front-ends 29 may then convert the IF signal to a carrier frequency and radiate it by one or more antennas of electronic device 10. In some embodiments, each of IF transceiver 28 and one or more mmWave front-ends 29 may be located on its own integrated circuit.

[0033] The power supply 26 of the electronic device 10 may include any suitable power source, such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter. In some embodiments, the electronic device 10 may take the form of a computer, a portable electronic device, a wearable electronic device, or other types of electronic devices. In some embodiments, the power supply 26 may include or represent a power management unit (PMU) that controls the power distribution throughout the electronic device 10. For example, the power management unit may control the power supplied to various subsystems and / or components of the electronic device 10, shut down (e.g., turn off) currently unused subsystems and / or components, and control the hibernation and / or power functions of various subsystems and / or components.

[0034] Figure 2 According to an embodiment of this disclosure, a plurality of transceivers 30A-E (collectively referred to as 30) and a connector 38 for communication between the transceivers 30A-E are included. Figure 1 A block diagram of the electronic device 10. Specifically, transceivers 30A-E may be part of the IF transceiver 28 and / or the mmWave front end 29, as... Figure 1As shown. For example, transceiver 30A may be part of IF transceiver 28, and each transceiver 30B-E may be part of mmWave front end 29. Transceiver 30A may be communicatively coupled to transceiver 30B-E via connector 38. Connector 38 may represent, for example, a cable, coupler, or other electrical interconnect. In some embodiments, each of IF transceiver 28 and one or more mmWave front ends 29 may be disposed on its own integrated circuit. In this way, connector 38 can couple IF transceiver 28 disposed on a first integrated circuit to one or more mmWave front ends 29 disposed on one or more other integrated circuits. It should be understood that electronic device 10 may include any suitable number of transceivers 30A-E for communication of various signals therein.

[0035] Connector 38 may represent a flexible connection, such as a flexible flat cable (FFC), between integrated circuits (e.g., having transceivers 30A-30E). It should be understood that while one connector 38 is shown between each transceiver in transceivers 30A-30E, any suitable number of cables may be included between one or more transceivers in transceivers 30A-30E. Furthermore, it should be understood that each connector 38 may enable one or more signals to propagate therein using multiplexing, such as frequency domain duplexing. For example, low-frequency control signals (e.g., having frequencies below 1 GHz) and high-frequency data signals (e.g., having frequencies of 1 GHz or higher, such as 10 GHz or higher, 20 GHz or higher, 30 GHz or higher) may communicate between transceivers 30A-E via connector 38. In some embodiments, connector 38 may be used to transmit and / or receive signals having intermediate frequency and / or baseband frequencies. That is, each transceiver in transceivers 30A-30E may transmit and / or receive signals of various frequencies (e.g., low and high frequencies). As shown in the figure, each transceiver 30A-E includes a transmitter 32 and a receiver 34. For example, the transmitter 32A enables the transceiver 30A to transmit various signals to other transceivers 30B-E, and the receiver 34A enables the transceiver 30A to receive various signals from other transceivers 30B-E.

[0036] Figure 3 It has Figure 2 A schematic diagram of a communication system 50 comprising a transceiver 30 coupled to an electronic device 10 via one or more cables 52, 54. Specifically, the communication system 50 includes a transmitter 32 and a receiver 34 coupled via one or more cables 52, 54. As shown in the figure, Figure 3 The transmitter 32 can represent Figure 2 The transmitter 32A in the intermediate frequency transceiver 30A, and Figure 3 The receiver 34 can represent Figure 2The transceiver 30C has a receiver 34C, but Figure 3 The transmitter 32 and receiver 34 can respectively represent Figure 2 Either the transmitter 32A-E or the receiver 34A-E.

[0037] Cables 52 and 54 can be represented Figure 2 Connector 38. That is, cables 52 and 54 may represent a single connector 38 between transmitter 32 and receiver 34. In this case, the signals propagated through cables 52 and 54 may include low-frequency control signals (e.g., frequencies less than 1 GHz) and high-frequency data signals (e.g., frequencies of tens of GHz) multiplexed on cables 52 and 54 using, for example, frequency domain duplexing. In other cases, cables 52 and 54 may be separate cables, and each cable may be used for a specific data type and / or signal frequency. For example, cable 52 may include an intermediate frequency cable or a baseband frequency cable for transmitting data signals and / or control signals between transmitter 32 and receiver 34. As another example, cable 54 may be used as a voltage supply and / or grounding cable between transmitter 32 and receiver 34.

[0038] As shown, transmitter 32 includes a transmission (TX) inverter 56 coupled to a power supply 58, which can introduce power supply transients 59 (e.g., power supply fluctuations). The output of inverter 56 is coupled to an amplifier-based driver 66 (e.g., an operational amplifier) ​​via a resistor divider including a first resistor R1 (e.g., an input resistor) 62 and a second resistor R2 (e.g., a feedback resistor) 64. In some embodiments, resistors 62, 64 may include variable resistors and the amplification factor of amplifier 66 may be set to the resistance value of the second resistor 64 divided by the resistance value of the first resistor 62. Amplifier 66 may also receive a transmission reference voltage (tx_ref) 68, which may be generated internally or externally to transmitter 32. Transmission reference voltage 68 can be used to convert analog transmission signals into digital transmission signals. The output of amplifier 66 may be coupled to a terminating resistor (Rterm) 70 and a duplexer 71. Duplexer 71 may include a low-pass filter (LPF) 72 and a high-pass filter (HPF) 74. As described above, duplexer 71 can combine a control signal (e.g., filtered by LPF 72) with an intermediate frequency (IF) signal (e.g., filtered by HPF 74) transmitted via cable 52 to receiver 34. That is, HPF 74 can receive the IF transmission signal 73 (e.g., a data signal) to be transmitted to receiver 34. In some cases, duplexer 71 can utilize frequency domain multiplexing.

[0039] Receiver 34 also includes a duplexer 71 with a low-pass filter (LPF) 76 and a high-pass filter (HPF) 78. The duplexer 71 of receiver 34 is coupled to receiver (RX) amplifier 84 (e.g., op-amp) via a resistor divider including a terminating resistor (Rterm) 80 and a variable resistor (Rfb) 82. If the duplexer 71 of transmitter 32 combines a low-voltage (e.g., control) signal and a transmit signal 73, the duplexer 71 of receiver 34 can separate the combined signal into a low-voltage signal and a transmit signal 73. In this case, the low-voltage signal can propagate to the terminating resistor 80 and amplifier 84.

[0040] Amplifier 84 can also receive a receive reference voltage (rx_ref) 86 that can be generated internally or externally to receiver 34. The receive reference voltage 86 can be used to convert the analog transmitted signal from transmitter 32 into a digital received signal. The output of amplifier 84 can be coupled to comparator 88.

[0041] High-pass filters 74 and 78 allow high-frequency (e.g., radio frequency (RF)) components of signals (e.g., data signals) to be transmitted between integrated circuits (e.g., those with transceivers 30A and 30B) via intermediate frequency cable 52. Low-pass filters 72 and 76 allow low-frequency components (e.g., baseband components) of control signals transmitted between transmitter 32 and receiver 34 to pass through cable 52. The positive terminals of amplifiers 66 and 84 can receive corresponding reference voltage signals (e.g., tx_ref and rx_ref) 68 and 86, which can define the common-mode voltages of transmitter 32 and receiver 34, respectively. For example, the common-mode voltage of transmitter 32 can be represented by Equation 1 below:

[0042]

[0043] Where V sup This is the supply voltage to the transmitter inverter or buffer 56, and V tx_gnd It is the ground bounce of 90 at transmitter 32.

[0044] The DC bias voltage between transmitter 32 and receiver 34 can be determined based on the mismatch between reference voltages 68 and 86, power supply fluctuations 59 (e.g., transients), and ground bounce 90. The mismatch between reference voltages 68 and 86 can be expressed as the difference between the transmitting reference voltage 68 and the receiving reference voltage 86, as represented by Equation 2 below:

[0045] V 偏置 =V tx_ref -V rx_ref (Equation 2)

[0046] Power supply fluctuation 59 can be caused by a power management unit (PMU) with power supply ripple (e.g., residual periodic variations in the supplied DC voltage derived from an AC source). Power supply ripple can cause variations in the supply voltage 59, and thus contribute to DC bias. Power supply fluctuation 59 can be represented by the following equation 3:

[0047]

[0048] Where R1 is the input resistor 62 of the TX op-amp 66, R2 is the feedback resistor 64 of the TX amplifier 66, and ΔV sup This is the power supply fluctuation 59 from the nominal voltage. Ground bounce 90 can be generated by the grounding resistance value of the power supply / grounding cable 54 between the transmitter 32 and the receiver 34. In some cases, ground bounce 90 can be tens of millivolts (mV) (e.g., 10mV, 20mV, 30mV, 40mV, 50mV, 60mV, 70mV, 80mV, 90mV, 100mV, etc.) and can be represented by the following equation 4:

[0049] V 偏置 =V tx_gnd (Equation 4)

[0050] Figures 4A to 4C It describes an implementation scheme according to this disclosure. Figure 3 Timing diagram of the DC bias of the transmission signal between transmitter 32 and receiver 34. Figures 4A to 4C Each image in the diagram depicts a representation of the source. Figure 3 The transmitter 32 and receiver 34 transmit signals via line 102, and the TX common-mode voltage 104 and RX reference voltage 106, such as... Figure 3 The DC bias between the RX reference voltage 86 and the DC bias between 108, 112, and 122.

[0051] More specifically, Figure 4A This is a timing diagram 100 showing the DC bias 108 caused by reference voltage mismatch. Figure 4B This is a timing diagram 110 showing the DC bias 112 caused by power supply fluctuation 59, and Figure 4C This is a timing diagram 120 showing the DC bias 122 caused by ground bounce 90. The larger the DC bias, the greater the impact on the transmitted signal 102. For example, the DC bias 108 caused by reference voltage mismatch is smaller than the DC bias 112 caused by power supply fluctuation 59. As shown, due to the larger DC bias 112 caused by power supply fluctuation (compared to the smaller DC bias 108 caused by reference voltage mismatch), Figure 4B The magnitude (e.g., amplitude) of the transmitted signal 102 is greater than Figure 4AThe magnitude of the transmitted signal. Therefore, any of the reference voltage mismatch, power supply fluctuation 59 and / or ground bounce 90 can result in a certain magnitude of DC bias 112, and when aggregated, can have a large DC bias 112, which can significantly degrade signal quality (e.g., in terms of eye diagram distortion, increased jitter and / or increased bit error rate).

[0052] Figure 5 It is an embodiment of this disclosure having coupling via cables 52, 54, 132. Figure 3 A schematic diagram of the communication system 130 of the transceiver 30 includes a shared reference voltage signal 146, a multi-input amplifier 134 (e.g., an operational amplifier), and a bias tracker 136. Specifically, the communication system 130 includes a transmitter 32 and a receiver 34 coupled via one or more cables 52, 54, 132. As shown in the figure, Figure 5 The transmitter 32 can represent Figure 2 The transmitter 32A in the intermediate frequency transceiver 30A, and Figure 5 The receiver 34 can represent Figure 2 The transceiver 30C has a receiver 34C, but Figure 5 The transmitter 32 and receiver 34 can respectively represent Figure 2 Any of the transmitters 32A-E and any of the receivers 34A-E.

[0053] As shown in the figure, a single reference voltage (ref) 146 is shared between transmitter 32 and receiver 34 via intermediate frequency (IF) reference voltage cable 132. In some cases, the shared reference voltage 146 can be transmitted between transmitter 32 and receiver 34 via an existing IF cable such as IF cable 52 (e.g., which may be in the form of a flexible flat cable). That is, because the shared reference voltage 146 is a low-frequency DC signal, it can be multiplexed and transmitted with additional signals (e.g., low-frequency control signals and / or high-frequency signals).

[0054] As shown, a reference voltage 146 is generated within receiver 34 as a voltage reference or other suitable reference voltage source 148 and transmitted to transmitter 32. However, it should be understood that in alternative embodiments, the reference voltage 146 may be generated in transmitter 32 (or at any other location in electronics 10 outside receiver 34) and provided to receiver 34 via reference voltage cable 132. As shown, reference voltage cable 132 is coupled to a first unit gain buffer (UGB) 144 at receiver 34 and a second UGB 138 at transmitter 32. Advantageously, sharing the reference voltage 146 reduces or effectively removes the impact of voltage fluctuations on the receiver 34. Figure 3 Any mismatch (e.g., DC bias) between the reference voltages used by the transmitter 32 and receiver 34 discussed.

[0055] exist Figure 5 In the embodiments depicted, the transmitter amplifier 134 is a multi-input op-amp with multiple positive terminals. For example, amplifier 134 may have a pair of positive input terminals P1 and P2, denoted as parameters a and 1-a, respectively, which may be programmable. The first positive terminal P1 of amplifier 134 may be coupled to bias tracker 136 (e.g., a power supply / ground tracker), and the second positive terminal P2 may be coupled to unit gain buffer 138 of transmitter 32 and configured to receive a shared reference voltage signal 146. Bias tracker 136 may track power supply fluctuation 59 and ground bounce 90. In some cases, the voltage from bias tracker 136 may be the voltage between power supply fluctuation 59 and ground bounce 90 (e.g., an intermediate voltage). In some embodiments, bias tracker 136 may be implemented as one or more resistor dividers.

[0056] Figure 5 The total DC bias of the implementation scheme can be represented by the following equation 5:

[0057]

[0058] If the voltage supplied to amplifier 134 by bias tracker 136 is programmed to The power supply and ground bounce transfer functions are zero, and therefore the DC bias becomes zero. That is, the bias tracker 136 can be programmed to effectively disable the power supply fluctuation 59 and the ground bounce 90 at the output of the transmitter 32. The effectiveness of DC bias cancellation can be determined based on the resistor ratio of the input resistor (R1) 62 and the feedback resistor (R2) 64 of the TX amplifier 134. Furthermore, in some embodiments, the bandwidth of the reference voltage cable 132 may be higher than the frequency content of the ground bounce 90.

[0059] As shown in the figure Figure 5 The communication system 130 does not include Figure 3 The duplexer 71. That is, Figure 5The proposed implementation reduces or mitigates the impact of DC bias on the control signals transmitted between transmitter 32 and receiver 34. Advantageously, the shared reference voltage 146 compensates for reference voltage mismatch and thus significantly reduces or mitigates DC bias caused by reference voltage mismatch. The bias tracker 136 and the multi-input amplifier 134 compensate for and thus significantly reduce or mitigate DC bias caused by power supply fluctuations 59 and ground bounce 90. That is, the implementation presented herein significantly reduces DC bias and improves or maintains low latency and low bit error rate (BER) without additional protocol complexity. As mentioned above, the shared reference voltage 146 can be transmitted between transmitter 32 and receiver 34 via existing cables. Therefore, the implementation presented herein reduces or mitigates DC bias without additional hardware overhead.

[0060] Figure 6 According to embodiments of this disclosure, a duplexer is included in both the transmitter 32 and the receiver 34. Figure 5 A schematic diagram of the communication system 130. That is, Figure 6 The communication system 130 is basically similar to Figure 6 The communication system 130 includes a duplexer 71 in each of the transmitter 32 and the receiver 34. Figure 6 The duplexer 71 can be basically similar to the one about Figure 3 The duplexer 71 under discussion. That is, the duplexer 71 of transmitter 32 can receive an intermediate frequency transmission signal 73A (e.g., a data signal) and a control signal via amplifier 134 and terminating resistor 70. In this case, duplexer 71 can combine the signals and transmit the combined signal to receiver 34 via cable 52. The duplexer 71 of receiver 34 can receive the combined signal via cable 52 and separate the data signal from the control signal. In this case, the control signal can pass through low-pass filter 76, and the data signal 73A can pass through high-pass filter 78. In some embodiments, transmitter 32 and receiver 34 may each include high-pass filters 140, 142, so that data signal 73B can propagate between transmitter and receiver via different cables or connectors such as reference voltage cable 132.

[0061] Figure 7 It is based on the implementation scheme of this disclosure. Figure 5 and Figure 6 A schematic diagram of amplifier 134 is shown. As shown, amplifier 134 is a two-stage op-amp comprising a first stage 152 and a second stage 154. Stages 152 and 154 can be amplification stages of amplifier 134. The first stage 152 of amplifier 134 is divided into multiple (N) slices. In some embodiments, the second stage 154 can be a Class AB amplifier with Miller compensation capacitors and resistors.

[0062] Each slice of the first stage 152 receives voltages: the voltage from the bias tracker 136 and the shared reference voltage 146. Additionally, each slice of the first stage 152 includes one or more current mirrors 158. A multiplexer 156 is connected to the positive input terminals P1 and P2, corresponding to the voltage from the bias tracker 136 and the shared reference voltage 146, respectively. The multiplexer 156 outputs a single positive signal Inp 160 to the first stage 152 of the amplifier 134 based on an N-bit control signal 150. The control signal 150 allows the values ​​(a) of the bias tracker 136 at the first positive terminal P1 of the amplifier 134 and the value (1-a) of the shared reference voltage 146 at the second positive terminal P2 of the amplifier 134 to be programmed to eliminate DC bias.

[0063] In some embodiments, a first portion of a slice of the first stage 152 may be coupled to a bias tracker 136, and a second portion of a slice of the first stage 152 may be coupled to a common reference voltage 146. In some embodiments, a smaller number of slices of the first stage 152 may be coupled to the bias tracker 136 to eliminate DC bias compared to the number of slices of the first stage 152 coupled to the common reference voltage 146. For example, approximately one-third of the slices of the first stage 152 may be coupled to the bias tracker 136, and approximately two-thirds of the slices of the first stage 152 may be coupled to the common reference voltage 146. In this way, one-third of the slices of the first stage 152 may be coupled to the bias tracker 136 to eliminate DC bias compared to two-thirds of the slices of the first stage 152 coupled to the common reference voltage 146. The output 162 of the amplifier 134 may be coupled to... Figure 5 and Figure 6 52. Medium frequency cable.

[0064] Figure 8 It is shown Figure 3 and Figure 5 A graph of the power supply rejection 200 of the communication systems 50 and 130. This graph includes a horizontal axis representing frequency on a logarithmic scale and a vertical axis representing the power supply rejection ratio (e.g., the ratio of supply voltage variation to output voltage). Specifically, the graph includes curves depicting frequencies up to an inflection point frequency 206. Figure 3 The communication system 50 has a power suppression of approximately -12 dB on the first line 202 and is depicted Figure 5 and Figure 6 The communication system 130 has a second line 204 with approximately -50dB power supply suppression. That is, before the inflection point frequency 206, it uses separate TX and RX reference voltages 68 and 86. Figure 3 Compared to the communication system 50, which includes a shared reference voltage 146 and a bias tracker 136, Figure 5 and Figure 6The communication system 130 provides an improvement of approximately 40 dB in power supply rejection. After the inflection point frequency 206, Figure 5 and Figure 6 The power suppression 204 of the communication system 130 is close to Figure 3 The power supply rejection 202 of the communication system 50 is ultimately matched to the peak frequency 208. The inflection point frequency 206 can be configured to any suitable frequency, such as 500 kHz or less, 1 MHz or less, 10 MHz or less, greater than 10 MHz, etc. Similarly, the peak frequency 208 can be configured to any suitable frequency, such as 10 MHz or less, 100 MHz or less, 1 GHz or less, greater than 1 GHz, etc. Therefore, Figure 5 and Figure 6 The shared reference voltage 146 and / or bias tracker 136 reduce power supply variations (e.g., transients), thereby... Figure 3 The communication system has reduced the number of communication systems by 50. Figure 5 and Figure 6 The communication system 130 is DC biased. Furthermore, Figure 5 and Figure 6 The shared reference voltage 146 and / or bias tracker 136 can target power supply variations at lower frequencies (e.g., below the configurable inflection point frequency 206) for greater effectiveness.

[0065] Figure 9 It is shown Figure 3 as well as Figure 5 and Figure 6 A graph of ground bounce suppression 210 for communication systems 50 and 130. This graph includes a horizontal axis representing frequency on a logarithmic scale and a vertical axis representing the ground bounce suppression ratio (e.g., the ratio of ground voltage variation to output voltage). Specifically, the graph includes a first line 212, which depicts the ground bounce suppression for use with separate TX and RX reference voltages 68 and 86 (and without...). Figure 5 and Figure 6 bias tracker 136) Figure 3 The communication system 50 exhibits approximately 0 dB (zero) ground bounce suppression. A second line 214 is drawn before the inflection frequency 218 for use with a shared reference voltage 146 but without a bias tracker 136. Figure 5 and Figure 6 The communication system 130 exhibits approximately -6 dB of ground bounce suppression. A third line 216 is drawn prior to the inflection point frequency 218 for use with a shared reference voltage 146 and a bias tracker 136. Figure 5 and Figure 6 The communication system 130 exhibits approximately -46 dB of ground bounce suppression. After the inflection point frequency 218, Figure 5 and Figure 6Ground bounce suppression of communication system 130 210 proximity Figure 3 The ground bounce suppression 202 of the communication system 50 ultimately matches it at the peak frequency 220. The inflection point frequency 218 can be configured to any suitable frequency, such as 10 kHz or less, 100 kHz or less, 1 MHz or less, or greater than 1 MHz. Similarly, the peak frequency 220 can be configured to any suitable frequency, such as 10 MHz or less, 100 MHz or less, 1 GHz or less, or greater than 1 GHz.

[0066] Thus, compared to using separate TX and RX reference voltages of 68 and 86... Figure 3 Compared to the communication system 50, using a shared reference voltage 146 (but without using a bias tracker 136) can... Figure 5 and Figure 6 The ground bounce suppression of the communication system 130 (e.g., depicted by the second line 214) is improved (e.g., reduced) by approximately 6 dB before the corner frequency 218. Furthermore, compared to using separate TX and RX reference voltages 68 and 86 and without... Figure 5 and Figure 6 The bias tracker 136 of the communication system 130 Figure 3 Compared to the communication system 50, using a shared reference voltage 146 and a bias tracker 136 can... Figure 5 and Figure 6 The ground bounce suppression of the communication system 130 (e.g., depicted by the third line 216) is improved (e.g., reduced) by approximately 45 dB. Furthermore, Figure 5 and Figure 6 The shared reference voltage 146 and / or bias tracker 136 can reduce ground bounce variations at lower frequencies (e.g., below the configurable inflection point frequency 218) for greater effectiveness.

[0067] Advantageously, the embodiments presented herein provide apparatus and techniques for reducing DC bias and thus improving or maintaining low latency and low bit error rate (BER) without additional protocol complexity or hardware overhead. Specifically, the embodiments presented herein can reduce DC bias caused by reference voltage mismatch, power supply fluctuations (transients), ground bounce, etc. To this end, the embodiments presented herein include a shared reference voltage between the transmitter and the corresponding receiver, a multi-input operational amplifier, and a power supply / ground tracker.

[0068] The specific embodiments described above have been illustrated by way of example, and it should be understood that various modifications and alternatives are permissible. It should also be understood that the claims are not intended to limit us to the specific forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the substance and scope of this disclosure.

[0069] The techniques described herein and protected by the claims are referenced and applied to specific examples of physical and practical nature, which significantly improve the technical field and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing] [function]..." or "steps for [performing] [function]...", those elements shall be interpreted in accordance with 35U.SC112(f). However, for any claim containing elements designated in any other manner, those elements shall not be interpreted in accordance with 35U.SC112(f).

[0070] As is widely recognized, the use of personally identifiable information should comply with privacy policies and practices that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

Claims

1. An electronic device, comprising: The receiver includes a first unit gain buffer configured to receive a reference voltage signal; The transmitter includes: A second unit gain buffer is coupled to the first unit gain buffer of the receiver and configured to receive the reference voltage signal via the first unit gain buffer. An amplifier, the amplifier including a first positive input configured to receive the reference voltage signal via a first unit gain buffer and a second unit gain buffer. A bias tracker is coupled to the second positive input of the amplifier; and A connector that couples the first unit gain buffer of the receiver to the second unit gain buffer of the transmitter.

2. The electronic device of claim 1, wherein the bias tracker is configured to compensate for DC bias caused by power supply fluctuations and ground bounce of the power supply signal received by the amplifier.

3. The electronic device of claim 1, wherein the amplifier includes an input resistor and a feedback resistor, and the input value received by the second positive input of the amplifier is based on a first resistance value of the input resistor and a second resistance value of the feedback resistor.

4. The electronic device of claim 3, wherein the input value indicates: the first resistance value of the input resistor divided by the sum of the first resistance value of the input resistor and the second resistance value of the feedback resistor.

5. The electronic device of claim 1, wherein the receiver further comprises a first high-pass filter coupled to the first unit gain buffer, and the transmitter further comprises a second high-pass filter coupled to the second unit gain buffer.

6. The electronic device of claim 1, wherein the amplifier includes a first set of amplification stages coupled to the bias tracker and a second set of amplification stages configured to receive the reference voltage signal.

7. A transmitter, comprising: The first unit gain buffer is coupled to the second unit gain buffer of the receiver via a coupler and is configured to receive a reference voltage signal from the second unit gain buffer; The bias tracker is configured to compensate for bias caused at least in part by variations in the power supply signal and ground bounce; and The amplifier includes a first input coupled to the second unit gain buffer and a second input coupled to the bias tracker.

8. The transmitter of claim 7, wherein the first input and the second input of the amplifier include the positive input of the amplifier.

9. The transmitter of claim 7, wherein the bias tracker is configured to compensate for at least a portion of the bias.

10. The transmitter of claim 7, wherein the second input of the amplifier is configured to receive a value indicating the voltage between a change in the power supplied by the power source and the ground bounce.

11. The transmitter of claim 7, wherein the amplifier includes a multiplexer, a first set of amplification stages, and a second set of amplification stages, the multiplexer being configured such that the first set of amplification stages can receive the reference voltage signal from the receiver and couple the second set of amplification stages to the bias tracker.

12. The transmitter of claim 11, wherein the first set of amplification stages includes a first number of amplification stages, the second set of amplification stages includes a second number of amplification stages, and the first number of amplification stages is greater than the second number of amplification stages.

13. The transmitter of claim 11, wherein the output of the multiplexer is based on a control signal for programming the output of the bias tracker to compensate for the bias.

14. An electronic device, comprising: A first integrated circuit, the first integrated circuit including a receiver, the receiver including a first unit gain buffer configured to receive a reference voltage signal; A second integrated circuit, the second integrated circuit including a transmitter, the transmitter comprising: power supply, The second unit gain buffer is configured to receive the reference voltage signal from the first unit gain buffer. An amplifier, coupled to the second unit gain buffer and configured to receive a power signal from the power supply, and A bias tracker, coupled to the amplifier and configured to compensate for DC voltage bias caused at least by variations in the power supply signal; and A connector that couples the first integrated circuit to the second integrated circuit, wherein the second unit gain buffer is configured to receive the reference voltage signal from the first integrated circuit via the connector.

15. The electronic device of claim 14, wherein the power supply is coupled to the amplifier via a resistor divider.

16. The electronic device of claim 14, wherein the transmitter is configured to transmit control signals and high-frequency data signals to the receiver via the connector.

17. The electronic device of claim 14, wherein the receiver includes a first high-pass filter coupled to the first unit gain buffer, and the transmitter includes a second high-pass filter coupled to the second unit gain buffer.

18. The electronic device of claim 14, wherein the amplifier includes a multiplexer, a first set of amplification stages configured to receive the reference voltage signal, and a second set of amplification stages configured to receive a signal from the bias tracker.

19. The electronic device of claim 18, wherein the multiplexer is configured to couple the first set of amplifier stages such that the first set of amplifier stages can receive the reference voltage signal via the second unit gain buffer and that the second set of amplifier stages can receive the signal from the bias tracker.

20. The electronic device of claim 14, wherein the amplifier includes an input resistor and a feedback resistor, and the input value received by the positive input of the amplifier is based on a first resistance of the input resistor and a second resistance of the feedback resistor.

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