FPGA-based inertial navigation time synchronization system

Abstract

This application provides an FPGA-based inertial navigation time synchronization system, including a processor, an FPGA circuit, and an inertial navigation device. One end of the FPGA circuit is connected to the processor, and the other end is connected to the inertial navigation device. The inertial navigation device includes a main inertial navigation interface and a backup inertial navigation interface. The main and backup inertial navigation interfaces transmit the same data. When the main inertial navigation interface fails, the system automatically switches to the backup inertial navigation interface. The FPGA circuit includes an inertial navigation uplink data transmission link, an inertial navigation downlink data reception link, and a processor interface module. The inertial navigation uplink data transmission link is used to transmit data sent from the processor to the inertial navigation device, the inertial navigation downlink data reception link is used to parse, identify, and transmit data sent from the inertial device to the processor, and the processor interface module is used to connect to the processor. The FPGA-based inertial navigation time synchronization system provided in this application has the advantages of high data transmission reliability, low processor occupancy, and small time deviation.

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