Method for simultaneous data transmission and distance measurement

Abstract

The invention relates to a method for simultaneous data transmission and distance measurement between a first device and a second device, wherein the first device and the second device each have a transmission device configured for optical data transmission, a receiving device configured for optical data reception and a control unit coupled to the transmission device and the receiving device and / or at least partially integrated with the transmission device and the receiving device, wherein a data signal is transmitted from the first device to the second device. The method is characterized in that a receiving clock signal is generated from the data signal and indicates clock information of the data signal, wherein a phase position of the receiving clock signal is determined and the distance between the first device and the second device is determined from the phase position.

Description

Technical Field

[0001] This invention relates to a method for simultaneously performing data transmission and distance measurement between a first device and a second device, wherein each of the first and second devices has a transmission device configured for optical data transmission, a receiving device configured for optical data reception, and a control unit coupled to and / or at least partially integrated with the transmission and receiving devices. In this respect, data signals are transmitted from the first device to the second device. Background Technology

[0002] For example, methods for simultaneously transmitting data and measuring distances are used in high-rise warehouses. Specifically, autonomous vehicles (e.g., storage and retrieval units, SRUs) establish continuous data connections with base stations to transmit control and / or sensor data between the base station and the autonomous vehicle, while simultaneously determining the vehicle's location (i.e., its distance from the base station) as accurately as possible.

[0003] For example, a method for simultaneously transmitting data and measuring distance is known from DE102014111589A1. In this method, the system clock is intentionally offset and extensive oversampling is performed to achieve accurate distance measurement.

[0004] However, this procedure is only possible at low data rates, because if the data rate in the data signal is too high, significant oversampling is usually no longer possible. Summary of the Invention

[0005] Therefore, the fundamental objective of this invention is to clearly demonstrate a method for simultaneously transmitting data and measuring distance, which enables highly accurate distance measurement even at high data rates (e.g., at least 1 gigabit per second (1 Gbit / s)).

[0006] This objective can be achieved by the method according to claim 1.

[0007] According to the method of the invention, the clock signal is generated from the data signal (in particular by the second device) and indicates the clock information of the data signal, wherein the phase position of the received clock signal is determined, and the distance between the first device and the second device is determined, in particular, at least according to the phase position.

[0008] This invention is based on the understanding that by using only the clock information of the data signal, rather than the data signal itself, very accurate distance measurement is possible even at high data rates. Furthermore, according to the invention, the hardware typically required for receiving such data signals can also be used for distance measurement, and particularly for the generation of the receiving clock signal, which is advantageous.

[0009] Further details of the present invention will now be described.

[0010] The method according to the invention is used for simultaneous data transmission and distance measurement between a first device and a second device. The first device may be, for example, the base station mentioned above, and the second device may be a device attached to an autonomous vehicle. However, in principle, the first device and the second device can have exactly the same design.

[0011] The first and second devices can be separated by a maximum distance of 100 m, 300 m, or 500 m, for example. Each device includes a transmitting device configured for optical data transmission and a receiving device configured for optical data reception. The transmitting and receiving devices can also be configured as units and can form a transceiver. The transmitting and receiving devices (or transceivers) are coupled to a control unit via a data connection and / or at least partially integrated into the control unit. For example, the optical transmitter (e.g., a laser diode or LED) of the transmitting device and the optical receiver (e.g., a photodiode) of the receiving device can be coupled to the control unit and can be connected, for example, to an output or input of the control unit. The generation of signals for the optical transmitter and / or the processing of signals for the optical receiver can be performed in the control unit, i.e., in an integrated manner.

[0012] During equipment operation, data signals are optically transmitted from the first device to the second device. Additionally, the second device may also optically transmit data signals to the first device. The data signals are optically transmitted by the corresponding transmission device and optically received by the receiving device of the corresponding other device.

[0013] The data signals (and further data signals described below) particularly include application data, such as control data or sensor data for (autonomous) vehicles. Preferably, the data signal transmitted from the first device to the second device is different from the data signal transmitted from the second device to the first device. Therefore, the data signal is not merely reflected on the first or second device. The transmission of information carrying data signals between devices can be encoded in binary by on-off keying (OOK), i.e., when a binary 1 is transmitted, the optical transmitter device is turned on; when a binary 0 is transmitted, the optical transmitter device is turned off. The optical transmitter can be configured as a laser, particularly a laser diode.

[0014] The data signal preferably includes a serial data signal, especially data for the purpose described above.

[0015] Preferably, data transmission and distance measurement are achieved using only a single communication channel (i.e., an optical data transmission communication channel between the two devices). The two devices are connected point-to-point. In particular, there is a direct line-of-sight connection between the two devices.

[0016] For distance measurement, the time required for data bits of a data signal to travel from the first device to the second device (or vice versa) can be determined. The distance between the first and second devices can then be determined based on the constant propagation speed of the data signal transmitted by light (i.e., the speed of light), for example, by one of the correspondingly designed control units.

[0017] According to the present invention, a received clock signal is generated or reconstructed based on a data signal. The received clock signal preferably includes clock information of the data signal, i.e., time information. For example, in the case of a serial signal, the clock information or time information enables the reconstruction of the serial signal in the receiving device and / or the control unit of the receiving device. The received clock signal may, for example, be a square wave signal, whose edges indicate the time position of each data bit in the data signal. According to the present invention, the phase position of the received clock signal is typically determined and / or evaluated, wherein the phase position can be determined, for example, by evaluating the position of the edges of the received clock signal.

[0018] Because the determination or evaluation of phase position according to the present invention can determine the distance between the first and second devices with significantly greater accuracy than, for example, by evaluating only transmitted symbols, bytes, words, or timestamps. The determined distance can then be output as a distance signal by at least one of the devices, and can be used, in particular, when operating the device or in a vehicle equipped with the device.

[0019] The generation of the receive clock signal and / or the evaluation of its phase position, as required by the present invention, can be performed partially or entirely in the control unit. The data signal upon which the receive clock signal is based preferably has a data rate of at least 1 gigabits per second or at least 1.3 gigabits per second.

[0020] Advantageous embodiments of the present invention can be seen from the description, drawings and dependent claims.

[0021] According to the first embodiment, the received clock signal includes a clock data recovery (CDR) signal. For example, the CDR signal can be generated by a PLL (phase-locked loop) circuit.

[0022] The unit that generates the CDR signal can be located in the receiving unit and / or control unit, and can reconstruct the serial signal in the data signal at the receiving end.

[0023] The received clock signal can be a direct CDR signal, can include a CDR signal, or can be derived from a CDR signal. Preferably, the received clock signal does not contain any data of any use from the data signal. For example, the received clock signal can be a square wave signal without data information. The square wave signal, for example, can simply consist of identical square wave pulses repeated at the same intervals.

[0024] In contrast to receiving clock signals, data signals therefore include applicable data that can be modulated onto the data signal.

[0025] According to a further embodiment, the received clock signal (at its frequency) is divided by a predetermined factor, preferably by a serial-to-parallel converter. A frequency divider can also be used as an alternative or supplement to the serial-to-parallel converter. For example, the serial-to-parallel converter can be a 20-bit converter. The frequency of the received clock signal or the frequency at which the edges of the received clock signal occur can be divided by the 20-bit converter by a predetermined factor (e.g., 20 in this example).

[0026] The pre-determinant factor can take values ​​other than 20, such as 5, 10, 15, 25, 36, 50, 64, 100, or 132. Specifically, the pre-determinant factor is the number of bits used to encode a data word or byte in the (optical) data signal. The pre-determinant factor can also be between half and twice the aforementioned values. When using the 8B10B encoding method (discussed later), the data word is represented by two bytes, so that in each case the data word is encoded with 20 bits, and in this case, the pre-determinant factor is 20.

[0027] Dividing the received clock signal by a predetermined factor is particularly helpful in simplifying subsequent sampling of the received clock signal, as will be described later.

[0028] According to a further embodiment, the received clock signal is output to the control unit and then keyed in again, preferably from the input of the (same) control unit. Specifically, the control unit can be an FPGA (Field-Programmable Gate Array), particularly a single FPGA; it can also be an ASIC (Application-Specific Integrated Circuit), particularly a single ASIC; or it is typically an integrated circuit, particularly a single integrated circuit. The output and input of the control unit can be, for example, an output pin or an input pin. Alternatively, the output of the control unit (e.g., an output pin) can be sampled or keyed in directly, so that the received clock signal does not need to be physically routed outside the control unit.

[0029] The output receiving the clock signal and the subsequent return or rekeying input have the advantage of having suitable hardware that can be used in the control unit for phase position detection, thereby achieving very high-resolution detection that is typically only available at a dedicated input of the control unit. Therefore, the output and input of the control unit can belong to the same integrated circuit.

[0030] Alternatively, the input can be located at another integrated circuit, such as an external evaluation unit, to transmit the received clock signal to the external evaluation unit.

[0031] According to a further embodiment, the received clock signal includes multiple edges, wherein at least two, preferably three, and particularly preferably four edges are sampled and / or evaluated to determine the phase position.

[0032] Specifically, the aforementioned multiple edges are sampled in combination during a single sampling process (e.g., simultaneously sampled and / or sampled as a common signal).

[0033] The number of edges mentioned above can be a minimum, but it is also possible that in every case it is exactly the prescribed number of edges for sampling and / or evaluation. Similarly, it is conceivable to have a larger number of edges, such as 6, 8, 10, 15, 20, 32, or even 64 edges, and the treatment is the same.

[0034] According to a further embodiment, before the phase position is determined, the edge steepness of the received clock signal (particularly all) is reduced, preferably by using a delay element. Thus, the slope steepness of the received clock signal edges is artificially or intentionally reduced. The purpose of this is to enable mapping more sampling points along the edges.

[0035] Specifically, the control unit can be configured to sample the corresponding edges of the received clock signal at multiple sampling points, for example, sampling at the corresponding edges with at least four, eight, or twelve sampling points.

[0036] In addition to delay elements (such as I / O delay blocks), or as an alternative to delay elements, operational amplifiers, logic gates, or the like can be used to reduce edge steepness.

[0037] The received clock signal may be alternatively or additionally provided with synthetic jitter due to delay elements and / or additional jitter units to reduce the edge steepness of the received clock signal. For example, the synthetic jitter may be configurable, for example, set in the range of 4ps to 60ps or 2ps to 100ps. The synthetic jitter can be varied between different sampling processes to determine the phase position. Since the magnitude of the synthetic jitter is known, it can be taken into account (e.g., calculated) when determining the phase position. By varying the synthetic jitter, the edges can be slightly offset in different sampling processes so that the sampling point can be located before and after the edge, or directly on the edge.

[0038] Specifically, sampling points can therefore be generated on the edges, these sampling points not only corresponding to the value of the clock signal received before or after the edge (e.g., 0 or 1), but also taking intermediate values, i.e., representing "analog" values. For example, due to the intermediate values, the position of the edge can be determined even more precisely; for example, the position of the zero-crossing point can be determined more precisely using the intermediate values ​​(e.g., corresponding to...). Figure 4 (N / 2 threshold in the text).

[0039] According to a further embodiment, at least one sampling process, particularly binary sampling, is performed to determine the phase position, wherein preferably, in each case, multiple edges of the received clock signal are sampled simultaneously or together, preferably by a double data rate circuit (DDR circuit).

[0040] The phase position is determined by the sampling process, specifically by determining the exact time position of one or more edges of the received clock signal.

[0041] Both falling and rising edges can be detected using DDR circuitry. For example, four clocks can be sampled or evaluated together. Therefore, four clocks with two edges can be sampled at 8 times the sampling rate. This 8 times sampling rate should be particularly noted when compared to the computing unit's sampling clock or system clock. For example, assuming the computing unit's system clock is 390MHz, at 8 times the sampling rate, it can be sampled at an effective sampling rate of 3.12 gigabits per second. This allows for very precise sampling, thus enabling the determination of phase positions.

[0042] For example, an 8x sampling rate can be achieved in particular by sampling at staggered times in each case, in addition to the preferred predefined times via the system clock or sampling clock. Generally, the device can be configured, for example, to generate multiple (e.g., four) additional signals from the sampling clock or system clock via further PLL circuitry, these additional signals being phase-shifted relative to the sampling clock or system clock, and then used similarly to sample the edges of the received clock signal. The phase shift of the additional signals can, in particular, be 45°, 90°, 135°, 225°, 270°, and / or 315°. The phase shift of the additional signals can be generated, for example, by SERDES cells (serializer-deserializer cells) available in many FPGAs. Due to the additional signals, the received clock signal can be sampled, and in particular, multiple edges can be sampled in combination.

[0043] Generally speaking, the sampling rate, especially the effective sampling rate, can be greater than 1 gigabyte per second, 2 gigabytes per second, or 3 gigabytes per second.

[0044] According to a further embodiment, the final phase position is generated based on the phase position determined in multiple sampling processes, particularly by forming a histogram.

[0045] Specifically, sampling points are accumulated (preferably coherently accumulated) to form a system clock or sampling clock. A predetermined time sequence of the received clock signal (e.g., a predetermined number of clock cycles, i.e., combinations of edges) is sampled, for example, the sampling is repeated N times. In this respect, in each sampling process, at time point t (0…n), the binary state is accumulated at time point t. This produces a histogram of depth N. Preferably, the distance between the first and second devices is (at least) determined based on the final phase position. Therefore, the final phase position should be understood as a result of the determination of the phase position. The final phase position is then incorporated into the determination or calculation of the distance between the first and second devices.

[0046] Specifically, the histogram is generated by (preferably coherently) accumulating multiple sampling processes over a measurement interval (e.g., 10 µs). During the accumulation process, edge locations, particularly those from a large number of sampling processes, are input into the histogram. Specifically, the histogram may include, for example, 10, 100, or 1000 sampling processes.

[0047] For example, the corresponding four edges can be sampled in a single sampling process and input into a histogram. Specifically, the phase position can then be determined, for example, based on the third rising edge in the histogram. The final phase position is thus defined, for example, by the third rising edge.

[0048] In principle, however, the distance can also be determined based on the phase position that exists after the corresponding processing steps, but it is preferred to determine the distance based on the final phase position.

[0049] The sampling of multiple edges, as further described above, is advantageous because the sequence (falling edge / rising edge) repeats after one clock cycle of the received clock signal. If the coarse measurement (described further below) varies based on the transmission and reception times (e.g., in the least significant bit (LSB), it is preferable to take this into account in the phase measurement by switching to different rising edges to determine the final phase position. Since this switching can occur in both the positive and negative directions, it is advantageous if the combination includes at least three edges (rising edges).

[0050] Preferably, the distance between the first and second devices is determined repeatedly, for example, at least every 1µs, every 10µs, or every 100µs. These times are short enough that phase drift of the system clock will not cause any related distortion in the distance measurement. Specifically, the first and second devices always remain within each other's line of sight in each case, allowing for continuous distance measurements. If the position of the edge used for distance determination shifts in the histogram, a new distance value is generated. If the shift in the position of the edge used for distance determination in the histogram is so great that the edge moves to the edge of the histogram or even disappears from the histogram, the adjacent edge (rising edge) is used to determine the distance.

[0051] According to a further embodiment, the distance between the first device and the second device is also determined based on characters encoded in the data signal.

[0052] Since distance is determined based on the phase position of the received clock signal, very precise distance measurements can be performed; however, for larger distances, the results may be ambiguous. Therefore, to generate a more precise distance, a (coarser) distance measurement based on the encoded characters in the data signal can also be used. This can be done, for example, via timestamp switching, which will be described in more detail below. If we assume the time resolution of timestamp switching is one-third of the system clock (390 MHz / 3 = 130 MHz), then the time resolution is 7.7 ns. This corresponds to a distance resolution of 2.3 m.

[0053] In data signals, transmitted characters can exist, for example, in the form of encoded data words, particularly using the 8B10B encoding method. The advantage of this encoding is that the optical signal has no DC component. Alternatively, for example, 16B18B or 64B66B codes can also be used for optical data transmission between the first and second devices. Generally, different encoding methods without DC components can also be selected.

[0054] According to a further embodiment, determining the distance based on the encoded characters in the data signal includes the following steps:

[0055] - The first device transmits a first data signal to the second device, the first data signal including and / or defining the transmission time point t of the first data signal. SycA (as encoded characters)

[0056] - The second device stores the time point t of receiving the first data signal. RecB ,

[0057] - The second device transmits a second data signal to the first device, the second data signal including and / or defining the transmission time point t of the second data signal. SycB (as encoded characters)

[0058] - The first device stores the receiving time point t of the second data signal. RecA .

[0059] Reception time point t RecA and t RecB It can be transmitted to other corresponding devices, preferably via data signals. Specifically, the transmission time point can be defined (i.e. determined) by transmitting data signals, and the transmission time point can only be subsequently transmitted to the other corresponding devices.

[0060] Generally, these two devices can exchange receive and / or transmit time points via data signals. For example, the receive and / or transmit time points can also be exchanged within the same grid (i.e., within the same time interval), with the distance between the two devices determined based on the phase position of the received clock signal (e.g., 10µs). The receive and / or transmit time points are, for example, counter readings generated by the system clock. Due to the synchronicity of the exchange of receive and / or transmit time points and the determination of the phase position, the distance between the two devices can be determined with particularly high precision.

[0061] Flight time can be calculated using the following formula:

[0062] [Formula 1]

[0063] TOF_A = 1 / 2 [(t RecA – tSycB ) + (t RecB – t SycA )).

[0064] The distance between the devices can then be determined by multiplying the time of flight by the speed of light.

[0065] It is understood that in the above procedure, the first device and the second device can be interchanged in each case.

[0066] Due to component tolerances and other factors, the time bases of the first and second devices may differ. The offset between the time bases of the first and second devices can be calculated using the following formula:

[0067] [Formula 2]

[0068] Offset = 1 / 2 [(t RecA – t SycB ) – (t RecB - t SycA )).

[0069] Distance measurements based on transmission and reception times can be described as coarse measurements, while distance measurements based on the received clock signal can represent fine measurements.

[0070] Due to the coarse measurement, a general distance range can be defined for the first and second devices. Based on the distance measurement on the received clock signal, the correct distance can then be determined in this way within the defined distance "window". Therefore, an ambiguous fine measurement based on the received clock signal can be made clear through a coarse measurement.

[0071] A special comma word can be transmitted to initialize distance measurements, establishing a connection between the first and second devices. Since the two transmitting and receiving devices preferably always see each other in normal or linear travel mode, thus ensuring continuous data signal exchange, the rising edge to be evaluated in the histogram only needs to be determined once during connection establishment. To evaluate the correct edge during resynchronization as well, a double-speed clock for timestamp exchange needs to be generated at the beginning, or this uniqueness can be established using dual measurements and phase shift periods. A double-speed clock can be implemented, for example, by temporarily using a double count rate on counter readings indicating transmission and / or reception times.

[0072] Because of phase drift between the system clocks of the two devices, the histogram may become blurred. Since this is undesirable, the first and second devices can be configured such that the phase drift of the system clocks of the first and second devices is less than 200 ps, ​​preferably less than 100 ps, ​​and more preferably less than 50 ps, ​​within a 10µs measurement interval.

[0073] To compensate for errors in the determined distance caused by phase drift between system clocks, the two devices can each independently determine the distance between the first and second devices, then exchange the determined distance via data signals, and form an average of the two distance values.

[0074] According to a further embodiment, the reception of the data signal, the generation of the receive clock signal, and the determination of the phase position of the receive clock signal are all performed by the same control unit, and particularly by the same FPGA. Alternatively, as described, an ASIC or another integrated circuit can be used instead of the FPGA.

[0075] Because the same control unit is used, both distance determination and phase position detection based on the encoded character data signal can be performed using the same system clock of the control unit. This reduces errors caused by clock differences, which in turn improves the accuracy of distance measurement and reduces hardware requirements.

[0076] Furthermore, the present invention relates to an apparatus for simultaneously performing data transmission and distance measurement, wherein the apparatus has a transmission device configured for optical data transmission, a receiving device configured for optical data reception, and a control unit coupled to and / or at least partially integrated with the transmission and receiving devices, wherein the apparatus is configured to receive data signals from a second device, particularly through the receiving device. According to the invention, the apparatus is configured to generate a received clock signal from the data signal indicating clock information of the data signal, wherein the apparatus is further configured to determine the phase position of the received clock signal and determine the distance between the apparatus and the second device, particularly determining the distance between the apparatus and the second device at least based on the phase position.

[0077] A further subject of the invention is a system comprising two devices of the aforementioned type, one device serving as a first device and the other as a second device. The first and second devices can be arranged such that they are within direct line of sight of each other. At least one of the devices can be mounted on a vehicle, particularly an autonomous vehicle.

[0078] In this system, an additional communication channel can be provided between the first and second devices for temperature compensation, specifically for compensating for temperature drift of the system clocks relative to each other. For example, this additional channel can also be configured for optical data transmission or radio data transmission. Since the temperature drift is compensated for, differences in the system clocks of the devices can be further compensated for, thereby enabling even more accurate distance measurements. For example, the corresponding device temperature and / or a correction value for the device temperature can be transmitted via the additional channel. Temperature drift can then be compensated for based on these values.

[0079] The description of the method according to the invention applies accordingly to the device and system according to the invention. This is particularly true of the embodiments and advantages. Furthermore, it is understood that all features mentioned herein may be combined with each other unless otherwise expressly stated. Attached Figure Description

[0080] The invention will now be described by way of example only with reference to the accompanying drawings. The drawings show:

[0081] Figure 1 This is a schematic representation of an unmanned transportation system;

[0082] Figure 2 This diagram illustrates the internal design of a device used for distance measurement.

[0083] Figure 3 The transmission of data signals used for distance measurement is shown; and

[0084] Figure 4 This shows a histogram used to record the position of the edge. Detailed Implementation

[0085] Figure 1 An unmanned transportation system 10 is schematically shown, which includes a storage and retrieval unit (SRU) 12 as an unmanned transportation vehicle. A first device 14 is attached to the SRU 12 and includes a first transmission device 16 and a first receiving device 18. The first transmission device 16 has a light source 17 in the form of a laser diode or LED, such as... Figure 2 As shown. The first receiving device 18 includes a photodiode-type light receiver 19, such as... Figure 2 As shown. The first transmitting device 16 and the first receiving device 18 together form a transceiver 20.

[0086] The first device also includes a control unit 22 (such as...) Figure 2 As shown), the control unit includes at least a transceiver 20.

[0087] For example, the second device 26 is fixedly attached to the wall 24. The design of the second device 26 is the same as that of the first device 14, and accordingly includes a second transmitting device 28, a second receiving device 30, and a control unit (not shown).

[0088] The first device 14 and the second device 26 are oriented such that the first transmitting device 16 transmits a data signal 32a transmitted via a light beam to the second receiving device 30. Correspondingly, the second transmitting device 28 transmits a second data signal 32b to the first receiving device 18. In particular, the optical data signal 32 may have a data rate of 1.3 gigabits per second.

[0089] The first data signal 32a and the second data signal 32b together form a transmission channel 34, through which application data encoded in binary mode, such as square wave pulses, is transmitted.

[0090] Figure 2 The first device 14 and the second device 26 are now shown in more detail. Specifically, the internal design of the second device 26 will be shown in more detail. The second device 26 includes the aforementioned light source 17 for transmitting data signal 32, which is coupled via amplifier 36 to an 8B10B encoder 38, which encodes the data signal generated by the control unit 22 into 8B10B format.

[0091] In order to receive optical data signals from the first device 14, the second device 26 includes an optical receiver 19, which is coupled to a CDR block 40 (clock data recovery block) via an amplifier 36. The CDR block 40 extracts a receive clock signal 42 from the data signal 32, the receive clock signal 42 having an initial frequency of 1.3 GHz, corresponding to the data rate of the data signal 32.

[0092] CDR block 40 also generates a serial data stream, which is decoded back to the format originally used by the first device by 8B10B decoder 44. Then, the reception or transmission time point can be determined based on the signal decoded in this way, for example, t. RecA .

[0093] The received clock signal 42 is transmitted to a 20-bit serial-to-parallel converter 46. The serial-to-parallel converter 46 divides the received clock signal by a factor of 20, so that the received clock signal 42 is now presented at a frequency of 65 MHz. Then, the received clock signal 42 is output from the control unit 22 via the output pin 48 and is again directly keyed into the control unit 22 via the input pin 50. For this purpose, the output pin 48 and the input pin 50 can be directly electrically connected together.

[0094] The received clock signal 42 is then sent from input pin 50 to delay element 52, and subsequently amplified again by amplifier 36. Delay element 52 causes an intentional or artificial reduction in the edge steepness of the edges contained in the received clock signal 42.

[0095] Finally, the received clock signal 42 is sent to the DDR circuit 54, which uses the two edges of the received clock signal to sample the corresponding four clocks, thereby obtaining a sampling rate of 3.12 gigabits per second (eight times higher than the 390 MHz clock).

[0096] To sample the received clock signal 42, the DDR circuit 54 receives the clock signal generated by the clock generator 60 of the control unit 22. The clock signal is also sent to a counter 62, which serves as the internal clock for the corresponding devices 14 and 26. The counter 62 can also be used to determine the transmission time point of transmitted or received data. Figure 2 t in SycA ) or the receiving time point (t) RecA ).

[0097] For example, the sampling edges are plotted in histogram 56 with a sampling period of 10 µs. Figure 4 A more detailed illustration of this histogram 56 is provided. Four rising edges are input into histogram 56. An N / 2 threshold 58 is plotted in histogram 56. The position of the corresponding edge is determined by interpolation to the intersection with the N / 2 threshold 58, thus achieving a resolution accurate to the picosecond level. Specifically, as... Figure 4 As shown, recording can be performed on the third rising edge. The position of this edge can then indicate the final phase position.

[0098] Since the position of the edge of the received clock signal 42 is determined, the phase position of the received clock signal 42 can be known, and thus the distance between the first device 14 and the second device 26 can be precisely measured using the phase position. Because the phase measurement (or histogram) includes four edges, the total measurement range of the phase measurement can be, for example, 4 x 15.4 ns, or 4 x 4.6 m. This is larger than the ambiguous range of the coarse measurement described later.

[0099] Now refer to Figure 3 Describes a rough measurement. Figure 3 In the example shown, the coarse measurement is initiated by the second device 26. For simplicity, and using the same formulas as specified above, the second device 26 will be referred to as device A and the first device 14 as device B below.

[0100] exist Figure 3As can be seen, the time bases of the first device 14 and the second device 26 are different. At the time point of 0 ns in the second device 26, the internal clock of the first device 14 is already 68 ns.

[0101] For the purpose of making a rough measurement, the second device 26 (i.e., device A) at time point t SycA (0 ns) A first data signal 32a is sent to the first device. The first data signal is received by the first device 14 after 30 ns, and then the internal clock of the first device 14 is 98 ns. In the first device 14, this time point is stored as t. RecB Then, the first device sends a second data signal 32b to the second device 26 after 10 ns, wherein the transmission time of the second data signal 32b is stored as t. SycB (108ns), and the receiving time point (70ns) is stored as t. RecA .

[0102] Using the transmission and reception times determined in this way, the flight time of data signal 32 can be determined by the following formula:

[0103] TOF_A = 1 / 2 [(t RecA – t SycB ) + (t RecB – t SycA )).

[0104] In this example, the light propagation time is 30 ns. For example, if the time resolution of timestamp exchange is 7.7 ns, then the error in coarse measurement or distance resolution in this respect might be in the range of 2.3 m.

[0105] By using histograms for finer measurements, such as achieving an accuracy of 10 ps, ​​the distance resolution can be improved to 3 mm. Therefore, it is possible to significantly improve distance resolution while achieving extremely high data rates.

[0106] Reference Number List

[0107] 10. Transportation System

[0108] 12 SRU

[0109] 14 First Equipment

[0110] 16 First Transmission Device

[0111] 17 Light Source

[0112] 18 First Receiving Device

[0113] 19 Optical Receiver

[0114] 20 transceivers

[0115] 22 Control Unit

[0116] 24 wall

[0117] 26 Second Equipment

[0118] 28 Second transmission device

[0119] 30 Second Receiving Device

[0120] 32 Data Signals

[0121] 34 transmission channels

[0122] 36 Amplifier

[0123] 38 8B10B encoder

[0124] 40 CDR blocks

[0125] 42 Receive clock signal

[0126] 44 8B10B decoder

[0127] 46 Serial-to-Parallel Converter

[0128] 48 output pins

[0129] 50 input pins

[0130] 52 Delay Components

[0131] 54 DDR circuit

[0132] 56 Histogram

[0133] 58 N / 2 threshold

[0134] 60 Clock Generator

[0135] 62-counter

Claims

1. A method for simultaneously transmitting data and measuring distance between a first device (14) and a second device (26), wherein, The first device (14) and the second device (26) each have a transmission device (16, 28) configured for optical data transmission, a receiving device (18, 30) configured for optical data reception, and a control unit (22) coupled to the transmission device (16, 28) and the receiving device (18, 30) and / or at least partially integrated with the transmission device (16, 28) and the receiving device (18, 30), wherein a data signal (32) is transmitted from the first device (14) to the second device (26). Its features are, A receive clock signal (42) generates and indicates clock information of the data signal (32) from the data signal (32), wherein the phase position of the receive clock signal (42) is determined, and the distance between the first device (14) and the second device (26) is determined according to the phase position.

2. The method according to claim 1, in, The received clock signal (42) includes or is based on a clock data recovery signal (CDR signal).

3. The method according to claim 1 or 2, in, The received clock signal (42) is divided by a predetermined factor, preferably by a serial-to-parallel converter (46).

4. The method according to any one of the preceding claims, in, The received clock signal (42) is output at the output (48) of the control unit (22), and preferably is keyed again at the input (50) of the control unit (22).

5. The method according to any one of the preceding claims, in, The received clock signal (42) includes multiple edges, wherein at least two, preferably three, and especially preferably four edges are sampled and / or evaluated to determine the phase position.

6. The method according to claim 5, in, Before the phase position is determined, the edge steepness of the received clock signal (42) is reduced, preferably by means of a delay element (52).

7. The method according to any one of the preceding claims, in, At least one sampling process, particularly binary sampling, is performed to determine the phase position, wherein preferably, in each case, multiple clocks and / or edges of the received clock signal (42) are sampled simultaneously or together, preferably by a double data rate circuit (DDR circuit (54)).

8. The method according to any one of the preceding claims, in, Based on the phase positions determined in multiple sampling processes, particularly by forming a histogram, a final phase position is generated, and the distance between the first device (14) and the second device (26) is determined based on the final phase position.

9. The method according to any one of the preceding claims, in, The distance between the first device (14) and the second device (26) is also determined based on the characters encoded in the data signal (32).

10. The method according to claim 9, in, In order to determine the distance based on the characters encoded in the data signal (32), - The first device (14) transmits a first data signal (32) to the second device (26), the first data signal (32) including and / or defining the transmission time point t of the first data signal (32). SycA , - The second device (26) stores the receiving time point t of the first data signal (32). RecB , - The second device (26) transmits a second data signal (32) to the first device (14), the second data signal (32) including and / or defining the transmission time point t of the second data signal (32). SycB , - The first device (14) stores the receiving time point t of the second data signal (32). RecA .

11. The method according to any one of the preceding claims, in, The reception of the data signal (32), the generation of the received clock signal (42), and the determination of the phase position of the received clock signal (42) are all performed via the same control unit (22), and especially via the same FPGA.

12. A device (14) for simultaneously performing data transmission and distance measurement, wherein, The device has a transmission device (16, 28) configured for optical data transmission, a receiving device (18, 30) configured for optical data reception, and a control unit (22) coupled to the transmission device (16, 28) and the receiving device (18, 30), wherein the device is configured to receive a data signal (32) from the second device (26). Its features are, The device (14) is configured to generate a received clock signal (42) from the data signal (32) indicating clock information of the data signal (32), wherein the device is further configured to determine the phase position of the received clock signal (42) and determine the distance between the first device (14) and the second device (26) based on the phase position.

13. A system comprising two devices (14, 26) according to claim 12, wherein one device serves as the second device (26).

Images