A hardware-based wireless communication precise transmission time control system and method

Abstract

The application discloses a kind of hardware-based wireless communication accurate sending time control system and method, it is related to wireless communication technical field.The system is integrated in the hardware MAC module of wireless communication equipment, high-precision clock, sending descriptor queue, time sorting unit and time-aware dispatcher.Software pre-submitted sending descriptor includes earliest sending time and latest sending time stamp.Time sorting unit is sorted according to EST descriptor automatically;Time-aware dispatcher is triggered to send based on high-precision clock only when current time meets EST and does not exceed LST, and provides two configurable retransmission management modes of conservative pre-detection and aggressive runtime abort, ensure that all transmission behaviors are strictly limited within the allocated TDMA time slot.The application completely eliminates software scheduling jitter, realizes nanosecond-level sending accuracy, rigidly guarantees TDMA time slot boundary, greatly reduces CPU overhead, and has fault safety mechanism.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and more specifically to a hardware-based precise transmission time control system and method for wireless communication. Background Technology

[0002] In applications with extremely high real-time requirements, such as industrial automation, remote control, and motion synchronization, wireless TDMA systems are widely used to provide deterministic data transmission services. The core of TDMA technology lies in dividing communication time into periodically repeating frames, each frame further divided into several fixed-length time slots. All devices in the network share a precise global clock, and each device must complete data transmission within its strictly allocated time slot. This mechanism aims to avoid signal collisions between different devices, ensuring predictable data transmission and low latency.

[0003] However, achieving precise transmission timing control in traditional software-based wireless communication systems faces significant challenges, primarily in the following three aspects:

[0004] Uncertainty in software scheduling: Traditional sending processes are entirely initiated by software (CPU). In general-purpose non-real-time operating systems (such as Linux), from the time the software generates a send command to its execution by the CPU, there are interrupt delays, context switching, and process scheduling involved. The jitter introduced by these processes is unpredictable and can typically reach the millisecond (ms) level. Even in real-time operating systems (RTOS), due to interference from other high-priority tasks or interrupts, this jitter is difficult to stably control below the microsecond (µs) level.

[0005] Uncertainty in protocol stack processing: Data frames are submitted from user-space applications to the underlying wireless hardware (MAC / PHY) for transmission, requiring them to traverse multiple protocol layers of the operating system kernel (such as the Socket interface, network protocol stack, driver interface, etc.). The time consumption of data copying, encapsulation / decapsulation, and other operations in this process also fluctuates, further exacerbating the uncertainty of transmission timing.

[0006] Uncertainty in wireless retransmission: This is a unique challenge in the field of wireless communication. Because wireless channels are susceptible to interference and packet transmission failure rates are high, retransmission mechanisms such as Automatic Repeat Request (ARQ) are commonly used to ensure reliability. A successful transmission may only take 0.5ms, but if channel conditions are poor and three retransmissions occur, the total time could become 2.0ms. This unpredictable number of retransmissions, dynamically determined by channel conditions, makes it extremely difficult for software to accurately predict when a data frame will be completely transmitted.

[0007] As per the appendix of this invention Figure 1As shown, in existing technology, the software attempts to initiate a transmission command at the start of the time slot (T_start). However, due to operating system scheduling jitter, the actual start time of hardware transmission is delayed to T_jitter. More seriously, due to multiple retransmissions during the transmission process, the end time of the entire transmission process overflows the time slot end time (T_end) originally allocated to this device, encroaching on the TDMA time slot allocated to the next device. This not only causes data transmission failure for this device but also interferes with the normal communication of other devices in the network, compromising the determinism of the entire network.

[0008] In summary, the pressing technical problem to be solved in this field is: how to design a hardware transmission control mechanism that is independent of software scheduling jitter and can actively manage and constrain the uncertainty of wireless retransmission, so as to ensure that the boundaries of TDMA time slots are rigidly adhered to, and fundamentally eliminate time slot overflow and signal collisions. Summary of the Invention

[0009] To address the problems in existing technologies where software scheduling jitter and wireless retransmissions lead to inaccurate TDMA transmission timing, easily causing time slot overflow and signal collisions, this invention aims to provide a hardware-based precise transmission timing control system and method for wireless communication. The core objective of this invention is to introduce a time-aware scheduler at the hardware MAC layer, taking over the transmission decision-making power from software, achieving ultra-high precision triggering of data frame transmission, and actively managing retransmission behavior based on configurable strategies to ensure that all transmission activities are strictly limited within the allocated time slot window.

[0010] To solve the above-mentioned technical problems, embodiments of the present invention provide the following technical solution: a hardware-based wireless communication precise transmission time control system, comprising:

[0011] A clock, used to provide a current global timestamp synchronized with the network's master clock;

[0012] A send descriptor queue is used to store send descriptors submitted by software, wherein the send descriptor contains at least a data frame pointer, an earliest send time EST, and a latest send time LST;

[0013] A time sorting unit, connected to the send descriptor queue, is used to automatically insert the send descriptor into the correct time position in the queue according to the value of its earliest send time (EST) field when the send descriptor is added to the queue, so that the send descriptors in the queue are arranged in order of EST from earliest to latest.

[0014] A time-aware scheduler, connected to the high-precision clock, the transmit descriptor queue, and the physical layer, is configured to: continuously compare the current global timestamp with the earliest transmission time (EST) of the transmit descriptor at the head of the transmit descriptor queue; and trigger the transmission process of the data frame corresponding to the transmit descriptor when the current global timestamp is greater than or equal to the EST. Simultaneously, the time-aware scheduler is also configured to perform a check based on the latest transmission time (LST) before triggering transmission or retransmission to ensure that the transmission behavior is completed or aborted within the time window defined by the LST.

[0015] Preferably, the time-aware scheduler is configured to execute the first retransmission management mode, namely the conservative pre-detection mode:

[0016] Before initiating the first transmission of a data frame, the time-aware scheduler performs a pre-calculation, which is: T_required = T_first_tx + (N_max_retries × T_retry), where T_first_tx is the duration required for the first transmission, N_max_retries is the maximum number of retransmissions, and T_retry is the duration required for a single retransmission.

[0017] Subsequently, the time-aware scheduler checks whether the sum of the current global timestamp T_current and T_required is greater than the latest transmission time LST;

[0018] If T_current + T_required > LST, the time-aware scheduler will directly abandon the transmission of the data frame and mark it as a timeout failure; otherwise, the first transmission will be allowed.

[0019] Preferably, the time-aware scheduler is configured to execute a second retransmission management mode, namely an aggressive runtime abort mode:

[0020] When the EST condition is met, the time-aware scheduler immediately allows the first transmission of the data frame;

[0021] If the first transmission fails and a retransmission is required, the time-aware scheduler performs the following check before each retransmission is initiated: calculate the sum of the current retransmission time T_current_retry and the duration required for a single retransmission T_one_retry, and determine whether the sum is greater than the latest transmission time LST.

[0022] If T_current_retry + T_one_retry > LST, the time-aware scheduler will abort this and all subsequent retransmissions and mark the data frame as timed out; otherwise, this retransmission will be allowed.

[0023] Preferably, it further includes a mode configuration register which can be configured by software to selectively enable the conservative pre-detection mode or the aggressive runtime abort mode.

[0024] Preferably, the time-aware scheduler is further configured to: before or simultaneously with comparing the current global timestamp with the EST of the head-of-queue transmit descriptor, check whether the current global timestamp has exceeded the LST of this descriptor;

[0025] If the current global timestamp has exceeded the LST, regardless of whether the EST condition is satisfied, the time-aware scheduler directly discards this data frame and marks it as a timeout failure.

[0026] Preferably, it further includes a time synchronization state machine which is connected to the time-aware scheduler;

[0027] The time synchronization state machine is configured to: continuously monitor the global clock synchronization state of the device, and when detecting the loss of time synchronization, send a shutdown signal to the time-aware scheduler;

[0028] In response to the shutdown signal, the time-aware scheduler immediately stops all scheduling and transmission activities and clears the transmit descriptor queue.

[0029] The present invention also proposes a hardware-based precise transmission time control method for wireless communication, which is applied to the above system, and the method includes:

[0030] Step S1: Software pre-submits one or more transmit descriptors to the transmit descriptor queue of the hardware, and each transmit descriptor includes a data frame pointer, an earliest transmission time EST, and a latest transmission time LST;

[0031] Step S2: When the transmit descriptor is added to the queue, the time sorting unit of the hardware automatically performs an insertion sort on the queue according to its EST value, so that the queue is sorted in ascending order of EST;

[0032] Step S3: The time-aware scheduler of the hardware continuously monitors the current global timestamp T_current provided by the high-precision clock;

[0033] Step S4: The time-aware scheduler checks the head-of-queue transmit descriptor. If T_current >= the EST of this descriptor, execute Step S5; if T_current < EST, continue to wait;

[0034] Step S5: The time-aware scheduler decides whether to trigger transmission, abandon transmission, or abort retransmission according to the preset retransmission management mode and the LST of this descriptor, so as to ensure that the transmission behavior is restricted before the LST.

[0035] Preferably, in step S5, when the system is configured in a conservative pre-detection mode, the specific steps include:

[0036] Step S51a: Before the first transmission, calculate the total time requirement in the worst case: T_required = T_first_tx + (N_max_retries × T_retry); where T_first_tx is the time required for the first transmission, N_max_retries is the maximum number of retransmissions, and T_retry is the time required for a single retransmission.

[0037] Step S52a: Determine whether T_current + T_required > LST is true;

[0038] Step S53a: If true, the hardware directly abandons sending the data frame, marks it as a timeout failure, and processes the next descriptor in the queue; if false, the first transmission of the data frame is triggered.

[0039] Preferably, in step S5, when the system is configured in an aggressive runtime abort mode, the specific steps include:

[0040] Step S51b: Immediately trigger the first transmission of this data frame;

[0041] Step S52b: If the first transmission fails and retransmission is required, before each retransmission, obtain the current time T_current_retry, calculate the sum of the current retransmission time T_current_retry and the time required for a single retransmission T_one_retry, and determine whether T_current_retry + T_one_retry > LST is true.

[0042] Step S53b: If true, the hardware immediately suspends all subsequent retransmissions of the data frame and marks it as a timeout failure; if false, the retransmission is allowed.

[0043] Preferably, it also includes a fail-safe control step:

[0044] The hardware time synchronization state machine continuously monitors the global clock synchronization status.

[0045] When a time synchronization loss is detected, the time synchronization state machine sends a shutdown signal to the time-aware scheduler.

[0046] Upon receiving the shutdown signal, the time-aware scheduler immediately stops all scheduling and transmission activities, clears the transmission descriptor queue, and reports an interrupt to the software.

[0047] The beneficial effects of the above-described technical solution of the present invention are as follows:

[0048] 1. This invention uses a hardware time sorting queue and a high-precision clock comparison logic to move the transmission trigger point from the unpredictable software level to the deterministic hardware level, completely eliminating the scheduling jitter introduced by the OS and software protocol stack, and improving the transmission trigger accuracy from milliseconds to nanoseconds.

[0049] 2. The innovative LST management mechanism of this invention enables hardware to proactively anticipate and manage the uncertainties brought about by wireless retransmissions. Whether it is the early abandonment in the conservative pre-detection mode or the timely braking in the aggressive runtime abort mode, it can ensure that the hard cutoff time (LST) of transmission behavior is strictly adhered to, fundamentally eliminating time slot overflow and signal collision, and providing a cornerstone for high deterministic networks.

[0050] 3. The software of this invention no longer needs to perform busy queries or high-precision timed waiting for precise timing of transmission. Instead, it can pre-submit multiple frames to be sent to the hardware queue in batches. The hardware is responsible for all subsequent timing management and triggering work, achieving deep decoupling between software and hardware, significantly freeing up CPU resources to handle other computing tasks.

[0051] 4. This invention provides two configurable LST processing modes, enabling the same hardware to flexibly adapt to different industrial application scenarios. For example, safety-priority emergency stop signals can use mode A to ensure they never cross the line, while throughput-priority non-critical sensor data can use mode B for best-effort transmission, achieving the best balance between performance and reliability.

[0052] 5. The time synchronization gating mechanism integrated in this invention ensures that the device will automatically enter a silent state in the event of time synchronization loss, preventing it from sending data in the wrong time slot due to time base error, thereby polluting the normal communication of the entire network and greatly improving the stability and fault tolerance of the entire TDMA system. Attached Figure Description

[0053] Figure 1 This is a schematic diagram illustrating time slot overflow caused by software scheduling and retransmission in existing technologies.

[0054] Figure 2 This is a block diagram of the hardware MAC module architecture according to an embodiment of the present invention.

[0055] Figure 3 This is a timing diagram of the process of the method of the present invention in mode A (conservative pre-detection mode).

[0056] Figure 4 This is a flowchart of the method of the present invention in mode B (aggressive runtime abort mode). Detailed Implementation

[0057] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0058] This invention provides a hardware MAC module for a wireless communication device, as shown in the attached figure. Figure 2 As shown, this module is specifically designed for precise control of the data frame transmission timing. The system mainly includes the following core components:

[0059] A high-precision clock: This clock is kept in high-precision synchronization with the network master clock via a hardware synchronization protocol (such as IEEE1588PTP) (e.g., synchronization accuracy better than 100ns) and provides the current global timestamp (T_current) for other modules in the system.

[0060] A send descriptor queue: This queue resides in hardware memory and is used to receive and buffer send descriptors submitted by software (driver or application) via DMA. Each descriptor contains metadata such as a pointer to the address (data pointer) of the data frame to be sent in memory.

[0061] A time sorting unit: This is a hardware logic module that is directly connected to the send descriptor queue.

[0062] A time-aware scheduler: This is the control core of the invention, which is a finite state machine implemented by hardware logic.

[0063] The core feature of this invention lies in its extension of the traditional send descriptor. In addition to essential information such as data pointers, each send descriptor also includes two key timestamp fields filled in by the software upon submission:

[0064] Earliest Transmit Time (EST): The earliest time at which this data frame is allowed to be transmitted. In TDMA systems, this typically corresponds to the start boundary of the time slot occupied by the device.

[0065] Latest Transmission Time (LST): The absolute deadline at which this data frame (including all possible retransmissions) must be transmitted. In a TDMA system, this strictly corresponds to the end boundary of the time slot occupied by the device.

[0066] Accordingly, the present invention provides a precise transmission time control method, as shown in the appendix. Figure 3 and attached Figure 4 As shown, its key features include two core components: automatic hardware sorting and hardware gating transmission.

[0067] 1. Automatic hardware sorting (EST processing):

[0068] The software can ignore the chronological order and pre-submit one or more descriptors to the hardware's transmit descriptor queue arbitrarily according to the data readiness status.

[0069] The time sorting unit inside the hardware is automatically triggered every time a new descriptor is added to the queue. This unit reads the EST value of the new descriptor, compares it with the ESTs of the existing descriptors in the queue, and quickly completes the insertion sorting through an efficient hardware comparison logic (such as a parallel comparator or a binary tree search), placing the new descriptor in the correct position in the queue sorted in ascending order of EST from earliest to latest. This process is completely completed by the hardware, is fast, and is not interfered with by the software.

[0070] 2. Hardware-gated transmission (LST processing):

[0071] The time-aware scheduler continuously monitors T_current output by the high-precision clock at each high-precision clock tick. To reduce the logic complexity and power consumption, it only checks the descriptor located at the physical head of the queue.

[0072] When the scheduler detects that T_current >= the EST of the descriptor at the head of the queue, the data frame is eligible for transmission. If T_current < EST, the hardware automatically waits until the time condition is met, achieving precise triggering at the nanosecond level.

[0073] Before making a transmission decision, the scheduler first checks whether T_current has already exceeded the LST of the descriptor at the head of the queue. If so, it means that the frame has expired at the factory and there is no possibility of completion within the time limit. At this time, the hardware will directly discard the frame, remove it from the queue, mark it as a timeout failure and return it to the software, and then continue to check the next descriptor at the head of the queue.

[0074] After the data frame becomes eligible for transmission, the scheduler does not send it immediately, but manages the entire transmission (including potential retransmissions) process according to a configurable LST processing mode. These two modes ensure that even in the case of retransmissions, the transmission behavior will never exceed the window defined by the LST.

[0075] Through the above software-hardware cooperation scheme, the transmission triggering of the data frame is completely automatically executed by the hardware based on an accurate global clock, completely eliminating the impact of software scheduling jitter; at the same time, the most intractable retransmission uncertainty in wireless communication is managed and constrained by the rigid rules based on LST by the hardware, thus fundamentally ensuring the inviolability of the TDMA time slot boundary.

[0076] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0077] Example 1: Implementation of a Hardware Time-Sorting Queue

[0078] See attached document Figure 2 The timing sorting unit can be implemented in hardware as a dedicated logic circuit module, such as consisting of a set of registers, multiplexers, and comparators. This unit is triggered when software writes a new transmit descriptor to the logical tail of the transmit descriptor queue via the DMA controller. The unit then reads the EST value from the new descriptor and compares it in parallel or serially with the EST values ​​of existing descriptors in the queue. Using an efficient hardware sorting algorithm (such as a hardware implementation of insertion sort), the unit can determine the correct position of the new descriptor in the queue within a few clock cycles and control the multiplexers to rearrange the descriptor pointers, thus physically maintaining the queue in ascending EST order. This hardware sorting is significantly faster than software sorting, with extremely low power consumption and latency.

[0079] The time-aware scheduler is a state machine that is activated at each high-precision clock tick (e.g., a 100ns tick). Since the queue is already maintained in an ordered state by the time-sorting unit, the scheduler only needs to perform one comparison operation per tick: comparing T_current with the EST of the physical queue head descriptor. This head-only design greatly simplifies the scheduler's logical complexity, enabling it to operate at extremely high clock frequencies and achieve nanosecond-level scheduling accuracy.

[0080] Example 2: Configurable LST Retransmission Management Mode (Core Innovation)

[0081] The LST processing logic of this invention includes two operating modes that can be selected by software through configuration of hardware registers to adapt to the trade-offs between reliability and throughput required in different industrial application scenarios.

[0082] Mode A: Conservative Pre-detection Mode

[0083] (1) Application scenarios: Suitable for safety-critical applications, such as emergency stop commands and safety door signals. Such applications absolutely do not allow network timing to be interfered with due to the transmission overflow of this device, even if it means sacrificing a data frame that could have been successfully retransmitted.

[0084] (2) Process (as attached) Figure 3 (as shown)

[0085] 1. When T_current>=EST, the scheduler prepares to trigger the first transmission.

[0086] 2. Before actually initiating transmission, the scheduler first performs a worst-case calculation. The calculation formula is: T_required = T_first_tx + (N_max_retries * T_retry). Where T_first_tx is the estimated time required for the first transmission based on the data frame length and physical layer rate; N_max_retries is the maximum number of retransmissions specified by the protocol, stored in a hardware register; and T_retry is the estimated round-trip time for a single retransmission (including data frame transmission, ACK timeout waiting, and retransmission processing).

[0087] 3. The scheduler calculates T_current + T_required and compares the result with the LST of the head descriptor.

[0088] 4. Decision: If T_current + T_required > LST, it means that even under the most ideal immediate transmission scenario, if the maximum number of retransmissions occurs, the transmission completion time will inevitably exceed the time slot boundary. In this case, the hardware will directly abandon this transmission, immediately mark the frame as an LST timeout failure and return it to the software, and then process the next descriptor. If the calculation result does not time out, the first transmission is allowed.

[0089] Mode B: Aggressive runtime abort mode

[0090] (1) Application scenarios: Suitable for high-throughput data applications, such as periodic sensor data uploads and video surveillance streams. These applications aim to maximize the use of allocated time slots and should try to transmit as much data as possible if there is a chance of success on the first send.

[0091] (2) Process (as attached) Figure 4 (as shown)

[0092] 1. When T_current>=EST, the scheduler does not perform any pre-detection and immediately allows and triggers the first transmission of the data frame.

[0093] 2. If the first transmission fails (e.g., no ACK is received), the MAC layer logic notifies the scheduler that a retransmission is required.

[0094] 3. Before initiating each retransmission, the scheduler is reactivated. It obtains the current precise time T_current_retry.

[0095] 4. The scheduler performs a lightweight calculation: T_required_retry = T_one_retry, where T_one_retry is the estimated duration of a single retransmission operation.

[0096] 5. The scheduler checks whether T_current_retry + T_one_retry is greater than LST.

[0097] 6. Decision: If yes, it means that the retransmission operation itself cannot be completed before LST. In this case, the hardware will actively abort this and all subsequent retransmission attempts, immediately mark the frame as having failed due to LST timeout, and return to the software. If no, the PHY layer is allowed to perform this retransmission. This mode allows the device to do its best within the time slot, while decisively braking at critical moments (when retransmission may cause overflow) to protect the time slot boundaries.

[0098] Example 3: Time Synchronization-Based Fail-Safe Gating

[0099] To ensure that the system's behavior remains reliable even under abnormal conditions, the time-aware scheduler of this invention is hardware-bound to an independent time-synchronized state machine.

[0100] This state machine continuously monitors the global clock synchronization status from the PHY layer or a dedicated time synchronization module (such as a PTP hardware auxiliary module). Its judgment can be based on whether the synchronization beacon or PTP synchronization message from the access point (AP) is successfully received within the expected time, and whether the deviation between the local clock and the master clock exceeds a preset tolerance.

[0101] Normal state: When the synchronization is good (e.g., the synchronization accuracy is stable within <100ns), the state machine outputs an enable signal to the time-aware scheduler, and the scheduler works normally.

[0102] Fault status: Once the state machine detects a loss of time synchronization (lack of lock), such as when no message is received for several consecutive synchronization cycles, it will immediately generate a shutdown signal and send it to the time-aware scheduler.

[0103] Upon receiving the shutdown signal, the scheduler must immediately cease all EST / LST-based scheduling logic and transmission behavior. Simultaneously, it will empty the entire transmit descriptor queue within a controllable timeframe (e.g., a few microseconds) and report a high-priority synchronization loss hardware interrupt to the software.

[0104] This fail-safe mechanism is crucial because it ensures that a device that has lost its global time reference will not send data arbitrarily on the network based on an incorrect local time, thereby preventing it from causing widespread pollution of the communication time slots of other normally synchronized devices in the network and greatly enhancing the robustness of the entire TDMA network.

[0105] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A hardware-based precise transmission time control system for wireless communication, characterized in that, include: A clock, used to provide a current global timestamp synchronized with the network's master clock; A send descriptor queue is used to store send descriptors submitted by software, wherein the send descriptor contains at least a data frame pointer, an earliest send time EST, and a latest send time LST; A time sorting unit, connected to the send descriptor queue, is used to automatically insert the send descriptor into the correct time position in the queue according to the value of its earliest send time (EST) field when the send descriptor is added to the queue, so that the send descriptors in the queue are arranged in order of EST from earliest to latest. A time-aware scheduler, connected to a high-precision clock, the transmit descriptor queue, and the physical layer, is configured to: continuously compare the current global timestamp with the earliest transmission time (EST) of the transmit descriptor at the head of the transmit descriptor queue; and trigger the transmission process of the data frame corresponding to the transmit descriptor when the current global timestamp is greater than or equal to the EST. Simultaneously, the time-aware scheduler is also configured to perform a check based on the latest transmission time (LST) before triggering transmission or retransmission to ensure that the transmission behavior is completed or aborted within the time window defined by the LST.

2. The system according to claim 1, characterized in that, The time-aware scheduler is configured to execute the first retransmission management mode, namely the conservative pre-detection mode: Before initiating the first transmission of a data frame, the time-aware scheduler performs a pre-calculation, which is: T_required = T_first_tx + (N_max_retries × T_retry), where T_first_tx is the duration required for the first transmission, N_max_retries is the maximum number of retransmissions, and T_retry is the duration required for a single retransmission. Subsequently, the time-aware scheduler checks whether the sum of the current global timestamp T_current and T_required is greater than the latest transmission time LST; If T_current + T_required > LST, the time-aware scheduler will directly abandon the transmission of the data frame and mark it as a timeout failure; otherwise, the first transmission will be allowed.

3. The system according to claim 1, characterized in that, The time-aware scheduler is configured to execute a second retransmission management mode, namely an aggressive runtime abort mode: When the EST condition is met, the time-aware scheduler immediately allows the first transmission of the data frame; If the first transmission fails and a retransmission is required, the time-aware scheduler performs the following check before each retransmission is initiated: calculate the sum of the current retransmission time T_current_retry and the duration required for a single retransmission T_one_retry, and determine whether the sum is greater than the latest transmission time LST. If T_current_retry + T_one_retry > LST, the time-aware scheduler will abort this and all subsequent retransmissions and mark the data frame as timed out; otherwise, this retransmission will be allowed.

4. The system according to claim 2 or 3, characterized in that, It further includes a mode configuration register which can be configured by software to selectively enable the conservative pre-detection mode or the aggressive runtime abort mode.

5. The system according to claim 1, characterized in that, The time-aware scheduler is further configured to: before or at the same time as comparing the current global timestamp with the EST of the head-of-queue transmit descriptor, check whether the current global timestamp has exceeded the LST of this descriptor; If the current global timestamp has exceeded the LST, regardless of whether the EST condition is satisfied, the time-aware scheduler directly discards this data frame and marks it as a timeout failure.

6. The system according to claim 1, characterized in that, It further includes a time synchronization state machine which is connected to the time-aware scheduler; The time synchronization state machine is configured to: continuously monitor the global clock synchronization state of the device, and when detecting a loss of time synchronization, send a shutdown signal to the time-aware scheduler; In response to the shutdown signal, the time-aware scheduler immediately stops all scheduling and transmission activities and clears the transmit descriptor queue.

7. A hardware-based method for precise transmission time control in wireless communication, applied to the system described in any one of claims 1-6, characterized in that, The method includes: Step S1: Software pre-submits one or more transmit descriptors to the transmit descriptor queue of the hardware, and each transmit descriptor includes a data frame pointer, an earliest transmit time EST, and a latest transmit time LST; Step S2: When the transmit descriptor is added to the queue, the time sorting unit of the hardware automatically performs an insertion sort on the queue according to its EST value, so that the queue is sorted in ascending order of EST; Step S3: The time-aware scheduler of the hardware continuously monitors the current global timestamp T_current provided by the high-precision clock; Step S4: The time-aware scheduler checks the head-of-queue transmit descriptor. If T_current >= the EST of this descriptor, step S5 is executed; if T_current < EST, continue to wait; Step S5: The time-aware scheduler decides whether to trigger transmission, abandon transmission, or abort retransmission according to the preset retransmission management mode and the LST of this descriptor, so as to ensure that the transmission behavior is constrained before the LST.

8. The method according to claim 7, characterized in that, In step S5, when the system is configured in the conservative pre-detection mode, it specifically includes: Step S51a: Before the first transmission, calculate the total time requirement T_required in the worst case = T_first_tx + (N_max_retries × T_retry); where T_first_tx is the duration required for the first transmission, N_max_retries is the maximum number of retransmissions, and T_retry is the duration required for a single retransmission; Step S52a: Judge whether T_current + T_required > LST holds; Step S53a: If it holds, the hardware directly abandons the transmission of this data frame, marks it as a timeout failure, and processes the next descriptor in the queue; if it does not hold, trigger the first transmission of this data frame.

9. The method according to claim 7, characterized in that, In step S5, when the system is configured in the aggressive runtime abort mode, it specifically includes: Step S51b: Immediately trigger the first transmission of this data frame; Step S52b: If the first transmission fails and retransmission is required, before each retransmission, obtain the current time T_current_retry, calculate the sum of the current retransmission time T_current_retry and the time required for a single retransmission T_one_retry, and determine whether T_current_retry + T_one_retry > LST is true. Step S53b: If true, the hardware immediately suspends all subsequent retransmissions of the data frame and marks it as a timeout failure; if false, the retransmission is allowed.

10. The method according to claim 7, characterized in that, It also includes a fail-safe control step: The hardware time synchronization state machine continuously monitors the global clock synchronization status. When a time synchronization loss is detected, the time synchronization state machine sends a shutdown signal to the time-aware scheduler. Upon receiving the shutdown signal, the time-aware scheduler immediately stops all scheduling and transmission activities, clears the transmission descriptor queue, and reports an interrupt to the software.

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