A master-slave network-based processing method for transmitting and receiving data signals based on power lines

Abstract

The embodiment of the present application relates to a kind of master-slave machine network based on the processing method of power line transceiving data signal, the method comprises: constructing master-slave machine network;When host sends high / low level data signal to slave, by host control its output level state presents opposite low / high level state and thus activate slave to complete corresponding high / low level data signal receiving processing locally;When slave sends high / low level data signal to host, on the premise that the output level state of host is high level state, by slave according to the high / low level feature of data signal, corresponding setting is completed locally by slave, and by host, according to the sampling voltage of current sampling resistance R S In host, data signal receiving processing is carried out.The difficulty and cost of implementation of master / slave machine can be reduced by the present application.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic circuit and communication technology, in particular to a processing method for transmitting and receiving data signals based on power lines in master-slave network. BACKGROUND

[0002] Electronic devices using power lines as data bus have only power supply interface and no redundant communication interface. The electronic devices transmit data using power lines as data bus, and corresponding data transmission protocols include power line carrier (PLC) communication protocol, Powerbus bus protocol, etc. We found in practice that the power line data transmission protocols such as PLC and Powerbus are all based on modulation and demodulation mode, that is, the corresponding signal modulation and demodulation modules need to be added at the transmitting and receiving ends of the master-slave electronic devices, and the implementation difficulty and cost of such signal modulation and demodulation modules are very high. If such electronic devices are applied in short-distance and simple-scheduling operation and maintenance network (such as smart home, smart building, smart community, etc.), the disadvantages are obvious: long development cycle, high cost, and high system operation and maintenance cost. SUMMARY

[0003] The present application aims at the defects of the prior art, and provides a processing method for transmitting and receiving data signals based on power lines in master-slave network. A master-slave network composed of one master and multiple slaves is constructed, and the connection from the master to each slave is realized based on two power lines. A processing mechanism for realizing high / low level data signal transmission and reception between the master and the slave is designed for the master-slave network. The processing mechanism causes the electrical state of the receiver (slave / master) to change correspondingly (the input level state of the slave changes / the voltage of the current sampling resistor of the master changes) by regulating the state (output level state / power line current state) of the power line of the sender (master / slave), and then the receiver confirms whether it is in high level data signal receiving state or low level data signal receiving state according to the changed state and completes the corresponding high / low level data signal receiving. The processing method can reduce the implementation difficulty and cost of the master / slave without complex modulation and demodulation operation on the power line. The master / slave realized based on the present application can shorten the development cycle, reduce the system cost and operation and maintenance cost when applied in short-distance and simple-scheduling operation and maintenance network (such as smart home, smart building, smart community, etc.).

[0004] To achieve the above-mentioned purpose, the embodiment of the present application provides a processing method for transmitting and receiving data signals based on power lines in master-slave network, which comprises:

[0005] The master-slave network is constructed, and the master-slave network comprises a master, a plurality of slaves, a first power line and a second power line; the master comprises first and second master access ends, which are connected with the first and second power lines respectively; the slave comprises first and second slave access ends, which are connected with the first and second power lines respectively;

[0006] When the master sends high / low level data signals to the slave, the master controls its output level state to be opposite low / high level state and activates the slave to complete corresponding high / low level data signal receiving processing locally;

[0007] When the slave sends high / low level data signals to the master, on the premise that the output level state of the master is high level state, the slave completes corresponding setting locally according to the high / low level characteristics of the data signals, and the master completes data signal receiving processing according to the sampling voltage of the current sampling resistor R S .

[0008] Preferably, the master comprises a power module, a crystal oscillator source, a master control module, a signal processing module and the current sampling resistor R S in addition to the first and second master access ends.

[0009] The power module is connected with the crystal oscillator source, the master control module and the signal processing module respectively, and is used to supply power to the crystal oscillator source, the master control module and the signal processing module respectively.

[0010] The crystal oscillator source is connected with the master control module, and is used to provide an external clock signal source for the master control module.

[0011] The current sampling resistor R S is marked with corresponding first and second side ports on both sides, wherein the first side port is connected with a first master output signal end of the master control module, and the second side port is connected with the first master access end.

[0012] The signal processing module is connected with the first and second side ports of the current sampling resistor R S respectively, and is also connected with a first master input signal end of the master control module.

[0013] The signal processing module is used to measure the voltage on both sides of the current sampling resistor R S to generate a corresponding sampling voltage, and to identify high / low level data signals according to the sampling voltage and output a corresponding identification signal to the first master input signal end of the master control module.

[0014] The port for processing data signal sending of the host control module includes the first host output signal end and the second host output signal end, and the port for processing data signal receiving is the first host input signal end; the second host output signal end is connected with the second host access end.

[0015] Further, the sending of the corresponding identification signal to the first host input signal end of the host control module according to the high and low level data signal identification output of the sampling voltage specifically includes:

[0016] The signal processing module identifies a preset processing mode; the processing mode includes a first mode and a second mode;

[0017] When the processing mode is the first mode, the sampling voltage is input into a built-in analog-to-digital converter for conversion to output a corresponding first conversion value; whether the first conversion value satisfies a preset high level conversion value range is identified; if the first conversion value satisfies the high level conversion value range, a corresponding first level state is set as a high level state; if the first conversion value does not satisfy the high level conversion value range, whether the first conversion value satisfies a preset low level conversion value range is identified; if the first conversion value satisfies the low level conversion value range, a corresponding first level state is set as a low level state; if the first conversion value does not satisfy the low level conversion value range, a corresponding first level state is set as an abnormal level state;

[0018] When the processing mode is the second mode, the sampling voltage is input into a first voltage comparator built-in and compared by the first voltage comparator based on a preset high-level reference voltage, and a corresponding first comparison result is true when the sampling voltage exceeds the high-level reference voltage, and the first comparison result is false when the sampling voltage does not exceed the high-level reference voltage; and the first comparison result is identified; if the first comparison result is true, a corresponding first level state is set as a high-level state; if the first comparison result is false, the sampling voltage is input into a second voltage comparator built-in and compared by the second voltage comparator based on a preset low-level reference voltage, and a corresponding second comparison result is true when the sampling voltage does not exceed the low-level reference voltage, and the second comparison result is false when the sampling voltage exceeds the low-level reference voltage, and the first level state is set as a low-level state when the second comparison result is true, and the first level state is set as an abnormal level state when the second comparison result is false; the first and second voltage comparators both include two input ends and one output end; one of the two input ends of the first voltage comparator is used for inputting the sampling voltage, and the other is used for inputting the high-level reference voltage, and the output end of the first voltage comparator is used for outputting the first comparison result; one of the two input ends of the second voltage comparator is used for inputting the sampling voltage, and the other is used for inputting the low-level reference voltage, and the output end of the second voltage comparator is used for outputting the second comparison result; the first and second comparison results have two values including true and false;

[0019] When the first level state obtained is not an abnormal level state, the first level state is sent to the first host input signal end of the host control module as the output identification signal.

[0020] Preferably, in addition to the first and second slave access ends, the slave also includes a rectification module composed of first, second, third and fourth diodes D1, D2, D3 and D4, first and second field effect tubes MOS1 and MOS2, first, second and third resistors R1, R2 and R3, a fifth diode D5, first and second capacitors C1 and C2, a low-dropout linear regulator LDO and a slave control module.

[0021] The rectifier module is a rectifier bridge composed of the first, second, third and fourth diodes D1, D2, D3 and D4; the first and second diodes D1 and D2 are connected in series to form a corresponding first series diode, and the third and fourth diodes D3 and D4 are connected in series to form a corresponding second series diode; the first and second series diodes are connected in parallel, the anodes of the first and third diodes D1 and D3 are connected, and the cathodes of the second and fourth diodes D2 and D4 are connected; the anode connection point of the first and third diodes D1 and D3 is connected to ground; the series connection point of the first and second diodes D1 and D2 is connected to the first slave access end; the series connection point of the third and fourth diodes D3 and D4 is connected to the second slave access end; the cathode connection point of the second and fourth diodes D2 and D4 is connected to the source of the first field effect transistor MOS1, the first side port of the first resistor R1 and the anode of the fifth diode D5, respectively; the output node of the rectifier module is the cathode connection point of the second and fourth diodes D2 and D4, and the output voltage of the rectifier module is the node voltage of the output node, which is denoted as a corresponding output voltage V p ; The voltage level state of the output voltage V p corresponds to the input level state of the first and second slave access ends, and when the input level state of the first and second slave access ends is in a high level state, the voltage level state of the output voltage V p is in a high level state, and when the input level state of the first and second slave access ends is in a low level state, the voltage level state of the output voltage V p is in a low level state.

[0022] The drain of the first field effect transistor MOS1 is connected to ground, and the gate is connected to the first slave output signal end of the slave master module; the first field effect transistor MOS1 is turned on when the first slave output signal end is in a high level state, and is turned off when the first slave output signal end is in a low level state; when the first field effect transistor MOS1 switches from off to on, the on-line current on the first power line increases; when the first field effect transistor MOS1 switches from on to off, the on-line current on the first power line decreases.

[0023] The first resistor R1 and the second resistor R2 are connected in series, the second side port of the first resistor R1 is connected to the first side port of the second resistor R2, and the second side port of the second resistor R2 is connected to ground; the series connection point of the first resistor R1 and the second resistor R2 is also connected to the gate of the second field effect transistor MOS2;

[0024] The gate voltage V 2g of the second field effect transistor MOS2 is V pR2 / (R1+R2); the source of the second field effect transistor MOS2 is grounded, and the drain is connected with the second side port of the third resistor R3 and the first slave input signal end of the slave master module respectively; the drain voltage of the second field effect transistor MOS2 is recorded as the corresponding drain voltage V 2d ; the second field effect transistor MOS2 is turned on when the output voltage V p is in a high level state, and the corresponding gate voltage V 2g is in a high level state, and the drain voltage V 2d is in a low level state; the second field effect transistor MOS2 is turned off when the output voltage V p is in a low level state, and the corresponding gate voltage V 2g is in a low level state, and the drain voltage V 2d is in a high level state;

[0025] The negative electrode of the fifth diode D5 is connected with the voltage input end V in of the low dropout linear regulator LDO and the positive electrode of the first capacitor C1 respectively; the negative electrode of the first capacitor C1 is grounded; the fifth diode D5 is turned on when the output voltage V p is in a high level state, and is turned off when the output voltage V p is in a low level state; the first capacitor C1 is charged by the rectifier module through the fifth diode D5 when the output voltage V p is in a high level state, and is discharged to supply power to the low dropout linear regulator when the output voltage V p is in a low level state;

[0026] The voltage output end V out of the low dropout linear regulator LDO is connected with the first side port of the third resistor R3, the positive electrode of the second capacitor C2 and the slave master module respectively; the ground end GND of the low dropout linear regulator LDO is used for grounding; the negative electrode of the second capacitor C2 is grounded; the low dropout linear regulator LDO is used for supplying power to the slave master module and charging the second capacitor C2; the second capacitor C2 is used for filtering the output voltage V out of the voltage output end V DD of the low dropout linear regulator LDO;

[0027] The port of the slave master module for processing data signal receiving is the first slave input signal end, and the port for processing data signal sending is the first slave output signal end; the slave master module takes the built-in RC crystal oscillator as a clock signal source.

[0028] Preferably, the slave machine is activated by the host machine to locally complete corresponding high / low level data signal receiving processing, specifically including:

[0029] When the host machine sends high level data signal to the slave machine, the host master module of the host machine controls the output level state of the first and second host access terminals to be opposite low level state by reducing the potential difference between the first and second host output signal terminals; and the slave machine locally completes corresponding high level data signal receiving processing when the output level state of the first and second host access terminals is low level state.

[0030] When the host machine sends low level data signal to the slave machine, the host master module of the host machine controls the output level state of the first and second host access terminals to be opposite high level state by increasing the potential difference between the first and second host output signal terminals; and the slave machine locally completes corresponding low level data signal receiving processing when the output level state of the first and second host access terminals is high level state.

[0031] Further, the slave machine locally completes corresponding high level data signal receiving processing when the output level state of the first and second host access terminals is low level state, specifically including:

[0032] When the output level state of the first and second host access terminals of the host machine is set to low level state, the input level state of the corresponding first and second slave access terminals of the slave machine becomes low level state, so that the output voltage V p of the rectifier module correspondingly becomes low level state, and then the drain voltage V 2d of the second field effect transistor MOS2 correspondingly becomes high level state, and the signal level state of the first slave input signal terminal of the slave master module connected with the drain of the second field effect transistor MOS2 becomes high level state.

[0033] The slave master module of the slave machine continuously collects the signal of the first slave input signal terminal when the level state of the first slave input signal terminal is high level state, to obtain corresponding high level data signal.

[0034] Further, the slave machine locally completes corresponding low level data signal receiving processing when the output level state of the first and second host access terminals is high level state, specifically including:

[0035] When the output level state of the first and second host access ends of the host is set to high level state, the input level state of the corresponding first and second slave access ends on the slave is changed to high level state, thereby making the output voltage V p of the rectifier module correspondingly change to high level state, and then making the drain voltage V 2d of the second field effect tube MOS2 change to low level state and making the signal level state of the first slave input signal end of the slave master module connected with the drain of the second field effect tube MOS2 change to low level state.

[0036] The slave master module of the slave continuously collects the signal of the first slave input signal end when the level state of the first slave input signal end is low level state, to obtain corresponding low level data signal.

[0037] Preferably, the corresponding setting is completed locally by the slave according to the high / low level characteristics of the data signal, and the data signal receiving processing is performed by the host according to the sampling voltage of the current sampling resistor R S in the host, specifically including:

[0038] When the slave sends high level data signal to the host, the first field effect tube MOS1 is turned on by the slave master module of the slave by setting the signal level state of the first slave output signal end to high level state; the voltage on both sides of the current sampling resistor R S is measured by the signal processing module of the host to generate corresponding sampling voltage, and high / low level data signal identification is performed according to the sampling voltage, and the corresponding identification signal is output to the first host input signal end of the host master module; and the signal of the first host input signal end is continuously collected by the host master module of the host when the identification signal input to the first host input signal end is high level state, to obtain corresponding high level data signal.

[0039] When the slave sends low level data signal to the host, the first field effect tube MOS1 is turned off by the slave master module of the slave by setting the signal level state of the first slave output signal end to low level state; the voltage on both sides of the current sampling resistor R SThe voltage on both sides of the power line is measured to generate corresponding sampling voltage, and the high / low level data signal is identified according to the sampling voltage, and the corresponding identification signal is output to the first host input signal end of the host control module; and the host control module of the host continuously collects the signal of the first host input signal end when the identification signal input by the first host input signal end is in a low level state, to obtain a corresponding low level data signal.

[0040] The embodiment of the present application provides a processing method for data signal transmission and reception of master-slave network based on power line; a master-slave network composed of one host and multiple slaves is constructed, and the connection from the host to each slave is realized based on two power lines; and a processing mechanism for realizing high / low level data signal transmission and reception between the master and the slave is designed for the master-slave network, which causes the electrical state of the receiver (slave / host) to change correspondingly (the input level state of the slave changes / the voltage of the current sampling resistor of the host changes) by the sender (host / slave) controlling the state of the power line (output level state / power line current state), and then the receiver confirms whether it is in a high level data signal receiving state or a low level data signal receiving state according to the changed state, and completes the corresponding high / low level data signal receiving. The processing method of the present application does not need to perform complex modulation and demodulation operation on the power line, and reduces the implementation difficulty and cost of the master / slave. The master / slave realized based on the present application is applied to short distance, simple scheduling operation and maintenance network (such as smart home, smart building, smart community, etc.), which shortens the development cycle, reduces the system cost and operation and maintenance cost. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 A processing method for data signal transmission and reception of master-slave network based on power line provided by the embodiment of the present application is shown in the figure;

[0042] Figure 2 A master-slave network provided by the embodiment of the present application is shown in the figure;

[0043] Figure 3 A host principle block diagram provided by the embodiment of the present application is shown in the figure;

[0044] Figure 4 A slave principle block diagram provided by the embodiment of the present application is shown in the figure;

[0045] Figure 5 A master-slave connection diagram provided by the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0046] In order to make the objects, technical solutions and advantages of the present application clearer, the following further describes the present application in detail with reference to the drawings. Obviously, the described embodiments are only a part but not all of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those ordinarily skilled in the art without creative effort belong to the scope of the present application.

[0047] The embodiment of the present application provides a processing method for transmitting and receiving data signals based on power lines in a master-slave network. Figure 1 The processing method for transmitting and receiving data signals based on power lines in a master-slave network provided by the embodiment of the present application is shown in a schematic diagram, and the method mainly comprises the following steps.

[0048] Step 1, constructing a master-slave network.

[0049] Here, the master-slave network of the embodiment of the present application is as shown in Figure 2 The master-slave network provided by the embodiment of the present application is shown in a schematic diagram, and comprises one master, a plurality of slaves, a first power line and a second power line; the master comprises first and second master access ends, and the first and second master access ends are connected with corresponding first and second power lines respectively; the slave comprises first and second slave access ends, and the first and second slave access ends are connected with corresponding first and second power lines respectively.

[0050] The following describes the module structure and working principle of the master and the slave respectively.

[0051] (I) Master:

[0052] a, the main working modules in the master of the embodiment of the present application and the connection relationship of the modules are as shown in Figure 3 The principle block diagram of the master provided by the embodiment of the present application is shown as follows:

[0053] In addition to the first and second master access ends, the master also comprises a power module, a crystal oscillator source, a master control module, a signal processing module and a current sampling resistor R S .

[0054] The power module is connected with the crystal oscillator source, the master control module and the signal processing module respectively; the crystal oscillator source is connected with the master control module; the two sides of the current sampling resistor R S are marked as corresponding first and second side ports, wherein the first side port is connected with the first master output signal end of the master control module, and the second side port is connected with the first master access end; the signal processing module is connected with the current sampling resistor R SThe first and second side ports are connected respectively, and are also connected with the first host input signal end of the host control module; on the host control module, the ports for processing data signal sending include the first host output signal end and the second host output signal end, and the port for processing data signal receiving is the first host input signal end, the first host output signal end is connected with the current sampling resistor R S The first side port is connected, the second host output signal end is connected with the second host access end, and the first host input signal end is connected with the signal processing module;

[0055] b, the function of the working module inside the host in the embodiment of the application is:

[0056] The power module is used for supplying power to the crystal oscillator source, the host control module and the signal processing module respectively;

[0057] The crystal oscillator source is used for providing an external clock signal source for the host control module;

[0058] The signal processing module is used for measuring the voltage on both sides of the current sampling resistor R S to generate corresponding sampling voltage, and outputting corresponding identification signals to the first host input signal end of the host control module according to the high / low level data signal identification based on the sampling voltage;

[0059] Here, the signal processing module of the host in the embodiment of the application is a working module for identifying the high / low level data receiving state of the host locally when the slave sends data to the host; wherein, the processing process of the signal processing module outputting corresponding identification signals to the first host input signal end of the host control module according to the high / low level data signal identification based on the sampling voltage, specifically includes the following steps A1-A4:

[0060] Step A1, the signal processing module identifies the preset processing mode;

[0061] Wherein, the processing mode includes the first and second modes;

[0062] Here, the signal processing module of the embodiment of the application provides two ways to identify high / low level data signals; in the first mode, the signal processing module converts the sampling voltage based on an analog to digital converter (ADC) and determines the high / low level data signal receiving state based on the value range interval to which the converted value belongs; in the second mode, the signal processing module uses a voltage comparator to compare the sampling voltage with reference voltage, and determines the high / low level data signal receiving state based on the comparison result;

[0063] Step A2, when the processing mode is the first mode, input the sampling voltage into the built-in analog-to-digital converter to convert and output a corresponding first conversion value; and identify whether the first conversion value meets a preset high-level conversion value range; if the first conversion value meets the high-level conversion value range, set the corresponding first level state as a high-level state; if the first conversion value does not meet the high-level conversion value range, identify whether the first conversion value meets a preset low-level conversion value range, if it meets, set the corresponding first level state as a low-level state, if it does not meet, set the corresponding first level state as an abnormal level state;

[0064] Here, the high-level conversion value range and the low-level conversion value range are two preset analog-to-digital converter conversion value ranges; here, the two conversion value ranges can be two different value ranges, and the high-level conversion value range is greater than the low-level conversion value range; it can also be two different values, and the single value corresponding to the high-level conversion value range is greater than the single value corresponding to the low-level conversion value range; it can also be two value domain ranges divided by an intermediate value greater than 0, the high-level conversion value range is a value domain range greater than the intermediate value, and the low-level conversion value range is a value domain range less than the intermediate value but greater than 0;

[0065] Step A3, when the processing mode is the second mode, input the sampling voltage into the built-in first voltage comparator and compare the sampling voltage based on a preset high-level reference voltage by the first voltage comparator, and output a corresponding first comparison result as true when the sampling voltage exceeds the high-level reference voltage, and output a corresponding first comparison result as false when the sampling voltage does not exceed the high-level reference voltage; and identify the first comparison result; if the first comparison result is true, set the corresponding first level state as a high-level state; if the first comparison result is false, input the sampling voltage into the built-in second voltage comparator and compare the sampling voltage based on a preset low-level reference voltage by the second voltage comparator, and output a corresponding second comparison result as true when the sampling voltage does not exceed the low-level reference voltage, and output a corresponding second comparison result as false when the sampling voltage exceeds the low-level reference voltage, and set the corresponding first level state as a low-level state when the second comparison result is true, and set the corresponding first level state as an abnormal level state when the second comparison result is false;

[0066] The first and second voltage comparators each include two input ends and one output end; one of the two input ends of the first voltage comparator is used for inputting the sampling voltage, and the other is used for inputting the high-level reference voltage, and the output end of the first voltage comparator is used for outputting the first comparison result; one of the two input ends of the second voltage comparator is used for inputting the sampling voltage, and the other is used for inputting the low-level reference voltage, and the output end of the second voltage comparator is used for outputting the second comparison result; the values of the first and second comparison results include true and false values;

[0067] Here, the high-level reference voltage and the low-level reference voltage are two pre-set reference voltages; it should be noted that when the processing mode is the second mode, the corresponding first level state can also be set by one voltage comparator and one reference voltage, specifically: the sampling voltage is input into the built-in voltage comparator, and the voltage comparator compares the sampling voltage based on the pre-set reference voltage, and outputs the corresponding first comparison result as true when the sampling voltage is greater than the reference voltage, and outputs the corresponding first comparison result as false when the sampling voltage is less than the reference voltage; and the first comparison result is identified; if the first comparison result is true, the corresponding first level state is set as the high-level state; if the first comparison result is false, the corresponding first level state is set as the low-level state;

[0068] Step A4, when the obtained first level state is not the abnormal level state, the first level state is taken as the identification signal output to the first host input signal end of the host control module of the host;

[0069] Here, as can be seen from the following, when the slave sends data to the host, the identification signal output by the signal processing module is actually the current specific high / low level data signal receiving state of the host;

[0070] c, the data sending / receiving principle of the host of the embodiment of the application is:

[0071] The host of the embodiment of the present application adjusts the output level state of the host on the first and second power lines to the low level state through the regulation mode of reducing the potential difference between the first and second host access ends when sending the high level data signal to the slave, at this time, the corresponding high level sampling signal is generated at the slave side to complete the receiving and processing of the high level data signal by the slave; on the contrary, the host adjusts the output level state of the host on the first and second power lines to the high level state through the regulation mode of increasing the potential difference between the first and second host access ends when sending the low level data signal to the slave, at this time, the corresponding low level sampling signal is generated at the slave side to complete the receiving and processing of the low level data signal by the slave; here, when the host adjusts the output level state of the host on the first and second power lines to the low level state through the regulation mode of reducing the potential difference between the first and second host access ends, the output level state can be adjusted to the standard low level state through the mode of dynamically regulating the potential difference between the first and second host access ends, and the output level state can also be set to the standard low level state through the mode of directly setting the potential difference between the first and second host access ends; similarly, when the host adjusts the output level state of the host on the first and second power lines to the high level state through the regulation mode of increasing the potential difference between the first and second host access ends, the output level state can be adjusted to the standard high level state through the mode of dynamically regulating the potential difference between the first and second host access ends, and the output level state can also be set to the standard high level state through the mode of directly setting the potential difference between the first and second host access ends;

[0072] As can be known from the following, the current value on the first power line when the slave sends high level data to the host is greater than the current value when the slave sends low level data to the host, based on this known condition, the first current value range corresponding to the case that all the slaves in the master-slave network are in the low level data sending state can be obtained by statistical and standardization processing of the current value range of the first power line, and the second current value range corresponding to the case that only one and a random slave in the master-slave network is in the high level data sending state can be obtained by statistical and standardization processing of the current value range of the first power line, and then the low and high level conversion value range of the analog-to-digital converter used by the signal processing module and the low / high level reference voltage referenced by the first and second voltage comparators can be configured correspondingly according to the first and second current value ranges obtained by statistics, so that the low / high level state of the data sent by the slave can be recognized through the signal processing module;

[0073] (II) Slave:

[0074] a、The main components inside the slave of the present application and the connection relationship between the components are as shown in the figure Figure 4 The principle block diagram of the slave provided by the embodiment of the present application is shown in the figure

[0075] In addition to the first and second slave access ends, the slave also includes a rectification module composed of first, second, third and fourth diodes D1, D2, D3, D4, first and second field effect transistors MOS1, MOS2, first, second and third resistors R1, R2, R3, a fifth diode D5, first and second capacitors C1, C2, a low-dropout linear regulator LDO (Low Drop Out) and a slave master module;

[0076] The rectification module is a rectification bridge composed of first, second, third and fourth diodes D1, D2, D3, D4; the first and second diodes D1, D2 are connected in series to form a corresponding first series diode, and the third and fourth diodes D3, D4 are connected in series to form a corresponding second series diode; the first and second series diodes are connected in parallel, the anodes of the first and third diodes D1, D3 are interconnected, and the cathodes of the second and fourth diodes D2, D4 are interconnected; the anode interconnection point of the first and third diodes D1, D3 is connected to ground; the series connection point of the first and second diodes D1, D2 is connected to the first slave access end; the series connection point of the third and fourth diodes D3, D4 is connected to the second slave access end; the cathode interconnection point of the second and fourth diodes D2, D4 is connected to the source of the first field effect transistor MOS1, the first side port of the first resistor R1 and the anode of the fifth diode D5, respectively; the output node of the rectification module is the cathode interconnection point of the second and fourth diodes D2, D4, and the output voltage of the rectification module is the node voltage of the output node, denoted as the corresponding output voltage V p ;

[0077] Here, the voltage level state of the output voltage V p corresponds to the input level state of the first and second slave access ends, and when the input level state of the first and second slave access ends is a high level state, the voltage level state of the output voltage V p is a high level state, and when the input level state of the first and second slave access ends is a low level state, the voltage level state of the output voltage V p is a low level state;

[0078] The drain of the first field effect transistor MOS1 is connected to ground, and the gate is connected to the first slave output signal end of the slave master module;

[0079] Here, the first field effect tube MOS1 is turned on when the first slave output signal end is in a high level state, and is turned off when the first slave output signal end is in a low level state; when the first field effect tube MOS1 switches from off to on, the on-line current of the first power line increases; when the first field effect tube MOS1 switches from on to off, the on-line current of the first power line decreases; it should be noted that, in order to make the on-line current of the first power line have a significant change when the first field effect tube MOS1 is turned on, a low-impedance field effect tube is used as the first field effect tube MOS1 by default; in addition, in order to improve the switching speed of the first field effect tube MOS1, an NMOS tube type is preferred when the MOS tube type of the first field effect tube MOS1 is selected;

[0080] The first resistor R1 and the second resistor R2 are connected in series, the second side port of the first resistor R1 is connected with the first side port of the second resistor R2, and the second side port of the second resistor R2 is grounded; the series connection point of the first resistor R1 and the second resistor R2 is also connected with the gate of the second field effect tube MOS2; the gate voltage V 2g of the second field effect tube MOS2 is V p *R2 / (R1+R2); the source of the second field effect tube MOS2 is grounded, and the drain is connected with the second side port of the third resistor R3 and the first slave input signal end of the slave master module respectively; the drain voltage of the second field effect tube MOS2 is recorded as the corresponding drain voltage V 2d .

[0081] Here, the second field effect tube MOS2 is turned on when the output voltage V p is in a high level state, the corresponding gate voltage V 2g is in a high level state, and the drain voltage V 2d is in a low level state; the second field effect tube MOS2 is turned off when the output voltage V p is in a low level state, the corresponding gate voltage V 2g is in a low level state, and the drain voltage V 2d is in a high level state; it should be noted that, in order to improve the switching speed of the second field effect tube MOS2, an NMOS tube type is preferred when the MOS tube type of the second field effect tube MOS2 is selected;

[0082] The negative electrode of the fifth diode D5 is connected with the voltage input end V in of the low dropout linear regulator LDO and the positive electrode of the first capacitor C1 respectively; the negative electrode of the first capacitor C1 is grounded;

[0083] Here, the fifth diode D5 is turned on when the output voltage V p is in a high level state, and is turned off when the output voltage V pturn off when in low level state; the first capacitor C1 filters the output voltage V p is charged by the rectifier module through the fifth diode D5 when in high level state, and the output voltage V p is supplied to the low dropout linear regulator in a discharging mode when in low level state;

[0084] The voltage output end V out of the low dropout linear regulator LDO is connected with the first side port of the third resistor R3, the positive pole of the second capacitor C2 and the slave master module respectively; the ground end GND of the low dropout linear regulator LDO is used for grounding; and the negative pole of the second capacitor C2 is grounded.

[0085] Here, the low dropout linear regulator LDO is used for supplying power to the slave master module and charging the second capacitor C2; the second capacitor C2 is used for filtering the output voltage V out of the voltage output end V DD of the low dropout linear regulator LDO; and the working voltage V DD of the slave master module is 3.3 volts by default.

[0086] The port for receiving data signals of the slave master module is the first slave input signal end, and the port for sending data signals is the first slave output signal end; the slave master module takes the built-in RC crystal oscillator as a clock signal source, and the RC crystal oscillator should have a low power consumption feature.

[0087] b、The data sending / receiving principle of the slave of the embodiment of the application is as follows:

[0088] When the slave sends high level data signals to the master, the slave master module sets the first slave output signal end to high level state, at this time, the corresponding first field effect transistor MOS1 is turned on, the on-line current on the first power line is increased, the signal processing module on the master side will confirm to enter high level data receiving state and thus high level data signal receiving is performed; conversely, when the slave sends low level data signals to the master, the slave master module sets the first slave output signal end to low level state, at this time, the corresponding first field effect transistor MOS1 is turned off, and the on-line current value on the first power line should be less than the current value when high level data signals are sent, the signal processing module on the master side will confirm to enter low level data receiving state and thus low level data signal receiving is performed.

[0089] As known from the foregoing, when the master sends high level data signals to the slave, the output level state of the first and second power lines will be adjusted to low level state, at this time, the output voltage V p of the rectifier module on the slave side will be in low level state, the second field effect transistor MOS2 is turned off, and the drain voltage V 2dThe first slave input signal end of the slave master module is in a high level state, and the slave master module starts to receive the corresponding high level data signal when the first slave input signal end is in a high level state. p The output voltage V 2d The first slave input signal end of the slave master module is in a low level state, and the slave master module starts to receive the corresponding low level data signal when the first slave input signal end is in a low level state.

[0090] As can be seen, the data transceiving mechanism between the master and the slave in the master-slave network of the embodiment of the application is that the state of the power line (the output level state / the power line current state) is regulated by the sender (the master / the slave) to cause the electrical state of the receiver (the slave / the master) to change correspondingly (the input level state of the slave changes / the voltage of the current sampling resistor of the master changes), and then the receiver confirms the high / low level data signal receiving state locally according to the changed state and completes the corresponding high / low level data signal receiving.

[0091] It should be noted that the embodiment of the application also provides that the master can send data to all slaves in the master-slave network, but all slaves cannot send data at the same time. In order to achieve the technical effect of single time period and single sending of the slave, the application protocol layer constructed based on the application scheme can be used for control. For example, the master-slave polling protocol constructed between the master and the slave is one of the solutions, the master broadcasts a polling instruction with a current polling identifier to all slaves through the method of the embodiment of the application, and only the slave with a local identifier matching the current polling identifier will send corresponding response data to the master through the method of the embodiment of the application after receiving the polling instruction. Of course, there are many application protocols that can control the slave to achieve single time period and single sending, which will not be described one by one here.

[0092] After the working principle of the master-slave network of the embodiment of the application is described above, the master / slave data transceiving process of steps 2-3 is well understood. In order to understand the following steps 2-3 more intuitively, the embodiment of the application also provides Figure 5 The master-slave connection schematic diagram provided by the embodiment of the application is used as a reference.

[0093] Step 2, when the host sends high / low level data signal to the slave, the host controls its output level state to be opposite low / high level state and activates the slave to complete corresponding high / low level data signal receiving processing locally;

[0094] Here, when the host sends high / low level data signal to the slave, the host of the embodiment of the application causes the drain voltage V 2d of the second MOS transistor MOS2 on the slave side to generate corresponding high / low level state mapping by controlling the output level state of the first and second power lines to be low / high level state, and the slave confirms locally whether it is in high level data signal receiving state or low level data signal receiving state according to the level state of the drain voltage V 2d , and performs corresponding high / low level data signal receiving based on the confirmed state;

[0095] Specifically includes: step 21, when the host sends high level data signal to the slave, the host control module of the host controls the output level state of the first and second host access ends to be opposite low level state by reducing the potential difference between the first and second host output signal ends; and the slave completes corresponding high level data signal receiving processing locally when the output level state of the first and second host access ends is low level state.

[0096] Specifically includes: step 211, when the host sends high level data signal to the slave, the host control module of the host controls the output level state of the first and second host access ends to be opposite low level state by reducing the potential difference between the first and second host output signal ends.

[0097] Step 212, and the slave completes corresponding high level data signal receiving processing locally when the output level state of the first and second host access ends is low level state.

[0098] Specifically includes: step 2121, when the output level state of the first and second host access ends of the host is set to low level state, the input level state of the corresponding first and second slave access ends of the slave becomes low level state, so that the output voltage V p of the rectifier module corresponds to low level state, and then the drain voltage V 2d of the second MOS transistor MOS2 corresponds to high level state, and the signal level state of the first slave input signal end of the slave control module connected to the drain of the second MOS transistor MOS2 becomes high level state.

[0099] Step 2122, the slave control module of the slave continuously collects the signal of the first slave input signal end when the level state of the first slave input signal end is high level state, and obtains corresponding high level data signal.

[0100] Here, the high level state of the first slave input signal end means that the slave confirms locally that it is currently in a high level data signal receiving state, and at this time the slave's slave control module continuously collects data signals from the first slave input signal end, which is naturally the high level data signal synchronized with the host side.

[0101] Step 22, when the host sends low level data signals to the slave, the host's host control module controls the output level state of the first and second host access ends to be opposite high level state by increasing the potential difference between the first and second host output signal ends; and the slave completes the corresponding low level data signal receiving processing locally when the output level state of the first and second host access ends is high level state.

[0102] Specifically, it includes: step 221, when the host sends low level data signals to the slave, the host's host control module controls the output level state of the first and second host access ends to be opposite high level state by increasing the potential difference between the first and second host output signal ends;

[0103] Step 222, and the slave completes the corresponding low level data signal receiving processing locally when the output level state of the first and second host access ends is high level state.

[0104] Specifically, it includes: step 2221, when the output level state of the first and second host access ends of the host is set to high level state, the input level state of the corresponding first and second slave access ends of the slave becomes high level state, so that the output voltage V p of the rectifier module corresponding to high level state, and then the drain voltage V 2d of the second field effect tube MOS2 corresponding to low level state, and the signal level state of the first slave input signal end of the slave control module connected to the drain of the second field effect tube MOS2 becomes low level state.

[0105] Step 2222, the slave control module of the slave continuously collects signals from the first slave input signal end when the level state of the first slave input signal end is low level state, and obtains the corresponding low level data signal.

[0106] Here, the low level state of the first slave input signal end means that the slave confirms locally that it is currently in a low level data signal receiving state, and at this time the slave's slave control module continuously collects data signals from the first slave input signal end, which is naturally the low level data signal synchronized with the host side.

[0107] Step 3, when the slave sends the high / low level data signal to the host, the slave completes the corresponding setting according to the high / low level characteristics of the data signal on the premise that the output level state of the host is in the high level state, and the host performs the data signal receiving processing according to the sampling voltage of the current sampling resistor R S ;

[0108] Here, the slave of the embodiment of the application must execute when the host's output level state is in the high level state when the slave sends the high / low level data signal to the host; the slave of the embodiment of the application causes the sampling voltage of the host side current sampling resistor R S to change by regulating the on-line current of the first power line, and the host side signal processing module generates the corresponding high / low level state mapping according to the sampling voltage, and the host confirms whether the current is in the high level data signal receiving state or the low level data signal receiving state according to the identification signal output by the signal processing module, and performs the corresponding high / low level data signal receiving based on the confirmed state.

[0109] It should be noted that the slave master module of the slave of the embodiment of the application can identify the output level state of the host according to the level state of the first slave input signal end, specifically: the slave master module of the slave identifies the level state of the first slave input signal end; if the level state of the first slave input signal end is in the low level state, it is confirmed that the input level state of the first and second slave access ends of the slave is in the high level state, and then it is confirmed that the output level state of the first and second host access ends of the host is in the high level state, that is, it is confirmed that the output level state of the host is in the high level state; if the level state of the first slave input signal end is in the high level state, it is confirmed that the input level state of the first and second slave access ends of the slave is in the low level state, and then it is confirmed that the output level state of the first and second host access ends of the host is in the low level state, that is, it is confirmed that the output level state of the host is in the low level state.

[0110] It should be further noted that in the above step 3, the slave completes the corresponding setting according to the high / low level characteristics of the data signal on the premise that the output level state of the host is in the high level state, and the host performs the data signal receiving processing according to the sampling voltage of the current sampling resistor R S , specifically including:

[0111] Step B1, when the slave sends the high level data signal to the host, the slave master module of the slave makes the first field effect transistor MOS1 conduct by setting the signal level state of the first slave output signal end to the high level state; and the signal processing module of the host samples the current of the current sampling resistor R SThe two sides voltage of the current sampling resistor R is measured to generate corresponding sampling voltage, and the high and low level data signal is identified according to the sampling voltage, and the corresponding identification signal is output to the first host input signal end of the host control module; and the host control module of the host continuously collects the signal of the first host input signal end when the identification signal input by the first host input signal end is in the high level state to obtain the corresponding high level data signal.

[0112] Here, once the first field effect tube MOS1 on the slave side is turned on, the output end of the current slave rectifier module will be grounded through the low impedance first field effect tube MOS1, which will reduce the equivalent impedance of the current slave, and will also increase the on-line current of the first power line; after the on-line current of the first power line increases, the voltage of the two sides of the current sampling resistor R S of the host side, that is, the sampling voltage obtained by the signal processing module, will also increase, and the identification signal output by the host signal processing module according to the sampling voltage will be in the high level state; at this time, the host will confirm that it is currently in the high level data signal receiving state, and the data signal continuously collected by the host control module from the first host input signal end is naturally the high level data signal synchronized with the slave side;

[0113] Step B2, when the slave sends low level data signal to the host, the first field effect tube MOS1 is turned off by the slave control module of the slave by setting the signal level state of the first slave output signal end to low level state; and the signal processing module of the host measures the voltage of the two sides of the current sampling resistor R S , generates corresponding sampling voltage, and outputs corresponding identification signal according to high and low level data signal identification, and sends it to the first host input signal end of the host control module; and the host control module of the host continuously collects the signal of the first host input signal end when the identification signal input by the first host input signal end is in the low level state to obtain the corresponding low level data signal.

[0114] Here, when the first field effect tube MOS1 on the slave side is in the off state, the equivalent impedance of the current slave increases, and the on-line current value of the first power line at this time is necessarily less than the current value in the on state of the first field effect tube MOS1, and the voltage of the two sides of the current sampling resistor R S of the host side, that is, the sampling voltage obtained by the signal processing module, will also be less than the sampling voltage in the on state of the first field effect tube MOS1, and the identification signal output by the host signal processing module according to the sampling voltage will be in the low level state; at this time, the host will confirm that it is currently in the low level data signal receiving state, and the data signal continuously collected by the host control module from the first host input signal end is naturally the low level data signal synchronized with the slave side.

[0115] In summary, the embodiment of the present application provides a processing method for master-slave network based on power line transceiving data signal; a master-slave network composed of one master and multiple slaves is constructed, and the connection from the master to each slave is realized based on two power lines; and a processing mechanism for realizing high / low level data signal transceiving between the master and the slave is designed for the master-slave network, which causes the electrical state of the receiver (slave / master) to change correspondingly (the input level state of the slave changes / the voltage of the current sampling resistor of the master changes) by the sender (master / slave) regulating the state of the power line (output level state / current state of the power line), and then the receiver confirms whether it is in high level data signal receiving state or low level data signal receiving state according to the changed state and completes the corresponding high / low level data signal receiving. The processing method of the present application does not need to perform complex modulation and demodulation operation on the power line, and reduces the implementation difficulty and cost of the master / slave. The master / slave realized based on the present application is applied to short distance and simple scheduling operation and maintenance network (such as smart home, smart building, smart community, etc.), which shortens the development cycle and reduces the system cost and operation and maintenance cost.

[0116] Those skilled in the art will further appreciate that the functions implemented by each of the examples described herein can be implemented in hardware, computer software, or combinations thereof. For purposes of discussion herein, the specifications and examples will be presented in a general context of computer software implementation. Those skilled in the art will recognize that each of the examples described herein can be implemented in a corresponding computer software object or module and that various examples of connection, physical views, and relative positioning can be implemented by computer software, in hardware, or in combinations thereof.

[0117] The steps of a method or algorithm described in connection with the examples disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in random access memory (RAM), non-volatile memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. The present application can be implemented as a method, apparatus, or article of manufacture using standard programming and / or engineering techniques to produce software, firmware, hardware, or any combination thereof to control a computer to implement various aspects of the present application.

[0118] The above detailed description has further explained the purpose, technical solutions and advantages of the present application. It should be understood that the above description is only a specific implementation of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for processing data signals for transmitting and receiving data in a master-slave network based on power line, characterized in that, The method includes: A master-slave network is constructed; the master-slave network includes one master, multiple slaves, a first power line and a second power line; the master includes a first master access terminal, which is connected to the corresponding first and second power lines respectively; the slaves include a first slave access terminal, which is connected to the corresponding first and second power lines respectively. When the host sends a high / low level data signal to the slave, the host controls its output level to be in the opposite low / high level state, thereby activating the slave to complete the corresponding high / low level data signal reception and processing locally. When the slave device sends a high / low level data signal to the master device, provided that the output level of the master device is confirmed to be high, the slave device completes the corresponding setting locally based on the high / low level characteristics of the data signal, and the master device determines the setting based on the current sampling resistor R within the master device. S The sampled voltage is used for data signal reception and processing; The slave device completes the corresponding settings locally based on the high / low level characteristics of the data signal, and the master device completes the settings based on the current sampling resistor R within the master device. S The sampled voltage is used for data signal reception and processing, specifically including: When the slave device sends a high-level data signal to the master device, the slave master control module of the slave device turns on the first field-effect transistor MOS1 connected to the first slave output signal terminal by setting the signal level of the first slave output signal terminal to a high level; and the signal processing module of the master device processes the current sampling resistor R. S The voltage on both sides is measured to generate the corresponding sampling voltage, and the high and low level data signal is identified based on the sampling voltage. The corresponding identification signal is then sent to the first host input signal terminal of the host main control module. When the identification signal input to the first host input signal terminal is in a high-level state, the host main control module continuously collects the signal at the first host input signal terminal to obtain the corresponding high-level data signal. When the slave device sends a low-level data signal to the master device, the slave device's master control module turns off the first field-effect transistor MOS1 by setting the signal level of the first slave device's output signal terminal to a low level; and the master device's signal processing module processes the current sampling resistor R. S The voltage on both sides is measured to generate the corresponding sampling voltage, and the high and low level data signals are identified according to the sampling voltage. The corresponding identification signal is then sent to the first host input signal terminal of the host main control module. When the identification signal input to the first host input signal terminal is in a low level state, the host main control module continuously collects the signal at the first host input signal terminal to obtain the corresponding low level data signal.

2. The method for processing master-slave network data signals based on power line transmission and reception according to claim 1, characterized in that, In addition to the first and second host access terminals, the host also includes a power module, a crystal oscillator, a host main control module, a signal processing module, and the current sampling resistor R. S ; The power supply module is connected to the crystal oscillator, the host main control module, and the signal processing module respectively; the power supply module is used to supply power to the crystal oscillator, the host main control module, and the signal processing module respectively; The crystal oscillator is connected to the host main control module; the crystal oscillator is used to provide an external clock signal source to the host main control module; The current sampling resistor R S The two sides are referred to as the first and second side ports, wherein the first side port is connected to the first host output signal terminal of the host main control module, and the second side port is connected to the first host access terminal; The signal processing module and the current sampling resistor R S The first and second side ports are connected respectively, and are also connected to the first host input signal terminal of the host main control module; The signal processing module is used to process the current sampling resistor R. S The voltage on both sides is measured to generate a corresponding sampling voltage, and a high and low level data signal is identified based on the sampling voltage. The corresponding identification signal is then sent to the first host input signal terminal of the host main control module. The host main control module has ports for processing data signal transmission, including the first host output signal terminal and the second host output signal terminal, and ports for processing data signal reception, including the first host input signal terminal; the second host output signal terminal is connected to the second host access terminal.

3. The method for processing master-slave network data signals based on power line transmission and reception according to claim 2, characterized in that, The step of identifying high and low level data signals based on the sampled voltage and outputting a corresponding identification signal to the first host input signal terminal of the host main control module specifically includes: The signal processing module identifies preset processing modes; the processing modes include a first mode and a second mode. When the processing mode is the first mode, the sampled voltage is input to the built-in analog-to-digital converter for conversion and outputs a corresponding first conversion value; and it is identified whether the first conversion value meets the preset high-level conversion value range; if the first conversion value meets the high-level conversion value range, the corresponding first level state is set to a high level state; if the first conversion value does not meet the high-level conversion value range, it is identified whether the first conversion value meets the preset low-level conversion value range; if it does, the corresponding first level state is set to a low level state; if it does not, the corresponding first level state is set to an abnormal level state. When the processing mode is the second mode, the sampled voltage is input to a built-in first voltage comparator, which compares the sampled voltage based on a preset high-level reference voltage. If the sampled voltage exceeds the high-level reference voltage, a corresponding first comparison result is output as true; if the sampled voltage does not exceed the high-level reference voltage, a corresponding first comparison result is output as false. The first comparison result is then identified. If the first comparison result is true, the corresponding first level state is set to a high level state. If the first comparison result is false, the sampled voltage is input to a built-in second voltage comparator, which compares the sampled voltage based on a preset low-level reference voltage. If the sampled voltage does not exceed the low-level reference voltage, a corresponding second comparison result is output as true. When the sample voltage exceeds the low-level reference voltage, the corresponding second comparison result is output as false. When the second comparison result is true, the corresponding first level state is set to a low level state. When the second comparison result is false, the corresponding first level state is set to an abnormal level state. Both the first and second voltage comparators include two input terminals and one output terminal. One of the two input terminals of the first voltage comparator is used to input the sample voltage, and the other is used to input the high-level reference voltage. The output terminal of the first voltage comparator is used to output the first comparison result. One of the two input terminals of the second voltage comparator is used to input the sample voltage, and the other is used to input the low-level reference voltage. The output terminal of the second voltage comparator is used to output the second comparison result. The values ​​of the first and second comparison results include both true and false values. When the obtained first level state is not an abnormal level state, the first level state is sent as the output identification signal to the first host input signal terminal of the host main control module.

4. The method for processing master-slave network data signals based on power line transmission and reception according to claim 2, characterized in that, In addition to the first and second slave access terminals, the slave device also includes a rectifier module composed of first, second, third and fourth diodes D1, D2, D3 and D4, first and second field-effect transistors MOS1 and MOS2, first, second and third resistors R1, R2 and R3, fifth diode D5, first and second capacitors C1 and C2, low dropout linear regulator LDO and slave master control module; The rectifier module is a rectifier bridge composed of the first, second, third, and fourth diodes D1, D2, D3, and D4. The first and second diodes D1 and D2 are connected in series to form the first series diode path, and the third and fourth diodes D3 and D4 are connected in series to form the second series diode path. The first and second series diode paths are connected in parallel, with the positive terminals of the first and third diodes D1 and D3 interconnected, and the negative terminals of the second and fourth diodes D2 and D4 interconnected. The positive terminal connection point of the first and third diodes D1 and D3 is grounded. The series connection point of the first and second diodes D1 and D2 is connected to the first slave input terminal. The series connection point of the third and fourth diodes D3 and D4 is connected to the second slave input terminal. The negative terminal connection point of the second and fourth diodes D2 and D4 is connected to the source of the first field-effect transistor MOS1, the first side port of the first resistor R1, and the positive terminal of the fifth diode D5, respectively. The output node of the rectifier module is the negative terminal connection point of the second and fourth diodes D2 and D4, and the output voltage of the rectifier module is the node voltage of the output node, denoted as the corresponding output voltage V. p The output voltage V p The voltage level state corresponds to the input level state of the first and second slave access terminals. When the input level state of the first and second slave access terminals is high, the output voltage V... p When the voltage level is high and the input levels of the first and second slave terminals are low, the output voltage V p The voltage level is in a low state. The drain of the first field-effect transistor MOS1 is grounded, and its gate is connected to the first slave output signal terminal of the slave master control module. The first field-effect transistor MOS1 is turned on when the first slave output signal terminal is in a high-level state and turned off when the first slave output signal terminal is in a low-level state. When the first field-effect transistor MOS1 switches from off to on, the line current on the first power line increases; when the first field-effect transistor MOS1 switches from on to off, the line current on the first power line decreases. The first resistor R1 and the second resistor R2 are connected in series. The second side port of the first resistor R1 is connected to the first side port of the second resistor R2, and the second side port of the second resistor R2 is grounded. The series connection point of the first resistor R1 and the second resistor R2 is also connected to the gate of the second field-effect transistor MOS2. The gate voltage V of the second field-effect transistor MOS2 2g =V p *R2 / (R1+R2); The source of the second field-effect transistor MOS2 is grounded, and its drain is connected to the second side port of the third resistor R3 and the first slave input signal terminal of the slave master control module, respectively; The drain voltage of the second field-effect transistor MOS2 is denoted as the corresponding drain voltage V. 2d The second field-effect transistor MOS2 is at the output voltage V p When in a high-level state, it is turned on, corresponding to the gate voltage V. 2g When in a high-level state, the drain voltage V 2d The second field-effect transistor MOS2 is in a low-level state at the output voltage V. p When in a low-level state, it is turned off, corresponding to the gate voltage V. 2g When in a low-level state, the drain voltage V 2d It is in a high-level state; The cathode of the fifth diode D5 is connected to the voltage input terminal V of the low-dropout linear regulator LDO. in The first capacitor C1 is connected to its positive terminal; the negative terminal of the first capacitor C1 is grounded; the fifth diode D5 is connected to the output voltage V. p It is turned on when it is in a high-level state, and the output voltage V p Turn off when in a low-level state; the first capacitor C1 is at the output voltage V p When in a high-level state, it is charged by the rectifier module through the fifth diode D5, and the output voltage V p When in a low-level state, power is supplied to the low-dropout linear regulator by discharging. The voltage output terminal V of the low dropout linear regulator (LDO) out The first terminal of the third resistor R3, the positive terminal of the second capacitor C2, and the slave master control module are connected respectively; the ground terminal GND of the low dropout linear regulator LDO is used for grounding; the negative terminal of the second capacitor C2 is grounded; the low dropout linear regulator LDO is used to power the slave master control module and charge the second capacitor C2; the second capacitor C2 is used to power the voltage output terminal V of the low dropout linear regulator LDO. out Output voltage V DD Perform filtering; The slave master control module uses the first slave input signal terminal as the port for processing data signal reception and the first slave output signal terminal as the port for processing data signal transmission; the slave master control module uses a built-in RC crystal oscillator as the clock signal source.

5. The method for processing master-slave network data signals based on power line transmission and reception according to claim 4, characterized in that, The process of controlling the output level state of the host to be in opposite low / high level states, thereby activating the slave device to complete the corresponding high / low level data signal reception and processing locally, specifically includes: When the host sends a high-level data signal to the slave, the host master control module of the host controls the output level states of the first and second host access terminals to be opposite low-level states by reducing the potential difference between the output signal terminals of the first and second hosts; and the slave completes the corresponding high-level data signal reception processing locally when the output level states of the first and second host access terminals are low-level states. When the host sends a low-level data signal to the slave, the host master control module of the host controls the output level states of the first and second host access terminals to be opposite high-level states by increasing the potential difference between the first and second host output signal terminals; and the slave completes the corresponding low-level data signal reception processing locally when the output level states of the first and second host access terminals are high-level states.

6. The method for processing master-slave network data signals based on power line transmission and reception according to claim 5, characterized in that, The process of receiving and processing a corresponding high-level data signal locally when the slave device's output level at the first and second host access terminals is low specifically includes: When the output level of the first and second host access terminals of the host is set to a low level, the input level of the corresponding first and second slave access terminals on the slave device becomes a low level, thereby causing the output voltage V of the rectifier module to... p Correspondingly, it changes to a low level state, thereby causing the drain voltage V of the second field-effect transistor MOS2 to decrease. 2d Correspondingly, it becomes a high-level state, and the signal level of the first slave input signal terminal of the slave master control module connected to the drain of the second field-effect transistor MOS2 becomes a high-level state; When the level of the first slave input signal terminal is high, the slave master control module continuously acquires the signal at the first slave input signal terminal to obtain the corresponding high-level data signal.

7. The method for processing master-slave network data signals based on power line transmission and reception according to claim 5, characterized in that, The process of receiving and processing a corresponding low-level data signal locally when the slave device's output level at the first and second host access terminals is high specifically includes: When the output level of the first and second host access terminals of the host is set to a high level, the input level of the corresponding first and second slave access terminals on the slave device becomes a high level, thereby causing the output voltage V of the rectifier module to... p Correspondingly, it becomes a high-level state, which in turn causes the drain voltage V of the second field-effect transistor MOS2 to change. 2d Correspondingly, it becomes a low-level state, and the signal level of the first slave input signal terminal of the slave master control module connected to the drain of the second field-effect transistor MOS2 becomes a low-level state; When the level state of the first slave input signal terminal is low, the slave master control module of the slave device continuously collects the signal of the first slave input signal terminal to obtain the corresponding low-level data signal.

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