Measurement method and network device

Abstract

The embodiment of the application provides a measurement method and network equipment, the method comprises the following steps: obtaining the processing time length of each processing module in at least one processing module in the process of processing the message to be measured. Based on the processing time length of each processing module, the total processing time length of at least one processing module to the message is obtained. The embodiment of the application can obtain the forwarding delay of the electronic equipment or single chip to the message in the process of processing the message. Therefore, in the scene of end-to-end delay measurement, the forwarding delay of each hop electronic equipment can be obtained, so that the problem electronic equipment in the message forwarding process can be accurately positioned.

Description

Technical Field

[0001] This application relates to the field of communications, and more particularly to a measurement method and network device. Background Technology

[0002] Currently, for network processor data forwarding chips, forwarding latency is a very important indicator for measuring chip capabilities, and forwarding latency has a significant impact on service performance.

[0003] Existing technologies for measuring latency in forwarding paths typically employ end-to-end measurements. For example, they can test the round-trip latency between one device and another, or measure the one-way latency between devices. However, when multiple devices exist along the forwarding path, end-to-end measurements cannot accurately pinpoint the faulty device. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a measurement method and a network device. In this method, an electronic device or chip can obtain the total processing time of a packet, thereby acquiring the forwarding delay of each hop of the electronic device on the end-to-end forwarding path, and thus accurately locating the faulty device.

[0005] Firstly, embodiments of this application provide a measurement method. The method includes: a device receiving a first measurement message; the device acquiring the processing time of each processing module in at least one processing module processing the first measurement message; and the device acquiring the total processing time of the at least one processing module processing the first measurement message based on the processing time of each processing module. Thus, embodiments of this application, by performing latency statistics on individual processing modules in each electronic device along the forwarding path, can obtain the processing latency of each device, thereby enabling accurate location of faulty devices and modules along the transmission path.

[0006] For example, an electronic device may include multiple modules, and at least one processing module may be some or all of the multiple modules.

[0007] For example, the total processing time is the sum of the processing times of each processing module.

[0008] According to the first aspect, the first measurement message includes indication information, which indicates that the processing time of the first measurement message needs to be measured. Thus, a test message can be generated by adding this indication information.

[0009] For example, a test message can be a standalone message or a data message.

[0010] For example, the indication information can be in the frame header of the message.

[0011] According to the first aspect, or any implementation of the first aspect above, receiving a first measurement message includes: the device generating an indication signal in response to the received first measurement message, the indication signal being used to instruct at least one processing module to begin processing the first measurement message, and sending a trigger signal. Thus, after recognizing that the current message carries indication information, the processing module in the chip can be triggered to perform time delay measurement by generating the indication signal.

[0012] For example, the embodiments of this application employ a first-in, first-out (FIFO) testing method, meaning that each processing module sends a trigger signal when it begins processing. In other words, a latency test is initiated when each processing module starts processing.

[0013] According to the first aspect, or any implementation of the first aspect above, receiving a first measurement message includes: in response to the received first measurement message, identifying whether the first measurement message includes specified feature information; when the first measurement message is identified to include specified feature information, generating an indication signal, the indication signal being used to instruct at least one processing module to start processing the first measurement message, and sending a trigger signal. Thus, embodiments of this application also provide another delay measurement triggering method, whereby the device can determine whether a delay test needs to be performed on the message by identifying specified feature information in the message.

[0014] According to the first aspect, or any implementation of the first aspect above, the processing time of each processing module in at least one processing module for processing the first measurement message is obtained, including: in response to a trigger signal sent by each processing module, recording the start time of each processing module processing the first measurement message. Thus, the processing time of each module can be obtained by recording the start time of each module.

[0015] According to the first aspect, or any implementation of the first aspect above, each processing module is connected in series, and the processing time of each processing module is the difference between the start times of the two processing modules connected in series.

[0016] For example, for modules that process in parallel, only the module with the longest processing time can be counted as the processing time of the two parallel modules.

[0017] According to the first aspect, or any implementation thereof, the processing time of each processing module in at least one processing module for processing the first measurement message is obtained, including: after the previous processing module in two serially connected processing modules has finished processing the first measurement message, the processed first measurement message and the indication signal are transmitted to the next processing module. In this way, the processing delay of each processing module is continuously triggered in a relay manner.

[0018] According to the first aspect, or any implementation of the first aspect above, the specified feature information is at least one of the following: destination MAC address information, source MAC address information, destination IP address information, source IP address information, and tag information. In this way, the chip can match packets by recognizing the specified feature information, such as any of the above addresses. When a match is successful, the packet delay can be measured.

[0019] Secondly, embodiments of this application provide a network device. The network device includes: a receiving module for receiving a first measurement message; an acquiring module for acquiring the processing time of each of the at least one processing module in processing the first measurement message; and the acquiring module is further configured to acquire the total processing time of the at least one processing module in processing the first measurement message based on the processing time of each processing module in processing the first measurement message.

[0020] According to the second aspect, the first measurement message contains indication information, which indicates that the processing time of the first measurement message needs to be measured.

[0021] According to the second aspect, or any implementation of the second aspect above, the receiving module is configured to: generate an indication signal in response to the received first measurement message, the indication signal being used to indicate that at least one processing module begins processing the first measurement message, and send a trigger signal.

[0022] According to the second aspect, or any implementation of the second aspect above, the receiving module is configured to: in response to the received first measurement message, identify whether the first measurement message includes specified feature information; when the first measurement message is identified to include specified feature information, generate an indication signal, the indication signal being used to instruct at least one processing module to start processing the first measurement message, and send a trigger signal.

[0023] According to the second aspect, or any implementation of the second aspect above, the acquisition module is used to: in response to the trigger signal sent by each processing module, record the start time of each processing module processing the first measurement message.

[0024] According to the second aspect, or any implementation of the second aspect above, each processing module is connected in series, and the processing time of each processing module is the difference between the start times of the two processing modules connected in series.

[0025] According to the second aspect, or any implementation of the second aspect above, after the first processing module in the two connected processing modules has finished processing the first measurement message, it transmits the processed first measurement message and the indication signal to the next processing module.

[0026] According to the second aspect, or any implementation of the second aspect above, the specified feature information is at least one of the following: destination MAC address information, source MAC address information, destination IP address information, source IP address information, and tag information.

[0027] The second aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the second aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0028] Thirdly, embodiments of this application provide a computer-readable medium for storing a computer program, the computer program including instructions for performing the method in the first aspect or any possible implementation of the first aspect.

[0029] The third aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the third aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0030] Fourthly, embodiments of this application provide a computer program including instructions for performing the method in the first aspect or any possible implementation thereof.

[0031] The fourth aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the fourth aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0032] Fifthly, embodiments of this application provide a chip including a processing circuit and transceiver pins. The transceiver pins and the processing circuit communicate with each other via an internal connection path. The processing circuit executes the method in the first aspect or any possible implementation of the first aspect to control the receiving pin to receive signals and to control the transmitting pin to transmit signals.

[0033] The fifth aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the fifth aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0034] Fifthly, embodiments of this application provide a network device. This network device can be used to send a first message to a destination device via a data link, the data link including at least one intermediate device. The network device is further used to receive first processing delay information sent by each of the at least one intermediate device, the first processing delay information indicating the processing time for at least one processing module in the intermediate device to process the first message; and to receive second processing delay information sent by the destination device, the second processing delay information indicating the processing time for at least one processing module in the destination device to process the first message. The network device is further used to determine, based on the first and second processing delay information, whether a fault processing module exists in either the at least one intermediate device or the destination device. Thus, the network device can locate faulty modules based on the processing times corresponding to each processing module fed back by each device, thereby achieving accurate location of forwarding faults on the link and quickly locating faulty devices and modules. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of a communication system as an example.

[0036] Figure 2 This is a schematic diagram of the structure of an exemplary device;

[0037] Figure 3a This is a schematic diagram of the chip structure as an example.

[0038] Figure 3b This is a schematic diagram of the measurement process as an example.

[0039] Figure 4 This is a schematic diagram of the chip structure as an example.

[0040] Figure 5 This is a schematic diagram of the chip structure as an example.

[0041] Figure 6 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0042] Figure 7 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0043] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0044] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0045] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0046] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0047] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0048] Before describing the technical solutions of the embodiments of this application, the communication system of the embodiments of this application will first be described with reference to the accompanying drawings. See also Figure 1 This diagram illustrates a communication system provided in an embodiment of this application. The communication system includes device 1, device 2, device 3, and device 4. Device 1 is communicatively connected to device 2, device 2 is communicatively connected to device 3, and device 3 is communicatively connected to device 4. Any two devices among devices 1 to 4 can communicate. In the specific implementation of this embodiment, devices 1 to 4 can be computers, smartphones, servers, or other devices. For example, the communication connection between devices 1 to 4 can be wired or wireless. Figure 1 The connection relationships and number of devices shown are merely illustrative examples, and this application does not limit them.

[0049] Figure 2 This is a structural diagram of a device. Figure 2 middle:

[0050] The device includes at least one processor 101, at least one memory 102, at least one transceiver 103, at least one network interface 104, and one or more antennas 105. The processor 101, memory 102, transceiver 103, and network interface 104 are connected, for example, via a bus. The antennas 105 are connected to the transceiver 103. The network interface 104 enables the device to connect to other communication devices via a communication link. In this embodiment, the connection may include various interfaces, transmission lines, or buses, etc., and this embodiment is not limited to these. It should be understood that... Figure 2 The device 100 shown is merely an example, and the device 100 may have more or fewer components than those shown in the figure, may combine two or more components, or may have different component configurations. Figure 2 The device shown may be Figure 1 Any of the devices from device 1 to device 4.

[0051] The processor in this embodiment, such as processor 101, may include at least one of the following types: a general-purpose central processing unit (CPU), a digital signal processor (DSP), a microprocessor, an application-specific integrated circuit (ASIC), a microcontroller unit (MCU), a field-programmable gate array (FPGA), or an integrated circuit for implementing logic operations. For example, processor 101 may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. At least one processor 101 may be integrated into a single chip or located on multiple different chips.

[0052] The memory in this application embodiment, such as memory 102, may include at least one of the following types: read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions; random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions; or electrically erasable programmable-only memory (EEPROM). In some scenarios, the memory may also be a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto.

[0053] The memory 102 can exist independently and be connected to the processor 101. Optionally, the memory 102 can also be integrated with the processor 101, for example, integrated within a single chip. The memory 102 can store program code that executes the technical solutions of the embodiments of this application, and its execution is controlled by the processor 101. The various types of computer program code being executed can also be considered as drivers for the processor 101. For example, the processor 101 executes the computer program code stored in the memory 102 to implement the technical solutions of the embodiments of this application. Optionally, the memory 102 can also be located outside the chip and connected to the processor 101 via an interface.

[0054] Transceiver 103 can be used to support the reception or transmission of radio frequency (RF) signals between the device and other devices. Transceiver 103 can be connected to antenna 105. Transceiver 103 includes a transmitter Tx and a receiver Rx. Specifically, one or more antennas 105 can receive RF signals. The receiver Rx of transceiver 103 is used to receive the RF signals from the antennas, convert the RF signals into digital baseband signals or digital intermediate frequency (IF) signals, and provide the digital baseband signals or IF signals to the processor 101 so that the processor 101 can perform further processing on the digital baseband signals or IF signals, such as demodulation and decoding. In addition, the transmitter Tx in transceiver 103 is also used to receive modulated digital baseband signals or IF signals from processor 101, convert the modulated digital baseband signals or IF signals into RF signals, and transmit the RF signals through one or more antennas 105. Specifically, the receiver Rx can selectively perform one or more stages of downmixing and analog-to-digital conversion on the radio frequency signal to obtain a digital baseband signal or a digital intermediate frequency (IF) signal. The order of the downmixing and IF conversion processes is adjustable. The transmitter Tx can selectively perform one or more stages of upmixing and digital-to-analog conversion on the modulated digital baseband signal or digital IF signal to obtain a radio frequency signal. The order of the upmixing and IF conversion processes is also adjustable. The digital baseband signal and the digital IF signal can be collectively referred to as digital signals.

[0055] In combination with the above, as follows Figure 1 The following is a schematic diagram of the communication system. The specific implementation scheme of this application is described below:

[0056] For example, in the case of Figure 1 When testing the latency of the communication system, any one of devices 1 to 4 can initiate the latency test process. For example, this embodiment uses device 1 initiating the latency test as an example.

[0057] For example, during the data interaction between device 1 and device 4, devices 2 and 3 act as intermediary devices between device 1 and device 4, and can be used to forward data from device 1 to device 4, or forward data from device 4 to device 1.

[0058] Optionally, the data packets described in the embodiments of this application may be Ethernet packets, IP packets, tunnel packets, etc., and this application does not impose any limitations.

[0059] The testing process will be explained below using specific application scenarios.

[0060] Scene 1

[0061] Device 1 sends a message to Device 2, Device 2 forwards the message to Device 3, and Device 3 forwards the message to Device 4. During the process of Device 1 sending a message to Device 4, if the forwarding delay of the message is large, the user can trigger Device 1 to test the transmission delay of the message.

[0062] For example, device 1 receives a user instruction to instruct a test on a specified message. For example, the specified message can be indicated based on a message address. For instance, the user instruction can be used to instruct a test on a message with a specified address (e.g., device 4), meaning that device 1, in response to the user instruction, will initiate a test on the transmission delay of the message with the specified address. For example, the specified message can also be indicated based on the message type. For instance, the user instruction can be used to instruct a test on a message of a specified type. That is, device 1, in response to the user instruction, will initiate a test on the transmission delay of the message of the specified type.

[0063] In one possible implementation, the user can trigger the device to test a specified message or a specified transmission path. For example, a user instruction can be used to instruct device 1 to test the forwarding path between device 1 and device 4. The forwarding path includes device 1, device 2, device 3, and device 4. In this scenario, device 1 can test the transmission latency of the transmission path based on any message transmitted on that path. For example, device 1 can also generate a test message, such as a Ping message, for testing. This application is not limited. That is, in the embodiments of this application, when testing the transmission latency on the transmission path, it can be a data message or based on a test message; this application is not limited. Wherein, if the setting is based on a data message, the data message carries not only the data sent by device 1 to device 4, but also indication information, used to instruct each device on the transmission path to test the latency of this device.

[0064] For example, this embodiment of the application illustrates a method where a user instructs device 1 to test a message sent to device 4, i.e., a message with a specified address (the address of device 4). For example, device 1 generates a data message in response to the received user instruction. This data message includes, but is not limited to: the address information of device 1, the address information of device 4, data information, and indication information. The indication information is used to instruct each device on the transmission path to test the latency of this device based on the data message.

[0065] For example, the indication information can be carried in a designated field of the data packet. Optionally, the designated field can be included in the header of the data packet, or in the data portion of the data packet, etc. This application does not impose any limitations. It should be noted that each device on the transmission path needs to support the parsing of the designated field. That is, when each device receives a packet containing indication information, it can correctly parse the designated field in the packet to obtain the indication information.

[0066] For example, device 1 sends the generated data packet to device 2. It should be noted that the forwarding process between devices 1 and 4, such as the process of querying the path forwarding table, can be referred to the specific details in the existing technical embodiments, and will not be repeated here.

[0067] For example, device 2 receives a data packet sent by device 1. Device 2 parses the data packet to obtain indication information in a specified field of the data packet. In response to the obtained indication information, device 2 tests its transmission latency.

[0068] The following is a detailed explanation of the process for testing the transmission delay of device 2 on this device. Figure 3a This is a schematic diagram illustrating the structure of the chip in device 2 as an example. Please refer to... Figure 3a For example, the chip includes, but is not limited to, a Profile module 301, a processing module 302, a processing module 303, a processing module 304, a processing module 305, and a recording module 306. For example, Profile module 301 is connected to processing module 302, processing module 302 is connected to processing module 303, processing module 303 is connected to processing module 304, processing module 304 is connected to processing module 305, and processing modules 302 to 305 are respectively connected to recording module 306. Optionally, the connection between the modules can be via a bus or based on other lines; this application does not limit this. It should be noted that... Figure 3a The names and number of modules in this application are merely illustrative examples and are not intended to limit the scope of the application.

[0069] exist Figure 3a Technically, Figure 3b This is a schematic diagram illustrating an exemplary measurement process. Please refer to... Figure 3b For example, chip 300 receives a data packet. In this embodiment, the example is illustrated by specifying a field carried in the header of the packet.

[0070] For example, the Profile module 301 can parse the header portion of the data packet to obtain the indication information. Specifically, the Profile module 301 can store the correspondence between packet types and specified fields. As mentioned above, this embodiment can be applied to test different types of packets. Optionally, the specified fields for different packet types can be different. Correspondingly, the Profile module 301 can identify the packet type based on the packet header. And it can obtain the specified field corresponding to the packet type based on the correspondence between the packet type and the specified field. For example, the Profile module 301 can read the specified field corresponding to the packet to detect whether the packet carries specified information. In this embodiment, the example is that the Profile module 301 reads the indication information carried in the data packet. It should be noted that if no indication information is read, it means that the data packet does not need to be tested for transmission delay and can be processed according to the normal processing procedure.

[0071] For example, the Profile module 301 detects that a data packet carries indication information and determines that a transmission delay test needs to be performed on the data packet. For example, after detecting the indication information, the Profile module 301 generates an indication signal. The indication signal is used to instruct at least one module in the chip that processes the data packet to perform a transmission delay test.

[0072] Still refer to Figure 3b For example, the Profile module 301 outputs an indication signal to the processing module 302. The processing module 302 obtains the data packet from the chip's interface and receives the indication signal input from the Profile module 301.

[0073] Optionally, while transmitting data packets, each processing module may also transmit a VLD (valid) signal to indicate that the packet being transmitted is valid. It should be noted that the transmission and generation of this signal can be found in existing embodiments, and will not be repeated here.

[0074] For example, processing module 302 receives a data packet and an indication signal. In response to the received indication signal, processing module 302 determines that the transmission delay of the data packet needs to be tested. For example, processing module 302 can generate a trigger signal 1 and output trigger signal 1 to recording module 306. Simultaneously, processing module 302 performs corresponding processing on the data packet.

[0075] It should be noted that the processing modules in this application embodiment may process messages in the same or different ways.

[0076] It should be further noted that the chip in this embodiment may include more modules. For example, the chip may include 10 processing modules, while the processing modules that process the data packets are only a portion of the processing modules. Figure 3b Processing modules 302 to 305 are included. Other processing modules may not perform any processing. Each module in the chip can be enabled based on the type of the received message. That is, for different types of messages, the enabled modules in the chip can be the same or different. This application does not impose any limitations. In the embodiments of this application, when measuring transmission delay, only the delay of at least one processing module that processes the message is counted.

[0077] Please refer to Figure 3. For example, the recording module 306 may be configured with multiple registers. Each register corresponds to one processing module. It should be noted that, as mentioned above, the chip may include more processing modules, such as 10 modules, and optionally, 10 registers may be included, each corresponding to one processing module.

[0078] For example, the recording module receives trigger signal 1 from the processing module 302. Optionally, the recording module 306 can determine that trigger signal 1 was input by the processing module 302 based on the connection path between it and the processing module 302. Accordingly, the recording module can query the register corresponding to the processing module 302 (e.g., register 1) and write the timestamp corresponding to the current time into register 1.

[0079] Optionally, the clock maintained by the recording module 306 can be the same as a real-world clock. Optionally, the clock maintained by the recording module 306 can also be a relative clock; for example, the clock maintained by the recording module 306 may start counting from the time the device 1 is powered on. This application does not impose any limitations. Optionally, the clock maintained by the recording module 306 can also be updated periodically to ensure the accuracy of the recorded clock.

[0080] For example, after processing the data packet, processing module 302 outputs the data packet and an indication signal to processing module 303. Optionally, processing module 302 may also output a VLD signal to processing module 303 (the concept can be referred to above).

[0081] For example, processing module 303 receives a data packet and an indication signal. In response to the received indication signal, processing module 303 determines that transmission delay measurement of the data packet is required. Processing module 303 generates trigger signal 2 and outputs trigger signal 2 to the recording module. Simultaneously, processing module 303 processes the data packet.

[0082] For example, when the recording module 306 receives the trigger signal 2 input by the processing module 303, it can record the current timestamp 2 into the register 2 corresponding to the processing module 2. Other details can be found above and will not be repeated here.

[0083] For example, both processing module 304 and processing module 305 perform the above steps. Correspondingly, recording module 306 records the corresponding timestamps (including timestamp 3 and timestamp 4) based on the trigger signals input by processing modules 304 and 305. For specific details, please refer to the relevant description of processing module 302, which will not be repeated here.

[0084] For example, after processing the data packet, the processing module 305 outputs the processed data packet to other chips or devices (such as device 3).

[0085] Optionally, in one example, after processing the data packet, the processing module 305 can send a trigger signal 5 to the recording module 306. Correspondingly, the recording module 306 records the corresponding timestamp. It can be understood that the time difference between the timestamp corresponding to the trigger signal 4 sent by the processing module 305 and the timestamp corresponding to the trigger signal 5 sent by the processing module 305 is the processing time of the processing module 305. In another example, the processing time of the processing module 305 can be set to a preset value. That is, in subsequent statistical processes, the total processing time of the chip can be compensated based on the preset value, i.e., by adding the preset value of the processing time corresponding to the processing module 305. In this embodiment, the example of the processing module 305 sending a trigger signal 5 after processing is described.

[0086] Optionally, device 2 may include one or more chips. For example, if multiple chips in device 2 process data packets, each chip may perform the same processing steps as chip 300 described in this embodiment.

[0087] For example, Figure 4 This is a schematic diagram of the structure of device 2 as an example. Please refer to... Figure 4 For example, device 2 includes chip 300 and chip 400. A description of chip 300 can be found in [reference needed]. Figure 3a and Figure 3b Details will not be elaborated here. Chip 400 includes, but is not limited to: processing module 401, processing module 402, processing module 403, and processing module 404, as well as recording module 405. Optionally, chip 2 may or may not include a profile module; this application does not impose any limitations.

[0088] For example, the modules in chip 300 are arranged according to Figure 3bAfter the illustrated process steps are completed, processing module 305 outputs data packets and indication signals to processing module 401 in chip 400 through the interface between it and chip 400. Processing module 401 receives the data packets and indication signals, generates a trigger signal, and outputs the trigger signal to recording module 405. Recording module 405 can record timestamp 6. The processing of processing modules 402 to 404 can be referred to the description in chip 300, and will not be repeated here. Correspondingly, recording module 405 can record the timestamps corresponding to processing modules 402 to 404.

[0089] For example, still using Figure 3b Taking chip 300 as an example. For instance, after receiving a trigger signal from processing module 305, the recording module 306 in chip 300 can optionally output multiple saved timestamps (including timestamp 1 to timestamp 5) to the processor. The processor can, as needed, statistically analyze the acquired timestamps to obtain the transmission delay (also called processing delay or processing duration) of each processing module, and / or the total processing duration of chip 300. This total processing duration is the transmission delay (also called forwarding delay) of chip 300 when transmitting (or forwarding) data packets. It should be noted that the processor mentioned above and chip 300 are different devices; that is, the processor is outside chip 300 and connected via a bus or other connection method.

[0090] For example, the transmission delay of processing module 302 is the difference between timestamp 1 and timestamp 2 (i.e., timestamp 2 minus timestamp 1). The transmission delay of processing module 303 is the difference between timestamp 3 and timestamp 2 (i.e., timestamp 3 minus timestamp 2). The transmission delay of processing module 304 is the difference between timestamp 4 and timestamp 3 (i.e., timestamp 4 minus timestamp 3). The transmission delay of processing module 305 is the difference between timestamp 5 and timestamp 4 (i.e., timestamp 5 minus timestamp 4).

[0091] For example, the total processing time of chip 300 can be obtained by summing the transmission delays of each processing module. For example, the total processing time of chip 300 can also be obtained by the difference between timestamp 1 and timestamp 5 (i.e., timestamp 5 minus timestamp 1).

[0092] The processor can feed back the measurement results it has obtained to the upper-layer application. The measurement results include the transmission latency of each processing module and / or the transmission latency of the chip (i.e., device 2). The upper-layer application can transmit the measurement results to device 1.

[0093] As described above, after processing the data packet, device 2 sends the data packet to device 3. Devices 3 and 4 can then sequentially measure the transmission delay based on the measurement method described above and feed the measurement results back to device 1.

[0094] For example, device 1 may optionally display the measurement results corresponding to each device in a display window. Optionally, device 1 may also calculate the total transmission delay. The total transmission delay is the sum of the transmission delays of each device.

[0095] For example, if the total transmission delay exceeds a set threshold, device 1 can locate the problematic device based on multiple acquired measurement results. For instance, device 1 can set ranges corresponding to different devices or to the processing time (i.e., transmission delay) of each processing module within a device. If the transmission delay of a device exceeds the set threshold, the device can be identified as a problematic (or faulty) device. For example, device 1 can further compare the delays corresponding to each processing module within the device with preset ranges for each module to further identify the problematic module.

[0096] It should be noted that, in one example, if the clocks of devices 1 through 4 are synchronized, device 1 can obtain the transmission delay between devices based on the timestamp corresponding to each device. For example, the difference between the last timestamp of device 2 and the first timestamp of device 3 is the time taken for device 2 to transmit the message to device 3 (i.e., the transmission delay). In another example, if the clocks of devices 1 through 4 are not synchronized, device 1 can optionally obtain the total time for device 1 to transmit the message to device 4, which can be obtained through a Ping message. This total time includes the processing time of each device and the transmission delay when transmitting messages between devices. For example, device 1 can obtain the sum of the total time and the processing time of each device obtained by measurement to obtain the actual transmission delay of the transmitted message. For example, if the measured processing time of each device is less than a set threshold, i.e., no abnormality occurs in each device, and the actual transmission delay of the transmitted message is greater than the set threshold, then it can be determined that the factor affecting the message transmission is the transmission cable between the devices. For fault location of cables, existing technologies can be referenced, and this application does not limit it.

[0097] In one possible implementation, Figure 5This is a schematic diagram illustrating the structure of chip 500 as an example. Chip 500 includes, but is not limited to: Profile module 501, processing module 502, processing module 503, processing module 504, processing module 505, processing module 506, and recording module 507. For example, processing module 503 processes data packets by saving them. That is, the processing by processing module 503 does not affect the transmission delay of the data packets. Optionally, Profile module 501 may send data packets and indication signals to processing module 502 to instruct processing module 502 to perform transmission delay measurement on the data packets. Profile module 501 may send data packets to processing module 503 without sending indication signals. Processing module 503 processes the data packets accordingly. In another example, Profile module 501 may send data packets and indication signals to processing modules 502 and 503. After receiving the data packets and indication signals, processing module 503 does not generate a trigger signal, but only processes the data packets accordingly. In another example, Profile module 501 can send data packets and indication signals to processing modules 502 and 503. In this example, processing modules 502 and 503 can be considered as parallel processing modules. Processing modules 502 and 503 can generate trigger signals and output them to recording module 507. Accordingly, when the processor calculates the processing time of the processing modules, it can determine that processing modules 502 and 503 are parallel processing modules based on their timestamps. For parallel processing modules, the processor can use the processing time of the module with the longest processing time as the transmission delay of the parallel processing module.

[0098] In another possible implementation, key modules can be pre-defined, where a key module is one or more of a plurality of processing modules that process messages. That is, in this embodiment, the processing latency of only at least one of the plurality of processing modules can be statistically analyzed.

[0099] In one possible implementation, device 1 can also periodically initiate the above test process to achieve automatic detection of transmission delay.

[0100] It should be noted that in the above embodiments, the transmission delay of the chip can optionally be the sum of the delays of each processing module. For example, ideally, the processing delay of a processing module is equal to the difference between the processing delay and the recorded timestamp. However, since the processing module outputs a trigger signal to the recording module, there may be a certain delay in the transmission of the trigger signal and the response of the recording module. Optionally, this delay can be set to a default value, which can be subtracted when calculating the transmission delay of each processing module. Optionally, since the distance between each processing module and the recording module is different, the transmission delay of the trigger signal of each processing module is also different. Accordingly, the processor can pre-record the transmission delay of the trigger signal corresponding to each processing module. The transmission delay of the trigger signal corresponding to each processing module can be the same or different; this application does not limit this. When calculating the transmission delay of each processing module, the transmission delay of the trigger signal corresponding to each module can be subtracted. Optionally, since the transmission delay of the trigger signal is relatively small, it can also be ignored.

[0101] It should be further noted that the processing time of the Profile module also takes a certain amount of time. Optionally, the processing time of the Profile module can also be a set default value, which can be subtracted when calculating the chip's transmission latency. Optionally, the processing time of the Profile module is relatively small and can be ignored.

[0102] It should be further noted that the time of multiple devices can be synchronized or asynchronous. That is to say, even if the time of multiple devices is not synchronized, it will not affect the transmission latency statistics of a single device.

[0103] Scene 2

[0104] Device 1 sends a message to Device 2, Device 2 forwards the message to Device 3, and Device 3 forwards the message to Device 4. During the transmission of a message from Device 1 to Device 4, if the forwarding delay of the message along this transmission path is significant, the user can trigger Devices 1 through 4 to test the transmission delay of that message. For example, as described above, the message includes, but is not limited to, address information and data information, where the address information includes source address information and destination address information.

[0105] For example, a user can configure at least one of devices 1 to 4 by issuing a command through device 1 or by manual configuration. In response to the received user command, devices 1 to 4 update the matching method of the Profile module so that the Profile module can identify data packets containing specified characteristic information. This can be understood as triggering any device on the transmission path to perform a latency test through this identification method. Optionally, the identification method can be further configured to be periodic, for example, performing a latency test on packets containing specified characteristic information every period (e.g., 10 minutes).

[0106] Optionally, the specified characteristic information includes, but is not limited to, the destination address information and the source address information in the message. The destination address information and the source address information can be the destination MAC (Media Access Control Address) address information and the source MAC address information, or the destination IP (Internet Protocol Address) address information and the source IP address information; this application does not impose any limitation on these.

[0107] For example, after receiving a message, the Profile module can identify the address information of the message. For example, if the message is found to carry specified address information, other processing modules in the chip are triggered to perform a latency test on the message. Other details not described herein can be found in the description of Scenario 1, and will not be repeated here.

[0108] The following describes an apparatus provided by an embodiment of this application. For example... Figure 6 As shown:

[0109] Figure 6 This is a schematic diagram of a communication device provided in an embodiment of this application. Figure 6 As shown, the communication device 600 may include: a processor 601, a transceiver 605, and optionally a memory 602.

[0110] The transceiver 605, which may be referred to as a transceiver unit, transceiver, or transceiver circuit, is used to implement transceiver functions. The transceiver 605 may include a receiver and a transmitter. The receiver, which may be referred to as a receiver or receiving circuit, is used to implement the receiving function; the transmitter, which may be referred to as a transmitter or transmitting circuit, is used to implement the transmitting function.

[0111] The memory 602 may store computer programs, software code, or instructions 604, which may also be referred to as firmware. The processor 601 can control the MAC layer and PHY layer by running the computer programs, software code, or instructions 603 therein, or by calling the computer programs, software code, or instructions 604 stored in the memory 602, to implement the OM negotiation method provided in the following embodiments of this application. The processor 601 may be a central processing unit (CPU), and the memory 602 may be, for example, read-only memory (ROM) or random access memory (RAM).

[0112] The processor 601 and transceiver 605 described in this application can be implemented on integrated circuits (ICs), analog ICs, radio frequency integrated circuits (RFICs), mixed-signal ICs, application-specific integrated circuits (ASICs), printed circuit boards (PCBs), electronic devices, etc.

[0113] The communication device 600 may also include an antenna 606. The modules included in the communication device 600 are merely illustrative examples and are not intended to limit the scope of this application.

[0114] As mentioned above, the communication device described in the embodiments above can be an access point or a station, but the scope of the communication device described in this application is not limited to this, and the structure of the communication device can be unrestricted. Figure 6 The communication device can be a standalone device or part of a larger device. For example, the communication device can be implemented as follows:

[0115] (1) A standalone integrated circuit IC, or chip, or chip system or subsystem; (2) A collection of one or more ICs, optionally including storage components for storing data or instructions; (3) A module that can be embedded in other devices; (4) Others, etc.

[0116] For communication devices implemented as chips or chip systems, please refer to [link / reference]. Figure 7 The diagram shows the structure of the chip. Figure 7 The chip shown includes a processor 701 and an interface 702. There can be one or more processors 701, and multiple interfaces 702. Optionally, the chip or chip system may include a memory 703.

[0117] All relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0118] Based on the same technical concept, embodiments of this application also provide a computer-readable storage medium storing a computer program containing at least one piece of code that can be executed by an electronic device to control the electronic device to implement the above-described method embodiments.

[0119] Based on the same technical concept, this application also provides a computer program, which, when executed by an electronic device, is used to implement the above-described method embodiments.

[0120] The program may be stored, in whole or in part, on a storage medium packaged with the processor, or in part or in whole on a memory not packaged with the processor.

[0121] Based on the same technical concept, embodiments of this application also provide a processor for implementing the above-described method embodiments. The processor may be a chip.

[0122] Based on the same technical concept, embodiments of this application also provide a communication system, which includes the nodes and control devices described in the above method embodiments.

[0123] The steps of the methods or algorithms described in conjunction with the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium well known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Additionally, the ASIC can reside in a network device. Alternatively, the processor and storage medium can exist as discrete components in the network device.

[0124] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0125] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A measurement method applied to an electronic device comprising multiple processing modules, characterized in that, include: Receive the first measurement message; In response to the received first measurement message, identify whether the first measurement message includes specified feature information; When the first measurement message is identified to include the specified feature information, an indication signal is generated. The indication signal is used to instruct at least two processing modules to start processing the first measurement message, and a trigger signal is sent. In response to the trigger signal sent by each processing module, the start time of each processing module processing the first measurement message is recorded; Obtain the processing time of each of the at least two processing modules for processing the first measurement message; Based on the processing time of each processing module in processing the first measurement message, the total processing time of the at least two processing modules in processing the first measurement message is obtained.

2. The method according to claim 1, characterized in that, Each processing module is connected in series, and the processing time of each of the at least two processing modules, except for the last processing module, is the difference between the start times of the two processing modules connected in series.

3. The method according to claim 2, characterized in that, The step of obtaining the processing time of each of the at least two processing modules for processing the first measurement message includes: After the first processing module in the two connected processing modules finishes processing the first measurement message, it transmits the processed first measurement message and the indication signal to the next processing module.

4. The method according to claim 1, characterized in that, The specified feature information is at least one of the following: Destination MAC address information, source MAC address information, destination IP address information, source IP address information, and tag information.

5. A network device, the network device comprising a plurality of processing modules, characterized in that, Also includes: The receiving module is used to receive the first measurement message; In response to the received first measurement message, identify whether the first measurement message includes specified feature information; When the first measurement message is identified to include the specified feature information, an indication signal is generated. The indication signal is used to instruct at least two processing modules to start processing the first measurement message, and a trigger signal is sent. The acquisition module is used to record the start time of each processing module's processing of the first measurement message in response to a trigger signal sent by each processing module. Obtain the processing time of each of the at least two processing modules for processing the first measurement message; The acquisition module is further configured to acquire the total processing time of the first measurement message by the at least two processing modules based on the processing time of each processing module in processing the first measurement message.

6. The network device according to claim 5, characterized in that, Each processing module is connected in series, and the processing time of each of the at least two processing modules, except for the last processing module, is the difference between the start times of the two processing modules connected in series.

7. The network device according to claim 5, characterized in that, After the first processing module in the two connected processing modules finishes processing the first measurement message, it transmits the processed first measurement message and the indication signal to the next processing module.

8. The network device according to claim 5, characterized in that, The specified feature information is at least one of the following: Destination MAC address information, source MAC address information, destination IP address information, source IP address information, and tag information.

9. An apparatus, characterized in that, It includes at least one processor and an interface; the processor receives or transmits data through the interface; the at least one processor is configured to invoke a software program stored in memory to perform the method as described in any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed on a computer or processor, causes the computer or processor to perform the method as described in any one of claims 1 to 4.

11. A computer program product, characterized in that, The computer program product includes a software program that, when executed by a computer or processor, causes the method described in any one of claims 1 to 4 to be performed.

12. A network device, characterized in that, include: A first measurement message is sent to the destination device via a data link, wherein the data link includes at least one intermediate device; Receive first processing delay information sent by each of the at least one intermediate device, wherein the first processing delay information is used to indicate the total processing time for at least two processing modules in the intermediate device to process the first measurement message; as well as, The device receives second processing delay information sent by the destination device, the second processing delay information being used to indicate the total processing time for at least two processing modules in the destination device to process the first measurement message; Based on the first processing delay information and the second processing delay information, determine whether there is a fault handling module in the at least one intermediate device and the destination device; Each intermediate device includes: The receiving module is used to receive the first measurement message; In response to the received first measurement message, identify whether the first measurement message includes specified feature information; When the first measurement message is identified to include the specified feature information, an indication signal is generated. The indication signal is used to instruct the at least two processing modules to start processing the first measurement message, and a trigger signal is sent. The acquisition module is configured to, in response to a trigger signal received from each processing module, record the start time of each processing module processing the first measurement message; and acquire the processing time of each of at least two processing modules processing the first measurement message. The acquisition module is further configured to acquire the total processing time of the first measurement message by the at least two processing modules based on the processing time of each processing module in processing the first measurement message.

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