Fast turn-on protection for cascode switches

Abstract

A fast turn-on protection for a cascode switch is presented herein. The cascode circuit includes a depletion mode field effect transistor and an enhancement mode field effect transistor electrically coupled in a cascode fashion. During turn-on, a protection circuit detects an overcurrent fault by observing a plateau of a cascode node voltage. The overcurrent fault can be detected in response to the plateau existing for greater than a threshold time duration.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 129,086, filed on December 22, 2020, which is incorporated herein by reference in its entirety.

[0003] Background Information Technical Field

[0004] This disclosure generally relates to overcurrent protection, and more specifically to fast-start protection for common-source cascode switches. Background Technology

[0005] Electronic devices operate using electricity. Switch-mode power converters are commonly used to power many of today's electronic devices due to their high efficiency, small size, and light weight. Conventional wall outlets provide high-voltage alternating current (AC). In a switch-mode power converter, the high-voltage AC input is converted by energy transfer elements to provide a well-regulated direct current (DC) output. Switch-mode power converter controllers typically provide output regulation by sensing one or more inputs representing one or more output quantities and controlling the output in a closed loop. During operation, switches are used to provide the desired output by changing the duty cycle (typically the ratio of the switch's on time to the total switching cycle), changing the switching frequency, or changing the number of pulses per unit time of the switch in the switch-mode power converter.

[0006] Gallium nitride (GaN) and other wide-bandgap nitride III-based direct transition semiconductor materials exhibit high breakdown electric fields and contribute to high current densities. In this regard, GaN-based semiconductor devices are actively studied as alternatives to silicon-based semiconductor devices in power and high-frequency applications. For example, compared to silicon power MOSFETs of comparable area, GaN HEMTs can offer lower specific on-resistance at higher breakdown voltages.

[0007] Power field-effect transistors (FETs) can be either enhancement-mode or depletion-mode. An enhancement-mode device can refer to a transistor (e.g., a field-effect transistor) that blocks current (i.e., is off) when no gate bias is applied (i.e., when the gate-to-source bias is zero). Conversely, a depletion-mode device can refer to a transistor that allows current (i.e., is on) when the gate-to-source bias is zero. Attached Figure Description

[0008] The following figures illustrate a non-limiting and non-exhaustive embodiment of fast-start protection for a common-source cascode switch, wherein, unless otherwise stated, the same reference numerals refer to the same parts in all the various views.

[0009] Figure 1A An example of a circuit according to one embodiment is shown, comprising a common-source cascode switch, a protection circuit, and a driver.

[0010] Figure 1B An example is shown of a power converter according to one embodiment, comprising a common source cascode switch, protection circuitry, and driver.

[0011] Figure 2 The turn-on waveforms for different operating modes, based on the teachings of this article, were compared.

[0012] Figure 3 An experimental waveform based on one implementation scheme is shown.

[0013] In all the views of the accompanying drawings, corresponding reference characters indicate corresponding parts. Those skilled in the art will understand that the elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to aid in understanding the various embodiments of this disclosure. Furthermore, common but easily understood elements that are useful or necessary in commercially viable embodiments are generally not depicted to facilitate viewing of these embodiments with less obstruction to the teachings herein. Detailed Implementation

[0014] In the following description, numerous specific details are set forth to provide a thorough understanding of the fast-start protection of common-source cascode switches. However, it will be apparent to those skilled in the art that the specific details are not required to practice the teachings herein. In other instances, well-known materials or methods have not been described in detail to avoid obscuring the contents of this disclosure.

[0015] Throughout this specification, references to "one embodiment," "an embodiment," "one example," or "an example" mean that a specific feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the teachings herein. Therefore, the phrases "in one embodiment," "an embodiment," "one example," or "an example" appearing in various places throughout this specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. Specific features, structures, or characteristics may be included in integrated circuits, electronic circuits, combinational logic circuits, or other suitable components that provide the described functionality. Additionally, it should be understood that the accompanying drawings are for illustrative purposes to those skilled in the art, and the drawings—including waveforms—are not necessarily drawn to scale.

[0016] In the context of this application, when a transistor is in an "off state" or "disconnected," it blocks current and / or substantially does not conduct current. Conversely, when a transistor is in an "on state" or "conducted," it is capable of significantly conducting current. By way of embodiment, the transistor may include an N-channel metal-oxide-semiconductor (NMOS) field-effect transistor (FET), wherein a high voltage is supported between a first terminal, i.e., the drain, and a second terminal, i.e., the source.

[0017] As discussed above, an enhancement-mode device can refer to a transistor that blocks current when the control voltage (e.g., gate-to-source voltage) is low (e.g., zero volts). In many circuit and switching applications, it may be desirable to use enhancement-mode transistors (i.e., enhancement-mode devices) to perform circuit functions. For example, in power applications, it is typically desirable to use power transistors as switches (i.e., power switches). Ideally, a power transistor can operate as a switch when it blocks current in one state (e.g., the state with zero control voltage) and provides current with low on-resistance and low power loss in a second state (e.g., the state with non-zero control voltage).

[0018] Additionally, in the context of this application, a cascode configuration can consist of two transistors (e.g., a field-effect transistor and / or a bipolar junction transistor). When a cascode is configured to operate as an amplifier, it can be referred to as a cascode amplifier. Furthermore, when a cascode is configured to operate as a switch, it can also be referred to as a cascode switch. Cascode configurations can also be classified based on transistor type; for example, a cascode configuration including a gallium nitride depletion-mode transistor can be referred to as a GaN cascode, a GaN cascode switch, and / or a GaN cascode amplifier. Alternatively and additionally, a cascode can be referred to as a cascode configuration, a cascode device, and / or a cascode circuit. Furthermore, during operation, a cascode can exhibit gain (e.g., voltage gain); and the gain of a cascode can be referred to as cascode gain, cascode circuit gain, cascode device gain, etc.

[0019] Modern high-power converters and power converters can use cascode devices, including gallium nitride (GaN) cascode devices (e.g., GaN cascode switches). Embodiments of modern high-power converters and / or modern power converters that may subject cascode devices (e.g., cascode switches) to failure and high currents may include, but are not limited to, power factor correction (PFC) converters, flyback converters, buck converters, and / or boost converters. For example, as used in a PFC converter, if the PFC inductor is short-circuited, the cascode switch (e.g., a GaN cascode switch) may experience very high currents (e.g., fifty amperes) for a short period of time (e.g., one hundred nanoseconds). Alternatively and additionally, as used in a boost converter, when the boost diode is short-circuited, the cascode switch (e.g., a GaN cascode switch) may experience very high currents.

[0020] Power converters, high-power converters, and their switches (e.g., cascode switches) typically require protection in case of faults and / or overcurrent conditions. Traditionally, overcurrent (i.e., overcurrent conditions) can be detected using protection circuitry and / or sensing field-effect transistors (FETs). Leading-edge blanking methods are often employed to avoid sensing information (e.g., current information) from the sensing FET during the initial transient. During the initial transient, the sensed information signal may contain noise with a considerable amplitude relative to the sensed information signal; and additional filtering may be required to extract the sensed information signal. Power converters using leading-edge blanking may wait for the protection circuitry and / or the sensing FET to reach a stable operating condition; and this may result in a longer time to detect overcurrent conditions.

[0021] Unfortunately, in modern power converters, overcurrent conditions (i.e., excessive current events) can occur rapidly after turn-on. For example, in low on-resistance (i.e., low RDS) devices (e.g., low RDS switches), overcurrent can occur rapidly on a time scale smaller than the leading-edge blanking time. Therefore, in modern power converters using low on-resistance cascode switches (e.g., GaN cascode switches and / or silicon carbide (SiC) cascode switches), overcurrent may occur too rapidly to be detected by conventional protection circuits using leading-edge blanking.

[0022] Therefore, a protection circuit is needed that can quickly detect overcurrent conditions after the circuit is switched on.

[0023] This paper presents a device and method for fast turn-on protection of a cascode switch. The cascode circuit includes a depletion-mode field-effect transistor and an enhancement-mode field-effect transistor electrically coupled in a cascode manner. During turn-on, the protection circuit detects overcurrent faults by observing the plateau period of the cascode node voltage. Overcurrent faults can be detected in response to the presence of the plateau period lasting for a duration greater than a threshold time.

[0024] Figure 1A A circuit 100 according to one embodiment is illustrated, including a cascode switch 101, a protection circuit 104, and a driver 110. The protection circuit 104 includes a comparator 105, an AND gate 106, and a controller 108. The cascode switch 101 may include a depletion-mode field-effect transistor 102 and an enhancement-mode field-effect transistor 103. The depletion-mode field-effect transistor 102 may be a gallium nitride (GaN) depletion-mode field-effect transistor (FET) 102 or a silicon carbide (SiC) depletion-mode field-effect transistor 102. The enhancement-mode field-effect transistor 103 may be a low-voltage field-effect transistor (FET) 103.

[0025] The GaN depletion-type FET 102 includes a GaN source SH, a GaN gate GH, and a GaN drain DH; and the low-voltage FET 103 includes a FET source S, a FET gate G, a FET drain D, and a FET body B. As illustrated, the GaN depletion-type FET 102 is electrically coupled to the low-voltage FET 103 in a cascode configuration, whereby the GaN source SH is electrically coupled to the FET drain D. Furthermore, the FET body B is electrically coupled to the FET source S; and the GaN gate GH and the FET source S are electrically coupled to ground GND.

[0026] With this configuration (i.e., cascode configuration), the cascode switch 101 can advantageously operate in enhancement mode (i.e., operate as a normally off device) in response to the gate voltage VGS applied to the FET gate G. For example, when the gate voltage VGS is less than the threshold voltage (e.g., two volts) of the low-voltage FET 103, the cascode switch 101 can block the cascode switching current ID; and when the gate voltage VGS is greater than the threshold voltage of the low-voltage FET 103, the cascode switch 101 can conduct the cascode switching current ID between the GaN drain DH and the FET source S. Therefore, the cascode switch 101 can be "turned on" when the gate voltage VGS transitions (i.e., switches) the cascode switch 101 from its off state to its on state.

[0027] As illustrated, the cascode switch 101 can support a drain voltage VDS between the GaN drain DH and the FET source S. Because the FET source S is electrically coupled to ground, the drain voltage VDS can also be referred to as the drain-to-source voltage VDS of the cascode switch 101.

[0028] As discussed above, the protection circuit 104 includes a comparator 105, an AND gate 106, and a controller 108. The non-inverting input of comparator 105 can be electrically coupled to the drain D of a FET to compare the cascode (e.g., cascode circuit) node voltage VDL with a threshold voltage HS_TH (e.g., five volts) at the inverting input of comparator 105. When the cascode node voltage VDL exceeds the threshold voltage HS_TH, the comparator output voltage VCMP can be asserted as high (i.e., logic state high).

[0029] Furthermore, as illustrated, the first input of AND gate 106 can be electrically coupled to the output of comparator 105 to receive the comparator output voltage VCMP. The second input of AND gate 106 can be electrically coupled to the output of controller 108; and the output of AND gate 106 can be electrically coupled to the input of controller 108. As shown, AND gate 106 provides the signal HSOUT as a logical AND function of the comparator output voltage VCMP and the enable signal ENHS.

[0030] According to the teachings of this document, during the turn-on period (i.e., after the gate voltage VGS is applied), the cascode node voltage VDL can exhibit a plateau period; and the protection circuit 104 can determine the presence of an overcurrent condition by monitoring the duration of this plateau period. For example, as described below regarding... Figure 2 As discussed in the waveform, controller 108 can assert the enable signal ENHS as high after calibration and / or a specified duration (e.g., three hundred nanoseconds) following the application of the gate voltage VGS.

[0031] Therefore, the signal HSOUT can indicate the duration during which the comparator output voltage VCMP remains high (i.e., the duration of the plateau period in the cascode node voltage VDL). Furthermore, the controller 108 can determine, in response to the signal HSOUT, that the cascode switch current ID is excessive and take corrective action (e.g., turn off the cascode switch). In one embodiment, the corrective action (e.g., turning off the cascode switch 101) can be performed after each turn-on event during a switching cycle. Alternatively and additionally, the corrective action can force the cascode switch 101 to remain off until the controller 108 is recycled.

[0032] Furthermore, driver 110 can be electrically coupled between controller 108 and cascode switch 101 to function as a gate driver. As illustrated, controller 108 provides a driver input voltage VDR to the input (I) of driver 110; consequently, driver 110 provides a gate voltage VGS at the output (O). For example, driver 110 can buffer (e.g., amplify) the driver input voltage VDR from controller 108 such that the gate voltage VGS is delivered with increased, sufficient power to drive the FET gate G.

[0033] Although driver 110 is shown external to controller 108, in other embodiments, driver 110 may be internal to controller 108. For example, controller 108 may utilize a low-impedance driver output port to directly drive the FET gate G at the gate voltage VGS.

[0034] Similarly, as those skilled in the art will understand, protection circuit 104 can be implemented using more or fewer circuit elements. Instead, as an alternative to using comparator 105 and / or AND gate 106, the cascode node voltage VDL can be directly provided to controller 108. Controller 108 can then use analog and / or digital processing to determine the duration of the plateau period.

[0035] Although controller 108 has been described above in the context of protection circuit 104, controller 108 can also provide the driver input voltage VDR based on additional system variables. For example, as in Figure 1B As shown, the controller 108 can also receive the output voltage VOUT and provide the driver input voltage VDR to regulate the output voltage VOUT.

[0036] Figure 1B An example is illustrated of a power converter 150 according to one embodiment, comprising a common-source common-gate switch 101, a protection circuit 104, and a driver 110. The power converter 150 includes... Figure 1AThe circuit consists of circuit 100, bridge rectifier 95, inductor L1, diode DB, output capacitor CB, and load RL. AC (ac) input power with AC voltage VAC can be delivered to bridge rectifier 95 between input terminals 91 and 93. Bridge rectifier 95 can then rectify the AC input power to provide rectified input power relative to ground GND (i.e., the input power signal including inductor current IL and input voltage VIN).

[0037] As illustrated, controller 108 can provide a driver input voltage VDR such that the gate voltage VGS turns the cascode switch 101 on and off according to the switching cycle. According to switching power supply theory, controller 108 can be part of a control loop configured to sample and regulate the output voltage VOUT. The output voltage VOUT can be regulated as controller 108 causes the cascode switch 101 to turn on and off according to the steady-state switching frequency. For example, power converter 150 can be configured as a boost converter and / or as a boost converter with power factor correction (PFC).

[0038] According to the teachings of this document, protection circuit 104 can protect cascode switch 101 each time it is switched on (i.e., switched on by gate voltage VGS). For example, if inductor L1 becomes short-circuited, this can cause an excessive, overcurrent condition in cascode switch 101. As described herein, protection circuit 104 can detect overcurrent rapidly (i.e., on the order of one hundred nanoseconds or less) by observing the duration of the plateau period in the cascode node voltage VDL.

[0039] Alternatively and additionally, protection circuit 104 can protect cascode switch 101 by turning it off for a longer time (e.g., one millisecond) than a switching cycle (e.g., ten microseconds). For example, in response to determining the presence of an overcurrent condition (e.g., a short circuit), protection circuit 104 can turn off cascode switch 101 and remain it off until controller 108 becomes refreshed. Furthermore, protection circuit 104 can determine a fault (e.g., a short circuit) after measuring the fault within several consecutive cycles (e.g., five consecutive switching cycles).

[0040] Based on the teachings of this paper, the threshold voltage HS_TH and threshold duration THS can be determined and / or calibrated experimentally to ensure that the protection circuit distinguishes between normal operating modes and fault modes (i.e., overcurrent and / or short-circuit conditions).

[0041] Transient behavior of common source cascode switch

[0042] For example, Figure 2The turn-on waveforms 201, 202a-c, 203a-c, 204a-c, 205a-c, 206a-c, 207, and 208c for different operating modes, according to the teachings of this paper, are compared. The different operating modes include discontinuous condition mode (DCM), continuous conduction mode (CCM), and fault modes (e.g., short-circuit or overcurrent conditions). As illustrated, waveforms 201, 202a-c, 203a-c, 204a-c, 205a-c, 206a-c, 207, and 208c are plotted as a time function of the turn-on event occurring at time t0. Therefore, times t1–t7 can describe the time events during the turn-on transient of the cascode switch 101.

[0043] As in Figure 2 As shown, waveform 201 depicts the driver input voltage VDR. Waveforms 202a-c illustrate the gate voltage VGS (i.e., gate-to-source voltage) of the low-voltage FET 103 during DCM, CCM, and fault modes, respectively. Waveforms 203a-c illustrate the cascode node voltage VDL during DCM, CCM, and fault modes, respectively. Waveforms 204a-c illustrate the cascode switching current ID during DCM, CCM, and fault modes, respectively. Waveforms 205a-c illustrate the drain-to-source voltage VDS during DCM, CCM, and fault modes, respectively. Waveforms 206a-c illustrate the comparator output voltage VCMP during DCM, CCM, and fault modes, respectively. Waveform 207 illustrates the enable signal ENHS from the controller 108; and waveforms 208a-c illustrate the signal HSOUT during fault mode.

[0044] Actions prior to activation at time t0

[0045] Before time t0, the driver input voltage VDR can be applied low (e.g., to zero volts), as shown by waveform 201. Simultaneously, driver 110 forces the FET gate G low, causing the cascode switch 101 to block current in its off state. Therefore, for times less than t0, driver 110 can maintain the gate voltage VGS at substantially zero, as indicated by waveforms 202a-c.

[0046] Furthermore, the cascode node voltage VDL can have a steady-state value that depends at least in part on the threshold voltage magnitude GaN_VTH (e.g., 10 volts) of the GaN depletion-mode FET 102. Therefore, for times less than time t0, the cascode node voltage VDL can maintain a maximum node voltage VDL_MX (e.g., 15 volts), as indicated by waveforms 203a-c. Additionally, in accordance with the teachings herein, the threshold voltage HS_TH can be selected (e.g., calibrated) to indicate overcurrent conditions; therefore, the threshold voltage HS_TH can have a value less than the threshold voltage magnitude GaN_VTH (e.g., 5 volts).

[0047] When the cascode switch 101 is operating in the open state before time t0, the cascode switch current ID can be substantially equal to its blocking state (e.g., leakage) current. Therefore, for times less than t0, the cascode switch current ID can be substantially equal to zero (e.g., less than one hundred microamps), as illustrated by waveforms 204a-c.

[0048] Meanwhile, prior to time t0, the cascode switch 101 can maintain a drain voltage VDS that is at least partially determined by the breakdown voltage (e.g., 800 volts) of the GaN depletion-type FET 102. Therefore, prior to time t0, the drain voltage VDS can be at its maximum drain voltage VDS_MX (e.g., 600 volts), as illustrated by waveforms 205a-c.

[0049] Additionally, before time t0, when the cascode switch 101 is open, the protection circuit 104 can be in standby mode and / or disabled by the enable signal ENHS. For example, referring to waveforms 203a-c, the cascode node voltage VDL can be greater than the threshold voltage HS_TH. Therefore, the comparator output voltage VCMP can indicate that the cascode node voltage VDL is greater than the threshold voltage HS_TH. Thus, before time t0, the comparator output voltage VCMP is logic high (e.g., five volts), as illustrated by waveforms 206a-c.

[0050] However, before time t0, controller 108 can apply the enable signal ENHS low, causing the output of logic AND gate 106 to remain low. Therefore, the enable signal ENHS can be applied low (e.g., zero volts), causing the signal HSOUT to remain low (e.g., zero volts), as illustrated by waveforms 207 and 208c.

[0051] Behavior at time t0

[0052] At time t0 (e.g., zero nanoseconds), controller 108 may apply driver input voltage VDR to initiate switching (e.g., to begin the process of switching on cascode switch 101). For example, as illustrated by waveform 201, driver input voltage VDR may be applied high (e.g., five volts) at time t0.

[0053] According to the teachings of this paper, the threshold duration THS can be a duration that begins simultaneously and / or substantially simultaneously with the start-up event at time t0. For example, an analog and / or digital timer can start timing the threshold duration THS at time t0; and the threshold duration THS can have a pre-selected value based on experimental data and / or calibration (e.g., 250 nanoseconds).

[0054] In response to the transition of the driver input voltage VDR at time t0, the driver 110 can begin to drive the FET gate G. For example, as illustrated by waveforms 202a-c, the gate voltage VGS can begin to ramp (i.e., increase in voltage).

[0055] Furthermore, at time t0, the low-voltage FET 103 can momentarily remain in its off state. Therefore, at time t0, the cascode switch 101 can be off. For example, as illustrated by waveforms 203a-c, the cascode node voltage VDL remains at its maximum node voltage VDL_MX. As illustrated by waveforms 204a-c, the drain current ID can be substantially equal to its blocking state (e.g., leakage) current; and according to waveforms 205a-c, the drain voltage VDS remains at its maximum drain voltage VDS_MX.

[0056] Additionally, as illustrated by waveforms 203a-c at time t0, the cascode node voltage VDL can remain greater than the threshold voltage HS_TH. Therefore, at time t0, the comparator output voltage VCMP remains logic high (e.g., five volts), as illustrated by waveforms 206a-c.

[0057] According to the teachings of this paper, the duration threshold can begin at time t0. Therefore, as illustrated by waveforms 207 and 208c, the enable signal ENHS can continue to be applied low (e.g., zero volts) so that the signal HSOUT remains low (e.g., zero volts) at time t0.

[0058] Behavior from time t0 to time t1

[0059] From time t0 to time t1, controller 108 may continue to apply the driver input voltage VDR high, as depicted by waveform 201. Furthermore, driver 110 continues to drive the FET gate G. Therefore, the gate voltage VGS may continue to increase (i.e., ramp up); and the rate of increase (i.e., the time derivative of the gate voltage VGS) may depend at least in part on the capacitance (e.g., the gate capacitance) of the low-voltage FET 103. Thus, as illustrated by waveforms 202a-c, the gate voltage VGS increases from its low value (e.g., zero volts) at time t0 (e.g., zero nanoseconds) towards its value VG1 (e.g., two volts) at time t1 (e.g., ten nanoseconds).

[0060] During the time interval from time t0 to time t1, the GaN depletion-mode FET 102 is not yet turned on; and the low-voltage FET 103 is not yet turned on with sufficient strength to pull down the GaN source SH. Therefore, from time t0 to time t1, the cascode switch 101 can remain off. For example, as illustrated by waveforms 203a-c, the cascode node voltage VDL remains at its maximum node voltage VDL_MX. As illustrated by waveforms 204a-c, the drain current ID can continue to be substantially equal to its blocking state (e.g., leakage) current; and according to waveforms 205a-c, the drain voltage VDS remains at its maximum drain voltage VDS_MX.

[0061] Additionally, as illustrated by waveforms 203a-c from time t0 to time t1, the cascode node voltage VDL can remain greater than the threshold voltage HS_TH. Therefore, from time t0 to time t1, the comparator output voltage VCMP remains logic high (e.g., five volts), as illustrated by waveforms 206a-c. Furthermore, as illustrated by waveforms 207 and 208c, the enable signal ENHS can continue to be applied low (e.g., zero volts), causing the signal HSOUT to remain low (e.g., zero volts) from time t0 to time t1.

[0062] Behavior at time t1

[0063] At time t1 (e.g., ten nanoseconds), controller 108 may continue to apply the driver input voltage VDR high, as depicted by waveform 201; and consequently, driver 110 continues to drive the FET gate G. The gate voltage VGS may reach a value VG1 (e.g., two volts), thereby giving the low-voltage FET 103 sufficient drive to begin pulling down the GaN source SH. For example, the value VG1 may be substantially equal to the threshold voltage of the low-voltage FET 103. Furthermore, the low-voltage FET 103 may begin to have increased gain, thereby causing an increase in the effective gate capacitance (e.g., Miller capacitance).

[0064] Therefore, at time t1, the rate of change of the gate voltage VGS can be reduced in part due to the increase in the effective gate capacitance at the FET gate G. Thus, as illustrated by waveforms 202a-c, the rate of change of the gate voltage VGS (i.e., the time derivative) decreases.

[0065] Additionally, at time t1, the GaN depletion-mode FET 102 is not yet turned on; however, the low-voltage FET 103 can have sufficient strength to pull down the GaN source SH. Therefore, as illustrated by waveforms 203a-c, the cascode node voltage VDL can begin to decrease from its maximum node voltage VDL_MX. As illustrated by waveforms 204a-c, the drain current ID can continue to be substantially equal to its blocking state (e.g., leakage) current; and according to waveforms 205a-c, the drain voltage VDS remains at the maximum drain voltage VDS_MX.

[0066] Additionally, as illustrated by waveforms 203a-c, the cascode node voltage VDL remains greater than the threshold voltage HS_TH. Therefore, at time t1, the comparator output voltage VCMP remains logic high (e.g., five volts), as illustrated by waveforms 206a-c. Furthermore, as illustrated by waveforms 207 and 208c, the enable signal ENHS can continue to be applied low (e.g., zero volts), causing the signal HSOUT to remain low (e.g., zero volts).

[0067] Behavior from time t1 to time t2

[0068] From time t1 to time t2, controller 108 can continue to apply the driver input voltage VDR high, as depicted by waveform 201; and consequently, driver 110 continues to drive the FET gate G. During the time period from time t1 to time t2, GaN depletion-type FET 102 can continue to be off; and low-voltage FET 103 can continue to have sufficient drive to begin pulling down the GaN source SH. Therefore, the rate of change of gate voltage VGS (i.e., the time derivative) can continue to be reduced due to the increased gain.

[0069] Therefore, as illustrated by waveforms 202a-c, the rate of change of the gate voltage VGS (i.e., the time derivative) has decreased, such that the gate voltage VGS at time t2 can be substantially equal to the gate voltage VGS at time t1 (i.e., the value VG1 at time t1).

[0070] Furthermore, from time t1 to time t2, the GaN depletion-mode FET 102 can be turned off, while the low-voltage FET 103 can continue to pull down the GaN source SH. Therefore, as illustrated by waveforms 203a-c, the cascode node voltage VDL can monotonically decrease from its maximum node voltage VDL_MX at time t1 toward the threshold voltage magnitude GaN_VTH. As illustrated by waveforms 204a-c, the drain current ID can continue to be substantially equal to its blocking state (e.g., leakage) current; and according to waveforms 205a-c, the drain voltage VDS can remain at the maximum drain voltage VDS_MX.

[0071] As illustrated by waveforms 203a-c, the cascode node voltage VDL remains greater than the threshold voltage HS_TH. Therefore, from time t1 to time t2, the comparator output voltage VCMP remains logic high (e.g., five volts), as illustrated by waveforms 206a-c. Furthermore, as illustrated by waveforms 207 and 208c, the enable signal ENHS can continue to be applied low (e.g., zero volts), causing the signal HSOUT to remain low (e.g., zero volts).

[0072] Behavior at time t2

[0073] At time t2 (e.g., twenty nanoseconds), controller 108 may continue to apply the driver input voltage VDR high, as depicted by waveform 201. Furthermore, driver 110 continues to drive the FET gate G, causing the GaN depletion-type FET 102 to turn on. As illustrated by waveforms 202a-c, the rate of change of the gate voltage VGS remains low.

[0074] When the GaN depletion-type FET 102 is turned on, the cascode switch 101 is turned on. Therefore, as depicted by waveforms 203a-c, the rate of change of the cascode node voltage VDL can be altered.

[0075] As illustrated by waveforms 203a-c, the cascode node voltage VDL can still be greater than the threshold voltage HS_TH. Therefore, the comparator output voltage VCMP remains logic high (e.g., five volts), as illustrated by waveforms 206a-c. Furthermore, as illustrated by waveforms 207 and 208c, the enable signal ENHS can continue to be applied low (e.g., zero volts), causing the signal HSOUT to remain low (e.g., zero volts).

[0076] According to the teachings of this article, when the cascode switch 101 is turned on, the transient behavior of the cascode switch 101 can also become mode-dependent at time t2.

[0077] DCM behavior after time t2

[0078] During the DCM period after time t2, the cascode node voltage VDL drops below the threshold voltage HS_TH during the threshold time duration THS (e.g., 250 nanoseconds) and at time t3 (e.g., 100 nanoseconds).

[0079] Under DCM, the common source cascode switch 101 can be quickly turned on and configured to operate as a zero current switch (ZCS).

[0080] After time t2, the controller 108 continues to apply the driver input voltage VDR high, as depicted by waveform 201.

[0081] As illustrated by waveform 202a, the rate of change of the gate voltage VGS remains low; and the gate voltage VGS is slightly greater than the value VG1 until time t4 (e.g., 150 nanoseconds). At time t4, the gate voltage VGS may increase at least in part due to the decrease in gain of the cascode switch. The decrease in gain may be accompanied by a decrease in capacitance (e.g., Miller capacitance) at the FET gate G. Therefore, the gate voltage VGS rises until it reaches its maximum limit VG2 (e.g., 20 volts).

[0082] As illustrated by waveform 203a, the cascode node voltage VDL drops to the threshold voltage HS_TH before time t3 (e.g., one hundred nanoseconds). As discussed below and in accordance with semiconductor device physics, the cascode node voltage VDL can reach the threshold voltage HS_TH before time t3, at least in part, due to the low voltage FET 103 exiting saturation.

[0083] As illustrated by waveform 204a, the cascode switching current ID increases and decreases depending on the DCM configuration and DCM operating conditions. Compared to waveforms 204b (CCM) and 204c (fault mode), waveform 204a exhibits the minimum cascode switching current ID as a function of time.

[0084] For example, under DCM operating conditions, the cascode switching current ID reaches its limit before time t3 and decreases toward its minimum value (e.g., approximately zero amperes) at time t4. Meanwhile, the low-voltage FET 103 can begin operating outside saturation based on the following relationship (Equation 1(EQ.1)) between the cascode switching current ID as a function of the transconductance GM_LVFET and the threshold voltage VTH of the low-voltage FET 103.

[0085] Equation 1: ID < (VGS - VTH) x GM_LVFET

[0086] Furthermore, the low-voltage FET 103 can pull the cascode node voltage VDL at an increased rate, which is determined at least in part by the ratio of the cascode switching current ID to the transconductance GM_LVFET (i.e., the ratio ID / GM_LVFET). For example, as shown by waveform 203a, the cascode node voltage VDL decreases at a faster rate after time t2.

[0087] As illustrated by waveform 205a, the drain voltage VDS decreases and reaches its low value (e.g., less than one volt) between time t3 and time t4.

[0088] As illustrated by waveform 206a, the comparator output voltage VCMP transitions from high (e.g., five volts) to low (e.g., zero volts) at time t3 in response to the cascode node voltage VDL reaching and / or falling below the threshold voltage HS_TH.

[0089] As illustrated by waveform 207, the threshold duration THS continues from time t0 to time t6 (e.g., 250 nanoseconds), at which time t6, the controller 108 can switch (i.e., apply) the enable signal ENHS high (e.g., 5 volts).

[0090] Because the comparator output voltage VCMP is applied low at time t3, before time t6, and throughout the threshold time duration THS, the AND gate 106 maintains the signal HSOUT low (e.g., zero volts) at all times (e.g., all times including t0-t7). In this way, the protection circuit 104 identifies the DCM as a normal mode without faults (e.g., no short circuits and / or overcurrent conditions).

[0091] CCM behavior after time t2

[0092] During the CCM period after time t2, the cascode node voltage VDL drops below the threshold voltage HS_TH during the threshold time duration THS (e.g., 250 nanoseconds) and at time t5 (e.g., 200 nanoseconds).

[0093] After time t2, the controller continues to apply the driver input voltage VDR high, as depicted by waveform 201.

[0094] As illustrated by waveform 202b, the rate of change of the gate voltage VGS remains low; and the gate voltage VGS is slightly greater than the value VG1 until time t6 (e.g., 250 nanoseconds). At time t6, the gate voltage VGS may increase at least in part due to the decrease in gain of the cascode switch. The decrease in gain may be accompanied by a decrease in capacitance (e.g., Miller capacitance) at the FET gate G. Therefore, the gate voltage VGS rises until it reaches its maximum limit VG2 (e.g., 20 volts).

[0095] As illustrated by waveform 203b, the cascode node voltage VDL drops to the threshold voltage HS_TH before time t5 (e.g., two hundred nanoseconds). As discussed herein and in accordance with semiconductor device physics, the cascode node voltage VDL can reach the threshold voltage HS_TH before time t5, at least in part, due to the low voltage FET 103 exiting saturation.

[0096] As illustrated by waveform 204b, the cascode switching current ID increases and decreases depending on the CCM configuration. The cascode switching current ID can ramp up (i.e., increase) until time t4. In one embodiment, at time t4, an external component, such as a boost diode (e.g., diode DB), can begin to recover, causing the cascode switching current ID to decrease. Waveform 204b exhibits a higher switching current ID than waveform 204a (DCM) and waveform 204c (failure mode); however, waveform 204b exhibits a lower switching current ID than waveform 204c (failure mode) for times greater than time t4.

[0097] For example, under CCM operation, the cascode switching current ID reaches its limit at time t4 and can change depending on the load conditions. Simultaneously, the low-voltage FET 103 can begin operating outside saturation based on the above relationship of the cascode switching current ID (Equation 1 (EQ.1)). Furthermore, the low-voltage FET 103 can pull the cascode node voltage VDL at an increasing rate, which is determined at least in part by the ratio of the cascode switching current ID to the transconductance GM_LVFET (i.e., the ratio ID / GM_LVFET). For example, as shown by waveform 203b, the cascode node voltage VDL decreases at a faster rate after time t4.

[0098] As illustrated by waveform 205b, the drain voltage VDS decreases and reaches its low value (e.g., less than one volt) between time t5 and time t6.

[0099] As illustrated by waveform 206b, the comparator output voltage VCMP transitions from high (e.g., five volts) to low (e.g., zero volts) at time t5 in response to the cascode node voltage VDL reaching and / or falling below the threshold voltage HS_TH.

[0100] As illustrated by waveform 207, the threshold duration THS continues from time t0 to time t6 (e.g., 250 nanoseconds), at which time t6, the controller 108 can switch (i.e., apply) the enable signal ENHS high (e.g., 5 volts).

[0101] Because the comparator output voltage VCMP is applied low at time t5, before time t6, and throughout the threshold time duration THS, the AND gate 106 maintains the signal HSOUT low (e.g., zero volts) at all times (e.g., all times including time t0-t7). In this way, the protection circuit 104 identifies the CCM as a normal mode without faults (e.g., no short circuits and / or overcurrent conditions).

[0102] Fault mode behavior after time t2

[0103] During the fault mode (e.g., short circuit and / or overcurrent condition) after time t2, the cascode node voltage VDL drops below the threshold voltage HS_TH at time t7 (e.g., 300 nanoseconds). As illustrated, time t7 occurs after the threshold duration THS (e.g., 250 nanoseconds).

[0104] After time t2, the controller 108 continues to apply the driver input voltage VDR high, as depicted by waveform 201.

[0105] As illustrated by waveform 202c, the rate of change of the gate voltage VGS remains low; and the gate voltage VGS is slightly greater than the value VG1. For example, the low-voltage FET 103 can continue to operate in saturation. Therefore, for all the illustrated times greater than time t2, the gate voltage VGS fails to reach the maximum limit VG2 (e.g., twenty volts).

[0106] As illustrated by waveform 203c, the cascode node voltage VDL gradually decreases (i.e., exhibits a plateau) and reaches the threshold voltage HS_TH before time t7 (e.g., 300 nanoseconds). The operation during the fault period, compared to operation during DCM and CCM, may be at least partially due to the low-voltage FET 103 remaining in saturation. The gradual decrease (i.e., plateau) of the cascode node voltage VDL may also be at least partially due to gain. As described above with respect to waveform 202c, the low-voltage FET 103 may operate with high gain in its saturation region. Therefore, the plateau can indicate gain and / or high gain; and the gain can be referred to as the cascode circuit gain.

[0107] As illustrated by waveform 204c, the cascode switching current ID ramps up (i.e., increases) depending on the fault condition (e.g., short circuit). Waveform 204c exhibits a higher switching current ID compared to waveforms 204a (DCM) and 204b (CCM). For example, as illustrated by waveform 204c, at time t7, the cascode switching current ID may ramp up to and / or exceed twenty amperes, at least in part due to the fault condition.

[0108] Compared to CCM and DCM, the cascode switching current ID increases during fault conditions, causing the low-voltage FET103 to continue operating in saturation. Therefore, the cascode switching current ID can continue to change according to the following relationship (Equation 2 (EQ.2)).

[0109] ID = (VGS - VTH) x GM_LVFET Equation 2

[0110] Furthermore, the cascode node voltage VDL can gradually decrease according to the following relationship (Equation 3 (EQ.3)) as the cascode switch current ID is a function of the transconductance GM_GaN of the depletion-mode FET 102.

[0111] VDL = GaN_VTH-ID / GM_GaN Equation 3

[0112] Therefore, when the transconductance GM_GaN is large, the cascode node voltage VDL can gradually decrease (i.e., with a small slope). Furthermore, during fault conditions, the GaN depletion-mode FET 102 may be exposed to high voltages.

[0113] For example, as illustrated by waveform 205c, the drain voltage VDS remains substantially equal to its maximum drain voltage VDS_MX for a time period greater than time t2.

[0114] As illustrated by waveform 206c, the comparator output voltage VCMP transitions from high (e.g., five volts) to low (e.g., zero volts) at time t7 in response to the cascode node voltage VDL reaching and / or falling below the threshold voltage HS_TH.

[0115] As illustrated by waveform 207, the threshold duration THS continues from time t0 to time t6 (e.g., 250 nanoseconds), at which time t6, the controller 108 can switch (i.e., apply) the enable signal ENHS high (e.g., 5 volts).

[0116] Because the comparator output voltage VCMP remains high after time t6 and after the threshold duration THS, the AND gate 106 switches (i.e. applies) the signal HSOUT high (e.g., five volts) at time t6. The signal HSOUT remains high until time t7, at which time the comparator output voltage VCMP is applied low.

[0117] In this way, the protection circuit 104 identifies the presence of a fault (e.g., an overcurrent and / or short circuit condition). During the time period from time t6 to time t7, when the signal HSOUT is applied high, the controller 108 can use the information to take corrective action. For example, as described below... Figure 3 As illustrated, controller 108 can immediately turn off common source cascode switch 101 in response to the signal HSOUT changing from low to high.

[0118] Figure 3 Experimental waveforms 301-302 according to one embodiment are illustrated. Waveform 301 depicts the cascode node voltage VDL from time TA to time TC, while waveform 302 depicts the cascode switching current ID from time TA to time TC. (Reference) Figure 2 Time TA can correspond to the transition of waveform 201 at time t0, time TB can correspond to time t6, and time TC can correspond to the time after time t6. Furthermore, the threshold duration can begin at time TA and end at time TB; and refer to... Figure 2 The time TC can correspond to any time interval from time t6 to time t7 during which the signal HSOUT is applied high. For example, time TA can be zero nanoseconds (0 ns). Time TB can be two hundred and fifty nanoseconds (250 ns); and time TC can be two hundred and fifty-five nanoseconds (255 ns).

[0119] refer to Figure 1BOvercurrent conditions may be at least partially due to short circuits. For example, inductor L1 may be short-circuited by a low impedance that is essentially zero ohms (e.g., a milliohm short circuit). The calibrated value of the threshold voltage HS_TH may be approximately four volts (e.g., 4.15 volts); and the calibrated value of the threshold duration THS may be less than three hundred nanoseconds (e.g., 250 nanoseconds).

[0120] Furthermore, as illustrated by waveforms 301-302, the cascode node voltage VDL can gradually decrease during overcurrent conditions (e.g., short-circuiting inductor L1) (i.e., exhibiting a plateau period). For example, the cascode node voltage VDL at time TA might be ten volts, and the cascode node voltage VDL at time TC might be seven volts. Therefore, at time TB after the threshold duration THS has expired, the protection circuit 104 can determine that the cascode node voltage VDL exceeds the threshold voltage HS_TH.

[0121] Furthermore, the protection circuit 104 can take corrective action to protect the cascode switch 101. For example, the drive signal VDR can be applied low by the controller 108 immediately at time TB (e.g., within nanoseconds). Furthermore, when the cascode switch current ID reaches forty amperes at time TC, the driver 110 can drive the gate voltage VGS low.

[0122] Therefore, in accordance with the teachings of this document, the protection circuit 104 can advantageously and rapidly (e.g., within three hundred nanoseconds) turn off the cascode switch 101 before the cascode switch current ID exceeds its maximum current rating (e.g., a maximum current rating of fifty amperes).

[0123] According to the teachings of this paper, the protection circuit 104 can observe the cascode node voltage VDL from the cascode switch 101 for all time immediately following time t0. Therefore, protection can be implemented quickly and without leading-edge blanking. Furthermore, according to the teachings of this paper, a fault condition may occur when the cascode node voltage exhibits a plateau and gradually decreases as a function of time. For example, waveform 203c may gradually decrease from time t2 to time t7; therefore, waveform 203c can be characterized as exhibiting a plateau between time t2 and time t7.

[0124] In addition, based on the teachings of this document, the protection circuit 104 can detect overcurrent conditions based on the following time relationship (Equation 4 (EQ.4)) of the common source cascode node voltage VDL over a time longer than time t0 (i.e., the turn-on time t0).

[0125] VDL≥HS_TH for {time: (t0+THS)≤time} Equation 4 Therefore, according to the above relationship (Equation 4 (EQ.4)), if the cascode node voltage VDL is substantially greater than and / or equal to the threshold voltage HS_TH for at least the threshold time duration THS, an overcurrent condition may exist.

[0126] In one implementation and depending on the operation of the semiconductor device, the plateau period may be a result of gain (e.g., cascode switch gain). For example, during the plateau period starting from time t2, the low-voltage FET 103 may operate in its saturation region (i.e., the high-gain, high-transconductance region).

[0127] Furthermore, protection circuit 104 can determine whether cascode switch 101 is operating in fault (i.e., overcurrent) mode by means of comparator 105 and by means of threshold time duration THS (i.e., time period THS). For example, threshold time duration THS (i.e., time period THS) can be determined by controller 108. In addition, comparator 105 can compare cascode node voltage VDL with threshold voltage HS_TH. If comparator 105 remains in a logic high state (e.g., comparator output voltage VCMP is high) for more than time THS, then controller 108 can apply enable signal ENHS to logic high (see waveform 207, for example, at time t6).

[0128] In one implementation, the controller can adaptively adjust the threshold time duration (THS) in response to system parameters. For example, the controller can adaptively adjust the threshold time duration (THS) based on the load.

[0129] In one aspect, a power converter includes a cascode circuit (e.g., a cascode switch 101) and an overcurrent detection circuit (e.g., a protection circuit 104). The cascode circuit includes a depletion-mode field-effect transistor 102 and an enhancement-mode field-effect transistor 103 electrically coupled in a cascode manner to provide a cascode node voltage VDL. The overcurrent detection circuit is configured to detect overcurrent fault conditions during turn-on (see, for example...). Figure 2 Waveform 207 is shown within the time interval t0-t6. The overcurrent condition occurs during the plateau period of the cascode node voltage VDL (i.e., when waveform 203c gradually decreases). As discussed above, the plateau period can indicate the gain of the cascode switch 101. For example, the plateau period can indicate that the low-voltage FET 103 is operating in saturation.

[0130] In another aspect, a method for detecting overcurrent in a gallium nitride (GaN) cascode circuit (e.g., cascode switch 101) includes: switching on the GaN cascode circuit with a transient step (e.g., waveform 201 at time t0); receiving the cascode node voltage VDL; determining when the cascode node voltage VDL enters a plateau period (e.g., waveform 203c); and indicating an overcurrent fault (e.g., waveforms 207, 208c). For example, protection circuit 104 and comparator 105 can determine that the cascode node voltage VDL is slowly decreasing by comparing it with a reference voltage HS_TH. If this condition persists for more than time THS, then an overcurrent condition may exist. Therefore, an overcurrent fault is indicated in response to the existence of a plateau period longer than a threshold time duration (i.e., time THS).

[0131] Protection circuit 104 can detect when the cascode switch 101 experiences a fault condition (e.g., excessive switching current ID), not limited to the manner in which the fault occurs and not limited to the power converter configuration. In one configuration, protection circuit 104 can be used to rapidly detect overcurrent (i.e., overcurrent of the cascode switch current ID). For example, in a PFC converter, if the PFC inductor is short-circuited, the cascode switch 101 may experience a very high current (e.g., fifty amperes) for a short period of time (e.g., one hundred nanoseconds). Alternatively and additionally, the cascode switch 101 (e.g., a GaN cascode switch) used as the main switch in a boost converter may experience a very high current when the boost diode is short-circuited.

[0132] In one application, controller 108 can protect cascode switch 101 by immediately shutting it off in response to a determined fault condition (i.e., an overcurrent condition). For example, controller 108 can apply input drive signal VDR low when signal HSOUT is applied high. Alternatively and additionally, controller 108 can prevent cascode switch 101 from turning on until controller 108 has been recycled. Furthermore, controller 108 can be programmed to shut off cascode switch 101 after an overcurrent condition is detected within a set number of switching cycles (e.g., five).

[0133] The above description of the illustrative embodiments of this disclosure, including those described in the abstract, is not intended to be exhaustive or to limit the precise forms disclosed. While specific embodiments and examples of fast-start protection for cascode switches have been described for illustrative purposes with reference to the accompanying drawings as described herein, various equivalent modifications are possible without departing from the broader spirit and scope of this disclosure. Indeed, it should be understood that specific example voltages, currents, frequencies, power range values, times, etc., are provided for illustrative purposes, and other values ​​may be used in other embodiments and examples in accordance with the teachings herein.

[0134] Although the invention is defined in the claims, it should be understood that the invention may alternatively be defined according to the following embodiments:

[0135] Example 1: A power converter includes a cascode circuit and an overcurrent detection circuit. The cascode circuit includes a depletion-mode field-effect transistor and an enhancement-mode field-effect transistor electrically coupled in a cascode manner. The cascode circuit is configured to provide a cascode node voltage. The overcurrent detection circuit is configured to detect an overcurrent fault condition during turn-on, wherein the overcurrent fault condition occurs during a steady period of the cascode node voltage, the steady period indicating an increase in the gain of the cascode circuit.

[0136] Example 2: The power converter according to Example 1, wherein the overcurrent detection circuit includes a comparator.

[0137] Example 3: A power converter according to any one of the foregoing embodiments, wherein the overcurrent detection circuit includes an AND gate.

[0138] Example 4: A power converter according to any one of the foregoing embodiments, wherein the overcurrent detection circuit includes a controller.

[0139] Example 5: A power converter according to any one of the preceding examples, wherein the depletion-type field-effect transistor is a gallium nitride (GaN) depletion-type transistor.

[0140] Example 6: A power converter according to any one of the preceding examples, wherein the depletion-type field-effect transistor is a silicon carbide (SiC) depletion-type transistor.

[0141] Example 7: A power converter according to any one of the foregoing embodiments, wherein the enhancement field-effect transistor is a low-voltage field-effect transistor.

[0142] Example 8: A method for detecting overcurrent in a gallium nitride (GaN) cascode circuit, comprising: transiently step-on of the GaN cascode circuit; receiving a cascode node voltage indicating the gain of the cascode circuit; determining when the cascode node voltage enters a plateau period indicating an increase in the gain of the cascode circuit; and indicating an overcurrent fault in response to the presence of the plateau period for a duration greater than a threshold time.

[0143] Example 9: According to any one of the preceding examples, turning on the GaN common source cascode circuit includes: providing a gate signal to a low voltage field-effect transistor.

[0144] Example 10: According to any one of the preceding embodiments, receiving the cascode node voltage indicating the gain of the cascode circuit includes: receiving the drain voltage of the low-voltage field-effect transistor.

[0145] Example 11: According to any one of the preceding embodiments, determining when the cascode node voltage enters the plateau period indicating an increase in the gain of the cascode circuit includes: comparing the drain voltage of the low-voltage field-effect transistor with a threshold voltage.

[0146] Example 12: The method according to any one of the foregoing embodiments, wherein indicating the overcurrent fault in response to the presence of the plateau period within a duration greater than the threshold time includes: using a controller to determine the threshold time duration.

[0147] Example 13: A method for rapidly detecting overcurrent in a power converter, comprising: transiently step-on switching on a cascode switch; receiving a cascode node voltage indicating the gain of the cascode circuit; determining when the cascode node voltage enters a plateau period indicating an increase in the gain of the cascode circuit; and indicating an overcurrent fault in response to the presence of the plateau period for a duration greater than a threshold time.

[0148] Example 14: The method according to any one of the preceding examples, wherein the common-source cascode switch includes a depletion-type field-effect transistor and an enhancement-type field-effect transistor electrically coupled in a common-source cascode manner.

[0149] Example 15: The method according to any one of the preceding embodiments, wherein turning on the common source cascode switch includes: providing a gate signal to the enhancement-mode field-effect transistor.

[0150] Example 16: According to any one of the preceding embodiments, receiving the cascode node voltage indicating the gain of the cascode circuit includes: receiving the drain voltage of the enhancement-mode field-effect transistor.

[0151] Example 17: According to any one of the preceding embodiments, determining when the cascode node voltage enters the plateau period indicating an increase in the gain of the cascode circuit includes: comparing the enhancement-mode field-effect transistor with a threshold voltage.

[0152] Example 18: The method according to any one of the foregoing examples, wherein the threshold voltage is between one volt and ten volts.

[0153] Example 19: The method according to any one of the foregoing embodiments, wherein indicating the overcurrent fault in response to the presence of the plateau period within a duration greater than the threshold time includes: using a controller to determine the threshold time duration.

[0154] Example 20: The method according to any one of the foregoing embodiments, wherein the threshold time duration is between one hundred nanoseconds and three hundred nanoseconds.

Claims

1. A power converter, comprising: A cascode circuit comprising a depletion-mode field-effect transistor and an enhancement-mode field-effect transistor electrically coupled in a cascode manner, the cascode circuit being configured to provide a cascode node voltage; as well as Overcurrent detection circuit, wherein the overcurrent detection circuit includes: A comparator, electrically coupled to the cascode node voltage, to compare the cascode node voltage with a threshold voltage. A controller configured to monitor the duration of a steady period, wherein the overcurrent detection circuit is configured to detect an overcurrent fault condition during the turn-on period when the duration exceeds a threshold duration.

2. The power converter of claim 1, wherein the overcurrent detection circuit comprises an AND gate.

3. The power converter according to claim 1, wherein the depletion-type field-effect transistor is a gallium nitride (GaN) depletion-type transistor.

4. The power converter according to claim 1, wherein the depletion-type field-effect transistor is a silicon carbide (SiC) depletion-type transistor.

5. The power converter of claim 1, wherein the enhancement field-effect transistor is a low-voltage field-effect transistor.

6. The power converter of claim 1, wherein the threshold voltage is between one volt and ten volts.

7. The power converter of claim 1, wherein the threshold time duration is between one hundred nanoseconds and three hundred nanoseconds.

8. A method for detecting overcurrent in a gallium nitride (GaN) cascode circuit, comprising: The GaN cascode circuit is switched on by a transient step, wherein switching on the GaN cascode circuit includes providing a gate signal to a low-voltage field-effect transistor. Receive the common-source cascode node voltage, wherein receiving the common-source cascode node voltage includes receiving the drain voltage of the low-voltage field-effect transistor; Determining when the cascode node voltage enters a stable period includes comparing the drain voltage of the low-voltage field-effect transistor with a threshold voltage. as well as In response to the presence of the plateau period within a duration greater than a threshold time, an overcurrent fault is indicated, wherein indicating the overcurrent fault in response to the presence of the plateau period within a duration greater than the threshold time includes using a controller to determine the threshold time duration.

9. The method according to claim 8, wherein: The GaN common-source cascode circuit includes a depletion-type field-effect transistor electrically coupled to the low-voltage field-effect transistor in a common-source cascode manner.

10. The method of claim 9, wherein the low-voltage field-effect transistor is an enhancement-mode field-effect transistor.

11. The method of claim 8, wherein the threshold voltage is between one volt and ten volts.

12. The method of claim 8, wherein the threshold time duration is between one hundred nanoseconds and three hundred nanoseconds.

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