Parasitic mode measurement method, device, apparatus and storage medium

Abstract

The present disclosure provides a method and device for measuring parasitic modes in a quantum chip layout, and a storage medium, relating to the field of computer, and particularly to the fields of quantum computing and quantum simulation. The specific implementation scheme is as follows: simulating a quantum chip layout to obtain target eigenmode information of a quantum device in the quantum chip layout and target parasitic mode information of the quantum chip layout; wherein the quantum device is one of a plurality of quantum devices included in the quantum chip layout; obtaining target coupling strength between a target parasitic mode corresponding to the target parasitic mode information of the quantum device and the target parasitic mode information based on the target eigenmode information of the quantum device and the target parasitic mode information of the quantum chip layout; wherein the target coupling strength is used to measure the degree of influence of the target parasitic mode information on a characteristic parameter of the quantum device.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to the fields of quantum computing and quantum simulation technology. Background Technology

[0002] For quantum chip layouts that characterize quantum chips (such as superconducting quantum chips), parasitic modes are one of the key factors affecting the performance of quantum chip layouts (such as the chip performance of superconducting quantum chips). For example, parasitic modes may cause abnormal coupling strength between quantum devices and reduced coherence time. Summary of the Invention

[0003] This disclosure provides a method, apparatus, device, and storage medium for measuring parasitic modes in a quantum chip layout.

[0004] According to one aspect of this disclosure, a method for measuring parasitic modes in a quantum chip layout is provided, comprising:

[0005] Simulation of a quantum chip layout yields target intrinsic mode information of quantum devices within the quantum chip layout, as well as target parasitic mode information; wherein the quantum device is one of multiple quantum devices included in the quantum chip layout.

[0006] Based on the target intrinsic mode information of the quantum device and the target parasitic mode information of the quantum chip layout, the target coupling strength between the quantum device and the target parasitic mode corresponding to the target parasitic mode information is obtained; wherein, the target coupling strength is used to measure the degree of influence of the target parasitic mode information on the characteristic parameters of the quantum device.

[0007] According to another aspect of this disclosure, a device for measuring parasitic modes in a quantum chip layout is provided, comprising:

[0008] The simulation unit is used to simulate the quantum chip layout to obtain the target intrinsic mode information of the quantum devices in the quantum chip layout, and to obtain the target parasitic mode information of the quantum chip layout; wherein, the quantum device is one of the multiple quantum devices included in the quantum chip layout;

[0009] The processing unit is used to obtain the target coupling strength between the quantum device and the target parasitic mode corresponding to the target parasitic mode information based on the target intrinsic mode information of the quantum device and the target parasitic mode information of the quantum chip layout; wherein, the target coupling strength is used to measure the degree of influence of the target parasitic mode information on the characteristic parameters of the quantum device.

[0010] According to another aspect of this disclosure, a computing device is provided, comprising:

[0011] At least one quantum processing unit (QPU);

[0012] A memory, coupled to the at least one QPU and used to store executable instructions,

[0013] The instruction is executed by the at least one QPU to enable the at least one QPU to perform the method described above;

[0014] Or, including:

[0015] At least one processor; and

[0016] A memory communicatively connected to the at least one processor; wherein,

[0017] The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method described above.

[0018] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions that, when executed by at least one quantum processing unit, cause the at least one quantum processing unit to perform the method described above.

[0019] Alternatively, the computer instructions may be used to cause the computer to perform the methods described above.

[0020] According to another aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by at least one quantum processing unit, implements the methods described above.

[0021] Alternatively, the computer program may implement the above-described method when executed by a processor.

[0022] Thus, this disclosed solution provides a method for measuring target parasitic mode information, namely, measuring the degree of influence of parasitic modes on the characteristic parameters of quantum devices based on the target coupling strength between quantum devices and target parasitic mode information. Moreover, this process does not require modeling, is simple and easy to implement, and is practical, providing quantitative and reliable data basis for subsequently determining the performance optimization direction of quantum chips.

[0023] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0024] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0025] Figure 1 This is a flowchart illustrating a method for measuring parasitic modes in a quantum chip layout according to an embodiment of this disclosure. Figure 1 ;

[0026] Figure 2 This is a flowchart illustrating a method for measuring parasitic modes in a quantum chip layout according to an embodiment of this disclosure. Figure 2 ;

[0027] Figure 3 This is a schematic diagram of the layout of a quantum chip according to a specific example of an embodiment of the present disclosure;

[0028] Figure 4 This is a schematic diagram of the implementation flow of program one according to the embodiment of this disclosure;

[0029] Figure 5 This is a schematic diagram of the implementation flow of the main program according to an embodiment of this disclosure;

[0030] Figure 6(a) is a schematic diagram of a structure in a verification example according to an embodiment of the present disclosure;

[0031] Figure 6(b) is a schematic diagram of the peak electric field distribution information corresponding to the target register mode in a verification example according to an embodiment of the present disclosure;

[0032] Figure 7 This is a schematic diagram of the structure of a measurement device for parasitic modes in a quantum chip layout according to an embodiment of the present disclosure;

[0033] Figure 8 This is a block diagram of a computing device used to implement a method for measuring parasitic modes in a quantum chip layout according to embodiments of the present disclosure. Detailed Implementation

[0034] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0035] In this document, the term "and / or" merely describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. The term "at least one" in this document indicates any combination of at least two of a plurality of elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C. The terms "first" and "second" in this document refer to and distinguish between multiple similar technical terms, not to restrict the order or to limit there to only two. For example, "first feature" and "second feature" refer to two categories / two features; the first feature can be one or more, and the second feature can also be one or more.

[0036] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can still be practiced even without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0037] As a logical inevitable breakthrough in chip size beyond the limits of classical physics and a landmark technology of the post-Moore's Law era, quantum computing has garnered significant attention. Currently, quantum computing is developing rapidly at the application, algorithm, and hardware levels. It is worth noting that the realization of quantum algorithms and applications is highly dependent on the development and progress of quantum hardware. Several different technological solutions exist for quantum hardware implementation, such as superconducting quantum circuits, ion traps, and optical quantum systems. Benefiting from its excellent scalability and mature semiconductor manufacturing processes, superconducting quantum circuits are considered one of the most promising technological routes. Furthermore, in recent years, with the development of superconducting quantum computing technologies and micro / nano fabrication processes, the number of qubits integrated on superconducting quantum chips is increasing, leading to richer and more comprehensive chip structures.

[0038] Similar to the development path of classical chips, expanding the number of qubits in superconducting quantum chips not only places higher demands on micro- and nano-fabrication processes, but also makes the simulation of superconducting quantum chips increasingly indispensable before formal fabrication. It should be noted that the simulation of superconducting quantum chips aims to characterize the chip's features as realistically as possible, enabling researchers to better predict chip performance during the design phase and reduce the material, human, and time costs of repeated experiments.

[0039] For the quantum chip layout used to characterize superconducting quantum chips, parasitic modes are one of the key factors affecting the performance of the quantum chip layout (i.e., the chip performance of the superconducting quantum chip). Here, a parasitic mode refers to a mode other than the device mode (or eigenmode) of the quantum device of interest in the quantum chip layout. This parasitic mode may cause anomalies in the coupling strength between quantum devices, a reduction in coherence time, etc. Currently, the industry commonly uses the following method to identify parasitic modes in the quantum chip layout: performing electromagnetic field simulation on the quantum chip layout and judging whether the current eigenmode belongs to the eigenmode of the quantum device based on the electric field intensity distribution information in the simulation results. If it does not belong to the eigenmode of the quantum device, the current eigenmode is a parasitic mode. However, unlike the eigenmode of the quantum device, parasitic modes cannot be modeled well, resulting in existing methods being unable to quantitatively characterize the impact of parasitic modes on quantum devices.

[0040] Based on this, this disclosure proposes a method for measuring parasitic modes in a quantum chip layout, thereby quantitatively characterizing the impact of parasitic modes on quantum devices.

[0041] Before explaining this disclosure, we will first clarify the relevant terms used in this disclosure:

[0042] (1) The intrinsic mode information of the quantum chip layout, that is, the adorned state information of the quantum chip layout, refers to the relevant information of the eigenstate of the quantum system corresponding to the superconducting quantum chip; further, in one example, the intrinsic mode information of the quantum chip layout corresponds to an eigenmode; based on this, the intrinsic mode information can specifically include the intrinsic frequency corresponding to the eigenmode and the peak distribution information of the electric field intensity corresponding to the eigenmode.

[0043] It should be noted that the intrinsic mode information of the quantum chip layout includes the intrinsic mode information of the quantum device, and may also include the parasitic mode information of the quantum chip layout.

[0044] (2) The intrinsic mode information of quantum devices refers to the intrinsic mode information of quantum devices in their environment (such as the surrounding environment of the location of the quantum device in the quantum chip layout), that is, the adorned state information of quantum devices, or the adorned state information of quantum devices in their environment. More specifically, it refers to the relevant information of the eigenstates of quantum devices in their environment.

[0045] It is understandable that if there are other quantum devices in the environment where quantum device A is located in the quantum chip layout, such as quantum device B and quantum device C, then quantum device B will affect the frequency of quantum device A, and / or, quantum device B will affect the coupling strength between quantum device A and other quantum devices (such as quantum device C) other than quantum device B. In this case, the eigenmode information of quantum device A refers to the relevant information of the eigenstate of quantum device A after being affected by other quantum devices in the environment.

[0046] It should be noted that the intrinsic mode information obtained after simulating the quantum chip layout is the intrinsic mode information of the quantum chip layout itself. After obtaining the intrinsic mode information of the quantum chip layout, it is necessary to determine the quantum device to which the intrinsic mode information of the quantum chip layout belongs. Based on this, the intrinsic mode information of the quantum device can be obtained. In other words, the intrinsic mode information of the quantum device is selected from the intrinsic mode information obtained from the simulation. For example, after simulating the quantum chip layout, intrinsic mode information A, intrinsic mode information B, and intrinsic mode information C are obtained. Here, the obtained intrinsic mode information A, intrinsic mode information B, and intrinsic mode information C are all intrinsic mode information of the quantum chip layout. Furthermore, if it is determined that intrinsic mode information A belongs to quantum device A, then the intrinsic mode information of quantum device A can be obtained, which is intrinsic mode information A.

[0047] (3) Bare-state information of a quantum device refers to the information related to the eigenstates of a quantum device when it is an isolated entity. In other words, it refers to the information related to the eigenstates of a quantum device that is not affected by its surrounding environment. For example, the bare-state information of a quantum device may specifically include the bare-state frequency of the quantum device.

[0048] For example, if a quantum chip layout includes quantum device A, quantum device B, and quantum device C, then for quantum device A, quantum device B will affect the frequency of quantum device A and / or affect the coupling strength between quantum device A and other quantum devices (such as quantum device C). In other words, quantum device A is affected by the surrounding environment. In this case, the mode information of quantum device A is the intrinsic mode information of quantum device A, rather than the bare state information.

[0049] (4) Parasitic mode information of the quantum chip layout, corresponding to a parasitic mode. Further, the parasitic mode information may include the parasitic frequency corresponding to the parasitic mode. Alternatively, the parasitic mode information may include the parasitic frequency corresponding to the parasitic mode and the peak distribution information of the electric field intensity corresponding to the parasitic mode.

[0050] Specifically, Figure 1 This is a schematic diagram of the implementation process of a method for measuring parasitic modes in a quantum chip layout according to an embodiment of this disclosure. Figure 1This method can be optionally applied to quantum computing devices that also have classical computing capabilities, or it can be applied to classical computing devices that also have quantum computing capabilities, or it can be directly applied to classical computing devices, such as personal computers, servers, server clusters and other electronic devices with classical computing capabilities, or it can be directly applied to quantum computers. This disclosure does not impose any restrictions on this method.

[0051] Furthermore, the method includes at least a portion of the following: (e.g.) Figure 1 As shown, it includes:

[0052] Step S101: Simulate the quantum chip layout to obtain the target intrinsic mode information of the quantum device in the quantum chip layout, and obtain the target parasitic mode information of the quantum chip layout; wherein, the quantum device is one of the multiple quantum devices included in the quantum chip layout.

[0053] Step S102: Based on the target intrinsic mode information of the quantum device and the target parasitic mode information of the quantum chip layout, obtain the target coupling strength between the quantum device and the target parasitic mode corresponding to the target parasitic mode information; wherein, the target coupling strength is used to measure the degree of influence of the target parasitic mode information on the characteristic parameters of the quantum device.

[0054] Thus, this disclosed solution provides a method for measuring target parasitic mode information, namely, measuring the degree of influence of parasitic modes on the characteristic parameters of quantum devices based on the target coupling strength between quantum devices and target parasitic modes. Moreover, this process does not require modeling, is simple and easy to implement, and is practical, providing quantitative and reliable data basis for subsequently determining the performance optimization direction of quantum chips.

[0055] It should be noted that step S101 is used to describe the results obtained after simulation, and does not limit the order of the results. In actual scenarios, the target intrinsic mode information of the quantum device and the target parasitic mode information of the quantum chip layout may not be obtained synchronously. In other words, the present disclosure does not restrict the execution order of obtaining the two.

[0056] In a specific example, the target intrinsic mode information of quantum devices and the target parasitic mode information of quantum chip layout can be obtained in the following way: First, the quantum chip layout is simulated to obtain multiple target intrinsic mode information of the quantum chip layout. At this time, the intrinsic mode information belonging to the quantum device can be identified from the multiple target intrinsic mode information of the quantum chip layout, and the intrinsic mode information belonging to the quantum device is taken as the target intrinsic mode information of the quantum device. In this way, the target intrinsic mode information of each quantum device is obtained. Second, after identifying the target intrinsic mode information of each quantum device, the target intrinsic mode information other than the target intrinsic mode information of each quantum device from the multiple target intrinsic mode information of the quantum chip layout is taken as the target parasitic mode information of the quantum chip layout.

[0057] Furthermore, for example, taking a quantum chip layout containing quantum device A and quantum device B as an example, after simulating the quantum chip layout, three target intrinsic mode information of the quantum chip layout are obtained, namely target intrinsic mode information 1, target intrinsic mode information 2, and target intrinsic mode information 3. Further, if target intrinsic mode information 1 is identified as belonging to quantum device A, then target intrinsic mode information 1 is taken as the target intrinsic mode information of quantum device A. Similarly, if target intrinsic mode information 2 is identified as belonging to quantum device B, then target intrinsic mode information 2 is taken as the target intrinsic mode information of quantum device B. Finally, the remaining target intrinsic mode information 3 is taken as the target parasitic mode information of the quantum chip layout.

[0058] In a specific example, the parameter characteristics of a quantum device can be specifically the frequency of the quantum device, or the coupling strength between the quantum device and other quantum devices. In this case, the target coupling strength can be used to measure the degree of influence of the target parasitic mode information on the frequency of the quantum device, or to measure the degree of influence of the target parasitic mode information on the coupling strength between the quantum device and other quantum devices. It is understood that the above parameter characteristics are merely illustrative; in practical applications, other parameters may also be used. This disclosure does not impose specific limitations on the parameter characteristics.

[0059] In one specific example, the quantum chip layout includes, but is not limited to, quantum bits, couplers, readout cavities, etc.

[0060] In a specific example, the quantum chip may be a superconducting quantum chip; here, the superconducting quantum chip refers to a quantum chip made of superconducting materials. For example, all components in the superconducting quantum chip (such as qubits, coupling devices, etc.) are made of superconducting materials. This allows the disclosed solution to be applied to superconducting quantum chips, enriching the application scenarios of the disclosed solution.

[0061] In a specific example of the disclosed scheme, the target coupling strength is further used to determine the structural features in the quantum chip layout that cause changes in the target parasitic mode information. In other words, the target coupling strength can also be used to determine which structural features of the quantum chip layout cause the target parasitic mode information, thus providing quantitative and reliable data for subsequently determining the direction of quantum chip performance optimization.

[0062] In a specific example of the disclosed scheme, a pre-simulation can be performed first to obtain the intrinsic mode information of the quantum device at a coarser precision, and then a formal simulation can be performed to obtain the target intrinsic mode information of the quantum device at a higher precision based on the results of the pre-simulation. This improves simulation efficiency and also enhances the accuracy of the simulation results. Specifically, the above-mentioned simulation of the quantum chip layout to obtain the target intrinsic mode information of the quantum device in the quantum chip layout includes:

[0063] At a first simulation precision, a pre-simulation of the quantum chip layout is performed to obtain the first intrinsic mode information of the quantum device in the quantum chip layout; the first intrinsic mode information of the quantum device is the intrinsic mode information of the quantum device at the first simulation precision.

[0064] At a target simulation accuracy, the quantum chip layout is simulated to obtain the system intrinsic mode information of the quantum chip layout at the target simulation accuracy; the target simulation accuracy is greater than the first simulation accuracy.

[0065] Based on the first intrinsic mode information of the quantum device, the target intrinsic mode information of the quantum device is determined from the system intrinsic mode information under the quantum chip layout at the target simulation accuracy.

[0066] It is understood that the target intrinsic mode information of the quantum device is the intrinsic mode information of the quantum device under the target simulation accuracy.

[0067] It should be noted that the system intrinsic mode information of the quantum chip layout under the target simulation accuracy is also the intrinsic mode information of the quantum chip layout under the target simulation accuracy. Here, in order to distinguish it from the first intrinsic mode information, the intrinsic mode information of the quantum chip layout under the target simulation accuracy is referred to as the system intrinsic mode information.

[0068] In other words, in this example, firstly, a pre-simulation of the quantum chip layout is performed at a lower simulation accuracy (i.e., the first simulation accuracy mentioned above) to obtain the first intrinsic mode information of the quantum device at the lower simulation accuracy; secondly, a formal simulation of the quantum chip layout is performed at a higher simulation accuracy (i.e., the target simulation accuracy mentioned above) to obtain the system intrinsic mode information of the quantum chip layout at the higher simulation accuracy; finally, from the system intrinsic mode information of the quantum chip layout at the higher simulation accuracy, the system intrinsic mode information that is closest to the first intrinsic mode information of the quantum device (i.e., the difference is within a preset range) is determined as the target intrinsic mode information of the quantum device.

[0069] Thus, this disclosure provides a specific method for obtaining target intrinsic mode information of a quantum device, thereby laying the foundation for obtaining the target coupling strength between the quantum device and the target parasitic mode, and further laying the foundation for determining the performance optimization direction of the quantum chip.

[0070] In a specific example of the disclosed solution, a pre-simulation can be performed first to obtain parasitic mode information with coarser precision, followed by a formal simulation. Based on the results of the pre-simulation, higher-precision target parasitic mode information can be obtained, thus improving simulation efficiency and the accuracy of the simulation results. Specifically, the above-mentioned simulation of the quantum chip layout to obtain the target parasitic mode information of the quantum chip layout includes:

[0071] At a first simulation precision, the quantum chip layout is pre-simulated to obtain at least one first parasitic mode information of the quantum chip layout at the first simulation precision.

[0072] The quantum chip layout is simulated at the target simulation accuracy to obtain the system eigenmode information of the quantum chip layout at the target simulation accuracy.

[0073] Based on at least one first parasitic mode information of the quantum chip layout at the first simulation accuracy, the target parasitic mode information of the quantum chip layout is determined from the system intrinsic mode information of the quantum chip layout at the target simulation accuracy.

[0074] It is understood that the target parasitic mode information of the quantum device is the parasitic mode information of the quantum chip layout under the target simulation accuracy.

[0075] It should be noted that in the pre-simulation process, the required preset frequency range can be set in advance, thereby obtaining at least one first parasitic mode information of the quantum chip layout with the frequency within the preset frequency range. Here, the preset frequency range can be determined based on at least one of the following two parameters: the frequency range of the intrinsic frequencies of each quantum device in the quantum chip layout, and the frequency range of the operating frequency required in the process of controlling the quantum chip.

[0076] In other words, in this example, firstly, a pre-simulation of the quantum chip layout is performed at a lower simulation accuracy (i.e., the first simulation accuracy mentioned above) to obtain at least one first parasitic mode information of the quantum chip layout at the lower simulation accuracy; secondly, a formal simulation of the quantum chip layout is performed at a higher simulation accuracy (i.e., the target simulation accuracy mentioned above) to obtain the system intrinsic mode information of the quantum chip layout at the higher simulation accuracy; finally, from the system intrinsic mode information of the quantum chip layout at the higher simulation accuracy, the system intrinsic mode information that is similar to the first parasitic mode information of the quantum chip layout (e.g., the difference is within a preset range) is determined as the target parasitic mode information of the quantum chip layout.

[0077] Thus, this disclosed solution provides a specific method for obtaining target parasitic mode information of a quantum chip layout. This lays the foundation for obtaining the target coupling strength between the quantum device and the target parasitic mode, and further provides a basis for determining the performance optimization direction of the quantum chip.

[0078] For example, Figure 2 This is a flowchart illustrating a method for measuring parasitic modes in a quantum chip layout according to an embodiment of this disclosure. Figure 2 This method can be optionally applied to quantum computing devices that also possess classical computing capabilities, or it can be applied to classical computing devices that also possess quantum computing capabilities, or it can be directly applied to classical computing devices, such as personal computers, servers, server clusters, and other electronic devices with classical computing capabilities, or it can be directly applied to quantum computers. This disclosure does not impose any limitations on these applications. It is understood that the above... Figure 1 The methods shown can also be applied to this example, and the related content will not be elaborated further in this example.

[0079] Furthermore, the method includes at least a portion of the following: (e.g.) Figure 2 As shown, it includes:

[0080] Step S201: Under the first simulation accuracy, perform pre-simulation on the quantum chip layout to obtain multiple first eigenmode information of the quantum chip layout under the first simulation accuracy.

[0081] Step S202: Identify the first eigenmode information of each quantum device in the quantum chip layout from multiple first eigenmode information of the quantum chip layout under the first simulation accuracy.

[0082] Step S203: Take the first intrinsic mode information of the quantum chip layout under the first simulation accuracy, excluding the first intrinsic mode information of each quantum device, as the first parasitic mode information of the quantum chip layout, so as to obtain at least one first parasitic mode information of the quantum chip layout.

[0083] For example, a quantum chip layout contains N qubits. The first intrinsic mode information of the quantum chip layout under the first simulation accuracy obtained by pre-simulation is M, and M is greater than N. Here, M is a positive integer greater than or equal to 2, and N is a positive integer greater than or equal to 1. At this time, the first intrinsic mode information of each quantum device can be identified from the M first intrinsic mode information of the quantum chip layout. For example, N first intrinsic mode information belonging to different quantum devices can be identified from the M first intrinsic mode information. At this time, the remaining (MN) first intrinsic mode information can be used as the first parasitic mode information.

[0084] Step S204: Simulate the quantum chip layout at the target simulation accuracy to obtain the system eigenmode information of the quantum chip layout at the target simulation accuracy.

[0085] Here, the target simulation accuracy is greater than the first simulation accuracy. For example, in one example, the target simulation accuracy may be specifically in the range of 0.1%-0.3%; the first simulation accuracy may be specifically in the range of 1%-5%.

[0086] Step S205: Based on the first eigenmode information of each quantum device in the quantum chip layout, determine the target eigenmode information of each quantum device from the system eigenmode information of the quantum chip layout under the target simulation accuracy.

[0087] For example, the system intrinsic mode information in the quantum chip layout under the target simulation accuracy, whose difference from the first intrinsic mode information of the quantum device is within a preset range, is taken as the target intrinsic mode information of the quantum device.

[0088] It is understood that the target intrinsic mode information of the quantum device is the intrinsic mode information of the quantum device under the target simulation accuracy, and the accuracy of the target intrinsic mode information of the quantum device is greater than the first intrinsic mode information of the quantum device obtained in step S202.

[0089] Step S206: Based on at least one first parasitic mode information of the quantum chip layout, determine a target parasitic mode information from the system intrinsic mode information of the quantum chip layout under the target simulation accuracy.

[0090] In other words, from the system intrinsic mode information of the quantum chip layout under the target simulation accuracy, the system intrinsic mode information that is similar to the first parasitic mode information of the quantum chip layout (for example, the difference is within a preset range) is determined as the target parasitic mode information of the quantum chip layout.

[0091] It should be noted that target parasitic mode information can also be obtained in the following ways: for example, from the system intrinsic mode information of the quantum chip layout under the target simulation accuracy, or from other system intrinsic mode information besides the target intrinsic mode information of the quantum device, one system intrinsic mode information can be selected as the target parasitic mode information.

[0092] Step S207: Based on the target intrinsic mode information of the quantum device and the target parasitic mode information of the quantum chip layout, obtain the target coupling strength between the quantum device and the target parasitic mode.

[0093] This provides a specific scheme for obtaining a metric for the target parasitic mode information. Moreover, the process does not require modeling, is simple and easy to implement, and is practical, providing quantitative and reliable data for determining the performance optimization direction of quantum chips.

[0094] In a specific example of the disclosed scheme, the target coupling strength can be obtained in the following manner: specifically, based on the target intrinsic mode information of the quantum device and the target parasitic mode information of the quantum chip layout, the target coupling strength between the quantum device and the target parasitic mode corresponding to the target parasitic mode information is obtained (e.g., step S102 or step S207), specifically including:

[0095] Step S1021: Based on the target parasitic mode information of the quantum chip layout and the target intrinsic mode information of the quantum device, the first conversion information is obtained.

[0096] Step S1022: Based on the first conversion information, construct the target conversion information.

[0097] Step S1023: Based on the target conversion information, obtain the target coupling strength between the quantum device and the target parasitic mode corresponding to the target parasitic mode information.

[0098] Thus, this disclosure provides a specific method for obtaining the target coupling strength between a quantum device and a target parasitic mode. This method can quickly obtain the target coupling strength between the quantum device and the target parasitic mode, and it is simple, easy to implement, and has a low barrier to entry. Therefore, it provides data support for effectively measuring the impact of target parasitic mode information on the characteristic parameters of quantum devices, and thus provides a reliable basis for subsequently determining the optimization direction of quantum chip performance.

[0099] In a specific example of the disclosed solution, the first conversion information can be obtained in the following manner. Specifically, the first conversion information is obtained by combining the target parasitic mode information based on the quantum chip layout and the target intrinsic mode information of the quantum device, as described above. This includes:

[0100] Based on the target parasitic mode information and the target intrinsic mode information of the quantum device, the inductance energy ratio of the quantum device under different target modes is obtained;

[0101] The first conversion information is obtained based on the proportion of inductor energy of the quantum device in different target modes.

[0102] It should be noted that each target intrinsic mode information corresponds to a specific target intrinsic mode. For example, the target intrinsic mode information may specifically include the intrinsic frequency corresponding to the target intrinsic mode. Based on this, the target intrinsic mode information of a quantum device corresponds to a specific target intrinsic mode. Similarly, each target parasitic mode information corresponds to a specific target parasitic mode. For example, the target parasitic mode information may specifically include the parasitic frequency corresponding to the target parasitic mode.

[0103] Furthermore, the mode set includes: the target intrinsic mode of each quantum device in multiple quantum devices, and the target parasitic mode corresponding to the target parasitic mode information of the quantum chip layout; the target mode is one of the elements in the mode set; in other words, the target mode is a target parasitic mode, or the target intrinsic mode corresponding to the quantum device.

[0104] Thus, this disclosed scheme provides a specific method for obtaining the first conversion information, laying the foundation for subsequently obtaining the target coupling strength between the quantum device and the target parasitic mode. At the same time, it also provides quantitative and reliable data basis for subsequently determining the performance optimization direction of the quantum chip.

[0105] In a specific example of the scheme disclosed herein, the target transformation information can be obtained in the following manner. Specifically, the above-described method of constructing the target transformation information based on the first transformation information (i.e., step S1022 described above) specifically includes:

[0106] The quantum chip layout includes N quantum devices, and the first conversion information is transmitted through a first conversion matrix U. (N+1)×NIn the case of representation, in the first transformation matrix U (N+1)×N Add N+1 first elements to obtain the target transformation matrix U′. (N+1)×(N+1) .

[0107] Here, the target transformation matrix U′ (N+1)×(N+1) This represents the target transformation information; the N+1 first elements are the target transformation matrix U′. (N+1)×(N+1) The (N+1)th column in; the first transformation matrix U (N+1)×N element u in mn Based on p mn The p obtained mn This represents the proportion of inductance energy of quantum device n in the target mode m of the mode set, where quantum device n is one of N quantum devices.

[0108] Based on this, the above-described method of obtaining the target coupling strength between the quantum device and the target parasitic mode information based on the target conversion information includes:

[0109] Determine the target transformation matrix U′ (N+1)×(N+1) The value of the first element that satisfies the preset matrix rules is used to obtain the target feature value of the first element;

[0110] When the first element is the target eigenvalue, based on the target transformation matrix U′ (N+1)×(N+1) The target coupling strength between the quantum device and the target parasitic mode information is obtained.

[0111] For specific examples, please refer to the relevant descriptions below, which will not be repeated here.

[0112] Thus, the disclosed scheme provides a specific method for obtaining the target coupling strength. Moreover, the process does not require modeling, is simple and easy to implement, and is practical, providing quantitative and reliable data for determining the performance optimization direction of quantum chips.

[0113] In a specific example of the disclosed scheme, the inductance energy ratio of the quantum device in different target modes can be obtained in the following manner; specifically, the above-mentioned method of obtaining the inductance energy ratio of the quantum device in different target modes based on the target parasitic mode information and the target intrinsic mode information of the quantum device includes:

[0114] The inductance energy percentage p of quantum device n in target mode m is obtained as follows: mn :

[0115] Based on the target parasitic mode information or the target intrinsic mode information of the quantum device, the inductance energy of the target mode m stored in the quantum device n is obtained. And obtain the total inductance energy stored in the target mode m. ;

[0116] Based on the inductor energy stored in quantum device n in the target mode m and the total inductance energy stored in the target mode m The inductance energy ratio p of quantum device n in target mode m was obtained. mn .

[0117] It should be noted here that each target eigenmode information corresponds to a target eigenmode. For example, the target eigenmode information may specifically include the eigenfrequency corresponding to the target eigenmode. Based on this, the target mode m mentioned above corresponds to the target eigenmode information of a quantum device. Furthermore, the target eigenmode information of the quantum device corresponding to target mode m is one of the target eigenmode information of each quantum device in the quantum chip layout.

[0118] It should be noted that, when the target mode m is the target eigenmode corresponding to the quantum device, the inductor energy... Total inductance energy It is obtained based on the target intrinsic mode information of quantum devices;

[0119] Alternatively, when the target mode m is the target parasitic mode corresponding to the quantum chip layout, the inductor energy... Total inductance energy It is obtained based on information about the target parasitic pattern.

[0120] In other words, in this example, the inductance energy of the target mode m stored in the quantum device n is first obtained. And obtain the total inductance energy stored in the target mode m. Then, based on the target mode m, the inductor energy stored in the quantum device n and the total inductance energy stored in the target mode m For example, based on the ratio of the two, the inductance energy ratio p of quantum device n in target mode m can be obtained. mn In this way, the inductance energy ratio of quantum devices in different target modes can be obtained.

[0121] For example, the inductance energy percentage of quantum device n in target mode m can be obtained by the following specific expression: p mn :

[0122]

[0123] Furthermore, based on the above formula, the inductance energy percentage of the quantum device in multiple target modes can be obtained. For example, if a quantum chip layout contains N quantum devices, after performing a formal simulation of the quantum chip layout, the target intrinsic mode information of each of the N quantum devices can be obtained, and each target intrinsic mode information corresponds to a target intrinsic mode. Then, the inductance energy percentage of quantum device n in the N target intrinsic modes can be obtained, which can be denoted as:

[0124] p 1n ,p 2n ,…,p mn ,…,p Nn .

[0125] Furthermore, the inductance energy percentage of quantum device n in the target parasitic mode is obtained, for example, it is p. (N+1)n .

[0126] Based on this, for N quantum devices, the energy percentage of each inductor can be obtained as (N+1)×N. In one example, for ease of subsequent processing, the energy percentage of each inductor can be represented by a matrix, such as by a parameter matrix P, which can be written as P = (p mn ) (N+1)×N Here, the rows in the parameter matrix P correspond to the target mode, and the columns correspond to the quantum devices.

[0127] It is understood that the attributes corresponding to the rows and columns of the parameter matrix P above are merely illustrative examples. In actual applications, the attributes corresponding to the rows and columns of the parameter matrix P can be interchanged, and this disclosure does not impose any restrictions on this.

[0128] Furthermore, the first transformation information can be obtained based on the parameter matrix P. For example, in one example, the first transformation information can also be represented by a matrix, such as the first transformation matrix U, where U = (u mn ) (N+1)×N Let this be expressed as follows: At this point, the elements in the first transformation matrix U and the elements in the parameter matrix P have the following relationship, namely...

[0129] Thus, this disclosed scheme provides a specific method for obtaining the inductance energy ratio of a quantum device in different modes. This provides quantifiable data support for subsequently obtaining the target coupling strength between the quantum device and the target parasitic mode. Moreover, the scheme is simple to implement, highly interpretable, and has strong practicality.

[0130] In a specific example of the scheme disclosed herein, the inductor energy described above can be obtained in the following manner. Specifically, the inductance energy of the target mode m stored in the quantum device n, as described above, is obtained. Specifically, it includes:

[0131] The inductance value L of the quantum device n was calculated. n And the voltage (i.e. peak voltage) V of the target mode m along the voltage integral line of the quantum device n in space is calculated. mn ;

[0132] Based on the inductance value L of quantum device n n The target mode m is the voltage V along the voltage integral line of the quantum device n in space. mn and the frequency ω′ corresponding to the target mode m m The inductance energy of the target mode m stored in the quantum device n is obtained.

[0133] Here, when the target mode m is the target eigenmode corresponding to the quantum device, the frequency ω′ corresponding to the target mode m is... m The intrinsic frequency ω′ corresponding to the target mode m m The intrinsic mode information corresponding to target mode m includes the intrinsic frequency ω′ corresponding to target mode m. m .

[0134] Alternatively, if the target mode m is the target parasitic mode corresponding to the quantum chip layout, the frequency ω′ corresponding to the target mode m is... m The parasitic frequency ω′ corresponding to the target mode m m The target parasitic mode information corresponding to target mode m includes the parasitic frequency ω′ corresponding to target mode m. m .

[0135] For example, in a specific instance, the target mode m is stored in the inductance energy of the quantum device n. It can be obtained through the following formula:

[0136]

[0137] in, This represents the magnetic flux of quantum device n in target mode m.

[0138] Thus, this disclosed scheme provides a method for obtaining the inductor energy of the target mode m stored in the quantum device n. The specific scheme provides quantifiable data support for obtaining the target coupling strength between the quantum device and the target parasitic mode. Moreover, the scheme is simple to implement, highly interpretable, and has strong practicality.

[0139] In a specific example of the scheme disclosed herein, the inductance value L of the quantum device n can be obtained in the following manner. n Specifically, the calculation yields the inductance value L of the quantum device n.n ,include:

[0140] The correlation is obtained, wherein the correlation is the correlation between the inductance energy ratio of quantum device n in different target modes;

[0141] Based on the correlation between the inductance energy ratio of quantum device n in different target modes, the inductance value L of quantum device n is obtained. n .

[0142] For example, based on the normalization relation, the correlation between the inductance energy percentage of quantum device n in different target modes can be specifically as follows:

[0143]

[0144] Here, for N+1 target patterns, m takes values ​​from 1 to N+1.

[0145] Furthermore, based on the above correlation, the inductance value L of the quantum device n can be obtained. n The specific expression is:

[0146]

[0147] Thus, this disclosed method provides a way to obtain the inductance value L of the quantum device n. n The specific scheme provides quantifiable data support for obtaining the target coupling strength between the quantum device and the target parasitic mode. Moreover, the scheme is simple to implement, highly interpretable, and has strong practicality.

[0148] Furthermore, in a specific example of the scheme disclosed herein, the voltage V of the eigenmode m along the voltage integral line of the quantum device n in space can be obtained in the following manner. mn Specifically, the above calculations yield the voltage V of the target mode m along the voltage integral line of the quantum device n in space. mn Specifically, it includes:

[0149] Based on the electric field intensity distribution information of the target mode m in space, the voltage V of the quantum device n along the voltage integral line in space is calculated. mn .

[0150] Here, when the target mode m is the target intrinsic mode corresponding to the quantum device, the target intrinsic mode information corresponding to the target mode m includes the electric field intensity distribution information of the target mode m in space; or, when the target mode m is the target parasitic mode corresponding to the quantum chip layout, the target parasitic mode information corresponding to the target mode m includes the electric field intensity distribution information of the target mode m in space.

[0151] In one example, the electric field intensity distribution information can be the peak electric field intensity distribution information, such as the peak electric field intensity distribution information of the target mode m in space.

[0152] For example, based on the peak electric field distribution information of the intrinsic mode m in space The voltage (i.e., peak voltage) V of the quantum device n along the voltage integral line in space for the target mode m can be obtained using the following formula. mn :

[0153]

[0154] here, This represents the voltage integral line vector of quantum device n in the quantum chip layout. For known terms, The length can be determined by the voltage integration line added during preprocessing, the voltage integration line vector. The direction can be determined based on the default positive direction of the coordinate system in which the quantum chip layout is located. The location vector representing the peak distribution information of the electric field intensity.

[0155] Thus, this disclosure provides a method for obtaining the voltage V of the target mode m along the voltage integral line of the quantum device n in space. mn The specific scheme provides quantifiable data support for obtaining the target coupling strength between the quantum device and the target parasitic mode. Moreover, the scheme is simple to implement, highly interpretable, and has strong practicality.

[0156] In a specific example of the scheme disclosed herein, the total inductance energy stored in the eigenmode m can be obtained in the following manner. Specifically, the total inductance energy stored in the target mode m is obtained as described above. ,include:

[0157] Based on the electric field intensity distribution information of the target mode m in space, the average electric field energy stored in space by the target mode m is obtained. ;

[0158] The average electric field energy stored in space for the target mode m The total inductance energy stored in the target mode m .

[0159] Here, when the target mode m is the target intrinsic mode corresponding to the quantum device, the target intrinsic mode information corresponding to the target mode m includes the electric field intensity distribution information of the target mode m in space; or, when the target mode m is the target parasitic mode corresponding to the quantum chip layout, the target parasitic mode information corresponding to the target mode m includes the electric field intensity distribution information of the target mode m in space.

[0160] For example, the average electric field energy stored in space by the target mode m It can be obtained through the following formula:

[0161]

[0162] here, The dielectric tensor, v, represents the dielectric tensor at different locations in space. full The volume of the space is represented by the above quantities, all of which are known quantities.

[0163] Furthermore, the average electric field energy stored in space for the target mode m The total inductance energy stored in the target mode m That is to say

[0164] Thus, the present disclosure provides a method for obtaining the total inductance energy stored in the target mode m. The specific scheme provides quantifiable data support for obtaining the target coupling strength between the quantum device and the target parasitic mode. Moreover, the scheme is simple to implement, highly interpretable, and has strong practicality.

[0165] The following detailed explanation of this disclosure is provided with specific examples. Based on the inductance energy participation ratio (iEPR), this disclosure proposes a simulation method for the coupling strength between quantum devices and parasitic modes in a quantum chip layout. For instance, firstly, a high-frequency electromagnetic field simulation is performed on the quantum chip layout to obtain the target intrinsic mode information and a target parasitic mode information of the quantum device in its environment. Secondly, using the iEPR method, the obtained target intrinsic mode information and target parasitic mode information of the quantum device in its environment are post-processed to obtain the coupling strength between the quantum device and the target parasitic mode. This quantitatively characterizes the influence of the target parasitic mode information on the quantum device, which has significant practical value for the design and optimization of quantum chip layouts.

[0166] The following section uses a superconducting quantum chip as an example and elaborates on the proposed solution from the following parts: Part 1 introduces the layout structure of the quantum chip; Part 2 describes the data post-processing flow based on the iEPR method; Part 3 describes the specific flow of the proposed solution; and Part 4 demonstrates the application to verify the effectiveness of the proposed solution.

[0167] Part 1: Quantum Chip Landscape

[0168] As the core carrier of superconducting quantum circuit technology, the development of superconducting quantum chips is crucial. Similar to classical chips, a complete quantum chip layout needs to be designed before formal production and processing. This layout includes all the core quantum devices, control lines, readout lines, etc., of the superconducting quantum chip. In practical applications, one of the most important quantum devices in the superconducting quantum chip layout is the qubit. A qubit is typically composed of a coplanar capacitor and a Josephson junction. In practice, a substrate (usually silicon or sapphire) is selected, an aluminum film is deposited on the substrate, and different shapes are etched onto the aluminum film to form the capacitance of the qubit. Finally, nonlinear devices, such as Josephson junctions, are placed between the substrate and the aluminum film.

[0169] For example, such as Figure 3 The diagram shown is a schematic diagram of the layout structure of a quantum chip containing two qubits. The quantum chip layout includes:

[0170] A qubit (Qubit) 301 represented by a cross-shaped structure, for example, Figure 3 As shown, a portion of the entire metal plate (e.g., a metal substrate with an aluminum film) is etched away to form a cross-shaped structure. In this case, the central area of ​​the cross-shaped structure is the metal plate, while the metal plate in the peripheral area of ​​the cross-shaped structure is etched away. The metal plate outside the cross-shaped structure can be used for grounding.

[0171] Furthermore, a Josephson junction 302 is also incorporated into the qubit 301; in electromagnetic simulations, this Josephson junction is typically modeled using an equivalent lumped inductance. For example, a Josephson junction 302 is inserted between the bottom of the central region of the cross-shaped structure and a grounded metal plate.

[0172] Similar to classical chips, quantum chip layouts require simulation verification before formal tape-out. The simulation verification of quantum chip layouts aims to realistically characterize the characteristic parameters of the quantum chip layout as much as possible, allowing researchers to better predict the performance of the quantum chip layout during the design phase and reduce the manpower and material costs of repeated experiments. However, the emergence of parasitic modes during the design process of quantum chip layouts is unpredictable, yet it has a significant impact on the performance of the quantum chip layout. Therefore, it is necessary to identify parasitic modes through electromagnetic simulation and quantitatively characterize their impact on quantum devices to determine subsequent optimization directions.

[0173] Based on this, the present disclosure provides a simulation scheme for the coupling strength between quantum devices and parasitic modes in a quantum chip layout, which can quantitatively characterize the impact of parasitic modes on quantum devices.

[0174] The second part, Program 1, consists of subroutines called by the main program. These subroutines are primarily used to calculate the inductor energy ratio (iEPR) and subsequently obtain the parameter matrix P.

[0175] The input to the second part is the simulation results obtained after simulating the quantum chip layout, such as the target intrinsic mode information of each quantum device under the target simulation accuracy, and the target parasitic mode information of the quantum chip layout; the output is the parameter matrix P.

[0176] like Figure 4 As shown, the specific steps include:

[0177] Step S401: Post-process the simulation results to obtain the iEPR of the quantum device in different target intrinsic modes, and the iEPR of the quantum device in the target parasitic mode corresponding to the quantum chip layout. That is, obtain the iEPR of the quantum device in different target modes.

[0178] Here, the target mode refers to the target intrinsic mode corresponding to the quantum device, or the target parasitic mode corresponding to the quantum chip layout. For details on the target mode, please refer to the above description, which will not be repeated here.

[0179] Specifically, the iEPR of quantum device n under different target modes will be explained in detail. Here, iEPR can characterize the proportion of inductance energy distributed on the quantum device under different target modes in a capacitively coupled quantum system to the total inductance energy of that target mode. For example, the iEPR of quantum device n under target mode m can be denoted as p. mn At this time, p mn It can be defined as:

[0180]

[0181] Furthermore, p can be calculated based on the following steps. mn Specifically, it includes:

[0182] Step S4011: Calculate the voltage (i.e., peak voltage) V across the voltage integral line of quantum device n in target mode m. mn The specific expression is as follows:

[0183]

[0184] in, This represents the voltage integral line vector of quantum device n in the quantum chip layout. , are known terms. The length can be determined by the voltage integration line added during preprocessing, the voltage integration line vector. The direction can be determined based on the default positive direction of the coordinate system in which the quantum chip layout is located.

[0185] Step S4012: Calculate the average inductance energy of the target mode m on the quantum device n in space, and use it as the inductance energy of the target mode m on the quantum device n in space.

[0186] The specific expression is as follows:

[0187]

[0188] in, L n Let be the inductance value of quantum device n, and be an unknown term.

[0189] Step S4013: Calculate the average electric field energy stored in space by the target mode m (which can be denoted as...). The total inductance energy stored in the target mode m is expressed as follows:

[0190]

[0191] in, This represents the electric field energy of the target mode m in space. The dielectric tensor, v, represents the dielectric tensor at different locations in space. full The volume of the space is represented by the above quantities, all of which are known quantities.

[0192] Step S4014: Based on the normalization relation, the following formula exists:

[0193]

[0194] Step S4015: Obtain the inductance value L of quantum device n n ,Right now:

[0195]

[0196] Step S4016: Obtain p mn Furthermore, the iEPR of quantum device n under different target modes can be obtained using the above method. Here, p mn This can be specifically expressed as:

[0197]

[0198] Step S402: Obtain the iEPR of different quantum devices in different target intrinsic modes in the quantum chip layout, and obtain the iEPR of different quantum devices in the target parasitic mode; that is, obtain the iEPR of different quantum devices in different target modes in the quantum chip layout.

[0199] Here, a parameter matrix can be constructed based on the iEPR of different quantum devices in different target intrinsic modes in the quantum chip layout, as well as the iEPR of different quantum devices in the target parasitic modes. For example, let the parameter matrix be P; then, p mn Let P be the element of the parameter matrix P. Further, we can denote the parameter matrix P = (p... mn Here, the rows in the parameter matrix P correspond to the target mode, and the columns correspond to the quantum devices.

[0200] Step S403: Output the parameter matrix P = (p mn ).

[0201] Here, it can be understood that the dimension of the parameter matrix P is related to the amount of target intrinsic mode information input to program one, in other words, to the number of quantum devices contained in the quantum chip layout.

[0202] The third part, the main program, is used to obtain the coupling strength between quantum devices and target parasitic modes in the quantum chip layout.

[0203] The input to the third part is a quantum chip layout containing N quantum devices; the output is the coupling strength between the quantum devices and the target parasitic mode.

[0204] like Figure 5 As shown, the specific steps include:

[0205] Step S501: Input a quantum chip layout containing N quantum devices.

[0206] Step S502: Pre-simulation; Under the first simulation accuracy, perform pre-simulation on the quantum chip layout to obtain multiple first intrinsic mode information of the quantum chip layout; Based on the multiple first intrinsic mode information of the quantum chip layout, identify the first intrinsic mode information of each quantum device in the quantum chip layout under its environment; and Based on the multiple first intrinsic mode information of the quantum chip layout, obtain at least one first parasitic mode information.

[0207] In one example, during the pre-simulation process, a desired preset frequency range can be pre-set to obtain at least one first parasitic mode information of the quantum chip layout whose intrinsic frequencies are within the preset frequency range. Here, the preset frequency range can be determined based on at least one of the following two parameters: the frequency range of the intrinsic frequencies of each quantum device in the quantum chip layout, and the frequency range of the operating frequencies required during the control of the quantum chip.

[0208] In other words, in this example, before performing a precise simulation (i.e., a formal simulation) of the quantum chip layout, a preliminary simulation is required. This involves performing a rough simulation of the quantum chip layout to analyze and obtain the approximate frequencies of each quantum device in the quantum chip layout. At the same time, the approximate frequencies of parasitic modes are also analyzed. This provides data support for the subsequent efficient and precise simulation of the quantum chip layout.

[0209] Step S503: Formal simulation; Under the target simulation accuracy, perform finite element electromagnetic simulation (such as high-frequency electromagnetic field simulation) on the quantum chip layout to obtain the target intrinsic mode information of each quantum device under the target simulation accuracy, and obtain the target parasitic mode information under the target simulation accuracy.

[0210] In one example, the target intrinsic mode information of each quantum device at the target simulation accuracy can be obtained based on the results of the pre-simulation in step S502, such as the first intrinsic mode information of the quantum device in its environment obtained after pre-simulation. Another example is that a target parasitic mode information at the target simulation accuracy can be obtained based on at least one first parasitic mode information obtained after pre-simulation. The specific determination method can be referred to the description above, which will not be repeated here.

[0211] Furthermore, in one example, the target intrinsic mode information corresponds to a target intrinsic mode. Accordingly, the target intrinsic mode information of each quantum device may specifically include: the intrinsic frequency corresponding to the target intrinsic mode, and the electric field intensity distribution information corresponding to the target intrinsic mode. Similarly, the target parasitic mode information corresponds to a target parasitic mode. Accordingly, the target parasitic mode information may specifically include: the parasitic frequency corresponding to the target parasitic mode, and the electric field intensity distribution information corresponding to the target parasitic mode.

[0212] For example, the intrinsic mode information of the target corresponding to the target mode m may specifically include:

[0213] (1) The eigenfrequency ω′ corresponding to the target mode m m ;

[0214] (2) Information on the electric field intensity distribution of the target mode m in space, such as the peak electric field intensity distribution.

[0215] Alternatively, the target parasitic mode information corresponding to target mode m may specifically include:

[0216] (1) Parasitic frequency ω′ corresponding to target mode m m ;

[0217] (2) Information on the electric field intensity distribution of the target mode m in space, such as the peak electric field intensity distribution.

[0218] It should be noted that, considering the characteristics of the iEPR method, the scheme disclosed herein can handle the coupling strength between one parasitic mode and each quantum device in multiple quantum devices in a single process. It is understood that to obtain the coupling strength between multiple parasitic modes and multiple quantum devices, the scheme disclosed herein can be executed multiple times.

[0219] It should be noted that the target simulation accuracy used in the formal simulation is greater than the first simulation accuracy used in the pre-simulation, which helps to improve simulation efficiency; further, in one example, the target simulation accuracy may be specifically in the range of 0.1%-0.3%; the first simulation accuracy may be specifically in the range of 1%-5%.

[0220] Step S504: Take the simulation results obtained in step S503, such as the target intrinsic mode information of each quantum device under the target simulation accuracy and the target parasitic mode information of the quantum chip layout, as input to program one to obtain the parameter matrix P = (p mn ).

[0221] Understandably, for the quantum chip layout containing N quantum devices in this example, there are N target intrinsic mode information and 1 target parasitic mode information input to Program 1. At this point, the inductance energy percentage of each of the N quantum devices under different target intrinsic modes (i.e., the target intrinsic modes corresponding to each of the N target intrinsic mode information, for a total of N target intrinsic modes) and the inductance energy percentage of each of the N quantum devices under the target parasitic mode can be calculated. Correspondingly, the parameter matrix can be denoted as P = (p mn ) (N+1)×NHere, m = 1, 2, ..., N+1, n = 1, 2, ..., N. For example, it can be specifically:

[0222]

[0223] Here, for p mn (m≠N+1) represents the proportion of inductor energy of quantum device n in the target eigenmode m. Here, the target eigenmode information corresponding to the target eigenmode m is one of N target eigenmode information; p N+1,n This represents the proportion of inductance energy of quantum device n in the target parasitic mode.

[0224] Step S505: Obtain the first transformation matrix U (representing the first transformation information described above). Here, the elements in the first transformation matrix U can be denoted as u. mn , that is U=(u mn ) (N+1)×N For example, it can be specifically described as:

[0225]

[0226] Here, the first transformation matrix U and the parameter matrix P have the following relationship:

[0227] It should be noted that, in one example, the matrix formed by the first N rows and N columns of the first transformation matrix U is a unitary matrix. Here, for ease of description, the matrix formed by the first N rows and N columns of the first transformation matrix U can be denoted as U1. This unitary matrix U1 is used to make the first device performance matrix... (Here, the first device performance information of the quantum chip layout, such as information characterizing the bare state frequency of the quantum device and the coupling strength between quantum devices, can be obtained through this first device performance matrix.) (This is represented as diagonalization, which is the following formula:)

[0228]

[0229] Here, ω′ i Represents the eigenfrequency of quantum device i (i.e., the frequency of the decorated state of quantum device i); the first device performance matrix. The specific form is:

[0230]

[0231] here, g ij ω represents the coupling strength between quantum device i and quantum device j. i ω represents the bare state frequency of quantum device i. j This represents the bare state frequency of quantum device j.

[0232] Here, in order to obtain the first transformation matrix U, we can introduce the symbol matrix S = (s mn ) (N+1)×N Let be the sign of the elements in the first transformation matrix U, then we have Among them, s mn Represents the element u in the first transformation matrix U. mn The plus or minus sign.

[0233] Furthermore, since matrix U1 in the first transformation matrix U is a unitary matrix and has the characteristic of orthogonal normalization, the following relationship exists:

[0234]

[0235] Here, for δ mn In other words, if m = n, then δ mn =1, otherwise, i.e., m≠n, then δ mn =0, k=1,2,…,N.

[0236] Furthermore, based on the above orthogonal normalization relation, the following rule is obtained to obtain the symbol matrix S = (s mn ) (N+1)×N :

[0237] (1) If V mn If > 0, then the element s of the symbol matrix S mn =1;

[0238] (2) When V mn If ≤0, then the elements s of the symbol matrix S mn =-1.

[0239] Here, V mn This represents the voltage across the voltage integral line of quantum device n under the target mode m described in Program 1.

[0240] Step S506: Based on the first transformation matrix U, construct the target transformation matrix U′ (representing the target transformation information mentioned above). Here, the target transformation matrix can be expressed as:

[0241] U′=(u mn ) (N+1)×(N+1) ;

[0242] In one example, the target transformation matrix U′ can be constructed as follows:

[0243] Considering that parasitic modes do not belong to any quantum device, therefore, in the first transformation matrix U = (u mn ) (N+1)NBy inserting a column of elements, such as N+1 first elements, we can construct the following target transformation matrix:

[0244]

[0245] Here, the N+1 first elements are the terms to be solved; furthermore, during the solution process, the initial values ​​of the N+1 first elements can be specific to non-zero random numbers.

[0246] Here, the constructed target transformation matrix U′ is also a unitary matrix, which makes the target device performance matrix... (Here, the target device performance information of the quantum chip layout, such as the bare state frequency of the quantum device, the coupling strength between quantum devices, and the coupling strength between the quantum device and the target parasitic frequency, can be obtained through the target device performance matrix.) (This is represented as diagonalization, which is the following formula:)

[0247]

[0248] Here, frequency ω′ i Let ω′ be the eigenfrequency of quantum device i (i.e., the frequency of the decorated state of quantum device i); N+1 Parasitic frequency corresponding to the target parasitic mode; target matrix The specific form is:

[0249]

[0250] here, Furthermore, if i = 1, 2, ..., N and j = 1, 2, ..., N, then g ij ω represents the coupling strength between quantum device i and quantum device j. i ω represents the bare state frequency of quantum device i. j Let g represent the bare state frequency of quantum device j. If i = N+1 and j = 1, 2, ..., N, then g (N+1)j ω represents the coupling strength between the target parasitic mode and the quantum device j, where ω N+1 ω represents the parasitic frequency corresponding to the target parasitic mode. j Let g represent the bare state frequency of quantum device j. If i = 1, 2, ..., N and j = N+1, then g i(N+1) ω represents the coupling strength between quantum device i and the target parasitic mode. i ω represents the bare state frequency of quantum device i. N+1 This indicates the parasitic frequency corresponding to the target parasitic pattern.

[0251] Step S507: Based on the Schmitt orthogonal normalization characteristic of unitary matrices, the values ​​of the first elements in the added column of the target transformation matrix U′ are obtained, and then the coupling strength between the quantum device and the target parasitic mode corresponding to the target parasitic mode information is obtained.

[0252] It should be noted that unitary matrices have the characteristic of orthogonal normalization between different columns. That is, when a column of a unitary matrix is ​​taken as a vector, the vectors corresponding to different columns are mutually orthogonal and normalized. Based on this characteristic, the last column of the target transformation matrix U′ can be taken as the (N+1)th vector. In this case, the (N+1)th vector needs to be mutually orthogonal and normalized with the vectors corresponding to other columns in the target transformation matrix U′ to ensure that the target transformation matrix U′ is a unitary matrix. Based on this characteristic, and using the Schmitt orthogonalization normalization method, the values ​​of each element in the (N+1)th vector can be obtained.

[0253] It is understandable that after obtaining the values ​​of the first elements in the last column of the target transformation matrix U′, the target device performance matrix described above can be obtained. The value of the last row or last column is used to obtain the coupling strength between the quantum device and the target parasitic mode corresponding to the target parasitic mode information.

[0254] Furthermore, in one example, the target parasitic mode θ is coupled with the target coupling strength g of the quantum device n. θn This can be specifically expressed as:

[0255]

[0256] Here, j,k = 1,2,…,N+1. ω′ N+1 This represents the parasitic frequency corresponding to the target parasitic mode θ.

[0257] Part Four: Validation of the Method

[0258] This section introduces specific examples to verify the effectiveness of the present invention.

[0259] (I) Territorial Structure

[0260] Figure 6(a) shows a schematic diagram of the quantum chip layout for verifying the effectiveness of the scheme. Q1 and Q2 represent qubits, C represents a coupler used to adjust the equivalent coupling strength between qubits, R1 is the readout cavity corresponding to qubit Q1, and R2 is the readout cavity corresponding to qubit Q2. Furthermore, in this example, the quantum chip layout has a size of 10mm × 10mm, a substrate thickness of 200µm, and the substrate material is sapphire with a relative permittivity of 10.

[0261] Furthermore, this example is used to verify the coupling strength between the qubit and the target parasitic mode. The specific steps include:

[0262] Step 1: Perform pre-simulation to obtain the target intrinsic mode information of the qubit and the target parasitic mode information in the frequency range of non-quantum devices. As shown in Figure 6(b), it is a schematic diagram of the peak electric field distribution information corresponding to the target parasitic mode obtained by simulation. It can be seen that the electric field represented by the peak electric field distribution information corresponding to the target parasitic mode is not distributed on a specific quantum device.

[0263] Step two: Perform formal simulation to simulate the target intrinsic modes of each of the two qubits, as well as a target parasitic mode.

[0264] Step 3: Using the methods described above, the coupling strength between the qubit and the target parasitic mode is obtained, as shown in the table below:

[0265] Q1 coupling strength to spurious modes 10.49515 MHz Q2 coupling strength to spurious modes 10.77526 MHz

[0266] The coupling strength between the qubit and the target parasitic mode was successfully calculated using the scheme disclosed herein. Moreover, the above values ​​show that the qubit is strongly affected by the target parasitic mode. Therefore, in the subsequent optimization of the quantum chip layout, it is possible to consider changing the layout structure to prioritize the elimination of this target parasitic mode.

[0267] In summary, the disclosed solution has the following advantages:

[0268] First, this disclosed scheme does not require modeling and can efficiently and quantitatively characterize the coupling strength between parasitic modes and quantum devices, thus demonstrating high efficiency.

[0269] Second, this disclosed solution provides reliable data for optimizing the performance of quantum chips, which is conducive to continuously improving the performance of quantum chips.

[0270] Third, this disclosed solution facilitates the automation of superconducting quantum chip design. This disclosed solution can effectively pre-identify sample box modes, chip modes, and other parasitic modes in superconducting quantum chip development, and determine the impact of these modes on core devices, providing a basis for subsequent optimization.

[0271] This disclosure also provides a device for measuring parasitic modes in a quantum chip layout, such as... Figure 7 As shown, it includes:

[0272] Simulation unit 701 is used to simulate the quantum chip layout to obtain the target intrinsic mode information of the quantum device in the quantum chip layout, and to obtain the target parasitic mode information of the quantum chip layout; wherein, the quantum device is one of the multiple quantum devices included in the quantum chip layout;

[0273] The processing unit 702 is used to obtain the target coupling strength between the quantum device and the target parasitic mode corresponding to the target parasitic mode information based on the target intrinsic mode information of the quantum device and the target parasitic mode information of the quantum chip layout; wherein, the target coupling strength is used to measure the degree of influence of the target parasitic mode information on the characteristic parameters of the quantum device.

[0274] In a specific example of the scheme disclosed herein, the target coupling strength is also used to determine the structural features in the quantum chip layout that cause changes in the target parasitic mode information.

[0275] In a specific example of the disclosed solution, the simulation unit is specifically used for:

[0276] At a first simulation precision, a pre-simulation of the quantum chip layout is performed to obtain the first intrinsic mode information of the quantum device in the quantum chip layout; the first intrinsic mode information of the quantum device is the intrinsic mode information of the quantum device at the first simulation precision.

[0277] At a target simulation accuracy, the quantum chip layout is simulated to obtain the system intrinsic mode information of the quantum chip layout at the target simulation accuracy; the target simulation accuracy is greater than the first simulation accuracy.

[0278] Based on the first intrinsic mode information of the quantum device, the target intrinsic mode information of the quantum device is determined from the system intrinsic mode information of the quantum chip layout under the target simulation accuracy.

[0279] In a specific example of the disclosed solution, the simulation unit is specifically used for:

[0280] At a first simulation precision, the quantum chip layout is pre-simulated to obtain at least one first parasitic mode information of the quantum chip layout at the first simulation precision.

[0281] At the target simulation accuracy, the quantum chip layout is simulated to obtain the system eigenmode information of the quantum chip layout at the target simulation accuracy; the target simulation accuracy is greater than the first simulation accuracy.

[0282] Based on at least one first parasitic mode information of the quantum chip layout at the first simulation accuracy, the target parasitic mode information of the quantum chip layout is determined from the system intrinsic mode information of the quantum chip layout at the target simulation accuracy.

[0283] In a specific example of the disclosed solution, the processing unit is specifically used for:

[0284] Based on the target parasitic mode information of the quantum chip layout and the target intrinsic mode information of the quantum device, the first conversion information is obtained;

[0285] Based on the first conversion information, target conversion information is constructed;

[0286] Based on the target conversion information, the target coupling strength between the quantum device and the target parasitic mode corresponding to the target parasitic mode information is obtained.

[0287] In a specific example of the disclosed solution, the processing unit is specifically used for:

[0288] Based on the target parasitic mode information and the target intrinsic mode information of the quantum device, the inductance energy ratio of the quantum device under different target modes is obtained; the target intrinsic mode information of the quantum device corresponds to a target intrinsic mode; the mode set includes: the target intrinsic mode of each quantum device in multiple quantum devices, and the target parasitic mode corresponding to the target parasitic mode information of the quantum chip layout; the target mode is one of the elements in the mode set;

[0289] The first conversion information is obtained based on the proportion of inductor energy of the quantum device in different target modes.

[0290] In a specific example of the scheme disclosed herein, the processing unit is specifically used to process the first transformation information through a first transformation matrix U in a quantum chip layout containing N quantum devices. (N+1)×N In the case of representation, in the first transformation matrix U (N+1)×N Add N+1 first elements to obtain the target transformation matrix U′. (N+1)×(N+1) Wherein, the target transformation matrix U′ (N+1)×(N+1) Used to represent the target transformation information; the N+1 first elements are the target transformation matrix U′ (N+1)×(N+1) The (N+1)th column in; the first transformation matrix U (N+1)×N element u in mn Based on p mn The p obtained mn p represents the proportion of inductor energy of quantum device n in target mode m of the mode set. mn The quantum device n is one of N quantum devices;

[0291] Furthermore, the processing unit is specifically configured to determine the target transformation matrix U′. (N+1)×(N+1)The value of the first element that satisfies the preset matrix rules is used to obtain the target feature value of the first element; when the first element is the target feature value, the target transformation matrix U′ is used as the basis. (N+1)×(N+1) The target coupling strength between the quantum device and the target parasitic mode information is obtained.

[0292] In a specific example of the disclosed solution, the processing unit is specifically used for:

[0293] The inductance energy percentage p of quantum device n in target mode m is obtained as follows: mn :

[0294] Based on the target parasitic mode information or the target intrinsic mode information of the quantum device, the inductance energy of the target mode m stored in the quantum device n is obtained. And obtain the total inductance energy stored in the target mode m. ;

[0295] Based on the inductor energy stored in quantum device n in the target mode m and the total inductance energy stored in the target mode m The inductance energy ratio p of quantum device n in target mode m was obtained. mn .

[0296] In a specific example of the disclosed solution, the processing unit is specifically used for:

[0297] The inductance value L of the quantum device n was calculated. n And the voltage V of the target mode m along the voltage integral line of the quantum device n in space is calculated. mn ;

[0298] Based on the inductance value L of quantum device n n The target mode m is the voltage V along the voltage integral line of the quantum device n in space. mn and the frequency ω′ corresponding to the target mode m m The inductance energy of the target mode m stored in the quantum device n is obtained. ;

[0299] Wherein, when the target mode m is a target eigenmode, the frequency ω′ corresponding to the target mode m is... m The intrinsic frequency ω′ corresponding to the target mode m m The intrinsic mode information corresponding to target mode m includes the intrinsic frequency ω′ corresponding to target mode m. m ;or,

[0300] When the target mode m is a target parasitic mode, the frequency ω′ corresponding to the target mode m mThe parasitic frequency ω′ corresponding to the target mode m m The target parasitic mode information corresponding to target mode m includes the parasitic frequency ω′ corresponding to target mode m. m .

[0301] In a specific example of the disclosed solution, the processing unit is specifically used for:

[0302] The correlation is obtained, wherein the correlation is the correlation between the inductance energy ratio of quantum device n in different target modes;

[0303] Based on the correlation between the inductance energy ratio of quantum device n in different target modes, the inductance value L of quantum device n is obtained. n .

[0304] In a specific example of the disclosed solution, the processing unit is specifically used for:

[0305] Based on the electric field intensity distribution information of the target mode m in space, the voltage V of the quantum device n along the voltage integral line in space is calculated. mn ;

[0306] Specifically, when the target mode m is a target intrinsic mode, the target intrinsic mode information corresponding to the target mode m includes the electric field intensity distribution information of the target mode m in space; or, when the target mode m is a target parasitic mode, the target parasitic mode information corresponding to the target mode m includes the electric field intensity distribution information of the target mode m in space.

[0307] In a specific example of the disclosed solution, the processing unit is specifically used for:

[0308] Based on the electric field intensity distribution information of the target mode m in space, the average electric field energy stored in space by the target mode m is obtained. ;

[0309] The average electric field energy stored in space for the target mode m The total inductance energy stored in the target mode m ;

[0310] Specifically, when the target mode m is a target intrinsic mode, the target intrinsic mode information corresponding to the target mode m includes the electric field intensity distribution information of the target mode m in space; or, when the target mode m is a target parasitic mode, the target parasitic mode information corresponding to the target mode m includes the electric field intensity distribution information of the target mode m in space.

[0311] For a description of the specific functions and examples of each unit of the apparatus in this disclosure embodiment, please refer to the relevant descriptions of the corresponding steps in the above method embodiments, which will not be repeated here.

[0312] This disclosure also provides a non-transitory computer-readable storage medium storing computer instructions that, when executed by at least one quantum processing unit, cause the at least one quantum processing unit to perform the method described above using a quantum computing device.

[0313] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the methods described above for use in classical computing devices.

[0314] Alternatively, the computer program, when executed by at least one quantum processing unit, implements the method applied to a quantum computing device.

[0315] This disclosure also provides a quantum computing device, the quantum computing device comprising:

[0316] At least one quantum processing unit;

[0317] A memory, coupled to the at least one QPU and used to store executable instructions,

[0318] The instructions are executed by the at least one quantum processing unit to enable the at least one quantum processing unit to perform the method applied to the quantum computing device.

[0319] It is understood that the quantum processing unit (QPU) used in the present disclosure may also be referred to as a quantum processor or quantum chip, and may involve a physical chip comprising multiple qubits interconnected in a specific manner.

[0320] Furthermore, it is understood that the qubit described in this disclosure can refer to the basic information unit of a quantum computing device. The qubit is contained within the QPU and extends the concept of the classical digital bit.

[0321] According to embodiments of this disclosure, this disclosure also provides a computing device, a readable storage medium, and a computer program product.

[0322] Figure 8A schematic block diagram of an example computing device 800 that can be used to implement embodiments of the present disclosure is shown. The computing device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The computing device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0323] like Figure 8 As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 802 or a computer program loaded from storage unit 808 into random access memory (RAM) 803. RAM 803 may also store various programs and data required for the operation of device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interface 805 is also connected to bus 804.

[0324] Multiple components in device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of monitors, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0325] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as the method for measuring parasitic modes in a quantum chip layout. For example, in some embodiments, the method for measuring parasitic modes in a quantum chip layout can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the method for measuring parasitic modes in a quantum chip layout described above can be performed. Alternatively, in other embodiments, computing unit 801 may be configured by any other suitable means (e.g., by means of firmware) to perform a method for measuring parasitic modes in a quantum chip layout.

[0326] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0327] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0328] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0329] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0330] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0331] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0332] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0333] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for measuring parasitic modes in a quantum chip layout, comprising: Simulation of a quantum chip layout yields target intrinsic mode information of quantum devices within the quantum chip layout, as well as target parasitic mode information; wherein the quantum device is one of multiple quantum devices included in the quantum chip layout. Based on the target intrinsic mode information of the quantum device and the target parasitic mode information of the quantum chip layout, the target coupling strength between the quantum device and the target parasitic mode corresponding to the target parasitic mode information is obtained; wherein, the target coupling strength is used to measure the degree of influence of the target parasitic mode information on the characteristic parameters of the quantum device; The method for obtaining the target coupling strength between the quantum device and the target parasitic mode corresponding to the target parasitic mode information based on the target intrinsic mode information of the quantum device and the target parasitic mode information of the quantum chip layout includes: Based on the target parasitic mode information of the quantum chip layout and the target intrinsic mode information of the quantum device, the first conversion information is obtained; The quantum chip layout includes N quantum devices, and the first conversion information is transmitted through a first conversion matrix. In the case of representing, in the first transformation matrix Add N+1 first elements to obtain the target transformation matrix. Wherein, the target transformation matrix Used to represent the target transformation information; the N+1 first elements are the target transformation matrix. The (N+1)th column in the first transformation matrix; elements in Based on The result, the stated This represents the proportion of inductor energy of quantum device n in the target mode m of the mode set. The quantum device n is one of N quantum devices; Based on the target conversion information, the target coupling strength between the quantum device and the target parasitic mode corresponding to the target parasitic mode information is obtained.

2. The method according to claim 1, wherein, The target coupling strength is also used to determine the structural features in the quantum chip layout that cause changes in the target parasitic mode information.

3. The method according to claim 1 or 2, wherein, The simulation of the quantum chip layout to obtain the target intrinsic mode information of the quantum devices in the quantum chip layout includes: At a first simulation precision, a pre-simulation of the quantum chip layout is performed to obtain the first intrinsic mode information of the quantum device in the quantum chip layout; the first intrinsic mode information of the quantum device is the intrinsic mode information of the quantum device at the first simulation precision. At a target simulation accuracy, the quantum chip layout is simulated to obtain the system intrinsic mode information of the quantum chip layout at the target simulation accuracy; the target simulation accuracy is greater than the first simulation accuracy. Based on the first intrinsic mode information of the quantum device, the target intrinsic mode information of the quantum device is determined from the system intrinsic mode information of the quantum chip layout under the target simulation accuracy.

4. The method according to claim 1 or 2, wherein, Simulation of the quantum chip layout yields information on the target parasitic modes of the quantum chip layout, including: At a first simulation precision, the quantum chip layout is pre-simulated to obtain at least one first parasitic mode information of the quantum chip layout at the first simulation precision. At a target simulation accuracy, the quantum chip layout is simulated to obtain the system eigenmode information of the quantum chip layout at the target simulation accuracy; the target simulation accuracy is greater than the first simulation accuracy. Based on at least one first parasitic mode information of the quantum chip layout at the first simulation accuracy, the target parasitic mode information of the quantum chip layout is determined from the system intrinsic mode information of the quantum chip layout at the target simulation accuracy.

5. The method according to claim 1 or 2, wherein, The first conversion information, derived from the target parasitic mode information based on the quantum chip layout and the target intrinsic mode information of the quantum device, includes: Based on the target parasitic mode information and the target intrinsic mode information of the quantum device, the inductance energy ratio of the quantum device under different target modes is obtained; the target intrinsic mode information of the quantum device corresponds to a target intrinsic mode; the mode set includes: the target intrinsic mode of each quantum device in multiple quantum devices, and the target parasitic mode corresponding to the target parasitic mode information of the quantum chip layout; the target mode is one of the elements in the mode set; The first conversion information is obtained based on the proportion of inductor energy of the quantum device in different target modes.

6. The method according to claim 1, wherein, The step of obtaining the target coupling strength between the quantum device and the target parasitic mode corresponding to the target parasitic mode information based on the target conversion information includes: Determine the target transformation matrix The value of the first element that satisfies the preset matrix rules is used to obtain the target feature value of the first element; When the first element is the target feature value, based on the target transformation matrix The target coupling strength between the quantum device and the target parasitic mode information is obtained.

7. The method according to claim 6, wherein, The method of obtaining the inductance energy percentage of the quantum device under different target modes based on the target parasitic mode information and the target intrinsic mode information of the quantum device includes: The inductance energy percentage of quantum device n in target mode m is obtained as follows: : Based on the target parasitic mode information or the target intrinsic mode information of the quantum device, the inductance energy of the target mode m stored in the quantum device n is obtained. And obtain the total inductance energy stored in the target mode m. ; Based on the inductor energy stored in quantum device n in the target mode m and the total inductance energy stored in the target mode m The inductance energy ratio of quantum device n in target mode m was obtained. .

8. The method according to claim 7, wherein, The inductor energy obtained from the target mode m is stored in the quantum device n. ,include: The inductance value of quantum device n was calculated. And the voltage of the target mode m along the voltage integral line of the quantum device n in space is calculated. ; Inductance value based on quantum device n The voltage of the target mode m along the voltage integral line of the quantum device n in space. and the frequency corresponding to the target mode m The inductance energy of the target mode m stored in the quantum device n is obtained. ; Wherein, when the target mode m is a target eigenmode, the frequency corresponding to the target mode m. The intrinsic frequencies corresponding to the target mode m The intrinsic mode information corresponding to target mode m includes the intrinsic frequencies corresponding to target mode m. ;or, When the target mode m is a target parasitic mode, the frequency corresponding to the target mode m Parasitic frequency corresponding to target mode m The target parasitic mode information corresponding to target mode m includes the parasitic frequency corresponding to target mode m. .

9. The method according to claim 8, wherein, The inductance value of the quantum device n is obtained through calculation. ,include: The correlation is obtained, wherein the correlation is the correlation between the inductance energy ratio of quantum device n in different target modes; Based on the correlation between the inductance energy ratio of quantum device n in different target modes, the inductance value of quantum device n is obtained. .

10. The method according to claim 8, wherein, The calculation yields the voltage of the target mode m along the voltage integral line of the quantum device n in space. ,include: Based on the electric field intensity distribution information of the target mode m in space, the voltage of the quantum device n along the voltage integral line in space is calculated. ; Specifically, when the target mode m is a target intrinsic mode, the target intrinsic mode information corresponding to the target mode m includes the electric field intensity distribution information of the target mode m in space; or, when the target mode m is a target parasitic mode, the target parasitic mode information corresponding to the target mode m includes the electric field intensity distribution information of the target mode m in space.

11. The method according to any one of claims 7-10, wherein, The total inductance energy stored in the target mode m is obtained. ,include: Based on the electric field intensity distribution information of the target mode m in space, the average electric field energy stored in space by the target mode m is obtained. ; The average electric field energy stored in space for the target mode m The total inductance energy stored in the target mode m ; Specifically, when the target mode m is a target intrinsic mode, the target intrinsic mode information corresponding to the target mode m includes the electric field intensity distribution information of the target mode m in space; or, when the target mode m is a target parasitic mode, the target parasitic mode information corresponding to the target mode m includes the electric field intensity distribution information of the target mode m in space.

12. A device for measuring parasitic modes in a quantum chip layout, comprising: The simulation unit is used to simulate the quantum chip layout to obtain the target intrinsic mode information of the quantum devices in the quantum chip layout, and to obtain the target parasitic mode information of the quantum chip layout; wherein, the quantum device is one of the multiple quantum devices included in the quantum chip layout; The processing unit is used to obtain the target coupling strength between the quantum device and the target parasitic mode corresponding to the target parasitic mode information based on the target intrinsic mode information of the quantum device and the target parasitic mode information of the quantum chip layout; wherein, the target coupling strength is used to measure the degree of influence of the target parasitic mode information on the characteristic parameters of the quantum device; Specifically, the processing unit is used to obtain first conversion information based on the target parasitic mode information of the quantum chip layout and the target intrinsic mode information of the quantum devices; the quantum chip layout contains N quantum devices, and the first conversion information is processed through a first conversion matrix. In the case of representing, in the first transformation matrix Add N+1 first elements to obtain the target transformation matrix. Wherein, the target transformation matrix Used to represent target transformation information; the N+1 first elements are the target transformation matrix. The (N+1)th column in the first transformation matrix; elements in Based on The result, the stated This represents the proportion of inductor energy of quantum device n in the target mode m of the mode set. The quantum device n is one of N quantum devices; based on the target conversion information, the target coupling strength between the quantum device and the target parasitic mode corresponding to the target parasitic mode information is obtained.

13. The apparatus according to claim 12, wherein, The target coupling strength is also used to determine the structural features in the quantum chip layout that cause changes in the target parasitic mode information.

14. The apparatus according to claim 12 or 13, wherein, The simulation unit is specifically used for: At a first simulation precision, a pre-simulation of the quantum chip layout is performed to obtain the first intrinsic mode information of the quantum device in the quantum chip layout; the first intrinsic mode information of the quantum device is the intrinsic mode information of the quantum device at the first simulation precision. The quantum chip layout is simulated at the target simulation accuracy to obtain the system eigenmode information of the quantum chip layout at the target simulation accuracy. The target simulation accuracy is greater than the first simulation accuracy; Based on the first intrinsic mode information of the quantum device, the target intrinsic mode information of the quantum device is determined from the system intrinsic mode information of the quantum chip layout under the target simulation accuracy.

15. The apparatus according to claim 12 or 13, wherein, The simulation unit is specifically used for: At a first simulation precision, the quantum chip layout is pre-simulated to obtain at least one first parasitic mode information of the quantum chip layout at the first simulation precision. The quantum chip layout is simulated at the target simulation accuracy to obtain the system eigenmode information of the quantum chip layout at the target simulation accuracy. The target simulation accuracy is greater than the first simulation accuracy; Based on at least one first parasitic mode information of the quantum chip layout at the first simulation accuracy, the target parasitic mode information of the quantum chip layout is determined from the system intrinsic mode information of the quantum chip layout at the target simulation accuracy.

16. The apparatus according to claim 12 or 13, wherein, The processing unit is specifically used for: Based on the target parasitic mode information and the target intrinsic mode information of the quantum device, the inductance energy ratio of the quantum device under different target modes is obtained; the target intrinsic mode information of the quantum device corresponds to a target intrinsic mode; the mode set includes: the target intrinsic mode of each quantum device in multiple quantum devices, and the target parasitic mode corresponding to the target parasitic mode information of the quantum chip layout; the target mode is one of the elements in the mode set; The first conversion information is obtained based on the proportion of inductor energy of the quantum device in different target modes.

17. The apparatus according to claim 12, wherein, The processing unit is specifically used to determine the target transformation matrix. The value of the first element that satisfies the preset matrix rules is used to obtain the target feature value of the first element; When the first element is the target feature value, based on the target transformation matrix The target coupling strength between the quantum device and the target parasitic mode information is obtained.

18. The apparatus according to claim 17, wherein, The processing unit is specifically used for: The inductance energy percentage of quantum device n in target mode m is obtained as follows: : Based on the target parasitic mode information or the target intrinsic mode information of the quantum device, the inductance energy of the target mode m stored in the quantum device n is obtained. And obtain the total inductance energy stored in the target mode m. ; Based on the inductor energy stored in quantum device n in the target mode m and the total inductance energy stored in the target mode m The inductance energy ratio of quantum device n in target mode m was obtained. .

19. The apparatus according to claim 18, wherein, The processing unit is specifically used for: The inductance value of quantum device n was calculated. And the voltage of the target mode m along the voltage integral line of the quantum device n in space is calculated. ; Inductance value based on quantum device n The voltage of the target mode m along the voltage integral line of the quantum device n in space. and the frequency corresponding to the target mode m The inductance energy of the target mode m stored in the quantum device n is obtained. ; Wherein, when the target mode m is a target eigenmode, the frequency corresponding to the target mode m. The intrinsic frequencies corresponding to the target mode m The intrinsic mode information corresponding to target mode m includes the intrinsic frequencies corresponding to target mode m. ;or, When the target mode m is a target parasitic mode, the frequency corresponding to the target mode m Parasitic frequency corresponding to target mode m The target parasitic mode information corresponding to target mode m includes the parasitic frequency corresponding to target mode m. .

20. The apparatus according to claim 19, wherein, The processing unit is specifically used for: The correlation is obtained, wherein the correlation is the correlation between the inductance energy ratio of quantum device n in different target modes; Based on the correlation between the inductance energy ratio of quantum device n in different target modes, the inductance value of quantum device n is obtained. .

21. The apparatus according to claim 19, wherein, The processing unit is specifically used for: Based on the electric field intensity distribution information of the target mode m in space, the voltage of the quantum device n along the voltage integral line in space is calculated. ; Specifically, when the target mode m is a target intrinsic mode, the target intrinsic mode information corresponding to the target mode m includes the electric field intensity distribution information of the target mode m in space; or, when the target mode m is a target parasitic mode, the target parasitic mode information corresponding to the target mode m includes the electric field intensity distribution information of the target mode m in space.

22. The apparatus according to any one of claims 18-21, wherein, The processing unit is specifically used for: Based on the electric field intensity distribution information of the target mode m in space, the average electric field energy stored in space by the target mode m is obtained. ; The average electric field energy stored in space for the target mode m The total inductance energy stored in the target mode m ; Specifically, when the target mode m is a target intrinsic mode, the target intrinsic mode information corresponding to the target mode m includes the electric field intensity distribution information of the target mode m in space; or, when the target mode m is a target parasitic mode, the target parasitic mode information corresponding to the target mode m includes the electric field intensity distribution information of the target mode m in space.

23. A computing device, comprising: At least one quantum processing unit (QPU); A memory, coupled to the at least one QPU and used to store executable instructions, The instructions are executed by the at least one QPU to enable the at least one QPU to perform the method of any one of claims 1-11; Or, including: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-11.

24. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, When at least one quantum processing unit is executed, the computer instructions cause the at least one quantum processing unit to perform the method according to any one of claims 1-11; Alternatively, the computer instructions are used to cause the computer to perform the method according to any one of claims 1-11.

25. A computer program product comprising a computer program that, when executed by at least one quantum processing unit, implements the method according to any one of claims 1-11; Alternatively, the computer program, when executed by a processor, implements the method according to any one of claims 1-11.

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