Selecting a stream for optimized inference

Abstract

The present disclosure relates to selecting a flow for optimizing inference. Apparatuses, systems, and techniques for selecting a flow to run inference based at least in part on heuristics. In at least one embodiment, the heuristics are generated based at least in part on information inferred using one or more machine learning models applied to the flow.

Description

Technical Field

[0001] At least one embodiment relates to a processor or computing system for selecting a stream for inference based at least in part on heuristics, according to the various new techniques described herein. Background Technology

[0002] Running inference across multiple data streams can be used in various domains. For example, one or more cameras can provide multiple streams of images and / or audio frames based on video surveillance of an entrance gate, garage, road, or factory line to detect, identify, or track one or more objects. To detect, identify, or track one or more objects, a system or application can use a machine learning model to perform inference across multiple data streams. Using machine learning models to perform inference across multiple data streams can be complex and may require significant computational resources. Attached Figure Description

[0003] Figure 1 A system for processing multiple data streams according to at least one embodiment is shown;

[0004] Figure 2 A system for processing multiple data streams according to at least one embodiment is shown;

[0005] Figure 3 An example block diagram is shown illustrating a heuristic-based selection of a data stream for inference according to at least one embodiment;

[0006] Figure 4 An example process for selecting a data stream for inference based on heuristics and user-defined parameters according to at least one embodiment is shown;

[0007] Figure 5 An example of selecting a data stream for inference according to at least one embodiment is shown;

[0008] Figure 6 An example process for processing a data stream prior to inference, according to at least one embodiment, is shown;

[0009] Figure 7A The logic according to at least one embodiment is shown;

[0010] Figure 7B The logic according to at least one embodiment is shown;

[0011] Figure 8 The training and deployment of a neural network according to at least one embodiment are illustrated;

[0012] Figure 9 An example data center system according to at least one embodiment is shown;

[0013] Figure 10A An example of an autonomous vehicle according to at least one embodiment is shown;

[0014] Figure 10B The illustration shows an embodiment according to at least one of the embodiments. Figure 10A Examples of camera positions and field of view for autonomous vehicles;

[0015] Figure 10C This is an illustration based on at least one embodiment. Figure 10A A block diagram of an example system architecture for an autonomous vehicle;

[0016] Figure 10D The illustration, according to at least one embodiment, is for one or more cloud-based servers and Figure 10A A diagram of a system for communication between autonomous vehicles;

[0017] Figure 11 This is a block diagram illustrating a computer system according to at least one embodiment;

[0018] Figure 12 This is a block diagram illustrating a computer system according to at least one embodiment;

[0019] Figure 13 A computer system according to at least one embodiment is shown;

[0020] Figure 14 A computer system according to at least one embodiment is shown;

[0021] Figure 15A A computer system according to at least one embodiment is shown;

[0022] Figure 15B A computer system according to at least one embodiment is shown;

[0023] Figure 15C A computer system according to at least one embodiment is shown;

[0024] Figure 15D A computer system according to at least one embodiment is shown;

[0025] Figure 15E and Figure 15F A shared programming model according to at least one embodiment is shown;

[0026] Figure 16 An exemplary integrated circuit and a related graphics processor according to at least one embodiment are shown;

[0027] Figures 17A to 17B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0028] Figures 18A to 18B Additional exemplary graphics processor logic according to at least one embodiment is shown;

[0029] Figure 19 A computer system according to at least one embodiment is shown;

[0030] Figure 20A A parallel processor according to at least one embodiment is shown;

[0031] Figure 20B A partitioning unit according to at least one embodiment is shown;

[0032] Figure 20C A processing cluster according to at least one embodiment is shown;

[0033] Figure 20D A graphics multiprocessor according to at least one embodiment is shown;

[0034] Figure 21 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0035] Figure 22 A graphics processor according to at least one embodiment is shown;

[0036] Figure 23 It is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0037] Figure 24 A deep learning application processor according to at least one embodiment is shown;

[0038] Figure 25 A block diagram of an example neuromorphic processor is shown according to at least one embodiment;

[0039] Figure 26 At least a portion of a graphics processor according to one or more embodiments is shown;

[0040] Figure 27 At least a portion of a graphics processor according to one or more embodiments is shown;

[0041] Figure 28 At least a portion of a graphics processor according to one or more embodiments is shown;

[0042] Figure 29 A block diagram of a graphics processing engine of a graphics processor is shown according to at least one embodiment;

[0043] Figure 30 This is a block diagram illustrating at least a portion of a graphics processor core according to at least one embodiment;

[0044] Figures 31A to 31B The diagram illustrates thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core;

[0045] Figure 32 A parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0046] Figure 33 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated;

[0047] Figure 34 A memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0048] Figure 35 A streaming multiprocessor according to at least one embodiment is illustrated;

[0049] Figure 36 This is an example data flow diagram of an advanced computing pipeline according to at least one embodiment;

[0050] Figure 37 This is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment;

[0051] Figure 38 Example illustrations of an advanced computing pipeline for processing imaging data according to at least one embodiment;

[0052] Figure 39A Includes example data flow diagrams of virtual instruments supporting ultrasound equipment according to at least one embodiment;

[0053] Figure 39B Includes example data flow diagrams of virtual instruments supporting CT scanners according to at least one embodiment;

[0054] Figure 40A A data flow diagram illustrating the process for training a machine learning model according to at least one embodiment is shown; and

[0055] Figure 40B This is an example illustration of a client-server architecture that utilizes a pre-trained annotation model to enhance an annotation tool, according to at least one embodiment. Detailed Implementation

[0056] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to those skilled in the art that the concepts of the invention can be practiced without one or more of these specific details.

[0057] In at least one embodiment, a system employing the techniques described herein uses one or more machine learning models to generate and / or modify heuristic information to infer information from one or more data streams of a specific number of frames. In one or more embodiments, the system may be implemented using or including pipelines with cascaded machine learning models, neural networks, or computer vision algorithms, which require different formats and frame resolutions as input. Inferring information from one or more data streams of a specific number of frames using one or more machine learning models, neural networks, or computer vision algorithms may result in the detection of multiple objects in a specific number of frames from one set of data streams, but not a smaller number of objects in a specific number of frames from another set of data streams. In another example, user-defined parameters may define the number of objects to be detected as a threshold for selecting the data stream used for inference. Therefore, both the heuristic information and the user-defined parameters can determine the set of data streams to be used for inference on a specific number of frames.

[0058] In at least one embodiment, other examples of user-defined parameters include the size of the object to be detected. This size may include the height, width, or both of a bounding box or one or more bounding boxes. In one example, the user may determine a region of interest (ROI). The ROI may be dynamic, depending on user preferences. Furthermore, the user may set parameters to specify one class in a multi-class neural network for priority ranking. User-defined parameters may also include determining the resolution of frames from the incoming data stream or determining their priority.

[0059] In at least one embodiment, the system determines how many frames to skip for one or more data streams based at least in part on heuristic information and / or various user-defined parameters. If more objects are detected in one or more data streams based at least in part on heuristic information and / or various user-defined parameters, the system can determine that one or more data streams have shorter skip intervals. Alternatively, if fewer objects are detected in one or more frames from one or more data streams based at least in part on heuristic information and / or various user-defined parameters, the system can determine that one or more data streams have longer skip intervals. In one example, 30 out of 100 data streams have shorter skip intervals because a certain number of objects are detected in the frames of those 30 data streams, while the remaining 100 data streams have longer skip intervals because fewer than a certain number of objects are detected in the frames of the remaining data streams. In another example, all data streams have different skip intervals because the number of objects detected in the frames from each stream is different. In one embodiment, each data stream may have the same skip interval, but the skip interval for each data stream may be varied, at least in part, based on heuristics and / or user-defined parameters. Dynamically selecting different skip intervals for one or more data streams can help save GPU resources.

[0060] In at least one embodiment, GPU resources saved by selectively inferring from frames of a particular data stream can be used for other operations of an application performed by a computing device. In one example, the application includes a pipeline that takes video as input and performs video analysis. The application includes using an auxiliary machine learning model in the pipeline by leveraging the saved GPU resources. The auxiliary machine learning model may include a classifier that classifies detected objects and a tracker that tracks objects detected in a previous batch of frames. Various components in the pipeline may have individual requirements for handling different inputs. To meet these requirements, one example could be converting one or more frames in a batch to a resolution or color format suitable or compatible with the neural network used to perform inference. Furthermore, converting frames to a resolution suitable or compatible with the neural network may include scaling up and down. The system can achieve optimal processing of one or more batches of frames by running various operations using the GPU resources saved from selective inference.

[0061] Figure 1The illustration depicts a system 100 for processing multiple data streams according to at least one embodiment. System 100 may be a computer system utilizing one or more processors, including a central processing unit (CPU), video image synthesizer (VIC), graphics processing unit (GPU), data processing unit (DPU), or other hardware such as a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC), to analyze traffic camera data, security camera footage, or typically analyze data from multiple sources by executing one or more processing pipelines.

[0062] In at least one embodiment, the processing pipeline performed by system 100 includes multiple components, such as, but not limited to, multiple decoders 112, 114, 116, 118 that receive data streams 102, 104, 106, 108, a stream multiplexer 120, and a master detector 130. Unless the context clearly indicates otherwise, each component of the processing pipeline within system 100 refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. The software can be embodied as a software package, code, and / or instruction set or instructions that, due to execution by one or more processors, enable the system to perform one or more video processing operations. These processors include a central processing unit (CPU), video image synthesizer (VIC), graphics processing unit (GPU), data processing unit (DPU), or other hardware such as a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). The term "hardware" as used in any of the embodiments described herein can include, for example, hard-wired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution unit circuitry, and / or firmware storing instructions executed by the programmable circuitry to perform one or more video processing operations, either individually or in any combination. These components can be embodied collectively or individually as circuitry forming part of a larger system, such as an integrated circuit (IC), a system-on-a-chip (SoC), etc. In one embodiment, system 100 is combined with... Figure 2 The system 200 described is associated with this.

[0063] In at least one embodiment, system 100 receives data streams 102, 104, 106, and 108. Alternatively, system 100 may receive only data stream 102. Data streams 102, 104, 106, and 108 may be generated using a camera or other sensors (microphone, radar, LiDAR, ultrasound, etc.) and originate from a network or local file system. Multiple cameras may be used to capture and provide data from data streams 102, 104, 106, 108, and 110. Cameras may include any particular lens type (e.g., pinhole, fisheye) or configuration or orientation (e.g., mono, stereo, depth). In one embodiment, the data streams may originate from different sources. For example, data stream 102 may be generated using a camera or other sensors (microphone, radar, LiDAR, ultrasound, etc.), and data stream 104 may originate from a network or local file system. A central processing unit (CPU) may capture, and a memory device may store the captured data streams 102, 104, 106, and 108. Data streams 102, 104, 106, and 108 can be encoded in different formats, such as, but not limited to, H.264, H.265, Audio Video Interleaved (AVI), Joint Picture Experts Group (JPEG), Motion JPEG (MJPEG), or SMPTE 421M / VC-1 format.

[0064] In at least one embodiment, system 100 sends frames from data streams 102, 104, 106, and 108 to corresponding decoders 112, 114, 116, and 118. Decoders 112, 114, 116, and 118 can convert the corresponding frames encoded in the above format from data streams 102, 104, 106, and 108 into a format acceptable to stream multiplexer 120. Example formats acceptable to stream multiplexer 120 may include NV12 or any other byte stream containing color data. Color data may be represented using YUV, RGB, or HSL. Decoders 112, 114, 116, and 118 can obtain frames from corresponding data streams 102, 104, 106, and 108 by decompressing them.

[0065] In at least one embodiment, stream multiplexer 120 receives decoded frames from decoders 112, 114, 116, and 118. Before stream multiplexer 120 receives the decoded frames, system 100 may combine... Figure 6The described method preprocesses decoded frames. Stream multiplexer 120 can form a batch of frames of size N by receiving each frame from N data streams. In one embodiment, the size of a batch of frames can be smaller than the number of data streams. In another embodiment, the size of the batch of frames can be larger than the number of data streams, such that multiple frames from one or more data streams are formed in a single batch of frames. In one embodiment, stream multiplexer 120 can form a batch of frames by receiving frames from a single data stream. Stream multiplexer 120 can form a batch of frames from decoded frames for a specific number of consecutive frames. Stream multiplexer 120 can use a cyclic algorithm to collect frames from decoded frames. Stream multiplexer 120 can make all frames in the batch have the same resolution. User-defined parameters can determine the resolution, and stream multiplexer 120 can scale the desired frames to the user-defined resolution. In one embodiment, a batch of frames can be formed in a buffer. In another embodiment, stream multiplexer 120 creates a buffer pool and allocates buffers to scale the desired frames to a specific resolution.

[0066] In at least one embodiment, the master detector 130 receives one or more batches of frames from the stream multiplexer 120. The master detector 130 may receive a buffer containing a batch of frames from a specific number of data streams. In one embodiment, the master detector 130 may have a batch size required for running inference. The master detector 130 may receive a batch of frames with a batch size larger than the required batch size, and the master detector 130 may run inference multiple times until all frames in the received batch have been processed. Alternatively, the master detector 130 may receive a batch of frames with a batch size smaller than the required batch size. The master detector 130 may process a batch of frames to detect objects within the frames.

[0067] In at least one embodiment, the master detector 130 infers on a batch of frames using one or more machine learning models. The one or more machine learning models may include, for example, but not limited to, one or more neural networks 180. In one embodiment, the one or more neural networks 180 may support, for example, but not limited to, multi-class object detection, multi-label classification, semantic segmentation, instance segmentation, radial basis function networks (RBNs), autoencoders (AEs), Boltzmann machines (BMs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), deep convolutional networks (DCNs), extreme learning machines (ELMs), deep residual networks (DRNs), and / or variations thereof. In one embodiment, running inference on frames from one or more data streams from a specific number of frames using one or more machine learning models may result in the detection of multiple objects in frames from a subset of the data streams. Alternatively, running inference on one or more data streams from a specific number of frames using one or more machine learning models may result in no objects being detected in frames from another subset of the data streams.

[0068] In at least one embodiment, the main detector 130 determines one or more bounding boxes for one or more objects depicted in one or more frames. According to embodiments, an object can refer to any suitable entity or object in a scene represented in one or more frames, such as a person, environmental object, vehicle, robot, and / or variations thereof. Furthermore, a bounding box can indicate the location and / or position of an object represented in an image. For example, a bounding box can define a set of coordinates corresponding to the corners of a particular bounding box that contains all or part of the object depicted in one or more frames. Furthermore, according to embodiments, a bounding box can indicate a region or area of ​​a frame that includes the depiction of an object. In various embodiments, the main detector 130 can determine bounding boxes for any number of objects represented in one or more frames and output bounding boxes and / or bounding box information (e.g., coordinates or other geometric information representing the bounding boxes) to the objects. The main detector 130 can determine bounding boxes for each frame and only for a subset of frames.

[0069] In at least one embodiment, a master detector 130 receives a first batch of frames from one or more data streams generated using one or more cameras or other sensors, networks, or local file systems. After receiving the first batch of frames, the master detector 130 can run inference on the first batch of frames using one or more machine learning models. The master detector 130 can generate heuristic information based at least in part on information inferred from the first batch of frames. The master detector 130 can then receive one or more additional batches of frames from the data streams using one or more cameras or other sensors, networks, or local file systems. The master detector 130 can select one or more frames from the other batches of frames to run inference using one or more machine learning models. The master detector 130 can update the heuristic information based at least in part on information inferred from one or more selected frames. The master detector 130 can provide inference information to system 100. In one embodiment, the generation and updating of heuristic information can be performed in other components of system 100.

[0070] In at least one embodiment, the master detector 130 includes multiple modes, such as a main mode and a preprocessed input mode. The main mode may preprocess batches of frames from the stream multiplexer 120 and run inference on the batches of frames. The preprocessed input mode may skip preprocessing before running inference on the batches of frames.

[0071] In at least one embodiment, the master detector 130 receives configuration parameters, such as, but not limited to: the number of classes detected by one or more neural networks 180, pixel normalization factor, pathname of the model file, pathname of the original text file, pathname of the integer 8 calibration file with dynamic range adjustment using a floating-point 32 model, the number of frames or objects jointly inferred in a batch, inference information in the form of metadata, size of the inference information, pathname of the serialized model engine file, pathname of the Universal File Format (UFF) model file, pathname of the Open Neural Network Exchange (ONNE) file, an indicator indicating whether to use an application with a density-based spatial clustering algorithm with noise, pathname of the text file containing model labels, pathname of the average data file in Portable Pixel Map (PPM) format, a unique identifier assigned to the GPU inference engine, the number of consecutive batches to be skipped for inference, the dimension of the UFF model, the data format used for inference, an array of average values ​​of color components to be subtracted from each pixel, an array of output layer names, the name of a custom bounding box parsing function, and a custom implementation. Examples of parameters include: the name of the segmentation parsing function, the absolute path name of the library containing the custom method implementation of the custom model, the color format required by the model, enabling inference for detected objects and asynchronous metadata attachments, the configuration of the primary mode or preprocessed input mode, the minimum threshold label probability, the name of the input large binary object in the UFF file, the object re-inference interval, an indication of whether to use a deep learning accelerator for inference, the neural network type 180, an indication of whether to maintain aspect ratio when scaling the input, an indication of whether to symmetrically fill the image when scaling the input, the name of the custom classifier output parsing function, the path name of the custom network's configuration file, the path name of the toolkit-encoded model, the key of the toolkit-encoded model, the confidence threshold for the valid class of the segmentation model's output pixels, the segmentation network output layer order, the workspace size used by the engine, an indication of the implicit batch dimension mode, the binding dimension set on the image input layer, the UFF input layer order, the type of clustering algorithm to use, the filter used for scaling the frame, the computer hardware used for scaling the frame, the data type specification, the device type specification, and the precision of any layer in the network or the order of the network input layers.

[0072] In at least one embodiment, the main detector 130 receives other parameters, such as, but not limited to: a detection threshold, an ε value, a group threshold, the minimum number of points required to form a dense region for an application with a noise-based spatial clustering, the minimum sum of confidence of all nearest neighbors in a cluster that would make it a valid cluster, a maximum crossover ratio threshold, an offset value of the region of interest, the minimum width or height (in pixels) of the detected objects, or the number of objects detected based at least in part on the highest detection score.

[0073] In at least one embodiment, the master detector 130 automatically changes parameters, such as, but not limited to: the absolute pathname of the configuration file, the configuration of the primary mode or preprocessed input mode, a unique identifier for the metadata, a unique identifier for the GPU inference engine to be assigned, the absolute pathname of the pre-generated serialization engine file for the mode, the number of frames / objects to be inferred together in a batch, the number of consecutive batches to skip for inference, the device identifier of the GPU used for preprocessing or inference, the pathname of the raw inference output file, a pointer to a callback function generated from the raw output, a pointer to user data to be provided along with the callback generated from the raw output, an indication of whether to attach the inference output as metadata, or an indication of whether to use the preprocessed input as metadata. In one embodiment, the master detector 130 may change the above parameters at least in part based on heuristic information, wherein the heuristic information is obtained by performing a combination Figure 4 or Figure 5 It is generated by one or more steps as described.

[0074] In at least one embodiment, the main detector 130 supports a clustering algorithm. The clustering algorithm can use a rectangular equivalence criterion to construct rectangles of similar size and location. In one example, the clustering algorithm can filter overlapping rectangles based on the degree of overlap. Overlapping rectangles with the highest confidence scores can be retained initially, while rectangles with overlap greater than a threshold can be iteratively removed. The main detector 130 can support a hybrid clustering algorithm that uses a rectangular equivalence criterion to construct clustered rectangles of similar size and location and filters overlapping rectangles based on the degree of overlap, where overlap can be used as a threshold.

[0075] Figure 2 The illustration depicts a system 200 for processing multiple video streams according to at least one embodiment. System 200 may be a computer system utilizing one or more processors, including a central processing unit (CPU), video image synthesizer (VIC), graphics processing unit (GPU), data processing unit (DPU), or other hardware such as a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC), to analyze traffic camera data, security camera footage, or typically by executing one or more processing pipelines to analyze data from multiple sources.

[0076] In at least one embodiment, the processing pipeline within system 200 includes multiple components, such as, but not limited to, a main detector 210, an object tracker 220, an auxiliary classifier 230, a visualizer 240, a local disk 250, a cloud 260, or a screen 270. Unless the context explicitly states otherwise, each component of the processing pipeline within system 200 refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. The software may be embodied as a software package, code, and / or a set of instructions or instructions that, due to execution by one or more processors, enable the system to perform one or more video processing operations. Processors include a central processing unit (CPU), a video image synthesizer (VIC), a graphics processing unit (GPU), a data processing unit (DPU), or other hardware such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). "Hardware" as used in any implementation described herein may include, for example, hardwired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution unit circuitry, and / or firmware storing instructions executed by programmable circuitry to perform one or more video processing operations. These components may be collectively or individually embodied as circuitry forming part of a larger system, such as integrated circuits (ICs), system-on-chips (SoCs), etc. In at least one embodiment, system 200 is combined with... Figure 1 The system 100 described is associated with this.

[0077] In at least one embodiment, the main detector 210 is identical to the main detector 130, which can perform various operations, not limited to preprocessing incoming batches of frames, performing inference on batches of frames based on one or more machine learning models including one or more neural networks 280, and receiving and modifying combinations. Figure 1 The various parameters described.

[0078] In at least one embodiment, object tracker 220 obtains inference information (e.g., the number of objects detected in one or more frames) from master detector 210. For example, object tracker 220 may execute one or more computer vision algorithms that determine bounding boxes for one or more frames to track the positions of multiple objects in adjacent frames. Master detector 210 and / or object tracker 220 may be configured with parameters (e.g., tracking distance) that determine which frames will be processed by master detector 210 and / or object tracker 220. For example, tracking distance may indicate the number of frames among those processed by master detector 210. Tracking distance can be any suitable integer value.

[0079] In at least one embodiment, object tracker 220 tracks detected objects within one or more frames having permanent or unique identifiers. Tracking can be accomplished by receiving one or more parameters from the user. In one embodiment, object tracker 220 determines bounding boxes based on data stream frames not processed by main detector 210. For example, main detector 210 may determine bounding boxes for every other frame (e.g., first frame, third frame, fifth frame, etc.) of one or more data streams, and object tracker 220 may determine bounding boxes for the remaining frames of one or more data streams (e.g., second frame, fourth frame, sixth frame, etc.). In various embodiments, object tracker 220 performs various object tracking procedures, such as one or more kernel-based tracking procedures and / or contour tracking procedures, to determine the bounding boxes of objects in a frame based on the bounding boxes of objects in the previous frame and / or the bounding boxes of objects in the subsequent frame.

[0080] In at least one embodiment, object tracker 220 determines bounding boxes for any number of objects in any suitable number of frames based on bounding boxes determined by master detector 210. Object tracker 220 may support discriminative learning algorithms for visual object tracking capabilities. Object tracker 220 may support tracking algorithms using deep cosine metric learning with a Re-ID neural network. The tracking algorithm can perform association between detector bounding boxes using the intersection of joint values ​​between two consecutive frames, or assign a new target identifier if no match is found.

[0081] In at least one embodiment, the primary detector 210 and / or object tracker 220 provide information (e.g., bounding boxes) to the auxiliary classifier 230. The auxiliary classifier 230 may include various machine learning models, such as perceptron models, radial basis function networks (RBNs), autoencoders (AEs), Boltzmann machines (BMs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), deep convolutional networks (DCNs), extreme learning machines (ELMs), deep residual networks (DRNs), logistic regression models, naive Bayes models, stochastic gradient descent models, K-nearest neighbor models, decision tree models, random forest models, support vector machine models, and / or variations thereof.

[0082] In at least one embodiment, the visualizer 240 includes a tiler that receives a batch of data from a main detector 210, an object tracker 220, and / or an auxiliary classifier 230. In one embodiment, the tiler may operate based on user-defined parameters. As a result, the tiler can synthesize two-dimensional tiles from the received batch, at least in part, based on data stream identifiers. Furthermore, data stream identifiers can be obtained in row-major order, starting from source 0, moving from left to right through the top row, and then through the next row. Each frame can be scaled to the corresponding position in the tiling's output buffer. If a new frame is added and the space allocated for the tiles is exceeded, the tiler can be reconfigured. If the frame rate of one data stream is lower than that of other data streams, the tiler can maintain a cache of older frames to avoid display flicker.

[0083] In at least one embodiment, the visualizer 240 receives a batch of frames from the main detector 210, the object tracker 220, or the auxiliary classifier 230 to draw bounding boxes, text, and region-of-interest polygons. The visualizer 240 may render a batch of frames to display some output, at least in part, based on user-defined parameters.

[0084] In at least one embodiment, system 200 receives output data from a main detector 210, an object tracker 220, an auxiliary classifier 230, or a visualizer 240. System 200 may provide the output data to a local disk 250 or the cloud 260 or render the output on a screen 270.

[0085] Figure 3 An example process for selecting frames from a data stream based on a heuristic according to at least one embodiment is illustrated. Although example process 300 is described as a series of steps or operations, it should be understood that embodiments of process 300 may include altered or reordered steps or operations, or certain steps or operations may be omitted unless explicitly stated or logically required, such as when the output of one step or operation is used as the input of another. Each block of process 300 described herein can be combined... Figure 1 and / or Figure 2 The described system is executed. In another embodiment, each block of process 300 can be executed using any combination of hardware, firmware, and / or software. For example, various functions can be performed by a processor executing instructions stored in memory. The method can also be embodied as computer-available instructions stored on a computer storage medium or provided by a standalone application, service, or hosting service (standalone or in combination with another hosting service).

[0086] In at least one embodiment, process 300 is executed in the system to perform inference on one or more data streams. At 302, the system may receive a first batch of frames. The first batch of frames may come from one or more cameras. Alternatively, the system may receive a first batch of frames from one or more data streams and generated using one or more cameras, other forms of sensors, networks, or local file systems. One or more processors may preprocess the first batch of frames before the system receives them. The first batch of frames can be combined with... Figure 6 The described steps involve one or more preprocessing steps. This can be combined with... Figure 1 The described method encodes or decodes the first batch of frames. The first batch of frames may be encoded in different formats, such as, but not limited to, H.264, H.265, Audio Video Interleaving (AVI), Joint Group of Picture Experts (JPEG), Motion JPEG (MJPEG), or SMPTE 421M / VC-1 format. Alternatively, the encoded data stream may be decoded before the system receives the first batch of frames. The first batch of frames may have the same resolution. In at least one embodiment, the system combines... Figure 1 The method described is used to receive the first batch of frames.

[0087] In 304, in at least one embodiment, the system performs inference on the first batch of frames. In one embodiment, combined with Figure 1 The described master detector 130 can run inference on the first batch of frames using one or more machine learning models. The machine learning models can include, for example, but are not limited to, one or more neural networks. One or more neural networks may require training. The result of training the neural networks can be the assignment of weights to one or more neurons of the neural networks.

[0088] In at least one embodiment, one or more neural networks support, for example, but not limited to, multi-class object detection, multi-label classification, semantic segmentation, instance segmentation, radial basis function networks (RBNs), autoencoders (AEs), Boltzmann machines (BMs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), deep convolutional networks (DCNs), extreme learning machines (ELMs), deep residual networks (DRNs), and / or variations thereof. Neural networks can organize patterns or datasets into predefined classes, predict expected outputs from given inputs, identify unique features of data and classify them without prior knowledge of data, or memorize patterns by associating new datasets with the most comparable versions.

[0089] In at least one embodiment, using one or more machine learning models to infer information about one or more data streams of a specific number of frames results in the detection, identification, or otherwise inference of information about multiple objects detected in one or more frames of one or more data streams. Alternatively, running inference using one or more machine learning models on one or more data streams of a specific number of frames may result in no objects being found in frames of another set of data streams. In another example, running inference using one or more machine learning models on one or more data streams of a specific number of frames may result in finding multiple objects within a region of interest in frames from one or more data streams. The region of interest may have a polygonal shape. One or more objects may be detected by drawing lines on one or more objects, determining whether the lines on one or more objects cross the region of interest, which may be a box or any polygon. In one example, one or more machine learning models may determine whether the top-left and bottom-right pixels are within the region of interest to determine whether an object has been detected.

[0090] In at least one embodiment, at 306, the system generates heuristic information. In one embodiment, the system may generate the heuristic information at least in part based on the inference information generated at 304. The inference information may be based on one or more machine learning models applied to one or more data streams of a specific number of frames. Alternatively, the heuristic information may be based at least in part on a combination of one or more machine learning models applied to a specific number of frames. Figure 1 The described one or more parameters and / or configuration data are used to perform inference on one or more data streams for a specific number of frames. In one example, heuristic information may include the number of objects detected in each frame for the specific number of frames. Furthermore, the heuristic information may include the type or classification of one or more objects detected in one or more data streams. Additionally, the heuristic information may include the number or type of objects detected in a specified region of interest in one or more data streams for the specific number of frames. Furthermore, the heuristic information may include the region of interest for one or more data streams. In at least one embodiment, the heuristic information is generated by a processor and stored in memory, wherein both the processor and the memory are different from the GPU.

[0091] In at least one embodiment, at point 308, the system receives an additional batch of frames from one or more data streams. In one embodiment, the system may receive one or more data streams from one or more cameras or other modal sensors. Alternatively, the system may receive one or more data streams from a network or local file system. Furthermore, one or more processors may preprocess the additional batch of frames before the system receives them. The additional first batch of frames may be combined with... Figure 6The preprocessing is described in a specific manner. The memory device can store the additional batch of frames. The system can encode the additional batch of frames into different formats, such as, but not limited to, H.264, H.265, Audio Video Interleaving (AVI), Joint Group of Picture Experts (JPEG), Motion JPEG (MJPEG), or SMPTE 421M / VC-1 format. Alternatively, the system can encode the frame data stream before receiving the additional batch of frames. All frames in the additional batch can have the same resolution. The system may combine... Figure 1 The method described describes receiving additional batches of frames. These additional batches of frames may originate from different sources than the first batch of frames in 302 (e.g., a camera, a sensor of another modality, or a server). Furthermore, the additional batches of frames may be encoded and / or decoded differently than the first batch of frames in 302.

[0092] In at least one embodiment, at 310, the system selects frames from one or more additional batches of frames, at least in part, based on heuristic information generated at 306. The system can determine from one or more data streams which frames should be skipped for a specific number of frames. Furthermore, frames from one or more data streams can have different skip intervals, at least in part, based on heuristic information. For example, a first data stream that detects more than 5 objects for a specific number of frames can always be selected for inference. A second data stream that detects 3 objects for a specific number of frames can have a skip interval of 5 frames. A third data stream that detects 0 objects for a specific number of frames can have a skip interval of 10 frames. The system can change the skip interval of frames from one or more data streams. Alternatively, the system can select all one or more data streams to run inference, meaning the system can choose to run inference on all frames from additional batches of frames.

[0093] In 312, in at least one embodiment, the system performs inference on one or more frames of the selected data stream. (Combined) Figure 1The described master detector 130 can run inference on a first batch of frames using one or more machine learning models. In one embodiment, some of the first batch of frames come from a data stream that is skipped for inference, at least partially based on heuristic information. The one or more machine learning models can include one or more neural networks that may need to be trained. Training the neural networks may result in assigning weights to one or more neurons of the neural networks. In one embodiment, various neural networks described at 306 can be used to run inference on selected data streams. In one embodiment, the one or more machine learning models used to run inference may be different from the machine learning models used at 306. In various embodiments, GPU resources can be saved by skipping one or more data streams that are not selected for inference.

[0094] In at least one embodiment, at 314, the system updates the heuristic. The system may update the heuristic information based at least in part on the inference information generated at 312. In one example, the system may compare the heuristic information generated at 312 with the heuristic information generated at 306. As a result, the system may select the heuristic information generated at 312. Alternatively, the system may select the heuristic information generated at 306 after comparing the heuristic information generated at 312 with the heuristic information generated at 306. The system may return to step 308 to receive additional batches of frames to generate and / or update the heuristic information by running inference on one or more frames from the additional batches of frames. In at least one embodiment, the system terminates or pauses the process and generates output based at least in part on the inference information.

[0095] Figure 4 The illustration depicts an example process for selecting frames from a data stream based on heuristics and user-defined parameters according to at least one embodiment. Although the example process 400 is depicted as a series of steps or operations, it should be understood that embodiments of process 400 may include modified or reordered steps or operations, or certain steps or operations may be omitted unless explicitly stated or logically required, such as when the output of one step or operation is used as the input to another. Each block of process 400 described herein can be combined... Figure 1 and / or Figure 2 The described system executes the process. Alternatively, each block of process 400 can be executed using any combination of hardware, firmware, and / or software. For example, various functions can be performed by the processor executing instructions stored in memory. The method can also be embodied as computer-available instructions stored on a computer storage medium or provided by a standalone application, service, or managed service (standalone or in combination with another managed service).

[0096] In at least one embodiment, process 400 is executed in the system to perform inference on one or more frames from one or more data streams. At 402, in at least one embodiment, the system receives a first batch of frames from one or more data streams. The system may receive the first batch of frames from one or more data streams generated using one or more cameras. Alternatively, the system may receive the first batch of frames from one or more data streams that were captured or generated using other sensors, networks, or local file systems using other modalities. One or more frames may be preprocessed before the system receives a batch of frames. The first batch of frames may be combined with... Figure 6 The system preprocesses the incoming first batch of frames in a manner described. The system can encode the first batch of frames into different formats, such as, but not limited to, H.264, H.265, Audio Video Interleaving (AVI), Joint Group of Picture Experts (JPEG), Motion JPEG (MJPEG), or SMPTE 421M / VC-1 format. Alternatively, the system can decode one or more data streams before forming the first batch of frames. In one embodiment, all frames in the first batch can have the same resolution. In one embodiment, the system can perform a combination... Figure 1 The described one or more steps receive the first batch of frames.

[0097] In error 404, in at least one embodiment, the system performs inference on the first batch of frames. This is achieved by using one or more machine learning models, combined with... Figure 1 The described master detector 130 can run inference on the first batch of frames. One or more machine learning models may include one or more neural networks. One or more neural networks may require training. One possible outcome of training a neural network is assigning weights to one or more neurons of the neural network.

[0098] In at least one embodiment, one or more neural networks support, for example, but not limited to, multi-class object detection, multi-label classification, semantic segmentation, instance segmentation, radial basis function networks (RBNs), autoencoders (AEs), Boltzmann machines (BMs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), deep convolutional networks (DCNs), extreme learning machines (ELMs), deep residual networks (DRNs), and / or variations thereof. The one or more neural networks listed above can organize patterns or datasets into predefined categories, predict expected outputs from given inputs, identify unique features of data and classify them without prior knowledge of data, or memorize patterns by associating new datasets with the most comparable versions.

[0099] In at least one embodiment, running inference using one or more machine learning models on one or more data streams of a specific number of frames results in finding multiple objects detected in one or more frames of one or more data streams. Alternatively, running inference using one or more machine learning models on one or more data streams of a specific number of frames may result in not finding any objects in frames of another set of data streams. In another example, running inference using one or more machine learning models on one or more data streams of a specific number of frames may result in finding multiple objects within a region of interest (ROI) of one or more frames from one or more data streams. The ROI may have a polygonal shape. One or more objects may be detected by drawing lines on one or more objects and determining whether the lines on one or more objects cross the ROI, which may be a box or any polygon. In one example, one or more machine learning models may determine whether the top-left and bottom-right pixels are within the ROI to determine whether an object has been detected.

[0100] In at least one embodiment, user-defined parameters are used to run inference on frames from one or more data streams. The user-defined parameters may include one or more regions of interest to run inference on one or more data streams, or to detect the length and height of an object by running inference on frames from one or more data streams using one or more machine learning models. Furthermore, the user-defined parameters may include the resolution required by the machine learning models. One or more machine learning models or one or more neural networks may have different resolutions, and the user-defined parameters may prioritize one or more machine learning models or one or more neural networks that can be used to run inference on frames from one or more data streams. In at least one embodiment, the user-defined parameters are combined with... Figure 1 and Figure 2 The described parameters are combined with the configuration data.

[0101] In at least one embodiment, at 406, the system generates heuristic information. In one embodiment, the system may generate the heuristic information at least in part based on the inference information generated at 404. The inference information may be based on one or more machine learning models applied to frames from one or more data streams for a specific number of frames. Alternatively, the heuristic information may be based on using one or more machine learning models in combination with... Figure 1The described one or more parameters and / or configuration data are used to perform inference on frames from one or more data streams for a specific number of frames. In one example, heuristic information may include the number of objects detected. Furthermore, heuristic information may include the type or classification of one or more objects detected in one or more frames. Additionally, heuristic information may include the number or type of objects detected in a region of interest specified in one or more data streams of a specific number of consecutive frames. Furthermore, heuristic information may include the region of interest of one or more data streams. In one embodiment, the heuristic information may be generated and / or updated by a processor and stored in memory, wherein the processor and memory are different from the GPU.

[0102] At 408, in at least one embodiment, the system examines user-defined parameters. For example, the system may receive user-defined parameters at 404 that are different from the user-defined parameters used to perform inference on frames from one or more data streams.

[0103] In at least one embodiment, at 410, the system receives one or more additional batches of frames. The system may receive additional batches of frames from data streams generated using one or more cameras. Alternatively, the system receives one or more additional batches of frames from data streams generated using one or more other sensor types, networks, or local file systems. Furthermore, one or more frames may be preprocessed before the system receives the additional batches of frames. The first batch of additional batches of frames can be processed by performing... Figure 6 The system may preprocess the additional batch of frames using one or more steps described herein. A memory device may store the additional batch of frames. The system may encode the additional batch of frames into, for example, but not limited to, H.264, H.265, Audio Video Interleaving (AVI), Joint Group of Picture Experts (JPEG), Motion JPEG (MJPEG), or SMPTE 421M / VC-1 format. Alternatively, the system may decode the encoded frames before receiving or forming the additional batch of frames. One or more frames from the additional batch may have the same resolution. The system may combine... Figure 1 The method described describes the reception of additional batches of frames. These additional batches of frames may originate from different sources compared to the first batch of frames in 402. Furthermore, the additional batches of frames may be encoded and / or decoded differently compared to 402.

[0104] In at least one embodiment, at 412, the system selects one or more data streams based at least in part on heuristic information generated at 406 and user-defined parameters. In one example, the system may determine one or more frames from one or more data streams to skip a specific number of frames. In another example, one or more data streams may have different skip intervals based at least in part on heuristic information and user-defined parameters. For example, based at least in part on heuristic information generated at 406 and user-defined parameters, a first data stream with more than 5 objects detected for a specific number of frames may always be selected for inference. Based at least in part on heuristic information generated at 406 and user-defined parameters, a second data stream with 3 objects detected for a specific number of frames may have a skip interval of 5 frames. Based at least in part on heuristic information generated at 406 and user-defined parameters, a third data stream with 0 objects detected for a specific number of frames may have a skip interval of 10 frames. In at least one embodiment, the skip interval may be based at least in part on the size of one or more objects detected in one or more data streams. For example, the size may include width, length, and height. In one embodiment, the system can change the skip interval of one or more data streams. In one embodiment, the system can select all data streams to run inference, meaning that all frames in a selected batch of frames are inferred. In one embodiment, user-defined parameters and heuristics generated at 406 can determine that 50 data streams should be skipped for a specific number of consecutive frames. In other words, the system may not run inference on half of the frames from a specific number of additional batches. In at least one embodiment, the region of interest for detecting one or more objects changes dynamically, at least in part, based on heuristics and / or user-defined parameters. In one example, the heuristics may include the number of objects detected within one or more regions of interest.

[0105] In 414, in at least one embodiment, the system performs inference on frames from a selected data stream. In one embodiment, combined with Figure 1 The described master detector 130 can run inference on a first batch of frames using one or more machine learning models. One or more machine learning models can include one or more neural networks. In one or more embodiments, training results in updating the weights of one or more neurons in the neural network. In one embodiment, the various neural networks described at 406 can be used to run inference on frames from a selected data stream. Alternatively, the one or more machine learning models used to run inference can be different from the machine learning model used at 406. In one embodiment, GPU resources can be saved by skipping frames from one or more data streams that were not selected for inference.

[0106] In at least one embodiment, at 416, the system updates the heuristic information. The system may update the heuristic information based at least in part on the inference information generated at 414. In one example, the system may compare the heuristic information generated at 414 with the heuristic information generated at 406. As a result, the system may select the heuristic information generated at 414. Alternatively, the system may select the heuristic information generated at 406 after comparing the heuristic information generated at 414 with the heuristic information generated at 406. In one embodiment, the system may return to step 408 to receive one or more additional batches of frames to run inference. Alternatively, the system may terminate or pause the process and generate output based at least in part on the inference information.

[0107] Figure 5 The illustration depicts an example of selecting frames from a data stream for inference according to at least one embodiment. Example 500 can be combined with... Figure 1 and or Figure 2 The system described executes. Example 500 can be combined with... Figure 3 and Figure 4 The described process 300 and / or process 400 are executed. The system can receive a specific number of frames of data stream 1 510, data stream 2 520, and data stream 3 530. The system can then determine to perform inference on data stream 1 FA 511, data stream 2 FA 521, and data stream 3 FA 531 in frame A 501. And this determination can be based at least in part on heuristic information and / or user-defined parameters. User-defined parameters may include a combination of... Figure 1 The description includes various parameters and configuration data. This can be combined with... Figure 1 , Figure 3 and / or Figure 4 Heuristic information is obtained in a described manner. In one embodiment, data stream 1 FA 511 may include one or more frames from data stream 1 510, data stream 2 FA 521 may include one or more frames from data stream 2 520, and data stream 3 FA 531 may include one or more frames from data stream 3 530. In various embodiments, frame A 501 may be one or more frames. In various embodiments, frame A 501 may have different numbers of frames for data stream 1 FA 511, data stream 2 FA 521, and data stream 3 FA 531.

[0108] In at least one embodiment, the system updates heuristic information and / or configuration. The system may determine to perform inference on one or more frames from data stream 2 FB 522, but skip data streams 1 FB 512 and 3 FB 532 in frame B 502. This determination may be based at least in part on heuristic information and / or user-defined parameters. User-defined parameters may include a combination of... Figure 1 The description includes various parameters and configuration data. This can be combined with... Figure 1 , Figure 3 and / or Figure 4 The described method acquires / updates heuristic information. In one embodiment, data stream 1 FB 512 may include one or more frames from data stream 1 510, stream 2 FB 522 may include one or more frames from data stream 2 520, and stream 3 FB 532 may include one or more frames from data stream 3 530. In various embodiments, frame B 502 may have one or more frames. In various embodiments, frame B 502 may have different numbers of frames for data stream 1 FB 512, data stream 2 FB 522, and data stream 3 FB 532. In various embodiments, frame B 502 may have different numbers of frames compared to frame A 501.

[0109] In at least one embodiment, the system updates heuristic information and / or configuration data. The system may determine to run inference on one or more frames from data stream 1 FC 513 and data stream 2 FC 523, but may skip data stream 3 FC 533 in frame C 503 at least in part based on heuristic information and / or user-defined parameters. User-defined parameters may include combinations of... Figure 1 The description includes various parameters and configuration data. This can be combined with... Figure 1 , Figure 3 and / or Figure 4 The described method acquires / updates heuristic information. In one embodiment, data stream 1 FC 513 may include one or more frames from data stream 1 510, data stream 2 FC 523 may include one or more frames from data stream 2 520, and data stream 3 FC 533 may include one or more frames from data stream 3 530. In various embodiments, frame C 503 may have one or more frames. In various embodiments, frame C 503 may have different numbers of frames for data stream 1 FC 513, data stream 2 FC 523, and data stream 3 FC 533. In various embodiments, frame C 503 may have different numbers of frames compared to frame A 501 and / or frame B 502.

[0110] In at least one embodiment, the system updates heuristic information and / or configuration. The system may determine to perform inference on one or more frames from data stream 2 FD 524, but may skip data streams 1 FD 514 and 3 FD 534 in frame D 504. This determination may be based at least in part on heuristic information and / or user-defined parameters. User-defined parameters may include a combination of... Figure 1 The description includes various parameters and configuration data. This can be combined with... Figure 1 , Figure 3 and / or Figure 4 The described method is used to obtain / update heuristic information. In one embodiment, data stream 1 FD 514 may include one or more frames from data stream 1 510, data stream 2 FD 524 may include one or more frames from data stream 2 520, and stream 3 FD 534 may include one or more frames from data stream 3 530. In various embodiments, frame D 504 may have one or more frames. In various embodiments, frame D 504 may have a different number of frames for streams 1 510, 2 520, and 3 530. In various embodiments, frame D 504 may have a different number of frames compared to frame A 501, frame B 502, and / or frame C 503.

[0111] Figure 6 An example process for processing a data stream prior to inference, according to at least one embodiment, is illustrated. Although the example process 600 is depicted as a series of steps or operations, it should be understood that embodiments of process 600 may include altered or reordered steps or operations, or certain steps or operations may be omitted unless explicitly stated or logically required, such as when the output of one step or operation is used as the input to another. In one embodiment, each block of process 600 may be combined... Figure 1 and / or Figure 2 Executed in the system. Alternatively, each block of process 600 can be executed using any combination of hardware, firmware, and / or software. For example, various functions can be performed by a processor executing instructions stored in memory. The method can also be embodied as computer-available instructions stored on a computer storage medium or provided by a standalone application, service, or managed service (standalone or in combination with another managed service). In another embodiment, process 600 can be executed in the system to perform inference on frames from one or more data streams. In at least one embodiment, process 600 is combined with... Figure 3 and Figure 4 The described process 300 and / or process 400 are executed together.

[0112] In 602, in at least one embodiment, the system receives a batch of frames from one or more data streams, at least in part based on heuristic information and / or user-defined parameters. In 604, in one embodiment, the system may perform operations on one or more frames from one or more data streams. One or more neural networks may require a specific input frame resolution to run inference, and one or more operations on the received frames may include scaling up or down to a certain resolution. For example, the resolution of the received frame may be 1920x1080, and the neural network may be configured, optimized, calibrated, or otherwise enabled to run inference on image frames with a resolution of 644x480; therefore, the system may perform one or more operations to scale down the received frame from 1920x1080 to 644x480. In another example, one or more neural networks in one or more machine learning models may require a specific color format or encoding to run inference on the frame. Furthermore, one or more operations on the received frame may include color conversion. For example, one or more operations on the received frame can convert the color format, which may include, but is not limited to, NV12, NV21, I420, P010_10LE, BGRx, RGBA, YUY, AB64, AR30, and RA. Other operations may include cropping one or more frames when converting to a different color format, rotating or flipping one or more frames when converting to a different color format, and dewarping one or more frames. Due to the combination... Figure 3 and / or Figure 4 The GPU resources saved by the described process or steps can be used to perform operations on the received data stream. This can be achieved by preprocessing only the data stream from the combined... Figure 3 and / or Figure 4 The described processes 300 and / or 400 select frames from the data stream to save additional GPU resources. At 606, in at least one embodiment, the system performs inference on frames from the processed data stream. In at least one embodiment, the system performs inference by performing a combination... Figure 3 and / or Figure 4 The described steps involve performing inference on frames from a processed data stream.

[0113] logic

[0114] Figure 7A Logic 715 is illustrated, and as described elsewhere herein, according to at least one embodiment, logic 715 can be used in one or more devices to perform operations such as those discussed herein. In at least one embodiment, logic 715 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 715 is inference and / or training logic. Details regarding logic 715 will be incorporated below. Figure 7AAnd / or 7B is provided. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide the functionality or operation described herein, wherein the logic may be collectively or individually embodied as circuitry forming part of a larger system, such as an integrated circuit (IC), a system-on-a-chip (SoC), or one or more processors (e.g., CPU, GPU).

[0115] In at least one embodiment, logic 715 may include, but is not limited to, code and / or data storage 701 for storing forward and / or output weights and / or input / output data, and / or other parameters configuring neurons or layers of a neural network trained for and / or used for inference in one or more embodiments. In at least one embodiment, logic 715 may include or be coupled to code and / or data storage 701 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 701 stores weight parameters and / or input / output data of each layer of a neural network trained or used in one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 701 may be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0116] In at least one embodiment, any portion of the code and / or data storage 701 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 701 may be a cache memory, dynamic random-addressable memory (“DRAM”), static random-addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 701 is internal or external to the processor, for example, or composed of DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip or off-chip storage space, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0117] In at least one embodiment, logic 715 may include, but is not limited to, code and / or data storage 705 for storing backpropagation and / or output weights and / or input / output data neural networks corresponding to neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, during training and / or inference using one or more embodiments, code and / or data storage 705 stores weight parameters and / or input / output data for each layer of a neural network trained or used in one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, logic 715 may include or be coupled to code and / or data storage 705 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)).

[0118] In at least one embodiment, code (such as graph code) causes the architecture of the neural network corresponding to that code to load weights or other parameter information into the processor ALU. In at least one embodiment, any portion of the code and / or data storage 705 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 705 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 705 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice between the code and / or data storage 705 being internal or external to the processor, for example, whether it consists of DRAM, SRAM, flash memory, or some other type of storage, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the data batch size used in the inference and / or training of the neural network, or some combination of these factors.

[0119] In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be separate storage structures. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be the same storage structure. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 701 and code and / or data storage 705 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0120] In at least one embodiment, logic 715 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 710 (including integer and / or floating-point units) for performing logical and / or mathematical operations at least in part based on training and / or inference code (e.g., graph code) or as instructed thereto, the results of which may produce activations (e.g., output values ​​from layers or neurons within a neural network) stored in activation storage 720, which are functions of input / output and / or weight parameter data stored in code and / or data storage 701 and / or code and / or data storage 705. In at least one embodiment, activation is activated in response to execution instructions or other code, and linear algebraic and / or matrix-based mathematical generation performed by ALU 710 is stored in activation storage 720, wherein weight values ​​stored in code and / or data storage 705 and / or code and / or data storage 701 are used as operands with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, and any or all of these can be stored in code and / or data storage 705 or code and / or data storage 701 or other on-chip or off-chip storage.

[0121] In at least one embodiment, one or more processors or other hardware logic devices or circuits include one or more ALUs 710, while in another embodiment, one or more ALUs 710 may be located outside the processor or other hardware logic device or the circuitry that uses them (e.g., a coprocessor). In at least one embodiment, one or more ALUs 710 may be included within an execution unit of a processor, or otherwise included in a group of ALUs accessible by the execution unit of the processor, which may be within the same processor or distributed among different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed-function unit, etc.). In at least one embodiment, code and / or data storage 701, code and / or data storage 705, and activation storage 720 may share a processor or other hardware logic device or circuitry, while in another embodiment, they may be located in different processors or other hardware logic devices or circuitry, or in some combination of the same and different processors or other hardware logic devices or circuitry. In at least one embodiment, any portion of activation storage 720 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be retrieved and / or processed using the processor’s fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0122] In at least one embodiment, the active memory 720 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the active memory 720 may be wholly or partially located inside or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the active memory 720 is internal to or external to the processor may depend on the availability of on-chip or off-chip storage, the latency requirements for training and / or inference functions, the batch size of the data used in inference and / or training the neural network, or some combination of these factors. For example, it may include DRAM, SRAM, flash memory, or other memory types.

[0123] In at least one embodiment, Figure 7A The logic 715 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as those from Google. Processing unit, from Graphcore TM Inference processing units (IPUs) or from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 7A The logic 715 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate array (“FPGA”)

[0124] Figure 7B A logic 715 according to at least one embodiment is illustrated. In at least one embodiment, the logic 715 is inference and / or training logic. In at least one embodiment, the logic 715 may include, but is not limited to, hardware logic, wherein computational resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 7B The logic 715 shown can be used in conjunction with application-specific integrated circuits (ASICs), such as those from Google. Processing unit, from Graphcore TM Inference processing units (IPUs) or from Intel Corp. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 7BThe logic 715 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field-programmable gate array (FPGA)). In at least one embodiment, logic 715 includes, but is not limited to, code and / or data storage 701 and code and / or data storage 705, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 7B In at least one embodiment shown, each of code and / or data storage 701 and code and / or data storage 705 is associated with dedicated computing resources (e.g., computing hardware 702 and computing hardware 706), respectively. In at least one embodiment, each of computing hardware 702 and computing hardware 706 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) only on the information stored in code and / or data storage 701 and code and / or data storage 705, respectively, and the results of the function execution are stored in activation storage 720.

[0125] In at least one embodiment, each of the code and / or data storage 701 and 705 and the corresponding computing hardware 702 and 706 corresponds to a different layer of the neural network, such that activation obtained from one “store / computation pair 701 / 702” of the code and / or data storage 701 and computing hardware 702 provides input as input to the next “store / computation pair 705 / 706” of the code and / or data storage 705 and computing hardware 706, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each store / computation pair 701 / 702 and 705 / 706 may correspond to more than one neural network layer. In at least one embodiment, additional store / computation pairs (not shown) may be included in logic 715 after or in parallel with the store / computation pairs 701 / 702 and 705 / 706.

[0126] Neural network training and deployment

[0127] Figure 8Training and deployment of a deep neural network according to at least one embodiment are illustrated. In at least one embodiment, an untrained neural network 806 is trained using a training dataset 802. In at least one embodiment, the training framework 804 is the PyTorch framework, while in other embodiments, the training framework 804 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 804 trains the untrained neural network 806 and enables it to be trained using the processing resources described herein to generate a trained neural network 808. In at least one embodiment, the weights may be randomly selected or pre-trained using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0128] In at least one embodiment, supervised learning is used to train an untrained neural network 806, wherein the training dataset 802 includes inputs paired with desired outputs for input, or wherein the training dataset 802 includes inputs with known outputs and the outputs of the untrained neural network 806 are manually graded. In at least one embodiment, the untrained neural network 806 is trained in a supervised manner, and inputs from the training dataset 802 are processed, and the resulting outputs are compared with a desired or desired set of outputs. In at least one embodiment, errors are then propagated back through the untrained neural network 806. In at least one embodiment, a training framework 804 adjusts the weights controlling the untrained neural network 806. In at least one embodiment, the training framework 804 includes tools for monitoring the degree to which the untrained neural network 806 converges to a model (e.g., a trained neural network 808) adapted to generate the correct answer (e.g., result 814) based on input data (e.g., a new dataset 812). In at least one embodiment, the training framework 804 repeatedly trains the untrained neural network 806 while adjusting the weights to improve the output of the untrained neural network 806 using a loss function and tuning algorithm (e.g., stochastic gradient descent). In at least one embodiment, the training framework 804 trains the untrained neural network 806 until the untrained neural network 806 reaches the desired accuracy. In at least one embodiment, the trained neural network 808 can then be deployed to implement any number of machine learning operations.

[0129] In at least one embodiment, unsupervised learning is used to train an untrained neural network 806, wherein the untrained neural network 806 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 802 will include input data without any associated output data or “benchmark real” data. In at least one embodiment, the untrained neural network 806 can learn groupings within the training dataset 802 and can determine how each input relates to the untrained dataset 802. In at least one embodiment, unsupervised training can be used to generate a self-organizing graph in a trained neural network 808, which is capable of performing operations useful for reducing the dimensionality of a new dataset 812. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in the new dataset 812 that deviate from the normal patterns of the new dataset 812.

[0130] In at least one embodiment, semi-supervised learning can be used, a technique in which a mixture of labeled and unlabeled data is included in the training dataset 802. In at least one embodiment, the training framework 804 can be used to perform incremental learning, for example, via a pass-through learning technique. In at least one embodiment, incremental learning enables the trained neural network 808 to adapt to a new dataset 812 without forgetting the knowledge injected into the trained neural network 808 during initial training.

[0131] In at least one embodiment, the training framework 804 is a framework processed by a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit such as that developed by Intel Corporation, Santa Clara, California. In at least one embodiment, OpenVINO includes or uses logic 715 to perform the operations described herein. In at least one embodiment, a SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0132] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications for various tasks and operations, particularly neural network applications, such as human visual simulation, speech recognition, natural language processing, recommender systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variations thereof.

[0133] In at least one embodiment, OpenVINO supports neural network models for a variety of tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., people and / or objects), monocular depth estimation, image inpainting, style transfer, action recognition, colorization, and / or variations thereof.

[0134] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as model optimizers. In at least one embodiment, the model optimizer is a command-line tool that facilitates the transition between training and deployment of a neural network model. In at least one embodiment, the model optimizer optimizes the neural network model for execution on various devices and / or processing units, such as GPUs, CPUs, PPUs, GPGPUs, and / or variants thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes model layers used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying the model's input (e.g., adjusting the size of the model's input), modifying the size of the model's input (e.g., modifying the model's batch size), modifying the model's structure (e.g., modifying the model's layers), normalizing, standardizing, quantizing (e.g., converting the model's weights from a first representation such as floating-point to a second representation such as integers), and / or variants thereof.

[0135] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as inference engines. In at least one embodiment, the inference engine is a C++ library or any suitable programming language library. In at least one embodiment, the inference engine is used to infer input data. In at least one embodiment, the inference engine implements various classes to infer input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions to process intermediate representations, set input and / or output formats, and / or execute models on one or more devices.

[0136] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computational processes and / or systems utilizing one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or portions of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, such as running a first portion of code on a CPU and a second portion of code on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., a first set of layers on a first device such as a GPU and a second set of layers on a second device such as a CPU).

[0137] In at least one embodiment, OpenVINO includes various functionalities similar to those associated with CUDA programming models, such as various neural network model operations associated with frameworks like TensorFlow, PyTorch, and / or variants thereof. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0138] Data Center

[0139] Figure 9 An example data center 900 that can be used with at least one embodiment is shown. In at least one embodiment, the data center 900 includes a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0140] In at least one embodiment, such as Figure 9As shown, the data center infrastructure layer 910 may include a resource coordinator 912, packet computing resources 914, and node computing resources (“nodes CR”) 916(1)-916(N), where “N” represents a positive integer (which may be an integer “N” different from the integers used in other diagrams). In at least one embodiment, nodes CR 916(1)-916(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 918(1)-918(N) (e.g., dynamic read-only memory, solid-state drives, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 916(1)-916(N) may be servers having one or more of the aforementioned computing resources.

[0141] In at least one embodiment, the grouped computing resource 914 may include individual groups (not shown) of node CRs housed within one or more racks, or a plurality of racks (also not shown) housed within data centers in various geographical locations. In at least one embodiment, the individual groups of node CRs within the grouped computing resource 914 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0142] In at least one embodiment, resource coordinator 912 may configure or otherwise control one or more nodes CR916(1)-916(N) and / or grouped computing resources 914. In at least one embodiment, resource coordinator 912 may include a Software Design Infrastructure (“SDI”) management entity for data center 900. In at least one embodiment, resource coordinator 912 may include hardware, software, or some combination thereof.

[0143] In at least one embodiment, such as Figure 9As shown, framework layer 920 includes a job scheduler 922, a configuration manager 924, a resource manager 926, and a distributed file system 928. In at least one embodiment, framework layer 920 may include a framework of software 932 supporting software layer 930 and / or one or more applications 942 supporting application layer 940. In at least one embodiment, software 932 or application 942 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 920 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark, which can utilize distributed file system 928 for large-scale data processing (e.g., "big data"). TM (Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 932 may include a Spark driver to facilitate the scheduling of workloads supported by various layers of the data center 900. In at least one embodiment, the configuration manager 924 may be able to configure different layers, such as the software layer 930 and the framework layer 920, which includes Spark and a distributed file system 928 for supporting large-scale data processing. In at least one embodiment, the resource manager 926 is able to manage cluster or group computing resources mapped to or allocated to support the distributed file system 928 and the job scheduler 922. In at least one embodiment, the cluster or group computing resources may include group computing resources 914 on the data center infrastructure layer 910. In at least one embodiment, the resource manager 926 may coordinate with the resource coordinator 912 to manage these mapped or allocated computing resources.

[0144] In at least one embodiment, the software 932 included in the software layer 930 may include software used by at least a portion of the nodes CR916(1)-916(N), the grouped computing resources 914, and / or the distributed file system 928 of the framework layer 920. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0145] In at least one embodiment, one or more applications 942 included in application layer 940 may include one or more types of applications used by at least a portion of nodes CR916(1)-916(N), grouped computing resources 914, and / or the distributed file system 928 of framework layer 920. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0146] In at least one embodiment, any of the configuration manager 924, resource manager 926, and resource coordinator 912 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 900 and can prevent underutilization and / or poor performance of the data center.

[0147] In at least one embodiment, data center 900 may include tools, services, software, or other resources to train one or more machine learning models or to use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 900. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 900 by using weight parameters calculated through one or more training techniques described herein.

[0148] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0149] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7BDetails regarding logic 715 are provided. In at least one embodiment, logic 715 can be in the system. Figure 9 Used in this context for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0150] In at least one embodiment, with the Figure 1 The corresponding embodiments include one or more processors, circuits, or systems that cause the selection of one or more data streams to run inference using one or more machine learning models, at least in part based on heuristic information and user-defined parameters.

[0151] Autonomous vehicles

[0152] Figure 10A An example of an autonomous vehicle 1000 according to at least one embodiment is shown. In at least one embodiment, the autonomous vehicle 1000 (which may alternatively be referred to herein as "vehicle 1000") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle capable of accommodating one or more passengers. In at least one embodiment, vehicle 1000 may be a semi-tractor-trailer for hauling goods. In at least one embodiment, vehicle 1000 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0153] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation in their standard “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of this standard). In at least one embodiment, vehicle 1000 may be able to function according to one or more of the levels of autonomous driving from Level 1 to Level 5. For example, in at least one embodiment, vehicle 1000 may be able to perform conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5).

[0154] In at least one embodiment, vehicle 1000 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1000 may include, but is not limited to, propulsion system 1050, such as an internal combustion engine, a hybrid electric unit, a fully electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1050 may be connected to the drivetrain of vehicle 1000, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 1000. In at least one embodiment, propulsion system 1050 may be controlled in response to receiving a signal from throttle / accelerator 1052.

[0155] In at least one embodiment, when the propulsion system 1050 is operating (e.g., when the vehicle 1000 is traveling), the steering system 1054 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 1000 (e.g., along a desired path or route). In at least one embodiment, the steering system 1054 may receive signals from the steering actuator 1056. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, the brake sensor system 1046 may be used to operate the vehicle brakes in response to signals received from the brake actuator 1048 and / or brake sensors.

[0156] In at least one embodiment, the controller 1036 may include, but is not limited to, one or more system-on-chips (“SoCs”). Figure 10AA controller 1036 (not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1000. For example, in at least one embodiment, controller 1036 may send signals to operate vehicle braking via brake actuator 1048, to operate steering system 1054 via one or more steering actuators 1056, and to operate propulsion system 1050 via one or more throttles / accelerators 1052. In at least one embodiment, one or more controllers 1036 may include one or more onboard (e.g., integrated) computing devices that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a driver in driving vehicle 1000. In at least one embodiment, one or more controllers 1036 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the functions described above, and two or more controllers may handle a single function and / or any combination thereof.

[0157] In at least one embodiment, one or more controllers 1036 provide signals for controlling one or more components and / or systems of vehicle 1000 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data can be received from sensors, including but not limited to one or more Global Navigation Satellite System (“GNSS”) sensors 1058 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1060, one or more ultrasonic sensors 1062, one or more LIDAR sensors 1064, one or more inertial measurement unit (IMU) sensors 1066 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1096, one or more stereo cameras 1068, one or more wide-angle cameras 1070 (e.g., fisheye cameras), one or more infrared cameras 1072, one or more surround cameras 1074 (e.g., 360-degree cameras), and remote cameras (…). Figure 10A (not shown in the image), medium-range camera ( Figure 10A(Not shown in the image) One or more speed sensors 1044 (e.g., for measuring the speed of vehicle 1000), one or more vibration sensors 1042, one or more steering sensors 1040, one or more brake sensors (e.g., as part of brake sensor system 1046) and / or other sensor types are received.

[0158] In at least one embodiment, one or more controllers 1036 may receive input (e.g., represented by input data) from the dashboard 1032 of the vehicle 1000 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1034, a voice signaler, a speaker, and / or other components of the vehicle 1000. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 10A The HMI display 1034 may display information such as (not shown in the image), location data (e.g., the location of vehicle 1000, for example on a map), direction, the location of other vehicles (e.g., occupancy raster), information about objects, and the state of objects sensed by one or more controllers 1036. For example, in at least one embodiment, the HMI display 1034 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving operations that the vehicle has already made, is making, or will make (e.g., changing lanes now, exiting exit 34B within two miles, etc.).

[0159] In at least one embodiment, the vehicle 1000 also includes a network interface 1024, which can communicate over one or more networks using one or more wireless antennas 1026 and / or one or more modems. For example, in at least one embodiment, the network interface 1024 may be able to communicate over Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1026 may also enable communication between objects in the environment (e.g., vehicles, mobile devices) using one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (hereinafter referred to as “LPWAN”) (e.g., LoRaWAN, SigFox, etc. protocols).

[0160] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 can be in the system. Figure 10A The operation is used to infer or predict the operation based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0161] In at least one embodiment, with the Figure 1 The corresponding embodiments include one or more processors, circuits, or systems that cause the selection of one or more data streams to run inference using one or more machine learning models, at least in part based on heuristic information and user-defined parameters.

[0162] Figure 10B The illustration shows an embodiment according to at least one of the embodiments. Figure 10A Examples of camera positions and fields of view for an autonomous vehicle 1000. In at least one embodiment, the camera and its respective field of view are exemplary embodiments and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 1000.

[0163] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for use with components and / or systems of vehicle 1000. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc. In at least one embodiment, the camera may be able to use a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-to-clear (“RCCC”) color filter array, a red-to-clear-blue (“RCCB”) color filter array, a red-blue-green (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera with an array of RCCC, RCCB and / or RBGC color filters, may be used to improve photosensitivity.

[0164] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0165] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (3D-printed) assembly, to cut out stray light and reflections within the vehicle 1000 (e.g., reflections from the dashboard in the windshield mirror), which may interfere with the camera's image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D-printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated within four pillars at each corner of the cabin.

[0166] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including a portion of the environment in front of the vehicle 1000 can be used for surround view and, with the assistance of one or more controllers 1036 and / or control SoCs, to help identify forward paths and obstacles, thereby providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (e.g., traffic sign recognition).

[0167] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal-oxide-semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1070 can be used to sense objects entering from the periphery (e.g., pedestrians, people crossing the street, or bicycles). Although in Figure 10BOnly one wide-angle camera 1070 is shown; however, in other embodiments, the vehicle 1000 may have any number (including zero) of wide-angle cameras. In at least one embodiment, any number of remote cameras 1098 (e.g., a pair of remote stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, the remote camera 1098 can also be used for object detection and classification, as well as basic object tracking.

[0168] In at least one embodiment, any number of stereo cameras 1068 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1068 may include an integrated control unit comprising a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1000, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1068 may include, but are not limited to, a compact stereo vision sensor, which may include, but is not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from the vehicle 1000 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1068 may also be used in addition to those described herein.

[0169] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including a portion of the environment on the sides of the vehicle 1000 can be used for surround viewing, thereby providing information for creating and updating the occupied grid, and generating a side collision warning. For example, in at least one embodiment, a surround camera 1074 (e.g., such as...) Figure 10B The four surround cameras shown can be positioned on vehicle 1000. In at least one embodiment, one or more surround cameras 1074 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye lenses, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye lens cameras can be located at the front, rear, and sides of vehicle 1000. In at least one embodiment, vehicle 1000 can use three surround cameras 1074 (e.g., left, right, and rear) and can utilize one or more other cameras (e.g., forward-facing cameras) as a fourth surround-view camera.

[0170] In at least one embodiment, a camera (e.g., a rear-view camera) having a field of view including a portion of the environment behind the vehicle 1000 can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy raster. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1098 and / or one or more mid-range cameras 1076, one or more stereo cameras 1068, one or more infrared cameras 1072, etc.), as described herein.

[0171] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Combined with Figure 7A and / or Figure 7B This document provides details regarding logic 715. In at least one embodiment, logic 715 can... Figure 10B Used in systems for reasoning or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0172] In at least one embodiment, with the Figure 1 The corresponding embodiments include one or more processors, circuits, or systems that cause the selection of one or more data streams to run inference using one or more machine learning models, at least in part based on heuristic information and user-defined parameters.

[0173] Figure 10C The illustration shows an embodiment according to at least one of the embodiments. Figure 10A A block diagram of an example system architecture for an autonomous vehicle 1000. In at least one embodiment, Figure 10C Each of one or more components, one or more features, and one or more systems of vehicle 1000 is shown as connected via bus 1002. In at least one embodiment, bus 1002 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as “CAN bus”). In at least one embodiment, CAN may be a network within vehicle 1000 used to help control various features and functions of vehicle 1000, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In one embodiment, bus 1002 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 1002 can be read to find steering wheel angle, ground speed, engine rotation speed (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1002 may be an ASIL B compliant CAN bus.

[0174] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or from CAN. In at least one embodiment, there may be any number of molded buses 1002, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for a collision avoidance function, and a second bus may be used for actuation control. In at least one embodiment, each of any number of System-on-Chip (“SoC”) 1004 (e.g., SoC 1004(A) and SoC 1004(B)), each of one or more controllers 1036, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of the vehicle 1000) and may be connected to a common bus, such as a CAN bus.

[0175] In at least one embodiment, vehicle 1000 may include one or more controllers 1036, such as those described herein. Figure 10A As described above. In at least one embodiment, controller 1036 can be used for a variety of functions. In at least one embodiment, controller 1036 can be coupled to any of various other components and systems of vehicle 1000 and can be used to control vehicle 1000, artificial intelligence of vehicle 1000, infotainment and / or other functions of vehicle 1000.

[0176] In at least one embodiment, vehicle 1000 may include any number of SoCs 1004. In at least one embodiment, each of the SoCs 1004 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1006, a graphics processing unit (“one or more GPUs”) 1008, one or more processors 1010, one or more caches 1012, one or more accelerators 1014, one or more data storage 1016, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1004 may be used to control vehicle 1000 on various platforms and systems. For example, in at least one embodiment, one or more SoCs 1004 may be combined with a high-definition (“HD”) map 1022 in a system (e.g., the system of vehicle 1000), the high-definition map 1022 being accessible from one or more servers via a network interface 1024. Figure 10C (Not shown in the image) Get map refresh and / or update.

[0177] In at least one embodiment, one or more CPUs 1006 may include CPU clusters or CPU complexes (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1006 may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPUs 1006 may include eight cores in an intercoupled multiprocessor configuration. In at least one embodiment, one or more CPUs 1006 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., 2MB L2 cache). In at least one embodiment, one or more CPUs 1006 (e.g., CCPLEX) may be configured to support simultaneous cluster operation, such that any combination of clusters of one or more CPUs 1006 can be active at any given time.

[0178] In at least one embodiment, one or more CPUs 1006 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware modules to conserve dynamic power when idle; clock gating of each core when the core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Event Wait (“WFE”) instructions; independent power supply for each core; clock gating of each core cluster when all cores are clock-gated or power-gated; and / or power gating of each core cluster when all cores are power-gated. In at least one embodiment, one or more CPUs 1006 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state for cores, clusters, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified power state input sequence in software, wherein the work is offloaded to the microcode.

[0179] In at least one embodiment, one or more GPUs 1008 may include integrated GPUs (or "iGPUs" herein). In at least one embodiment, one or more GPUs 1008 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1008 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1008 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 ("L1") cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512KB of storage capacity). In at least one embodiment, one or more GPUs 1008 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1008 may use a computation application programming interface (API). In at least one embodiment, one or more GPUs 1008 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0180] In at least one embodiment, one or more GPUs 1008 may be power-optimized for optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPUs 1008 may be fabricated on a FinFET (“FinFET”) circuit. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores divided into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a scheduler (e.g., a thread bundle scheduler) or sequencer, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include separate parallel integer and floating-point data paths to provide efficient execution of workloads that combine computation and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0181] In at least one embodiment, one or more GPUs 1008 may include high-bandwidth memory (“HBM”) and / or a 16GB HBM2 memory subsystem to provide a peak storage bandwidth of approximately 900GB / s in some examples. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”) may be used, such as graphics double data rate type five synchronous random access memory (“GDDR5”).

[0182] In at least one embodiment, one or more GPUs 1008 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support may be used to allow one or more GPUs 1008 to directly access the page tables of one or more CPUs 1006. In at least one embodiment, when a memory management unit (“MMU”) of one or more GPUs 1008 experiences a miss, an address translation request may be sent to one or more CPUs 1006. In response, in at least one embodiment, two CPUs of one or more CPUs 1006 may look up the virtual-physical mapping of the address in their page tables and transfer the translation back to one or more GPUs 1008. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for the memory of both one or more CPUs 1006 and one or more GPUs 1008, thereby simplifying the programming of one or more GPUs 1008 and the porting of applications to one or more GPUs 1008.

[0183] In at least one embodiment, one or more GPUs 1008 may include any number of access counters that can track the frequency of memory accesses by one or more GPUs 1008 to other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of shared memory ranges between processors.

[0184] In at least one embodiment, one or more SoCs 1004 may include any number of caches 1012, including those described herein. For example, in at least one embodiment, one or more caches 1012 may include a Level 3 (“L3”) cache available for one or more CPUs 1006 and one or more GPUs 1008 (e.g., connected to CPUs 1006 and GPUs 1008). In at least one embodiment, one or more caches 1012 may include a write-back cache that can, for example, track the state of a line using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, according to an embodiment, the L3 cache may include 4 MB of memory or more.

[0185] In at least one embodiment, one or more SoCs 1004 may include one or more accelerators 1014 (e.g., hardware accelerators, software accelerators, or combinations thereof). In at least one embodiment, one or more SoCs 1004 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1008 and offload some tasks from one or more GPUs 1008 (e.g., freeing up more cycles from one or more GPUs 1008 to perform other tasks). In at least one embodiment, one or more accelerators 1014 may be used for target workloads that are sufficiently stable to withstand acceleration testing (e.g., perceptual, convolutional neural networks (“CNN”), recurrent neural networks (“RNN”), etc.). In at least one embodiment, the CNN may include region-based or region convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0186] In at least one embodiment, one or more accelerators 1014 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more Tensor Processing Units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, quickly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphones; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for safety and / or safety-related events.

[0187] In at least one embodiment, the DLA can perform any function of one or more GPUs 1008, and by using inference accelerators, for example, the designer can target one or more DLAs or one or more GPUs 1008 for any function. For example, in at least one embodiment, the designer can concentrate the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 1008 and / or one or more accelerators 1014.

[0188] In at least one embodiment, one or more accelerators 1014 may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1038, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0189] In at least one embodiment, the RISC core can interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, the RISC core may use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or storage devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0190] In at least one embodiment, DMA enables components of the PVA to access system memory independently of one or more CPUs 1006. In at least one embodiment, DMA can support any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0191] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may serve as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0192] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute general-purpose computer vision algorithms, except on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on a single image, or even execute different algorithms on a sequence of images or portions of images. In at least one embodiment, among others, any number of PVAs may be included in the hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error-correcting code (“ECC”) memory to enhance overall system security.

[0193] In at least one embodiment, one or more accelerators 1014 may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 1014. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone providing high-speed access to the memory for both the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0194] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0195] In at least one embodiment, one or more SoCs 1004 may include a real-time eye-tracking hardware accelerator. In at least one embodiment, the real-time eye-tracking hardware accelerator may be used to quickly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0196] In at least one embodiment, one or more accelerators 1014 have broad applications for autonomous driving. In at least one embodiment, PVA can be used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVA with low power consumption and low latency are well-matched to algorithmic domains requiring predictable processing. In other words, PVA performs well in semi-intensive or intensive conventional computations, even on small datasets that may require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in vehicle 1000, PVA may be designed to run classic computer vision algorithms, as they are efficient in object detection and integer mathematical operations.

[0197] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching during operation (e.g., structure recovery from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0198] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0199] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks whose output is used for a confidence score for each object detection. In at least one embodiment, the confidence score can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. In at least one embodiment, the confidence score measurement enables the system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score value. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, acquired ground plane estimate (e.g., from another subsystem), and outputs of one or more IMU sensors 1066 related to the vehicle 1000 orientation, distance, and 3D position estimate of the object acquired from the neural network and / or other sensors (e.g., one or more LiDAR sensors 1064 or one or more RADAR sensors 1060).

[0200] In at least one embodiment, one or more SoCs 1004 may include one or more data storage devices 1016 (e.g., memory). In at least one embodiment, one or more data storage devices 1016 may be on-chip memory of one or more SoCs 1004, which may store neural networks to be executed on one or more GPUs 1008 and / or DLAs. In at least one embodiment, one or more data storage devices 1016 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data storage devices 1016 may include L2 or L3 caches.

[0201] In at least one embodiment, one or more SoCs 1004 may include any number of processors 1010 (e.g., embedded processors). In at least one embodiment, one or more processors 1010 may include a startup and power management processor, which may be a dedicated processor and subsystem for handling startup power and management functions, as well as associated security implementations. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 1004s and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 1004s, and / or power state management of one or more SoCs 1004s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 1004s may use the ring oscillator to detect the temperature of one or more CPUs 1006s, one or more GPUs 1008s, and / or one or more accelerators 1014s. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 1004s into a lower power state and / or place the vehicle 1000 into a driver's safe stopping pattern (e.g., bring the vehicle 1000 to a safe stop).

[0202] In at least one embodiment, one or more processors 1010 may further include a set of embedded processors that can serve as an audio processing engine. The audio processing engine may be an audio subsystem capable of providing full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor having dedicated RAM.

[0203] In at least one embodiment, one or more processors 1010 may also include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processor on the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, peripheral support (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0204] In at least one embodiment, one or more processors 1010 may further include a secure clustering engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the secure clustering engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1010 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1010 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0205] In at least one embodiment, one or more processors 1010 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by the video playback application to generate the final video for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1070, one or more surround cameras 1074, and / or one or more cabin monitoring camera sensors. In at least one embodiment, preferably, the cabin monitoring camera sensors are monitored by a neural network running on another instance of SoC 1004, the neural network being configured to recognize cabin events and respond accordingly. In at least one embodiment, the cabin system may perform, but is not limited to, lip reading to activate cellular service and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, and are otherwise disabled.

[0206] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for simultaneous spatial and temporal denoising. For example, in at least one embodiment, when motion occurs in the video, denoising appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, when the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0207] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereo lens frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing and does not require one or more GPUs 1008 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1008 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 1008 to improve performance and responsiveness.

[0208] In at least one embodiment, one or more SoCs of SoC 1004 may also include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs of SoC 1004 may also include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0209] In at least one embodiment, one or more SoCs of SoC 1004 may also include extensive peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. In at least one embodiment, one or more SoCs of SoC 1004 may be used to process data from (e.g., connected via gigabit multimedia serial links and Ethernet channels) cameras, sensors (e.g., one or more LiDAR sensors 1064, one or more RADAR sensors 1060, etc., which may be connected via Ethernet channels), data from bus 1002 (e.g., vehicle 1000 speed, steering wheel position, etc.), data from one or more GNSS sensors 1058 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more SoCs of SoC 1004 may also include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to free one or more CPUs of SoC 1006 from routine data management tasks.

[0210] In at least one embodiment, one or more SoCs 1004 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy. This provides a platform offering a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 1004 can be faster, more reliable, and even more energy and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1014, when combined with one or more CPUs 1006, one or more GPUs 1008, and one or more data storage devices 1016, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0211] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute multiple processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0212] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPU 1020s) may include text and word recognition, thereby allowing a supercomputer to read and understand traffic signs, including signs for which the neural network has not yet been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing semantic understanding of symbols, and passing this semantic understanding to a path planning module running on a CPU Complex.

[0213] In at least one embodiment, for drives of levels 3, 4, or 5, multiple neural networks can run simultaneously. For example, in at least one embodiment, a warning sign consisting of a light bulb accompanied by the warning sign “Caution: flashing lights indicate icy conditions” can be interpreted independently or jointly by multiple neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text “flashing lights indicate icy conditions” can be interpreted by a second deployed neural network, which informs the vehicle’s path planning software (preferably executed on the CPU Complex) that icing conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, informing the vehicle’s path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1008.

[0214] In at least one embodiment, the CNN for facial recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 1000. In at least one embodiment, a normally open sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves it. In this way, one or more SoCs 1004 provide protection against theft and / or carjacking.

[0215] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 1096 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1004 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles in the area where the vehicle is operating, as identified by one or more GNSS sensors 1058. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1062, to execute emergency vehicle safety routines, slow the vehicle, pull the vehicle to the side of the road, stop, and / or leave the vehicle idle until the emergency vehicle passes.

[0216] In at least one embodiment, vehicle 1000 may include one or more CPUs 1018 (e.g., one or more discrete CPUs or one or more dCPUs) coupled to one or more SoCs 1004 via high-speed interconnects (e.g., PCIe). In at least one embodiment, one or more CPUs 1018 may include x86 processors, and one or more CPUs 1018 may be used to perform any of a variety of functions, such as arbitrating the results of potential inconsistencies between ADAS sensors and one or more SoCs 1004, and / or monitoring the status and health of one or more monitoring controllers 1036 and / or on-chip information systems (“information SoCs”) 1030. In at least one embodiment, one or more SoCs 1004 include one or more interconnects, and the interconnects may include high-speed peripheral component interconnects (PCIe).

[0217] In at least one embodiment, vehicle 1000 may include one or more GPUs 1020 (e.g., one or more discrete GPUs or one or more dGPUs) coupled to one or more SoCs 1004 via high-speed interconnects (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 1020 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on inputs from sensors of vehicle 1000 (e.g., sensor data).

[0218] In at least one embodiment, vehicle 1000 may also include a network interface 1024, which may include, but is not limited to, one or more wireless antennas 1026 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1024 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., passenger client devices) via Internet cloud services (e.g., using servers and / or other network devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and the Internet) may be established between vehicle 1000 and another vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1000 with information about vehicles near vehicle 1000 (e.g., vehicles in front, to the side, and / or behind vehicle 1000). In at least one embodiment, the foregoing functionality may be part of a cooperative adaptive cruise control function of vehicle 1000.

[0219] In at least one embodiment, network interface 1024 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 1036 to communicate over a wireless network. In at least one embodiment, network interface 1024 may include a radio frequency (RF) front-end for up-conversion from baseband to RF and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed using known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0220] In at least one embodiment, the vehicle 1000 may also include one or more data storage units 1028, which may include, but are not limited to, off-chip (e.g., one or more SoC 1004) storage. In at least one embodiment, the one or more data storage units 1028 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk and / or other components and / or devices capable of storing at least one bit of data.

[0221] In at least one embodiment, the vehicle 1000 may also include one or more GNSS sensors 1058 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1058 may be used, including, for example, but not limited to, GPS sensors connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0222] In at least one embodiment, vehicle 1000 may also include one or more RADAR sensors 1060. In at least one embodiment, one or more RADAR sensors 1060 may be used by vehicle 1000 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 1060 may use a CAN bus and / or bus 1002 (e.g., to transmit data generated by one or more RADAR sensors 1060) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 1060 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 1060 are pulse Doppler RADAR sensors.

[0223] In at least one embodiment, one or more RADAR sensors 1060 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 250m range). In at least one embodiment, one or more RADAR sensors 1060 can help distinguish between stationary and moving objects and can be used by the ADAS system 1038 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1060 included in the long-range RADAR system may include, but are not limited to, a monostatic multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas, can create a focused beammap designed to record the vehicle 1000's surroundings at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling rapid detection of vehicles 1000 entering or leaving the lane.

[0224] In at least one embodiment, as an example, a mid-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1060 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rearward direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system may be used in ADAS system 1038 for blind spot detection and / or lane change assistance.

[0225] In at least one embodiment, the vehicle 1000 may also include one or more ultrasonic sensors 1062. In at least one embodiment, one or more ultrasonic sensors 1062, which may be positioned at the front, rear, and / or sides of the vehicle 1000, may be used for parking assistance and / or creating and updating occupancy detectors. In at least one embodiment, a wide variety of ultrasonic sensors 1062 may be used, and different ultrasonic sensors 1062 may be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 1062 may operate at the ASIL B functional safety level.

[0226] In at least one embodiment, vehicle 1000 may include one or more LiDAR sensors 1064. In at least one embodiment, one or more LiDAR sensors 1064 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LiDAR sensors 1064 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1000 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 1064 that can use Ethernet channels (e.g., providing data to a Gigabit Ethernet switch).

[0227] In at least one embodiment, one or more LiDAR sensors 1064 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 1064 may, for example, have an advertising range of approximately 100m, an accuracy of 2cm-3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors may be used. In such embodiments, one or more LiDAR sensors 1064 may include small devices that can be embedded in the front, rear, side, and / or corner locations of a vehicle 1000. In at least one embodiment, one or more LiDAR sensors 1064, in such embodiments, can provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, one or more forward-facing LiDAR sensors 1064 may be configured for a horizontal field of view between 45 degrees and 105 degrees.

[0228] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200m around vehicle 1000. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and reflected light on each pixel, which in turn corresponds to the range from vehicle 1000 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of vehicle 1000. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture reflected laser light as a 3D ranging point cloud and co-registered intensity data.

[0229] In at least one embodiment, vehicle 1000 may further include one or more IMU sensors 1066. In at least one embodiment, one or more IMU sensors 1066 may be located at the center of the rear axle of vehicle 1000. In at least one embodiment, one or more IMU sensors 1066 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, a magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1066 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1066 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0230] In at least one embodiment, one or more IMU sensors 1066 may be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide position, velocity, and attitude estimations; in at least one embodiment, one or more IMU sensors 1066 may enable vehicle 1000 to estimate heading without input from a magnetic sensor obtained by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1066. In at least one embodiment, one or more IMU sensors 1066 and one or more GNSS sensors 1058 may be combined in a single integrated unit.

[0231] In at least one embodiment, vehicle 1000 may include one or more microphones 1096 placed inside and / or around vehicle 1000. In at least one embodiment, in addition, one or more microphones 1096 may be used for emergency vehicle detection and identification.

[0232] In at least one embodiment, vehicle 1000 may also include any number of camera types, including one or more stereo cameras 1068, one or more wide-angle cameras 1070, one or more infrared cameras 1072, one or more surround cameras 1074, one or more long-range cameras 1098, one or more mid-range cameras 1076, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 1000. In at least one embodiment, the type of camera used depends on vehicle 1000. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 1000. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1000 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may be, by way of example but not limited to, supporting gigabit multimedia serial link (“GMSL”) and / or gigabit Ethernet communication. In at least one embodiment, previously referenced herein Figure 10A and Figure 10B Each camera can be described in more detail.

[0233] In at least one embodiment, the vehicle 1000 may also include one or more vibration sensors 1042. In at least one embodiment, the one or more vibration sensors 1042 can measure vibrations of components of the vehicle 1000 (e.g., axles). For example, in at least one embodiment, changes in vibration can indicate changes in road surface conditions. In at least one embodiment, when two or more vibration sensors 1042 are used, differences between vibrations can be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a free-rotating axle).

[0234] In at least one embodiment, vehicle 1000 may include ADAS system 1038. In at least one embodiment, ADAS system 1038 may include, but is not limited to, SoC. In at least one embodiment, ADAS system 1038 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions, and combinations thereof.

[0235] In at least one embodiment, the ACC system may use one or more RADAR sensors 1060, one or more LIDAR sensors 1064, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle adjacent to vehicle 1000 and automatically adjusts the speed of vehicle 1000 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance holding and suggests that vehicle 1000 change lanes when necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0236] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from other vehicles via network interface 1024 and / or one or more wireless antennas 1026 via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Typically, V2V communication provides information about the vehicle immediately preceding it (e.g., a vehicle immediately in front of vehicle 1000 and in the same lane as it), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles preceding vehicle 1000, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0237] In at least one embodiment, the FCW system is designed to warn the driver of a hazard so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1060, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to components providing driver feedback, such as a display, speaker, and / or vibration. In at least one embodiment, the FCW system can provide warnings, for example, in the form of audible, visual, haptic, and / or rapid braking pulses.

[0238] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply brakes if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system may automatically apply brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic braking to support and / or brakes for impending collisions.

[0239] In at least one embodiment, when vehicle 1000 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is inactive when the driver indicates intentional lane departure, such as by activating turn signals. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1000 begins to leave the lane, the LKA system provides steering input or braking to correct vehicle 1000.

[0240] In at least one embodiment, the BSW system detects and warns the driver of a vehicle in the blind spot. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses the turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback, such as a display, speaker, and / or vibration assembly.

[0241] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when an object is detected outside the range of the rear camera while the vehicle 1000 is reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure the vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as displays, speakers, and / or vibration components.

[0242] In at least one embodiment, conventional ADAS systems may be prone to generating false alarms, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems warn the driver and allow the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, vehicle 1000 itself decides whether to follow the result of the main computer or the auxiliary computer (e.g., the first or second controller of controller 1036). For example, in at least one embodiment, ADAS system 1038 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from ADAS system 1038 may be provided to a monitoring MCU. In at least one embodiment, if the output from the main computer and the output from the auxiliary computer conflict, the monitoring MCU decides how to reconcile the conflict to ensure safe operation.

[0243] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU to indicate the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflicting), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0244] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the auxiliary computer provides a false alarm based on outputs from a host computer and an auxiliary computer. In at least one embodiment, the neural network in the supervisory MCU may learn when the outputs of the auxiliary computer can be trusted and when they cannot. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, the neural network in the supervisory MCU may learn when the FCW system recognizes a metallic object that is not actually dangerous, such as a drain grating or manhole cover that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC 1004s.

[0245] In at least one embodiment, the ADAS system 1038 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of a neural network in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and different software code running on the auxiliary computer provides consistent overall results, the supervisory MCU can more confidently assume that the overall result is correct and that the vulnerability in the software or hardware on the host computer will not lead to a significant error.

[0246] In at least one embodiment, the output of the ADAS system 1038 can be input to the perception module and / or the dynamic driving task module of the host computer. For example, in at least one embodiment, if the ADAS system 1038 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when identifying the object. In at least one embodiment, as described herein, the assistance computer can have its own neural network trained to reduce the risk of false alarms.

[0247] In at least one embodiment, vehicle 1000 may also include an infotainment SoC 1030 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1030 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1030 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to vehicle 1000. For example, the infotainment SoC 1030 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, vehicle, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 1034, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 1030 may further be used to provide information (e.g., visual and / or auditory) to a user of vehicle 1000, such as information from ADAS system 1038, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0248] In at least one embodiment, the infotainment SoC 1030 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1030 may communicate with other devices, systems, and / or components of the vehicle 1000 via bus 1002. In at least one embodiment, the infotainment SoC 1030 may be coupled to a monitoring MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of the main controller 1036 (e.g., the main computer and / or backup computer of the vehicle 1000). In at least one embodiment, the infotainment SoC 1030 may cause the vehicle 1000 to enter a driver-to-safe-stop mode, as described herein.

[0249] In at least one embodiment, vehicle 1000 may also include instrument panel 1032 (e.g., digital instrument panel, electronic instrument panel, digital instrument control panel, etc.). In at least one embodiment, instrument panel 1032 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). In at least one embodiment, instrument panel 1032 may include, but is not limited to, any number and combination of a set of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1030 and instrument panel 1032. In at least one embodiment, instrument panel 1032 may be included as part of infotainment SoC 1030, or vice versa.

[0250] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 can be in the system. Figure 10C The operation is used to infer or predict the operation based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0251] In at least one embodiment, with the Figure 1 The corresponding embodiments include one or more processors, circuits, or systems that cause the selection of one or more data streams to run inference using one or more machine learning models, at least in part based on heuristic information and user-defined parameters.

[0252] Figure 10DIt is based on at least one embodiment in a cloud-based server and Figure 10A A diagram of a system 1076 for communication between autonomous vehicles 1000. In at least one embodiment, system 1076 may include, but is not limited to, one or more servers 1078, one or more networks 1090, and any number and type of vehicles, including vehicle 1000. In at least one embodiment, one or more servers 1078 may include, but is not limited to, multiple GPUs 1084(A)-1084(H) (collectively referred to herein as GPU 1084), PCIe switches 1082(A)-1082(D) (collectively referred to herein as PCIe switch 1082), and / or CPUs 1080(A)-1080(B) (collectively referred to herein as CPU 1080). GPU 1084, CPU 1080, and PCIe switch 1082 may be interconnected with high-speed connection cables, such as, but not limited to, NVLink interface 1088 developed by NVIDIA and / or PCIe connection 1086. In at least one embodiment, the GPU 1084 is connected via NVLink and / or NVSwitchSoC, and the GPU 1084 and PCIe switch 1082 are connected via PCIe interconnect. Although eight GPUs 1084, two CPUs 1080, and four PCIe switches 1082 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 1078 may include, but is not limited to, any combination of any number of GPUs 1084, CPUs 1080, and / or PCIe switches 1082. For example, in at least one embodiment, one or more servers 1078 may each include eight, sixteen, thirty-two, and / or more GPUs 1084.

[0253] In at least one embodiment, one or more servers 1078 may receive image data representing images from vehicles via one or more networks 1090, the images showing unexpected or changed road conditions, such as recently started roadworks. In at least one embodiment, one or more servers 1078 may transmit updated neural network 1092 and / or map information 1094, including but not limited to information about traffic and road conditions, to vehicles via one or more networks 1090. In at least one embodiment, updating the map information 1094 may include, but is not limited to, updating the HD map 1022, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, the neural network 1092 and / or map information 1094 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed in a data center (e.g., using one or more servers 1078 and / or other servers).

[0254] In at least one embodiment, one or more servers 1078 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1090), and / or the machine learning model may be used by one or more servers 1078 to remotely monitor the vehicle.

[0255] In at least one embodiment, one or more servers 1078 may receive data from the vehicle and apply the data to state-of-the-art real-time neural networks for real-time intelligent inference. In at least one embodiment, one or more servers 1078 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1084, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1078 may include a deep learning infrastructure in a data center using CPU power.

[0256] In at least one embodiment, the deep learning infrastructure of one or more servers 1078 may be capable of fast, real-time inference and can use this capability to assess and verify the health of the processor, software, and / or associated hardware in vehicle 1000. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1000, such as image sequences and / or objects located by vehicle 1000 in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1000, and if the results do not match and the deep learning infrastructure determines that the AI ​​in vehicle 1000 is malfunctioning, one or more servers 1078 may signal to vehicle 1000 to instruct the fail-safe computer of vehicle 1000 to take control, notify passengers, and complete a safe stopping operation.

[0257] In at least one embodiment, one or more servers 1078 may include one or more GPUs 1084 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration enables real-time response. In at least one embodiment, for example, where performance is less critical, servers driven by CPUs, FPGAs, and other processors may be used for inference. In at least one embodiment, hardware architecture 715 is used to execute one or more embodiments. This document incorporates... Figure 7A and / or Figure 7B Provide details about the hardware architecture of 715.

[0258] Computer System

[0259] Figure 11 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to this disclosure, such as the embodiments described herein, computer system 1100 may include, but is not limited to, components such as processor 1102, whose execution unit includes logic to execute algorithms for process data. In at least one embodiment, computer system 1100 may include a processor, such as those available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM A microprocessor may be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, computer system 1100 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0260] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0261] In at least one embodiment, computer system 1100 may include, but is not limited to, processor 1102, which may include, but is not limited to, one or more execution units 1108, to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1100 is a single-processor desktop or server system, but in another embodiment, computer system 1100 may be a multiprocessor system. In at least one embodiment, processor 1102 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1102 may be coupled to processor bus 1110, which can transmit data signals between processor 1102 and other components in computer system 1100.

[0262] In at least one embodiment, processor 1102 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1102. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 1106 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0263] In at least one embodiment, an execution unit 1108, including but not limited to logic for performing integer and floating-point operations, is also located within the processor 1102. In at least one embodiment, the processor 1102 may further include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, the execution unit 1108 may include logic for processing a packaged instruction set 1109. In at least one embodiment, by including the packaged instruction set 1109 in the instruction set of a general-purpose processor, along with the associated circuitry for executing the instructions, the packaged data in the processor 1102 can be used to perform operations used by numerous multimedia applications. In at least one embodiment, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor’s data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor’s data bus to perform one or more operations on one data element at a time.

[0264] In at least one embodiment, execution unit 1108 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1100 may include, but is not limited to, memory 1120. In at least one embodiment, memory 1120 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or another storage device. In at least one embodiment, memory 1120 may store instructions 1119 and / or data 1121 represented by data signals that can be executed by processor 1102.

[0265] In at least one embodiment, the system logic chip may be coupled to processor bus 1110 and memory 1120. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1116, and processor 1102 may communicate with MCH 1116 via processor bus 1110. In at least one embodiment, MCH 1116 may provide a high-bandwidth memory path 1118 to memory 1120 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1116 may initiate data signals between processor 1102, memory 1120, and other components in computer system 1100, and bridge data signals between processor bus 1110, memory 1120, and system I / O interface 1122. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1116 can be coupled to memory 1120 via high-bandwidth memory path 1118, and graphics / video card 1112 can be coupled to MCH 1116 via Accelerated Graphics Port (“AGP”) interconnect 1114.

[0266] In at least one embodiment, the computer system 1100 may use the system I / O interface 1122 as a proprietary hub interface bus to couple the MCH 1116 to the I / O controller hub (“ICH”) 1130. In at least one embodiment, the ICH 1130 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1120, chipset, and processor 1102. Examples may include, but are not limited to, an audio controller 1129, a firmware hub (“Flash BIOS”) 1128, a wireless transceiver 1126, a data storage 1124, a conventional I / O controller 1123 including a user input and keyboard interface, a serial expansion port 1127 (e.g., a Universal Serial Bus (USB) port), and a network controller 1134. In at least one embodiment, the data storage 1124 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0267] In at least one embodiment, Figure 11 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 11 The SoC can be shown. In at least one embodiment, Figure 11The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 1100 are interconnected using a Compute Fast Link (CXL) interconnect.

[0268] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 can be... Figure 11 Used in systems for reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0269] In at least one embodiment, with the Figure 1 The corresponding embodiments include one or more processors, circuits, or systems that cause the selection of one or more data streams to run inference using one or more machine learning models, at least in part based on heuristic information and user-defined parameters.

[0270] Figure 12 This is a block diagram illustrating an electronic device 1200 for utilizing a processor 1210 according to at least one embodiment. In at least one embodiment, the electronic device 1200 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0271] In at least one embodiment, the electronic device 1200 may include, but is not limited to, a processor 1210 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1210 is coupled using a bus or interface, such as I... 2 C-bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Accessory (“SATA”) bus, Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 12 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 12 An exemplary SoC can be shown. In at least one embodiment, Figure 12 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 12 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0272] In at least one embodiment, Figure 12 It may include a display 1224, a touch screen 1225, a touchpad 1230, a near field communication unit (“NFC”) 1245, a sensor hub 1240, a thermal sensor 1246, a fast chipset (“EC”) 1235, a trusted platform module (“TPM”) 1238, a BIOS / firmware / flash (“BIOS, FW Flash”) 1222, a DSP 1260, a drive 1220 (e.g., a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1250, a Bluetooth unit 1252, a wireless wide area network unit (“WWAN”) 1256, a global positioning system (GPS) unit 1255, a camera (“USB 3.0 camera”) 1254 (e.g., a USB 3.0 camera), and / or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1215 implemented in, for example, the LPDDR3 standard. These components can each be implemented in any suitable way.

[0273] In at least one embodiment, other components may be communicatively coupled to processor 1210 via the components described herein. In at least one embodiment, accelerometer 1241, ambient light sensor (“ALS”) 1242, compass 1243, and gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, thermal sensor 1239, fan 1237, keyboard 1236, and touchpad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, speaker 1263, earphone 1264, and microphone (“mic”) 1265 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1262, which in turn may be communicatively coupled to DSP 1260. In at least one embodiment, audio unit 1262 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1257 may be communicatively coupled to WWAN unit 1256. In at least one embodiment, components such as WLAN unit 1250, Bluetooth unit 1252, and WWAN unit 1256 can be implemented as next-generation form factor (NGFF).

[0274] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7BDetails regarding logic 715 are provided. In at least one embodiment, logic 715 may be used in system diagram 15 for reasoning or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0275] In at least one embodiment, with the Figure 1 The corresponding embodiments include one or more processors, circuits, or systems that cause the selection of one or more data streams to run inference using one or more machine learning models, at least in part based on heuristic information and user-defined parameters.

[0276] Figure 13 A computer system 1300 according to at least one embodiment is shown. In at least one embodiment, the computer system 1300 is configured to implement various processes and methods described throughout this disclosure.

[0277] In at least one embodiment, the computer system 1300 includes, but is not limited to, at least one central processing unit (“CPU”) 1302 connected to a communication bus 1310 implemented using any suitable protocol, such as PCI (“Peripheral Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1300 includes, but is not limited to, main memory 1304 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data may be stored in main memory 1304 in the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“Network Interface”) 1322 provides an interface to other computing devices and networks for receiving data using the computer system 1300 and transferring data to other systems.

[0278] In at least one embodiment, the computer system 1300 includes, but is not limited to, an input device 1308, a parallel processing system 1312, and a display device 1306, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”) display, plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1308 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein may reside on a single semiconductor platform to form the processing system.

[0279] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Provide details about reasoning and / or training logic 715.

[0280] In at least one embodiment, logic 715 can be in the system Figure 13 It is used to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture or neural network use cases described herein.

[0281] In at least one embodiment, with the Figure 1 The corresponding embodiments include one or more processors, circuits, or systems that cause the selection of one or more data streams to run inference using one or more machine learning models, at least in part based on heuristic information and user-defined parameters.

[0282] Figure 14 A computer system 1400 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1400 includes, but is not limited to, a computer 1410 and a USB flash drive 1420. In at least one embodiment, the computer 1410 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1410 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0283] In at least one embodiment, the USB flash drive 1420 includes, but is not limited to, a processing unit 1430, a USB interface 1440, and USB interface logic 1450. In at least one embodiment, the processing unit 1430 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1430 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1430 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1430 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1430 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0284] In at least one embodiment, the USB interface 1440 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1440 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1440 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1450 may include any amount and type of logic enabling the processing unit 1430 to connect to a device (e.g., computer 1410) via the USB connector 1440.

[0285] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 can be in the system. Figure 14 In use, at least in part, the operation is based on weight parameters, neural network functions and / or architectures computed using neural network training operations, or neural network use cases described herein to infer or predict operations.

[0286] In at least one embodiment, with the Figure 1 The corresponding embodiments include one or more processors, circuits, or systems that cause the selection of one or more data streams to run inference using one or more machine learning models, at least in part based on heuristic information and user-defined parameters.

[0287] Figure 15A An exemplary architecture is shown in which multiple GPUs 1510(1)-1510(N) are communicatively coupled to multiple multi-core processors 1505(1)-1505(M) via high-speed links 1540(1)-1540(N) (e.g., bus / point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1540(1)-1540(N) support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, “N” and “M” represent positive integers, and their values ​​may vary from figure to figure. In at least one embodiment, one or more of the multiple GPUs 1510(1)-1510(N) include one or more graphics cores (also simply referred to as “cores”) 1800, such as Figure 18A and Figure 18BAs disclosed in the literature. In at least one embodiment, one or more graphics cores 1800 may be referred to as a streaming multiprocessor (“SM”), streaming processor (“SP”), streaming processing unit (“SPU”), compute unit (“CU”), execution unit (“EU”), and / or slice, wherein a slice in this context may refer to a portion of the processing resources in a processing unit (e.g., 16 cores, ray tracing unit, thread director, or scheduler).

[0288] Furthermore, in one embodiment, two or more GPUs 1510 are interconnected via high-speed links 1529(1)-1529(2), which can be implemented using a protocol / link similar to or different from that used for high-speed links 1540(1)-1540(N). Similarly, two or more multi-core processors 1505 can be connected via high-speed link 1528, which can be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, similar protocols / links (e.g., via a common interconnect structure) can be used. Figure 15A This shows all communication between the various system components.

[0289] In at least one embodiment, each multi-core processor 1505 is communicatively coupled to processor memory 1501(1)-1501(M) via memory interconnects 1526(1)-1526(M), and each GPU 1510(1)-1510(N) is communicatively coupled to GPU memory 1520(1)-1520(N) via GPU memory interconnects 1550(1)-1550(N). In at least one embodiment, memory interconnects 1526 and 1550 may utilize similar or different memory access technologies. By way of example and not limitation, processor memory 1501(1)-1501(M) and GPU memory 1520 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3D XPoint or Nano-RAM. In at least one embodiment, some portions of the processor memory 1501 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0290] As described herein, although the various multi-core processors 1505 and GPUs 1510 can be physically coupled to specific memories 1501 and 1520 respectively, and / or can implement a unified memory architecture, in which the virtual system address space (also known as the “effective address” space) is distributed among the various physical memories. For example, processor memories 1501(1)-1501(M) can each contain 64GB of system memory address space, and GPU memories 1520(1)-1520(N) can each contain 32GB of system memory address space, resulting in a total addressable memory size of 256GB when M=2 and N=4. N and M may also be other values.

[0291] Figure 15B Additional details are shown regarding the interconnection between a multi-core processor 1507 and a graphics acceleration module 1546 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1546 may include one or more GPU chips integrated on a line card coupled to the processor 1507 via a high-speed link 1540 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1546 may optionally be integrated on a package or chip having the processor 1507.

[0292] In at least one embodiment, the processor 1507 includes a plurality of cores 1560A-1560D (which may be referred to as “execution units”), each core having a translation back cover buffer (“TLB”) 1561A-1561D and one or more caches 1562A-1562D. In at least one embodiment, the cores 1560A-1560D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, the caches 1562A-1562D may include level 1 (L1) and level 2 (L2) caches. Furthermore, one or more shared caches 1556 may be included in the caches 1562A-1562D and shared by the respective groups of cores 1560A-1560D. For example, one embodiment of the processor 1507 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1507 and the graphics acceleration module 1546 are connected to the system memory 1514, which may include... Figure 15A The processor memory 1501(1)-1501(M) is included.

[0293] In at least one embodiment, consistency of data and instructions stored in the various caches 1562A-1562D, 1556 and system memory 1514 is maintained via inter-core communication through the consistency bus 1564. In at least one embodiment, for example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 1564 in response to the detection of a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the consistency bus 1564 to snoop on cache accesses.

[0294] In at least one embodiment, proxy circuitry 1525 communicatively couples graphics acceleration module 1546 to coherence bus 1564, thereby allowing graphics acceleration module 1546 to participate in cache coherence protocols as a peer of cores 1560A-1560D. Specifically, in at least one embodiment, interface 1535 provides connectivity to proxy circuitry 1525 via high-speed link 1540, and interface 1537 connects graphics acceleration module 1546 to high-speed link 1540.

[0295] In at least one embodiment, the accelerator integrated circuit 1536 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546. In at least one embodiment, each of the graphics processing engines 1531(1)-1531(N) may include a separate graphics processing unit (GPU). In at least one embodiment, the plurality of graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546 includes, as combined with Figure 18A and Figure 18B The discussion focuses on one or more graphics cores 1800. In at least one embodiment, graphics processing engines 1531(1)-1531(N) may optionally include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1546 may be a GPU having multiple graphics processing engines 1531(1)-1531(N), or graphics processing engines 1531(1)-1531(N) may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0296] In at least one embodiment, the accelerator integrated circuit 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1514. In at least one embodiment, the MMU 1539 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, a cache 1538 may store commands and data for efficient access by the graphics processing engines 1531(1)-1531(N). In at least one embodiment, a fetch unit 1544 may be used to keep data stored in the cache 1538 and graphics memories 1533(1)-1533(M) consistent with core caches 1562A-1562D, 1556 and system memory 1514. As previously mentioned, this task can be accomplished via proxy circuitry 1525 representing cache 1538 and graphics memory 1533(1)-1533(M) (e.g., sending updates related to the modification / access of cache lines on processor caches 1562A-1562D, 1556 to cache 1538 and receiving updates from cache 1538).

[0297] In at least one embodiment, a set of registers 1545 stores context data of threads executed by graphics processing engines 1531(1)-1531(N), and context management circuitry 1548 manages the thread context. For example, context management circuitry 1548 can perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1548 can store the current register value to a designated area in memory (e.g., identified by a context pointer). The register value can then be restored when returning to the context. In at least one embodiment, interrupt management circuitry 1547 receives and processes interrupts received from system devices.

[0298] In at least one embodiment, MMU 1539 translates virtual / effective addresses from graphics processing engine 1531 into real / physical addresses in system memory 1514. In at least one embodiment, accelerator integrated circuit 1536 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1546 and / or other accelerator devices. In at least one embodiment, graphics accelerator module 1546 may be dedicated to a single application executing on processor 1507, or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented, wherein resources of graphics processing engines 1531(1)-1531(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0299] In at least one embodiment, the accelerator integrated circuit 1536 acts as a bridge to the system of the graphics acceleration module 1546 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1536 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1531(1)-1531(N).

[0300] In at least one embodiment, since the hardware resources of the graphics processing engines 1531(1)-1531(N) are explicitly mapped to the real address space seen by the host processor 1507, any host processor can directly address these resources using valid address values. In at least one embodiment, a function of the accelerator integrated circuit 1536 is to physically separate the graphics processing engines 1531(1)-1531(N) so that they appear as independent units to the system.

[0301] In at least one embodiment, one or more graphics memories 1533(1)-1533(M) are coupled to each graphics processing engine 1531(1)-1531(N), and N = M. In at least one embodiment, the graphics memories 1533(1)-1533(M) store instructions and data processed by each graphics processing engine 1531(1)-1531(N). In at least one embodiment, the graphics memories 1533(1)-1533(M) may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3DXPoint or Nano-RAM.

[0302] In at least one embodiment, to reduce data traffic on the high-speed link 1540, a biasing technique can be used to ensure that the data stored in the graphics memory 1533(1)-1533(M) is the data most frequently used by the graphics processing engine 1531(1)-1531(N), and preferably not used (or at least infrequently used) by the cores 1560A-1560D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data needed by the cores (and preferably not the graphics processing engine 1531(-1)-1531(N)) in the caches 1562A-1562D, 1556 and system memory 1514.

[0303] Figure 15C Another exemplary embodiment is shown, wherein the accelerator integrated circuit 1536 is integrated within the processor 1507. In this embodiment, the graphics processing engines 1531(1)-1531(N) communicate directly with the accelerator integrated circuit 1536 via a high-speed link 1540 through interfaces 1537 and 1535 (which may also be any form of bus or interface protocol). In at least one embodiment, the accelerator integrated circuit 1536 can perform operations related to... Figure 15B The described operation is similar, but due to its close proximity to the coherence bus 1564 and caches 1562A-1562D, 1556, it may have higher throughput. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1536 and a programming model controlled by the graphics acceleration module 1546.

[0304] In at least one embodiment, graphics processing engines 1531(1)-1531(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1531(1)-1531(N), thereby providing virtualization within a VM / partition.

[0305] In at least one embodiment, graphics processing engines 1531(1)-1531(N) can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1531(1)-1531(N) to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns graphics processing engines 1531(1)-1531(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1531(1)-1531(N) to provide access to each process or application.

[0306] In at least one embodiment, the graphics acceleration module 1546 or the individual graphics processing engine 1531(1)-1531(N) uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1514 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 1531(1)-1531(N) (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0307] Figure 15D An exemplary accelerator integration slice 1590 is illustrated. In at least one embodiment, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit 1536. In at least one embodiment, the application is an effective address space 1582 in system memory 1514, which stores process element 1583. In at least one embodiment, process element 1583 is stored in response to a GPU call 1581 from an application 1580 executing on processor 1507. In at least one embodiment, process element 1583 contains the process state of the corresponding application 1580. In one embodiment, a job descriptor (WD) 1584 contained in process element 1583 may be a single job requested by the application, or it may contain a pointer to a job queue. In at least one embodiment, WD 1584 is a pointer to a job request queue in the effective address space 1582 of the application.

[0308] In at least one embodiment, the graphics acceleration module 1546 and / or the various graphics processing engines 1531(1)-1531(N) may be shared by all processes or subsets of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1584 to the graphics acceleration module 1546 to begin operations in a virtualized environment.

[0309] In at least one embodiment, the dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either the graphics acceleration module 1546 or an individual graphics processing engine 1531. In at least one embodiment, when the graphics acceleration module 1546 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1546 is assigned, the operating system initializes the accelerator integrated circuit 1536 for the owned process.

[0310] In at least one embodiment, during operation, the WD acquisition unit 1591 in the accelerator integration slice 1590 acquires the next WD 1584, which includes instructions for work to be performed by one or more graphics processing engines of the graphics acceleration module 1546. In at least one embodiment, data from the WD 1584 may be stored in register 1545 and used by MMU 1539, interrupt management circuitry 1547, and / or context management circuitry 1548, as shown. For example, one embodiment of MMU 1539 includes segment / page roaming circuitry for accessing segment / page tables 1586 within the OS virtual address space 1585. In at least one embodiment, interrupt management circuitry 1547 may process interrupt events 1592 received from the graphics acceleration module 1546. In at least one embodiment, when performing graphics operations, a valid address 1593 generated by graphics processing engines 1531(1)-1531(N) is translated into a real address by MMU 1539.

[0311] In at least one embodiment, register 1545 is copied for each graphics processing engine 1531(1)-1531(N) and / or graphics acceleration module 1546, and said register 1545 may be initialized by a hypervisor or operating system. In at least one embodiment, each of these copied registers may be included in accelerator integration slice 1590. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.

[0312]

[0313]

[0314] Table 2 shows exemplary registers that can be initialized by the operating system.

[0315]

[0316] In at least one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engine 1531(1)-1531(N). In at least one embodiment, it contains all the information required for the graphics processing engine 1531(1)-1531(N) to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0317] Figure 15E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1598, in which a list of process elements 1599 is stored. In at least one embodiment, the hypervisor real address space 1598 can be accessed via a hypervisor 1596, which virtualizes the graphics acceleration module engine for an operating system 1595.

[0318] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1546. In at least one embodiment, there are two programming models in which the graphics acceleration module 1546 is shared by multiple processes and partitions, namely, time-slice sharing and graphics-oriented sharing.

[0319] In at least one embodiment, in this model, the hypervisor 1596 owns the graphics acceleration module 1546 and makes its functionality available to all operating systems 1595. In at least one embodiment, for the graphics acceleration module 1546 to support virtualization through the hypervisor 1596, the graphics acceleration module 1546 may comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1546 must provide a context saving and recovery mechanism, (2) the graphics acceleration module 1546 guarantees that the job requests of the application are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 1546 provides the ability to preempt job processing, and (3) when operating in a directed shared programming model, fairness between the processes of the graphics acceleration module 1546 must be ensured.

[0320] In at least one embodiment, application 1580 needs to make system calls to operating system 1595 using the graphics acceleration module type, working descriptor (WD), permission mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1546 and can take the form of graphics acceleration module 1546 commands, valid address pointers to user-defined structures, valid address pointers to command queues, or any other data structure describing the work to be performed by graphics acceleration module 1546.

[0321] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1536 (not shown) and the graphics acceleration module 1546 does not support the User Rights Mask Overwrite Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1596 may selectively apply the current Rights Mask Overwrite Register (AMOR) value before placing the AMR into the process element 1583. In at least one embodiment, CSRP is one of the registers 1545 that contains the effective address of a region in the effective address space 1582 of the application for the graphics acceleration module 1546 to save and restore the context state. In at least one embodiment, this pointer is optional if it is not necessary to save state between jobs or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0322] Upon receiving a system call, the operating system 1595 can verify that the application 1580 has been registered and granted permission to use the graphics acceleration module 1546. Then, in at least one embodiment, the operating system 1595 uses the information shown in Table 3 to invoke the hypervisor 1596.

[0323]

[0324]

[0325] In at least one embodiment, upon receiving a hypervisor call, hypervisor 1596 verifies that operating system 1595 has been registered and granted permission to use graphics acceleration module 1546. Then, in at least one embodiment, hypervisor 1596 adds process element 1583 to a linked list of process elements of the corresponding graphics acceleration module 1546 type. In at least one embodiment, the process element may include the information shown in Table 4.

[0326]

[0327] In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 1590 registers 1545.

[0328] like Figure 15F As shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1501(1)-1501(N) and GPU memories 1520(1)-1520(N). In this implementation, operations performed on GPUs 1510(1)-1510(N) utilize the same virtual / effective memory address space to access processor memories 1501(1)-1501(M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1501(1), a second portion to second processor memory 1501(N), a third portion to GPU memory 1520(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1501 and GPU memory 1520, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0329] In at least one embodiment, the bias / coherence management circuitry 1594A-1594E within one or more MMUs 1539A-1539E ensures cache coherence between one or more host processors (e.g., 1505) and the cache of the GPU 1510, and implements biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, although in Figure 15F Several instances of bias / coherence management circuitry 1594A-1594E are shown, but bias / coherence circuitry can be implemented within the MMU of one or more host processors 1505 and / or within the accelerator integrated circuit 1536.

[0330] One embodiment allows GPU memory 1520 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU memory 1520 as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the host processor 1505 to software-set operands and access computation results without the overhead of conventional I / O DMA data copying. In at least one embodiment, such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1520 without cache coherence overhead may be critical to the execution time of offloaded computations. In at least one embodiment, for example, in cases with high streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1510. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0331] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which may be a page-granular structure (e.g., controlled at the memory page level) comprising one or two bits of memory pages attached to each GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPU 1510, the bias table can be implemented across one or more stolen memory ranges of GPU memory 1520. Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0332] In at least one embodiment, prior to actual access to GPU memory, an access to the bias table entry associated with each access to GPU-attached memory 1520 is performed, resulting in the following operations: In at least one embodiment, a local request from GPU 1510 to find its page in the GPU bias is forwarded directly to the corresponding GPU memory 1520. In at least one embodiment, a local request from the GPU to find its page in the host bias is forwarded to processor 1505 (e.g., via the high-speed link described herein). In at least one embodiment, a request from processor 1505 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request for a page pointing to the GPU bias can be forwarded to GPU 1510. In at least one embodiment, if the GPU is not currently using the page, the GPU may subsequently migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed through a software-based mechanism, a hardware-assisted software mechanism, or, in limited cases, a purely hardware-based mechanism.

[0333] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which subsequently invokes the GPU's device driver. The device driver then sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migration, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migration from the host processor 1505 bias to the GPU bias, but not for the reverse migration.

[0334] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1505 cannot cache. In at least one embodiment, to access these pages, the processor 1505 may request access from the GPU 1510, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between the processor 1505 and the GPU 1510, it is beneficial to ensure that the GPU bias pages are pages needed by the GPU, not those needed by the host processor 1505, and vice versa.

[0335] One or more hardware structures 715 are used to execute one or more embodiments. This document may combine... Figure 7A and / or Figure 7B Provide details about one or more hardware structures 715.

[0336] Figure 16Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0337] Figure 16 This is a block diagram illustrating an exemplary system on a chip integrated circuit 1600 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1600 includes one or more application processors 1605 (e.g., CPU), at least one graphics processor 1610, and may additionally include an image processor 1615 and / or a video processor 1620, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1600 includes peripheral or bus logic, which includes a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I... 2 2S / I 2 2C controller 1640. In at least one embodiment, integrated circuit 1600 may include display device 1645 coupled to one or more of High Definition Multimedia Interface (HDMI) controller 1650 and Mobile Industrial Processor Interface (MIPI) display interface 1655. In at least one embodiment, storage may be provided by flash memory subsystem 1660, including flash memory and flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 1665 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include embedded security engine 1670.

[0338] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 may be used in integrated circuit 1600 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0339] In at least one embodiment, with the Figure 1 The corresponding embodiments include one or more processors, circuits, or systems that cause the selection of one or more data streams to run inference using one or more machine learning models, at least in part based on heuristic information and user-defined parameters.

[0340] Figures 17A-17BExemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0341] Figures 17A-17B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 17A An exemplary graphics processor 1710 of a system-on-a-chip integrated circuit according to at least one embodiment is shown. The system-on-a-chip integrated circuit can be manufactured using one or more IP cores. Figure 17B Further exemplary graphics processor 1740 of a system-on-a-chip integrated circuit according to at least one embodiment is shown. The system-on-a-chip integrated circuit can be manufactured using one or more IP cores. In at least one embodiment, Figure 17A The graphics processor 1710 is a low-power graphics processor core. In at least one embodiment, Figure 17B The graphics processor 1740 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1710, 1740 may be... Figure 16 A variant of the 1610 graphics processor.

[0342] In at least one embodiment, the graphics processor 1710 includes a vertex processor 1705 and one or more fragment processors 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D to 1715N-1 and 1715N). In at least one embodiment, the graphics processor 1710 can execute different shader programs via separate logic, such that the vertex processor 1705 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1715A-1715N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 1705 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1715A-1715N use the primitive and vertex data generated by the vertex processor 1705 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 1715A-1715N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0343] In at least one embodiment, the graphics processor 1710 additionally includes one or more memory management units (MMUs) 1720A-1720B, one or more caches 1725A-1725B, and one or more circuit interconnects 1730A-1730B. In at least one embodiment, one or more MMUs 1720A-1720B provide virtual-to-physical address mappings for the graphics processor 1710, including for vertex processors 1705 and / or fragment processors 1715A-1715N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1725A-1725B. In at least one embodiment, one or more MMUs 1720A-1720B can be synchronized with other MMUs within the system, including with... Figure 16 One or more application processors 1605, graphics processors 1615, and / or video processors 1620 are associated with one or more MMUs, enabling each processor 1605-1620 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B enable the graphics processor 1710 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0344] In at least one embodiment, the graphics processor 1740 includes one or more shader cores 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F to 1755N-1 and 1755N), such as Figure 17B As shown, it provides a unified shader core architecture, where a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1740 includes an inter-core task manager 1745, which acts as a thread dispatcher to assign execution threads to one or more shader cores 1755A-1755N and stitching units 1758 to accelerate tile-based rendering stitching operations, where scene rendering operations are subdivided in image space, for example, to utilize local spatial consistency within the scene or optimize the use of internal caches.

[0345] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 can be integrated into an integrated circuit. Figure 17A and / or Figure 17B The above is used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions or architectures, or neural network use cases described herein.

[0346] In at least one embodiment, with the Figure 1 The corresponding embodiments include one or more processors, circuits, or systems that cause the selection of one or more data streams to run inference using one or more machine learning models, at least in part based on heuristic information and user-defined parameters.

[0347] Figures 18A-18B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, combined with… Figures 18A-18B The components shown and described are integrated into a single system, such as a graphics processing unit (GPU), a SoC, or other type of processor. In at least one embodiment, Figure 18A It shows that it can be included in Figure 16 The graphics core 1800 within the graphics processor 1610, and in at least one embodiment, may be as follows: Figure 17B The unified shader cores shown are 1755A-1755N. Figure 18B A highly parallel general-purpose graphics processing unit (“GPGPU”, also referred to as a “graphics processing unit”) 1830 suitable for deployment on a multi-chip module is illustrated in at least one embodiment. In at least one embodiment, the graphics processing unit 1830 is a GPGPU that includes a graphics processor. In at least one embodiment, the integrated circuit 1600 includes a graphics core 1800, for example, to form an integrated circuit and / or a SoC, wherein such an integrated circuit and / or such a SoC performs the operations described herein.

[0348] In at least one embodiment, the graphics core 1800 includes a shared instruction cache 1802, texture units 1818, and cache / shared memory 1820 (e.g., including L1, L2, L3, last-level cache, or other caches), which are common to the execution resources within the graphics core 1800. In at least one embodiment, the graphics core 1800 may include multiple slices 1801A-1801N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 1800. In at least one embodiment, each slice 1801A-1801N refers to the graphics core 1800. In at least one embodiment, slices 1801A-1801N have sub-slices that are part of slices 1801A-1801N. In at least one embodiment, slices 1801A-1801N are independent of or dependent on other slices. In at least one embodiment, slices 1801A-1801N may include supporting logic, including local instruction caches 1804A-1804N, thread schedulers (orderers) 1806A-1806N, thread dispatchers 1808A-1808N, and a set of registers 1810A-1810N. In at least one embodiment, slices 1801A-1801N may include a set of additional functional units (AFU 1812A-1812N), floating-point units (FPU 1814A-1814N), integer arithmetic logic units (ALU 1816A-1816N), address calculation units (ACU 1813A-1813N), double-precision floating-point units (DPFPU 1815A-1815N), and matrix processing units (MPU 1817A-1817N). In at least one embodiment, the MPU 1817A-1817N is referred to as a matrix engine.

[0349] In at least one embodiment, each slice 1801A-1801N includes one or more engines for floating-point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large dataset workloads. In at least one embodiment, one or more slices 1801A-1801N include one or more vector engines for computing vectors (e.g., computing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations of 16-bit floating-point (also known as "FP16"), 32-bit floating-point (also known as "FP32"), or 64-bit floating-point (also known as "FP64"). In at least one embodiment, one or more slices 1801A-1801N include 16 vector engines paired with 16 matrix math units for computing matrix / tensor operations, wherein the vector engines and math units are exposed via matrix extensions. In at least one embodiment, a designated portion of the processing resources of a processing unit is sliced, for example, 16 cores and a ray tracing unit or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units of the processor. In at least one embodiment, the graphics core 1800 includes one or more matrix engines to compute matrix operations, such as when computing tensor operations.

[0350] In at least one embodiment, one or more slices 1801A-1801N include one or more ray tracing units to compute ray tracing operations (e.g., each slice 1801A-1801N has 16 ray tracing units). In at least one embodiment, the ray tracing units compute ray traversal, triangle intersection, bounding box intersection, or other ray tracing operations.

[0351] In at least one embodiment, one or more slices 1801A-1801N include media slices that encode, decode and / or transcode data, scale and / or format convert data and / or perform video quality operations on video data.

[0352] In at least one embodiment, one or more slices 1801A-1801N are linked to an L2 cache and memory architecture, link connectors, a high-bandwidth memory (HBM) (e.g., HBM2e, HDM3) stack, and a media engine. In at least one embodiment, one or more slices 1801A-1801N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16 units) paired with each core. In at least one embodiment, one or more slices 1801A-1801N have one or more L1 caches. In at least one embodiment, one or more slices 1801A-1801N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data, e.g., corresponding to the instructions; one or more samplers for sampling the data; one or more ray tracing units for performing ray tracing operations; one or more geometries for performing operations in the geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., shapes) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by shapes); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel back-ends. In at least one embodiment, slices 1801A-1801N include memory structures, such as L2 caches.

[0353] In at least one embodiment, the FPU 1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1815A-1815N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1816A-1816N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1817A-1817N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1817-1817N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 1812A-1812N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine). Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This is combined with... Figure 7A and / or Figure 7BDetails regarding logic 715 are provided. In at least one embodiment, logic 715 may be used in graphics core 1800 for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0354] In at least one embodiment, the graphics core 1800 includes interconnects and a link structure sublayer attached to a switch and a GPU-GPU bridge, the GPU-GPU bridge enabling multiple graphics processors 1800 (e.g., eight) to be interconnected without being glued together with load / memory units (LSUs), data transfer units, and synchronization semantics across the multiple graphics processors 1800. In at least one embodiment, the interconnect includes a standardized interconnect (e.g., PCIe) or some combination thereof.

[0355] In at least one embodiment, the graphics core 1800 includes multiple tiles. In at least one embodiment, a tile is a single die or one or more dies, wherein the single die may be connected to an interconnect (e.g., an Embedded Multi-Die Interconnect Bridge (EMIB)). In at least one embodiment, the graphics core 1800 includes compute tiles, memory tiles (e.g., memory tiles may be accessed by different tiles or different chipsets such as Rambo tiles), substrate tiles, base tiles, HMB tiles, link tiles, and EMIB tiles, wherein all tiles are packaged together in the graphics core 1800 as part of the GPU. In at least one embodiment, the graphics core 1800 may include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, the compute tile may have eight graphics cores 1800 and an L1 cache; and the base tile may have host interfaces with PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with eight links, and eight ports with an embedded switch. In at least one embodiment, the blocks are connected via fine-pitch 36-micron microbumps (e.g., copper pillars) in a face-to-face (F2F) on-chip bonding manner. In at least one embodiment, the graphics core 1800 includes a memory structure comprising memory and being blocks accessible by multiple blocks. In at least one embodiment, the graphics core 1800 stores, accesses, or loads its own hardware context in memory, wherein the hardware context is a set of data loaded from registers prior to process resumption, and wherein the hardware context can indicate the state of the hardware (e.g., the state of the GPU).

[0356] In at least one embodiment, the graphics core 1800 includes a serializer / deserializer (SERDES) circuitry that converts a serial data stream into a parallel data stream or a parallel data stream into a serial data stream.

[0357] In at least one embodiment, the graphics core 1800 includes a high-speed coherent unified architecture (GPU-to-GPU), load / store units, bulk data transfer and synchronization semantics, and GPUs connected via an embedded switch, wherein the GPU-to-GPU bridge is controlled by a controller.

[0358] In at least one embodiment, the graphics core 1800 executes an API, wherein the API abstracts the hardware of the graphics core 1800 and uses instruction access libraries to perform mathematical operations (e.g., a mathematical kernel library), deep neural network operations (e.g., a deep neural network library), vector operations, collective communication, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0359] In at least one embodiment, with the Figure 1 The corresponding embodiments include one or more processors, circuits, or systems that cause the selection of one or more data streams to run inference using one or more machine learning models, at least in part based on heuristic information and user-defined parameters.

[0360] Figure 18B A general-purpose processing unit (GPGPU) 1830 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by a set of graphics processing units. In at least one embodiment, the GPGPU 1830 can be directly linked to other instances of the GPGPU 1830 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 1830 includes a host interface 1832 for connection to a host processor. In at least one embodiment, the host interface 1832 is a PCI Express interface. In at least one embodiment, the host interface 1832 may be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1830 receives commands from the host processor and uses a global scheduler 1834 (which may be referred to as a thread sequencer and / or asynchronous computing engine) to allocate the execution threads associated with those commands to a set of computing clusters 1836A-1836H. In at least one embodiment, the computing clusters 1836A-1836H share a cache memory 1838. In at least one embodiment, cache memory 1838 can be used as a higher-level cache than cache memory within compute clusters 1836A-1836H. In at least one embodiment, compute clusters 1836A-1836H include a slice, or referred to as a "slice". In at least one embodiment, GPGPU 1830 is part of a SoC, such as integrated circuit 1600. Figure 16 Part of ).

[0361] In at least one embodiment, the GPGPU 1830 includes memories 1844A-1844B, which are coupled to a computing cluster 1836A-1836H via a set of memory controllers 1842A-1842B (e.g., one or more controllers for HBM2e). In at least one embodiment, memories 1844A-1844B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0362] In at least one embodiment, each of the computing clusters 1836A-1836H includes a set of graphics cores, for example... Figure 18A The graphics core 1800 may include various types of integer and floating-point logic units that can perform computational operations across a range of precisions, including precisions suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 1836A-1836H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0363] In at least one embodiment, multiple instances of the GPGPU 1830 can be configured as a computing cluster. In at least one embodiment, the communication used for synchronization and data exchange by the computing clusters 1836A-1836H varies between embodiments. In at least one embodiment, the multiple instances of the GPGPU 1830 communicate via a host interface 1832. In at least one embodiment, the GPGPU 1830 includes an I / O hub 1839 that couples the GPGPU 1830 to a GPU link 1840, enabling direct connection to other instances of the GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between the multiple instances of the GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, the multiple instances of the GPGPU 1830 reside in a separate data processing system and communicate via network devices accessible through the host interface 1832. In at least one embodiment, GPU link 1840 may be configured to enable connection to a host processor other than or as a replacement for host interface 1832.

[0364] In at least one embodiment, the GPGPU 1830 can be configured to train a neural network. In at least one embodiment, the GPGPU 1830 can be used within an inference platform. In at least one embodiment, when the GPGPU 1830 is used for inference, the GPGPU 1830 may include fewer compute clusters 1836A-1836H compared to when the GPGPU 1830 is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 1844A-1844B can differ between inference and training configurations, with higher bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1830 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0365] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 may be used in the GPGPU 1830 for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein.

[0366] In at least one embodiment, with the Figure 1 The corresponding embodiments include one or more processors, circuits, or systems that cause the selection of one or more data streams to run inference using one or more machine learning models, at least in part based on heuristic information and user-defined parameters.

[0367] Figure 19A block diagram of a computer system 1900 according to at least one embodiment is shown. In at least one embodiment, the computer system 1900 includes a processing subsystem 1901 having one or more processors 1902 and a system memory 1904 communicating via an interconnect path that may include a memory hub 1905. In at least one embodiment, the memory hub 1905 may be a separate component within a chipset assembly or may be integrated within one or more processors 1902. In at least one embodiment, the memory hub 1905 is coupled to an I / O subsystem 1911 via a communication link 1906. In one embodiment, the I / O subsystem 1911 includes an I / O hub 1907 that enables the computer system 1900 to receive input from one or more input devices 1908. In at least one embodiment, the I / O hub 1907 enables a display controller to provide output to one or more display devices 1910A, the display controller being included in one or more processors 1902. In at least one embodiment, one or more display devices 1910A coupled to the I / O hub 1907 may include local, internal, or embedded display devices.

[0368] In at least one embodiment, the processing subsystem 1901 includes one or more parallel processors 1912 coupled to the memory hub 1905 via a bus or other communication link 1913. In at least one embodiment, the communication link 1913 may use any of many standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, one or more parallel processors 1912 form a computationally concentrated parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In at least one embodiment, one or more parallel processors 1912 form a graphics processing subsystem that can output pixels to one or more display devices 1910A coupled via an I / O hub 1907. In at least one embodiment, the parallel processors 1912 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1910B. In at least one embodiment, one or more parallel processors 1912 include one or more cores, such as the graphics core 1800 discussed herein.

[0369] In at least one embodiment, system storage unit 1914 may be connected to I / O hub 1907 to provide a storage mechanism for computer system 1900. In at least one embodiment, I / O switching switch 1916 may be used to provide an interface mechanism to enable connection between I / O hub 1907 and other components, such as network adapter 1918 and / or wireless network adapter 1919 which may be integrated into the platform, and various other devices that can be added via one or more attachment devices 1920. In at least one embodiment, network adapter 1918 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1919 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless devices.

[0370] In at least one embodiment, the computer system 1900 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 1907. In at least one embodiment, the interconnection can be implemented using any suitable protocol (e.g., PCI-based protocols such as PCI-Express or other bus or point-to-point communication interfaces and / or protocols). Figure 19 The communication paths of the various components, such as NV-Link high-speed interconnect or interconnect protocols.

[0371] In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU), such as a graphics core 1800. In at least one embodiment, the parallel processors 1912 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computer system 1900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, the parallel processor 1912, memory hub 1905, processor 1902, and I / O hub 1907 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computer system 1900 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 1900 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computer system.

[0372] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 can be... Figure 19 The system 1900 is used for reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0373] In at least one embodiment, with the Figure 1 The corresponding embodiments include one or more processors, circuits, or systems that cause the selection of one or more data streams to run inference using one or more machine learning models, at least in part based on heuristic information and user-defined parameters.

[0374] processor

[0375] Figure 20A A parallel processor 2000 according to at least one embodiment is illustrated. In at least one embodiment, various components of the parallel processor 2000 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2000 is according to an exemplary embodiment. Figure 19 Variations of the one or more parallel processors 1912 shown. In at least one embodiment, the parallel processor 2000 includes one or more graphics cores 1800.

[0376] In at least one embodiment, the parallel processor 2000 includes a parallel processing unit 2002. In at least one embodiment, the parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of the parallel processing unit 2002. In at least one embodiment, the I / O unit 2004 can be directly connected to other devices. In at least one embodiment, the I / O unit 2004 is connected to other devices using a hub or switching interface (e.g., a memory hub 2005). In at least one embodiment, the connection between the memory hub 2005 and the I / O unit 2004 forms a communication link 2013. In at least one embodiment, the I / O unit 2004 is connected to a host interface 2006 and a memory crossbar switch 2016, wherein the host interface 2006 receives commands for performing processing operations, and the memory crossbar switch 2016 receives commands for performing memory operations.

[0377] In at least one embodiment, when host interface 2006 receives a command buffer via I / O unit 2004, host interface 2006 can direct work operations to execute those commands to front end 2008. In at least one embodiment, front end 2008 is coupled to scheduler 2010 (which may be referred to as sequencer), which is configured to assign commands or other work items to processing cluster array 2012. In at least one embodiment, scheduler 2010 ensures that processing cluster array 2012 is correctly configured and in an active state before assigning tasks to processing cluster array 2012. In at least one embodiment, scheduler 2010 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2010 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing array 2012. In at least one embodiment, host software can demonstrate workloads for scheduling on processing array 2012 via one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed on the processing array 2012 by the scheduler 2010 logic within the microcontroller, which includes the scheduler 2010.

[0378] In at least one embodiment, the processing cluster array 2012 may include up to "N" processing clusters (e.g., clusters 2014A, 2014B to 2014N), where "N" represents a positive integer (which may be an integer different from the integer "N" used in other diagrams). In at least one embodiment, each cluster 2014A-2014N of the processing cluster array 2012 can execute a large number of concurrent threads. In at least one embodiment, the scheduler 2010 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2014A-2014N of the processing cluster array 2012, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2010, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2012. In at least one embodiment, the different clusters 2014A-2014N of the processing cluster array 2012 may be assigned to process different types of programs or to perform different types of computations.

[0379] In at least one embodiment, the processing cluster array 2012 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2012 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2012 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0380] In at least one embodiment, the processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2012 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2012 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2002 may transfer data from system memory via I / O unit 2004 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) and then written back to system memory.

[0381] In at least one embodiment, when the parallel processing unit 2002 is used to perform graphics processing, the scheduler 2010 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 2014A-2014N of the processing cluster array 2012. In at least one embodiment, portions of the processing cluster array 2012 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2014A-2014N may be stored in a buffer to allow intermediate data to be transferred between the clusters 2014A-2014N for further processing.

[0382] In at least one embodiment, the processing cluster array 2012 may receive processing tasks to be executed via a scheduler 2010, which receives commands defining the processing tasks from the front end 2008.

[0383] In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2010 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2008. In at least one embodiment, the front end 2008 may be configured to ensure that the processing cluster array 2012 is configured to be active before starting the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0384] In at least one embodiment, each of one or more instances of the parallel processing unit 2002 may be coupled to the parallel processor memory 2022. In at least one embodiment, the parallel processor memory 2022 may be accessed via a memory crossbar switch 2016, which may receive memory requests from the processing cluster array 2012 and the I / O unit 2004. In at least one embodiment, the memory crossbar switch 2016 may access the parallel processor memory 2022 via a memory interface 2018. In at least one embodiment, the memory interface 2018 may include a plurality of partition units (e.g., partition units 2020A, 2020B to 2020N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2022. In at least one embodiment, the plurality of partition units 2020A-2020N are configured to be equal to the number of memory units, such that the first partition unit 2020A has a corresponding first memory unit 2024A, the second partition unit 2020B has a corresponding memory unit 2024B, and the Nth partition unit 2020N has a corresponding Nth memory unit 2024N. In at least one embodiment, the number of partition units 2020A-2020N may not be equal to the number of memory units.

[0385] In at least one embodiment, memory cells 2024A-2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2024A-2024N may also include 3D stacked memory, including but not limited to high-bandwidth memory (HBM), HBM2e, or HDM3. In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 2024A-2024N, allowing partitioning cells 2020A-2020N to write portions of each rendering target in parallel, to efficiently utilize the available bandwidth of the parallel processor memory 2022. In at least one embodiment, local instances of the parallel processor memory 2022 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0386] In at least one embodiment, any of clusters 2014A-2014N of the processing cluster array 2012 can process data to be written to any memory cell 2024A-2024N within the parallel processor memory 2022. In at least one embodiment, the memory crossbar switch 2016 can be configured to transfer the output of each cluster 2014A-2014N to any partition cell 2020A-2020N or another cluster 2014A-2014N, and clusters 2014A-2014N can perform further processing operations on the output. In at least one embodiment, each cluster 2014A-2014N can communicate with the memory interface 2018 via the memory crossbar switch 2016 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 2016 has a connection to a memory interface 2018 for communication with I / O unit 2004, and a connection to a local instance of parallel processor memory 2022, thereby enabling processing units within different processing clusters 2014A-2014N to communicate with system memory or other memory not local to parallel processing unit 2002. In at least one embodiment, the memory crossbar switch 2016 may use virtual channels to separate traffic flows between clusters 2014A-2014N and partition units 2020A-2020N.

[0387] In at least one embodiment, multiple instances of the parallel processing unit 2002 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2002 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2002 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 2002 or the parallel processor 2000 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0388] Figure 20B This is a block diagram of a partitioning unit 2020 according to at least one embodiment. In at least one embodiment, the partitioning unit 2020 is... Figure 20A This is an example of one of the partitioning units 2020A-2020N. In at least one embodiment, the partitioning unit 2020 includes an L2 cache 2021, a frame buffer interface 2025, and a ROP 2026 (raster operation unit). In at least one embodiment, the L2 cache 2021 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 2016 and the ROP 2026. In at least one embodiment, the L2 cache 2021 outputs read misses and urgent write-back requests to the frame buffer interface 2025 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via the frame buffer interface 2025. In at least one embodiment, the frame buffer interface 2025 communicates with memory cells in the parallel processor memory (such as...). Figure 20A The memory cells 2024A-2024N (e.g., within the parallel processor memory 2022) interact with each other.

[0389] In at least one embodiment, ROP 2026 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2026 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 2026 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2026 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0390] In at least one embodiment, ROP 2026 is included within each processing cluster (e.g., Figure 20A Clusters 2014A-2014N are used instead of partition units 2020. In at least one embodiment, read and write requests for pixel data are made via memory crossbar switch 2016 instead of pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device (such as...). Figure 19 One or more display devices 1910) display, routed by processor 1902 for further processing, or by Figure 20A One of the processing entities within the parallel processor 2000 is routed for further processing.

[0391] Figure 20C This is a block diagram of a processing cluster 2014 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is... Figure 20A An example of one of the processing clusters 2014A-2014N. In at least one embodiment, the processing cluster 2014 can be configured to execute a number of threads in parallel, where a "thread" refers to an instance of a specific program executing on a specific set of input data. In at least one embodiment, Single Instruction Multiple Data (SIMD) instruction issuing technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, Single Instruction Multiple Threading (SIMT) technology is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0392] In at least one embodiment, the operation of the processing cluster 2014 can be controlled by a pipeline manager 2032 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2032... Figure 20AThe scheduler 2010 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2034 and / or texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2014 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2014 may include one or more instances of the graphics multiprocessor 2034. In at least one embodiment, the graphics multiprocessor 2034 can process data, and the data crossover switch 2040 can be used to distribute the processed data to one of a number of possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2032 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossover switch 2040.

[0393] In at least one embodiment, each graphics multiprocessor 2034 within the processing cluster 2014 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0394] In at least one embodiment, instructions sent to the processing cluster 2014 constitute threads. In at least one embodiment, a set of threads executed across a group of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a general program on different input data. In at least one embodiment, each thread within a thread group may be assigned to a different processing engine within the graphics multiprocessor 2034. In at least one embodiment, a thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, a thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 2034, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2034.

[0395] In at least one embodiment, the graphics multiprocessor 2034 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2034 may forgo the internal cache and use a cache memory within the processing cluster 2014 (e.g., L1 cache 2048). In at least one embodiment, each graphics multiprocessor 2034 may also access partition units (e.g., Figure 20A The L2 cache is located within partition units 2020A-2020N, ​​which are shared among all processing clusters 2014 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2034 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2002 can be used as global memory. In at least one embodiment, the processing cluster 2014 includes multiple instances of the graphics multiprocessor 2034, which can share common instructions and data that can be stored in the L1 cache 2048.

[0396] In at least one embodiment, each processing cluster 2014 may include a memory management unit (“MMU”) 2045 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2045 may reside in Figure 20A The memory interface 2018 is located within the MMU 2045. In at least one embodiment, the MMU 2045 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2045 may include an address translation lookup buffer (TLB) or a cache that may reside within the graphics multiprocessor 2034, the L1 cache 2048, or the processing cluster 2014. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0397] In at least one embodiment, the processing cluster 2014 can be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2034 outputs a processed task to a data cross switch 2040 to provide the processed task to another processing cluster 2014 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory cross switch 2016. In at least one embodiment, a preROP 2042 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2034 and direct the data to a ROP unit, which can be associated with a partitioning unit (e.g., [missing information]). Figure 20A The PreROP 2042 unit is located together with the partition units 2020A-2020N. In at least one embodiment, the PreROP 2042 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0398] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 7A and / or Figure 7B Details regarding logic 715 are provided. In at least one embodiment, logic 715 can be used in a graphics processing cluster 2014 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0399] In at least one embodiment, with the Figure 1 The corresponding embodiments include one or more processors, circuits, or systems that cause the selection of one or more data streams to run inference using one or more machine learning models, at least in part based on heuristic information and user-defined parameters.

[0400] Figure 20DA graphics multiprocessor 2034 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2034 is coupled to a pipeline manager 2032 of a processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 has an execution pipeline including, but not limited to, an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more general-purpose graphics processing unit (GPGPU) cores 2062, and one or more load / store units 2066, wherein one or more load / store units 2066 can perform load / store operations to load / store instructions corresponding to the execution operations. In at least one embodiment, the GPGPU cores 2062 and the load / store units 2066 are coupled to a cache memory 2072 and a shared memory 2070 via a memory and cache interconnect 2068. In at least one embodiment, the GPGPU cores 2062 are part of a SoC, for example... Figure 16 Part of the integrated circuit 1600.

[0401] In at least one embodiment, instruction cache 2052 receives a stream of instructions to be executed from pipeline manager 2032. In at least one embodiment, instructions are cached in instruction cache 2052 and dispatched to instruction unit 2054 for execution. In one embodiment, instruction unit 2054 may dispatch instructions as thread groups (e.g., thread bundles, wavefronts, waves), assigning each thread of the thread group to a different execution unit within GPGPU core 2062. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2056 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by load / store unit 2066.

[0402] In at least one embodiment, register file 2058 provides a set of registers for functional units of graphics multiprocessor 2034. In at least one embodiment, register file 2058 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 2034 (e.g., GPGPU core 2062, load / store unit 2066). In at least one embodiment, register file 2058 is partitioned between each functional unit, such that a dedicated portion of register file 2058 is allocated to each functional unit. In at least one embodiment, register file 2058 is partitioned between different thread bundles (which may be referred to as wavefronts and / or waves) being executed by graphics multiprocessor 2034.

[0403] In at least one embodiment, each of the GPGPU cores 2062 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2034. In at least one embodiment, the GPGPU cores 2062 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2062 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 2034 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2062 may also include fixed-function or special-function logic.

[0404] In at least one embodiment, the GPGPU core 2062 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 2062 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0405] In at least one embodiment, the memory and cache interconnect 2068 is an interconnect network connecting each functional unit of the graphics multiprocessor 2034 to the register file 2058 and the shared memory 2070. In at least one embodiment, the memory and cache interconnect 2068 is a cross-switch interconnect that allows the load / store unit 2066 to perform load and store operations between the shared memory 2070 and the register file 2058. In at least one embodiment, the register file 2058 can operate at the same frequency as the GPGPU core 2062, resulting in very low latency for data transfer between the GPGPU core 2062 and the register file 2058. In at least one embodiment, the shared memory 2070 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 2034. In at least one embodiment, the cache memory 2072 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 2036. In at least one embodiment, the shared memory 2070 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in cache memory 2072, the thread executing on GPGPU core 2062 can also programmatically store data in shared memory.

[0406] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the SoC includes a parallel processor or GPGPU as described herein, wherein the parallel processor or the SoC performs the operations described herein. In at least one embodiment, the GPU may be integrated with the core on a package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0407] The logic 715 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 7A and / or Figure 7BDetails regarding logic 715 are provided. In at least one embodiment, logic 715 may be used in a graphics multiprocessor 2034 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0408] In at least one embodiment, with the Figure 1 The corresponding embodiments include one or more processors, circuits, or systems that cause the selection of one or more data streams to run inference using one or more machine learning models, at least in part based on heuristic information and user-defined parameters.

[0409] Figure 21 A multi-GPU computing sys...

Claims

1. A computer-implemented method, comprising: Using a machine learning model, heuristic information is generated based at least in part on inference information about the first batch of frames from the data stream collection, the heuristic information including skip intervals corresponding to the data stream collection; A subset of streams is selected from the set of data streams, at least in part, based on the heuristic information, to generate a second batch of frames; Use one or more machine learning models to infer information about the second batch of frames; as well as The heuristic information is updated based at least in part on inference information from the second batch of frames; The first batch of frames and the second batch of frames each include video frames, which in turn include corresponding image frame sequences.

2. The method according to claim 1, wherein the computer-implemented method further comprises: Obtain one or more configuration parameters, wherein the selection of a subset of the streams is also based at least in part on the one or more configuration parameters.

3. The method of claim 2, wherein the one or more configuration parameters indicate the number of detected objects.

4. The method according to claim 1, wherein, The heuristic information is updated based on the number of objects detected using the second batch of frames.

5. The method according to claim 1, wherein, Each stream in the data stream set is generated by a different camera.

6. A system comprising: One or more processors; as well as A memory that stores instructions that, if executed by one or more processors, cause the system to: Heuristic information is obtained at least in part based on information applied to inference from one or more machine learning models in the first frame of the data stream collection, wherein the heuristic information includes one or more skip intervals corresponding to the data stream collection; The second frame is determined by selecting a subset of data streams from the data stream set, at least in part, based on the heuristic information, wherein one or more processing operations for the subset are skipped; and The heuristic information is updated at least in part based on information applied to inference by one or more machine learning models from the second frame of the subset of the data stream; The first frame and the second frame comprise a sequence of image frames.

7. The system of claim 6, wherein the memory further stores instructions that, upon execution by the one or more processors, cause the system to acquire one or more configuration parameters, wherein the selection of the subset of data streams is also performed at least in part based on the one or more configuration parameters.

8. The system of claim 7, wherein the one or more configuration parameters indicate the number of detected objects.

9. The system of claim 7, wherein the one or more configuration parameters further indicate at least one of the following: the resolution of the first frame from the data stream set, the size of one or more objects represented using the first frame from the data stream set, and the proximity of one or more regions of interest (ROIs) depicted in the first frame from the data stream set.

10. The system of claim 6, wherein the memory further stores instructions that, if executed by the one or more processors, cause the system to use one or more auxiliary machine learning models to infer auxiliary information about a third frame from the data stream set that is not part of the subset of the data stream.

11. The system according to claim 6, wherein, The one or more machine learning models are deployed to perform at least one of the following: object detection, image segmentation, or object classification.

12. The system of claim 6, wherein the updated heuristic information includes additional skip intervals for the subset of data streams, the additional skip intervals being different from the one or more skip intervals.

13. A machine-readable medium having an instruction set stored thereon, which, if executed by one or more processors, causes said one or more processors to: Heuristic information is determined at least in part based on information inferred from the first frame corresponding to the data stream set, the heuristic information including one or more skip intervals corresponding to the data stream set; This results in the execution of one or more inference operations on a second frame from a subset of data streams, the subset of data streams being selected from the set of data streams at least in part based on the heuristic information; and The heuristic information is updated at least in part based on the results of one or more of the reasoning operations; The first frame and the second frame comprise a sequence of image frames.

14. The machine-readable medium of claim 13, wherein performing the one or more inference operations on a second frame of the subset of the data stream is at least in part based on the one or more configuration parameters.

15. The machine-readable medium of claim 14, wherein the one or more configuration parameters indicate the number of detected objects.

16. The machine-readable medium of claim 13, wherein, The selection of the data stream subset is based at least in part on the type of one or more objects detected from the first frame.

17. The machine-readable medium of claim 13, wherein the updated heuristic information includes one or more additional skip intervals of the data stream subset, the one or more additional skip intervals being shorter than the one or more skip intervals.

18. The machine-readable medium of claim 13, wherein the instruction set further comprises an instruction, if executed by the one or more processors, such that, as a result of selecting the subset of the data stream, a third frame in the data stream set is skipped according to the one or more skip intervals.

Images