A shift register, a gate driving circuit and a display device

Abstract

The present disclosure provides a shift register, a gate driving circuit and a display device, and belongs to the technical field of display. The shift register is configured to provide a gate driving signal for a pixel driving circuit. The shift register comprises an input sub-circuit, an output sub-circuit, an operation sub-circuit and a clock driving sub-circuit. The input sub-circuit is configured to receive an input signal and pre-charge a pull-up node through the input signal. The pull-up node is a connection node between the input sub-circuit and the output sub-circuit. The output sub-circuit is configured to output a first clock signal input into a first clock signal end through a signal output end under the control of a potential of the pull-up node. The operation sub-circuit is configured to compare a pixel voltage of the pixel driving circuit collected and a reference voltage to generate a first control signal. The clock driving sub-circuit is configured to input the first clock signal into the first clock signal end according to the first control signal.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a shift register, a gate driving circuit and a display device. BACKGROUND

[0002] The gate driving circuit of the display device comprises a plurality of cascaded shift registers, and the plurality of shift registers sequentially output scan signals. At present, the resolution requirement of the display device is higher and higher. Due to the large load of the clock signal line (the load comprises a parasitic capacitance and a parasitic resistance on a wire), the clock signal is distorted in the transmission process, and then the actual charging time of the pixel driving circuit is shortened, so that the brightness difference appears on the display panel, and the display panel is defective. SUMMARY

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provide a shift register, a gate driving circuit and a display device.

[0004] In a first aspect, a technical solution adopted by the present disclosure to solve the technical problems of the present disclosure is a shift register configured to provide a gate driving signal for a pixel driving circuit, the shift register comprising:

[0005] an input sub-circuit, an output sub-circuit, an operation sub-circuit and a clock driving sub-circuit; wherein

[0006] The input sub-circuit is configured to receive an input signal and pre-charge a pull-up node through the input signal; the pull-up node is a connection node between the input sub-circuit and the output sub-circuit;

[0007] The output sub-circuit is configured to output a first clock signal input to a first clock signal terminal through a signal output terminal under the control of a potential of the pull-up node;

[0008] The operation sub-circuit is configured to compare a pixel voltage of the pixel driving circuit collected and a reference voltage to generate a first control signal;

[0009] The clock driving sub-circuit is configured to input the first clock signal to the first clock signal terminal according to the first control signal.

[0010] In some embodiments, the reference voltage is a sawtooth wave voltage.

[0011] In some embodiments, the input sub-circuit comprises a first transistor and a second transistor.

[0012] The control electrode of the first transistor is connected to a second clock signal end, the first electrode of the first transistor is connected to a signal input end, the second electrode of the first transistor is connected to the first electrode of the second transistor, the control electrode of the second transistor is connected to a first voltage end, and the second electrode of the second transistor is connected to an up pull node.

[0013] In some embodiments, the shift register further comprises a voltage holding sub-circuit;

[0014] The voltage holding sub-circuit is configured to store a second voltage under the control of the first clock signal and output the second voltage to the second electrode of the first transistor under the control of the potential of the pull-down node.

[0015] In some embodiments, the voltage holding sub-circuit comprises a seventh transistor and an eighth transistor;

[0016] The control electrode of the seventh transistor is connected to the first clock signal end, the first electrode of the seventh transistor is connected to the second electrode of the first transistor, and the second electrode of the seventh transistor is connected to the first electrode of the eighth transistor; the control electrode of the eighth transistor is connected to the pull-down node, and the second electrode of the eighth transistor is connected to the second voltage end.

[0017] In some embodiments, the output sub-circuit comprises a third transistor and a first capacitor;

[0018] The control electrode of the third transistor is connected to the up pull node, the first electrode of the third transistor is connected to the first clock signal end, and the second electrode of the third transistor is connected to a signal output end; the first plate of the first capacitor is connected to the control electrode of the third transistor, and the second plate of the first capacitor is connected to the second electrode of the third transistor.

[0019] In some embodiments, the shift register further comprises a pull-down control sub-circuit;

[0020] The pull-down control sub-circuit is configured to transmit a first voltage to the pull-down node under the control of a second clock signal and transmit the second clock signal to the pull-down node under the control of the potential of the up pull node.

[0021] In some embodiments, the pull-down control sub-circuit comprises a fourth transistor and a fifth transistor;

[0022] The control electrode of the fourth transistor is connected to the second clock signal end, the first electrode of the fourth transistor is connected to the first voltage end, and the second electrode of the fourth transistor is connected to the pull-down node; the control electrode of the fifth transistor is connected to the input sub-circuit, the first electrode of the fifth transistor is connected to the second clock signal end, and the second electrode of the fifth transistor is connected to the pull-down node.

[0023] In some embodiments, the shift register further comprises a pull-down sub-circuit;

[0024] The pull-down sub-circuit is configured to transmit the second voltage to the signal output end under the control of the pull-down node potential.

[0025] In some embodiments, the pull-down sub-circuit comprises a sixth transistor and a second capacitor;

[0026] The control electrode of the sixth transistor is connected to the pull-down node, the first electrode of the sixth transistor is connected to the signal output end, and the second electrode of the sixth transistor is connected to the second voltage end; the first plate of the second capacitor is connected to the control electrode of the sixth transistor, and the second plate of the second capacitor is connected to the second electrode of the sixth transistor.

[0027] In a second aspect, the embodiments of the present disclosure further provide a gate drive circuit comprising a plurality of cascaded shift registers as described in any one of the above embodiments; wherein,

[0028] The signal input end of the first stage shift register is connected to the start signal end;

[0029] In addition to the first stage shift register, the signal output end of the current stage shift register is connected to the reset signal end of the previous stage shift register and the signal input end of the next stage shift register.

[0030] In a third aspect, the embodiments of the present disclosure further provide a display device comprising the gate drive circuit as described in the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 It is a schematic diagram of an exemplary display device;

[0032] Figure 2 It is a schematic diagram of the brightness difference between the two ends of the display panel;

[0033] Figure 3a It is a schematic diagram of the working principle of the pixel driving circuit in the embodiments of the present disclosure;

[0034] Figure 3b It is a driving timing diagram of the pixel driving circuit shown in the above; Figure 3a

[0035] Figure 4a It is a structural schematic diagram of a shift register provided in the embodiments of the present disclosure;

[0036] Figure 4b It is a driving timing diagram of the shift register shown in the above; Figure 4a

[0037] Figure 5 ​​Fig. 1 is a schematic diagram of the working principle of the operation sub-circuit in the embodiment of the present disclosure;

[0038] Figure 6 Fig. 2 is a schematic diagram of the working principle of the clock driving sub-circuit in the embodiment of the present disclosure.

[0039] In the figure, the reference signs are as follows: 1, shift register; 01, pixel unit; 10, input sub-circuit; 20, output sub-circuit; 30, operation sub-circuit; 40, clock driving sub-circuit; 50, voltage holding sub-circuit; 60, pull-down control sub-circuit; 70, pull-down sub-circuit; PU, pull-up node; PD, pull-down node; GSTV, signal input end; GCB, first clock signal end; GCK, second clock signal end; Gout, signal output end; U1, first control signal; T11, first reset transistor; T12, threshold compensation transistor; T13, driving transistor; T14, data writing transistor; Cst, storage capacitor; Vcst, voltage of the storage capacitor; Vsw, sawtooth wave voltage; T15, first light-emitting control transistor; T16, second light-emitting control transistor; T17, second reset transistor; D, light-emitting device; Gate, gate line; Data, data line; Elvdd, first power voltage end; Vinit, reset power signal end; Reset, reset control signal end; EM, light-emitting control end; Elvss, second power voltage end; T21, first transistor; T22, second transistor; VGL, first voltage end; VGH, second voltage end; N1, first node; N2, second node; T27, seventh transistor; T28, eighth transistor; T23, third transistor; C1, first capacitor; T24, fourth transistor; T25, fifth transistor; T26, sixth transistor; C2, second capacitor. DETAILED DESCRIPTION

[0040] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be combined with the accompanying drawings of the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. The components of the embodiments of the present disclosure described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed present disclosure, but only represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0041] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning as understood by a person having ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" and similar terms do not denote a quantity of particular mentioned items, but mean that there is at least one of the items present. The terms "comprises", "comprising", "includes", "including" and the like can mean the presence of a stated element or item and the like, but do not preclude the presence or addition of another element or item. The terms "connected", "coupled", and the like, do not necessarily denote a physical or mechanical connection or coupling, but can include an electrical connection or coupling, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like, are used only to indicate relative positions, and when the absolute positions of the described objects are changed, the relative positions can also be changed accordingly.

[0042] In the present disclosure, "a plurality of or several" means two or more. The term "and / or" describes an associated relationship with the associated objects, and means that there can be three relationships, for example, A and / or B, which means that A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after it.

[0043] Figure 1 An exemplary display device is shown in FIG. 1, which includes pixel units 01 in a display area, the pixel units 01 including pixel driving circuits, and further includes gate driving circuits and source driving circuits in a peripheral area surrounding the display area. The gate driving circuits include a plurality of cascaded shift registers 1, which are connected to gate lines Gate and sequentially input scan signals to each row of pixel driving circuits; the source driving circuits provide data signals to each column of pixel driving circuits through data lines Data. Figure 1

[0044] The clock signal line is used to input a clock signal to the shift register, to control the scan signal input to the pixel driving circuit, and further control the time of writing the data signal by the pixel driving circuit, i.e., to control the actual charging time of the pixel driving circuit. Figure 2 An exemplary display panel with luminance difference at both ends is shown in FIG. 2, which shows that due to the large load of the clock signal line (the load includes parasitic capacitance and parasitic resistance on the wire), the clock signal is distorted during transmission, which further causes the actual charging time of the pixel driving circuit to be shortened, resulting in luminance difference on the display panel and causing the display panel to be defective. Figure 2

[0045] ​​Specifically, the principle of the malformation is as follows: as people have higher and higher requirements for the resolution of display panels, the load on the clock signal line increases, which leads to distortion of the clock signal waveform transmitted to the far end of the driver IC of the display panel, so that the actual charging time of the pixel driving circuit is shortened, and then the voltage written into the pixel driving circuit is lower than expected, and finally the brightness at the far end of the Driver IC is different from the brightness at the near end of the Driver IC, that is, the display panel malfunctions.

[0046] The inventors find that in the prior art, the problem of brightness difference between the two ends of the display panel caused by RC delay is mainly solved by optimizing the display panel wiring material, reducing the wiring length, and reducing the parasitic resistance and parasitic capacitance on the wiring, but these measures can only alleviate the malformation and cannot completely eliminate the brightness abnormality, and also increase the production cost of the panel factory and the difficulty of the layout of the flexible printed circuit (FPC) line.

[0047] In view of this, the present disclosure provides a shift register, the clock signal of which can be adjusted according to the pixel voltage actually input to the pixel driving circuit, so as to adjust the actual charging time of the pixel driving circuit, and finally improve the problem of display brightness difference caused by load distribution of the display panel.

[0048] It should be noted that the shift register provided in the embodiments of the present disclosure can be applied in different pixel driving circuits. For example, the pixel driving circuit can be a 5T2C driving circuit, or a 7T1C driving circuit, and the like, and the present disclosure does not make special limitations on this. For the convenience of description and understanding, the pixel driving circuit in the embodiments of the present disclosure is taken as a 7T1C (i.e. seven transistors and one capacitor structure) pixel driving circuit for example, Figure 3a is a schematic diagram of the working principle of the pixel driving circuit in the embodiments of the present disclosure; Figure 3b is a driving timing diagram of the pixel driving circuit shown in Figure 3a , as shown in Figure 3a and Figure 3b , the pixel driving circuit includes a first reset transistor T11, a threshold compensation transistor T12, a driving transistor T13, a data writing transistor T14, a storage capacitor Cst, a first light-emitting control transistor T15, a second light-emitting control transistor T16, a second reset transistor T17, and a light-emitting device D.

[0049] It should be noted that the pixel voltage actually input to the pixel driving circuit in the embodiments of the present disclosure is taken as the voltage Vcst of the storage capacitor of the pixel driving circuit shown in Figure 3a

[0050] ​It should be noted that the transistor used in the embodiments of the present disclosure can be a thin film transistor or a field effect transistor or other same devices with different characteristics. Since the source and drain of the transistor used are symmetrical, the source and drain are not distinguished. In the embodiments of the present disclosure and the following description, one of the poles is referred to as the first pole, the other pole is referred to as the second pole, and the gate is referred to as the control pole. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. When a P-type transistor is used, the first pole is the source of the P-type transistor, the second pole is the drain of the P-type transistor, and the gate inputs a low-level signal, and the source and drain are turned on. When an N-type transistor is used, the first pole is the source of the N-type transistor, the second pole is the drain of the N-type transistor, and the gate inputs a high-level signal, and the source and drain are turned on. In the embodiments of the present disclosure, the first reset transistor T11, the threshold compensation transistor T12, the driving transistor T13, the data writing transistor T14, the first light-emitting control transistor T15, the second light-emitting control transistor T16, and the second reset transistor T17 are all taken as examples of P-type transistors for specific description.

[0051] Specifically, a second electrode of the data write transistor T14 is electrically connected with a first electrode of the driving transistor T13, a first electrode of the data write transistor T14 is configured to be electrically connected with a data line Data to receive a data signal, a control electrode of the data write transistor T14 is configured to be electrically connected with a signal output terminal Gout to receive a first clock signal; a second plate of the storage capacitor Cst is electrically connected with a first power voltage terminal Elvdd, a first plate of the storage capacitor Cst is electrically connected with the control electrode of the driving transistor T13; a first electrode of the threshold compensation transistor T12 is electrically connected with the control electrode of the driving transistor T13, a second electrode of the threshold compensation transistor T12 is electrically connected with a second electrode of the driving transistor T13, a control electrode of the threshold compensation transistor T12 is configured to be electrically connected with the signal output terminal Gout to receive a compensation control signal; a first electrode of the first reset transistor T11 is configured to be electrically connected with a reset power signal terminal Vinit to receive a reset signal, a second electrode of the first reset transistor T11 is electrically connected with the control electrode of the driving transistor T13, a control electrode of the first reset transistor T11 is configured to be electrically connected with a reset control signal terminal Reset to receive a reset control signal; a second electrode of the second reset transistor T17 is configured to be electrically connected with the reset power signal terminal Vinit to receive the reset signal, a first electrode of the second reset transistor T17 is electrically connected with a first electrode of the light emitting device D, a control electrode of the second reset transistor T17 is configured to be electrically connected with the reset control signal terminal Reset to receive the reset control signal; a first electrode of the first light emitting control transistor T15 is electrically connected with the first power voltage terminal Elvdd, a second electrode of the first light emitting control transistor T15 is electrically connected with the first electrode of the driving transistor T13, a control electrode of the first light emitting control transistor T15 is configured to be electrically connected with a light emitting control terminal EM to receive a light emitting control signal; a first electrode of the second light emitting control transistor T16 is electrically connected with the second electrode of the driving transistor T13, a second electrode of the second light emitting control transistor T16 is electrically connected with the first electrode of the light emitting device D, a control electrode of the second light emitting control transistor T16 is configured to be electrically connected with the light emitting control terminal EM to receive the light emitting control signal; a second electrode of the light emitting device D is electrically connected with a second power voltage terminal Elvss.

[0052] It should be noted that one of the first power voltage terminal Elvdd and the second power voltage terminal Elvss is a high voltage terminal, and the other is a low voltage terminal. For example, the first power voltage terminal Elvdd is a voltage source to output a constant first power voltage, and the first power voltage is a positive voltage; and the second power voltage terminal Elvss can be a voltage source to output a constant second power voltage, and the second power voltage is a negative voltage. For example, in some embodiments, the second power voltage terminal Elvss can be grounded.

[0053] The scan signal and the compensation control signal can be the same, i.e., the control electrode of the data writing transistor T14 and the control electrode of the threshold compensation transistor T12 can be electrically connected to the same signal line to receive the same signal (e.g., a scan signal, i.e., a first clock signal in the embodiment of the present disclosure), thereby reducing the number of signal lines. Of course, it can be understood that the control electrode of the data writing transistor T14 and the control electrode of the threshold compensation transistor T12 can also be electrically connected to different signal lines, respectively.

[0054] The scan signal and the compensation control signal can also be different, so that the control electrode of the data writing transistor T14 and the control electrode of the threshold compensation transistor T12 can be separately controlled, increasing the flexibility of controlling the pixel circuit. In the embodiment of the present disclosure, the control electrode of the data writing transistor T14 and the control electrode of the threshold compensation transistor T12 are electrically connected to the signal output end Gout as an example.

[0055] The control electrode of the first light emitting control transistor T15 and the control electrode of the second light emitting control transistor T16 can be electrically connected to the same signal line, e.g., the light emitting control end EM, to receive the same signal, thereby reducing the number of signal lines. Of course, it can be understood that the control electrode of the first light emitting control transistor T15 and the control electrode of the second light emitting control transistor T16 can also be electrically connected to different signal lines, respectively. In the embodiment of the present disclosure, the control electrode of the first light emitting control transistor T15 and the control electrode of the second light emitting control transistor T16 are electrically connected to the light emitting control end EM as an example.

[0056] The control electrode of the first reset transistor T11 and the control electrode of the second reset transistor T17 can be electrically connected to the same signal line, e.g., the reset control signal end Reset, to receive the same signal, thereby reducing the number of signal lines. Of course, it can be understood that the control electrode of the first reset transistor T11 and the control electrode of the second reset transistor T17 can also be electrically connected to different signal lines, respectively. In the embodiment of the present disclosure, the control electrode of the first reset transistor T11 and the control electrode of the second reset transistor T17 are electrically connected to the reset control signal end Reset as an example.

[0057] The first electrode of the first reset transistor T11 and the second electrode of the second reset transistor T17 can be electrically connected to the same signal line, for example, a reset power signal terminal Vinit. The reset power signal terminal Vinit can be a direct current reference voltage terminal to output a constant direct current reference voltage. The reset power signal terminal Vinit can be a high voltage terminal or a low voltage terminal, as long as it can provide a reset signal to reset the control electrode of the driving transistor T13 and the first electrode of the light emitting element. The embodiment of the present disclosure is not limited in this regard. In the embodiment of the present disclosure, the first electrode of the first reset transistor T11 and the second electrode of the second reset transistor T17 are electrically connected to the reset power signal terminal Vinit. In addition, the specific structure of the pixel driving circuit shown in FIG. 7 can be set according to actual application requirements, and the embodiment of the present disclosure is not limited in this regard. Figure 3a The working process of the pixel driving circuit shown in FIG. 7 is divided into a reset stage t1, a data writing and threshold compensation stage t2, and a light emitting stage t3.

[0058] As shown in FIG. 7, the working process of the pixel driving circuit shown in FIG. 7 is divided into a reset stage t1, a data writing and threshold compensation stage t2, and a light emitting stage t3. Figure 3b As shown in FIG. 7, the working process of the pixel driving circuit shown in FIG. 7 is divided into a reset stage t1, a data writing and threshold compensation stage t2, and a light emitting stage t3.

[0059] Reset stage (t1): The reset control signal terminal Reset writes a low level signal, the signal output terminal Gout and the light emitting control terminal EM write a high level signal; the first reset transistor T11 and the second reset transistor T17 are turned on, and the control electrode of the driving transistor T13 is written with an initial voltage by the reset power signal terminal Vinit, to prepare for writing the data voltage of the next frame. The anode of the light emitting device D is written with an initial voltage by the second reset transistor T17, so that the light emitting device D is no longer in a forward conduction state, and the internal electric field formed by the directional movement of impurity ions in the light emitting device D gradually disappears, thereby restoring the characteristics of the light emitting device D.

[0060] Data writing and threshold compensation stage (t2): the signal output terminal Gout writes a low level signal, the reset control signal terminal Reset and the first light emitting control terminal EM write a high level signal; the data writing transistor T14 and the threshold compensation transistor T12 are turned on. The driving transistor T13 is connected into a diode structure by the threshold compensation transistor T12, and the data voltage written on the data line Data is written into the control electrode of the driving transistor T13 through the data writing transistor T14 and the threshold compensation transistor T12, until the driving transistor T13 is cut off, and the voltage of the control electrode of the driving transistor T13 is stored in the storage capacitor Cst.

[0061] Light-emitting stage (t3): A low-level signal is written to the light-emitting control terminal EM, and a high-level signal is written to the signal output terminal Gout and the reset control signal terminal Reset. Both the first light-emitting control transistor T15 and the second light-emitting control transistor T16 are turned on. The first terminal of the driving transistor T13 is connected to the first power supply voltage terminal Elvdd, and the voltage at the first terminal of the driving transistor T13 instantaneously changes from the data voltage of the previous stage to the first power supply voltage. The light-emitting device D emits light under the drive of the driving transistor T13. At this time, the driving transistor T13 operates in the saturation region until the reset stage of the next frame.

[0062] The expression for the luminous current of the light-emitting device D is as follows:

[0063] I ds =β(V Elvdd -V Data ) 2

[0064] in,

[0065] Among them, I ds V represents the driving current of the light-emitting device D; Elvdd Indicates the first power supply voltage; V Data This indicates the data voltage.

[0066] β is a parameter for the driving transistor T13. Indicates the channel width-to-length ratio of a thin-film transistor; C ox denoted by dielectric constant; μ represents equivalent mobility, which is the average drift velocity of charge carriers under a unit electric field.

[0067] Therefore, the higher the data voltage, the lower the driving current of the light-emitting device D, and the lower the brightness of the light-emitting device D. When the clock signal waveform transmitted to the far end of the Driver IC in the display panel is distorted, the actual charging time of the pixel driving circuit becomes shorter, which in turn causes the voltage written into the pixel driving circuit to be lower than expected. Ultimately, this results in the brightness of the far end of the Driver IC being higher than the brightness of the near end of the Driver IC, i.e., the display panel malfunctions.

[0068] The shift register provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0069] Firstly, the technical solution adopted to solve the technical problem of this disclosure is a shift register. Figure 4a This is a schematic diagram of the structure of a shift register provided in an embodiment of the present disclosure, as shown below. Figure 4a As shown, the shift register is configured to provide gate drive signals to the pixel driving circuit through the gate lines. The shift register includes: input sub-circuit 10, output sub-circuit 20, operation sub-circuit 30 and clock drive sub-circuit 40.

[0070] Specifically, the input sub-circuit 10 is connected with the signal input end GSTV and the pull-up node PU; wherein the pull-up node PU is a connection node between the input sub-circuit 10 and the output sub-circuit 20. The output sub-circuit 20 is connected with the first clock signal end GCB, the pull-up node PU and the signal output end Gout.

[0071] The input sub-circuit 10 is configured to receive the input signal input by the signal input end GSTV and pre-charge the pull-up node PU by the input signal. The output sub-circuit 20 is configured to output the first clock signal input to the first clock signal end GCB through the signal output end Gout under the control of the pull-up node PU potential. The operation sub-circuit 30 is configured to compare the collected pixel voltage of the pixel driving circuit and the reference voltage to generate the first control signal U1. The clock driving sub-circuit 40 is configured to input the first clock signal to the first clock signal end GCB according to the first control signal U1.

[0072] Figure 5 For the working principle of the operation sub-circuit in the embodiment of the present disclosure, as shown in Figure 4a and Figure 5 The pixel voltage of the pixel driving circuit in the embodiment of the present disclosure is actually the voltage Vcst of the storage capacitor in the pixel driving circuit. The reference voltage in the embodiment of the present disclosure is actually the sawtooth wave voltage Vsw input by the oscillator. By comparing the voltage Vcst of the storage capacitor in the pixel driving circuit and the sawtooth wave voltage Vsw input by the oscillator, a first control signal U1 with a duty cycle changing with the voltage Vcst of the storage capacitor can be output.

[0073] Further, in some embodiments, the operation sub-circuit 30 can be a PWM regulator. The non-inverting input end of the PWM regulator is connected with the oscillator, the inverting input end of the PWM regulator is connected with the first plate of the storage capacitor Cst of the pixel driving circuit, and the output end of the PWM regulator is connected with the clock driving sub-circuit 40. In the embodiment of the present disclosure, the non-inverting input end of the PWM regulator inputs the sawtooth wave voltage Vsw generated by the oscillator, the inverting input end of the PWM regulator inputs the voltage Vcst of the storage capacitor of the pixel driving circuit, and the PWM regulator compares the sawtooth wave voltage Vsw and the voltage Vcst of the storage capacitor and outputs the first control signal U1 with a certain duty cycle to achieve the final change of the clock signal input to the output sub-circuit 20.

[0074] Specifically, as shown in Figure 5As shown, the non-inverting input of the PWM regulator inputs the sawtooth wave voltage Vsw generated by the oscillator, and the inverting input of the PWM regulator inputs the voltage Vcst of the storage capacitor of the pixel driving circuit. The PWM regulator compares the sawtooth wave voltage Vsw and the voltage Vcst of the storage capacitor, and outputs a high level at the output of the PWM regulator when the sawtooth wave voltage Vsw input at the non-inverting input of the PWM regulator is greater than the voltage Vcst of the storage capacitor input at the inverting input of the PWM regulator, and outputs a low level otherwise. In this process, the period of the first control signal U1 does not change, and the duty cycle of the first control signal U1 changes when the slope of the sawtooth wave voltage Vsw generated by the oscillator changes, according to different use scenarios and settings. In this way, the first control signal U1 with a certain duty cycle is output to achieve the final change of the first clock signal input to the output sub-circuit 20. The specific parameters of the sawtooth wave signal are not particularly limited in the present disclosure.

[0075] Figure 6 The working principle of the clock driving sub-circuit in the embodiment of the present disclosure is shown in the schematic diagram of Figure 4a and Figure 6 As shown, the first control signal U1 output by the operation sub-circuit 30 has weak driving capability, and the clock driving sub-circuit 40 is needed to convert the first control signal U1 into a first clock signal with stronger driving capability. In the embodiment of the present disclosure, the clock driving sub-circuit 40 can pull up the high level voltage of the first control signal U1 to VGH and pull down the low level voltage of the first control signal U1 to VGL. For example, the first clock signal is a group of pulse wave signals, the high level voltage of which is VGH, and the low level voltage of which is VGL. The specific values of the high level voltage VGH and the low level voltage VGL are not particularly limited in the present disclosure, and can be changed according to actual products.

[0076] In the embodiment of the present disclosure, the voltage Vcst of the storage capacitor in the pixel driving circuit and the sawtooth wave voltage Vsw input by the oscillator are compared by setting the operation sub-circuit 30, and the duty cycle of the first clock signal finally input to the output sub-circuit 20 is adjusted in real time according to the comparison result, which can increase or decrease the actual charging time of the corresponding pixel driving circuit, and finally improve the display brightness difference problem caused by load distribution in the display panel.

[0077] In some embodiments, as Figure 4aAs shown, the input sub-circuit 10 includes a first transistor T21 and a second transistor T22. The control electrode of the first transistor T21 is connected to the second clock signal terminal GCK, the first electrode of the first transistor T21 is connected to the signal input terminal GSTV, the second electrode of the first transistor T21 is connected to the first electrode of the second transistor T22, the control electrode of the second transistor T22 is connected to the first voltage terminal VGL, and the second electrode of the second transistor T22 is connected to the pull-up node PU.

[0078] In some embodiments, as shown in FIG. 2, the shift register further includes a voltage holding sub-circuit 50. The voltage holding sub-circuit 50 is configured to store the second voltage under the control of the first clock signal and output the second voltage to the second electrode of the first transistor T21 under the control of the potential of the pull-down node PD. Figure 4a

[0079] In some embodiments, as shown in FIG. 3, the voltage holding sub-circuit 50 includes a seventh transistor T27 and an eighth transistor T28. The control electrode of the seventh transistor T27 is connected to the first clock signal terminal GCB, the first electrode of the seventh transistor T27 is connected to the second electrode of the first transistor T21, the second electrode of the seventh transistor T27 is connected to the first electrode of the eighth transistor T28, the control electrode of the eighth transistor T28 is connected to the pull-down node PD, and the second electrode of the eighth transistor T28 is connected to the second voltage terminal VGH. Figure 4a

[0080] In some embodiments, as shown in FIG. 4, the output sub-circuit 20 includes a third transistor T23 and a first capacitor C1. The control electrode of the third transistor T23 is connected to the pull-up node PU, the first electrode of the third transistor T23 is connected to the first clock signal terminal GCB, the second electrode of the third transistor T23 is connected to the signal output terminal Gout, the first plate of the first capacitor C1 is connected to the control electrode of the third transistor T23, and the second plate of the first capacitor C1 is connected to the second electrode of the third transistor T23. Figure 4a

[0081] In some embodiments, as shown in FIG. 5, the shift register further includes a pull-down control sub-circuit 60. The pull-down control sub-circuit 60 is configured to transmit the first voltage to the pull-down node PD under the control of the second clock signal and transmit the second clock signal to the pull-down node PD under the control of the potential of the pull-up node PU. Figure 4a

[0082] In some embodiments, as shown in FIG. 6, the pull-down control sub-circuit 60 includes a ninth transistor T29 and a tenth transistor T30. The control electrode of the ninth transistor T29 is connected to the second clock signal terminal GCK, the first electrode of the ninth transistor T29 is connected to the first voltage terminal VGL, the second electrode of the ninth transistor T29 is connected to the first electrode of the tenth transistor T30, the control electrode of the tenth transistor T30 is connected to the pull-up node PU, and the second electrode of the tenth transistor T30 is connected to the pull-down node PD. Figure 4a ​​​​As shown, the pull-down control sub-circuit 60 comprises a fourth transistor T24 and a fifth transistor T25. The control electrode of the fourth transistor T24 is connected to the second clock signal end GCK, the first electrode of the fourth transistor T24 is connected to the first voltage end VGL, and the second electrode of the fourth transistor T24 is connected to the pull-down node PD. The control electrode of the fifth transistor T25 is connected to the input sub-circuit 10, the first electrode of the fifth transistor T25 is connected to the second clock signal end GCK, and the second electrode of the fifth transistor T25 is connected to the pull-down node PD.

[0083] In some embodiments, as shown in FIG. 1, the shift register further comprises a pull-down control sub-circuit 60. Figure 4a As shown, the shift register further comprises a pull-down sub-circuit 70. The pull-down sub-circuit 70 is configured to transmit the second voltage to the signal output end Gout under the control of the pull-down node PD potential.

[0084] In some embodiments, as shown in FIG. 1, the shift register further comprises a pull-down control sub-circuit 60. Figure 4a As shown, the pull-down sub-circuit 70 comprises a sixth transistor T26 and a second capacitor C2. The control electrode of the sixth transistor T26 is connected to the pull-down node PD, the first electrode of the sixth transistor T26 is connected to the signal output end Gout, and the second electrode of the sixth transistor T26 is connected to the second voltage end VGH. The first plate of the second capacitor C2 is connected to the control electrode of the sixth transistor T26, and the second plate of the second capacitor C2 is connected to the second electrode of the sixth transistor T26.

[0085] It should be noted that the first clock signal end GCB and the second clock signal end GCK output signals have the same frequency and opposite phases in the embodiments of the present disclosure. The first transistor T21, the second transistor T22, the third transistor T23, the fourth transistor T24, the fifth transistor T25, the sixth transistor T26, the seventh transistor T27, and the eighth transistor T28 in the shift register are all taken as P-type transistors as an example. The first voltage end VGL outputs a constant low level, and the second voltage end VGH outputs a constant high level as an example.

[0086] Next, a complete shift register as shown in FIG. 1 will be described in detail. In the embodiments of the present disclosure, the shift register comprises an input sub-circuit 10, an output sub-circuit 20, an operation sub-circuit 30, a clock driving sub-circuit 40, a voltage holding sub-circuit 50, a pull-down control sub-circuit 60, and a pull-down sub-circuit 70. Figure 4a Specifically, the input sub-circuit 10 comprises a first transistor T21 and a second transistor T22; the output sub-circuit 20 comprises a third transistor T23 and a first capacitor C1; the pull-down control sub-circuit 60 comprises a fourth transistor T24 and a fifth transistor T25; the pull-down sub-circuit 70 comprises a sixth transistor T26 and a second capacitor C2; and the voltage holding sub-circuit 50 comprises a seventh transistor T27 and an eighth transistor T28.

[0087] ​

[0088] Specifically, the control electrode of the first transistor T21, the control electrode of the fourth transistor T24 and the first electrode of the fifth transistor T25 are connected with the second clock signal end GCK, the first electrode of the first transistor T21 is connected with the signal input end GSTV, the second electrode of the first transistor T21, the first electrode of the second transistor T22, the control electrode of the fifth transistor T25 and the first electrode of the seventh transistor T27 are connected with the second node N2, the control electrode of the second transistor T22 and the first electrode of the fourth transistor T24 are connected with the first voltage end VGL, the second electrode of the second transistor T22, the control electrode of the third transistor T23 and the first plate of the first capacitor C1 are connected with the pull-up node PU, the first electrode of the third transistor T23 and the control electrode of the seventh transistor T27 are connected with the first clock signal end GCB, the second electrode of the third transistor T23, the second plate of the first capacitor C1 and the first electrode of the sixth transistor T26 are connected with the signal output end Gout, the second electrode of the fourth transistor T24, the second electrode of the fifth transistor T25, the control electrode of the eighth transistor T28, the control electrode of the sixth transistor T26 and the first plate of the second capacitor C2 are connected with the pull-down node PD, the second electrode of the sixth transistor T26, the second plate of the second capacitor C2 and the second electrode of the eighth transistor T28 are connected with the second voltage end VGH, and the second electrode of the seventh transistor T27 and the first electrode of the eighth transistor T28 are connected with the first node N1.

[0089] Figure 4b For Figure 4a a driving timing diagram of the shift register shown in FIG. 1 is shown in FIG. 2, where GSTV = 1; GCK = 0; GCB = 1 in the first stage T1. Wherein "0" represents low level, "1" represents high level, which will not be repeated hereinafter. In addition, the first voltage end VGL outputs low level, and the second voltage end VGH outputs high level. Figure 4a Figure 4b At this time, the signal input end GSTV outputs high level, the second clock signal end GCK outputs low level, and the first clock signal end GCB outputs high level. The first transistor T21, the second transistor T22, the fourth transistor T24, the sixth transistor T26 and the eighth transistor T28 are all turned on, and the third transistor T23, the fifth transistor T25 and the seventh transistor T27 are all turned off.

[0090] At this time, the signal input end GSTV outputs high level, the second clock signal end GCK outputs low level, and the first clock signal end GCB outputs high level. The first transistor T21, the second transistor T22, the fourth transistor T24, the sixth transistor T26 and the eighth transistor T28 are all turned on, and the third transistor T23, the fifth transistor T25 and the seventh transistor T27 are all turned off.

[0091] ​Specifically, the second clock signal terminal GCK outputs low level, the first transistor T21 and the fourth transistor T24 are turned on. The first voltage terminal VGL outputs low level, the second transistor T22 is turned on. The high level output by the signal input terminal GSTV is transmitted to the second node N2 through the first transistor T21 and to the pull-up node PU through the second transistor T22. The low level output by the first voltage terminal VGL is transmitted to the control electrode of the eighth transistor T28 and the pull-down node PD through the fourth transistor T24, and the eighth transistor T28 and the sixth transistor T26 are both turned on, at this time, the high level output by the second voltage terminal VGH is output to the signal output terminal Gout.

[0092] In the second stage T2, GSTV = 1; GCK = 1; GCB = 0.

[0093] At this time, the signal input terminal GSTV outputs high level, the second clock signal terminal GCK outputs high level, and the first clock signal terminal GCB outputs low level. The second transistor T22, the sixth transistor T26, the seventh transistor T27 and the eighth transistor T28 are all turned on, and the first transistor T21, the fourth transistor T24, the third transistor T23 and the fifth transistor T25 are all turned off.

[0094] Specifically, the first clock signal terminal GCB outputs low level, and the seventh transistor T27 is turned on. The first voltage terminal VGL outputs low level, and the second transistor T22 is turned on. Under the control of the pull-down node PD, the sixth transistor T26 and the eighth transistor T28 are turned on, at this time, the high level output by the second voltage terminal VGH is output to the signal output terminal Gout.

[0095] In the third stage T3, GSTV = 0; GCK = 0; GCB = 1. At this time, the second clock signal terminal GCK outputs low level, and the first transistor T21 and the fourth transistor T24 are turned on. The low level output by the signal input terminal GSTV is transmitted to the second node N2 through the first transistor T21, and then transmitted to the pull-up node PU through the turned-on second transistor T22. Under the control of the second node N2, the fifth transistor T25 is turned on. The low level output by the first voltage terminal VGL is transmitted to the pull-down node PD through the fourth transistor T24, and the low level output by the second clock signal terminal GCK is transmitted to the pull-down node PD through the fifth transistor T25.

[0096] Specifically, the eighth transistor T28 is turned on, the seventh transistor T27 is turned off, and the high level output by the second voltage terminal VGH is transmitted through the eighth transistor T28, which can be stored in the parasitic capacitor GS formed by the gate and the source (or the drain) of the seventh transistor T27, and the parasitic capacitor GD formed by the gate and the drain (or the source) of the eighth transistor T28, that is, the high level output by the second voltage terminal VGH is stored at the first node N1.

[0097] Under the control of the pull-up node PU, the third transistor T23 is turned on, and the high level output by the first clock signal end GCB is transmitted to the signal output end Gout. Under the control of the pull-down node PD, the sixth transistor T26 is turned on, and the high level output by the second voltage end VGH is transmitted to the signal output end Gout.

[0098] In the fourth stage T4, GSTV = 1; GCK = 1; GCB = 0.

[0099] At this time, the second clock signal end GCK outputs a high level, and the first transistor T21 and the fourth transistor T24 are cut off. Under the bootstrap action of the first capacitor C1, the pull-up node PU keeps a low level. At this time, the third transistor T23 keeps the conductive state, and outputs the low level of the first clock signal end GCB to the signal output end Gout. Under the control of the pull-up node PU, the fifth transistor T25 is turned on, and the high level output by the second clock signal end GCK is transmitted to the pull-down node PD. At this time, the eighth transistor T28 and the sixth transistor T26 are cut off.

[0100] In the fifth stage T5, GSTV = 1; GCK = 0; GCB = 1.

[0101] At this time, under the control of the low level output by the second clock signal end GCK, the first transistor T21 and the fourth transistor T24 are turned on, the high level output by the signal input end GSTV is transmitted to the pull-up node PU, and the third transistor T23 and the fifth transistor T25 are cut off.

[0102] The low level of the first voltage end VGL is transmitted to the pull-down node PD through the fourth transistor T24, the sixth transistor T26 is turned on, and the eighth transistor T28 is turned on. The high level of the second voltage end VGH is transmitted to the signal output end Gout through the sixth transistor T26, and is stored to the first node N1 through the eighth transistor T28. Under the control of the first clock signal end GCB, the seventh transistor T27 is cut off.

[0103] In the sixth stage T6, GSTV = 1; GCK = 1; GCB = 0.

[0104] At this time, the first transistor T21 and the fourth transistor T24 are turned off under the control of the high level of the second clock signal terminal GCK. The pull-down node PD keeps the low level of the previous stage under the discharge of the second capacitor C2. At this time, the sixth transistor T26 and the eighth transistor T28 are turned on. Under the control of the low level of the first clock signal terminal GCB, the seventh transistor T27 is turned on, and the high level at the first node N1 is transmitted to the second node N2 and the pull-up node PU, and the third transistor T23 and the fifth transistor T25 are turned off. The high level of the second voltage terminal VGH is transmitted to the signal output terminal Gout through the sixth transistor T26, and the signal output terminal Gout keeps the high level output.

[0105] In the embodiment of the present disclosure, the effective level input to the pixel driving circuit as shown in Figure 3a In the fourth stage T4, the low level of the first clock signal terminal GCB is output to the signal output terminal Gout, so that the data voltage written on the data line Data of the pixel driving circuit as shown in Figure 3a

[0106] In some embodiments, when the voltage Vcst of the storage capacitor is relatively low, the display brightness of the display panel at this position is relatively high in actual use. By changing the first clock signal output by the signal output terminal Gout, the duration of the low level of the first clock signal can be increased, so that the pixel charging time is increased, that is, the voltage Vcst of the storage capacitor is increased, and then the brightness of the display panel is reduced, and finally the technical effect of improving the local bright defect on the display panel is achieved.

[0107] In some embodiments, when the voltage Vcst of the storage capacitor is relatively high, the display brightness of the display panel at this position is relatively low in actual use. By changing the first clock signal output by the signal output terminal Gout, the duration of the low level of the first clock signal can be reduced, so that the pixel charging time is reduced, that is, the voltage Vcst of the storage capacitor is reduced, and then the brightness of the display panel is increased, and finally the technical effect of improving the local dark defect on the display panel is achieved.

[0108] It should be noted that the transistors in the shift register and the transistors in the pixel driving circuit in the embodiment of the present disclosure are all taken as P-type transistors for illustration. When the transistors in the shift register and the transistors in the pixel driving circuit are N-type transistors, part of the control signals need to be inverted, and the positions of the first voltage terminal VGL and the second voltage terminal VGH need to be exchanged, but the working process of the shift register can be obtained by analogy, and details are not described here. ​

[0109] In a second aspect, the embodiments of the present disclosure further provide a gate drive circuit, which comprises a plurality of cascaded shift registers according to any one of the above embodiments. Wherein, the signal input end GSTV of the first stage shift register is connected to the start signal end, and the shift register starts to work after the start signal end inputs the start signal; and the signal output end Gout of the current stage shift register is connected to the reset signal end of the previous stage shift register and the signal input end GSTV of the next stage shift register, except for the first stage shift register. The gate drive circuit in the embodiments of the present disclosure has the same technical effects as the shift register provided in the above embodiments, and will not be described here.

[0110] In a third aspect, the embodiments of the present disclosure further provide a display device, which comprises the gate drive circuit according to any one of the above embodiments. The gate drive circuit in the display device provided by the embodiments of the present disclosure has the same technical effects as the shift register provided in the above embodiments, and since the structure and advantages of the shift register have been described in detail in the above embodiments, they will not be described here.

[0111] It should be noted that in the embodiments of the present disclosure, the display device can be an organic light emitting diode display device or a liquid crystal display device, and the present disclosure does not make special limitations thereon. For example, the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0112] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the present disclosure, but the present disclosure is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the present disclosure.

Claims

1. A shift register configured to provide a gate drive signal for a pixel driving circuit, characterized by, The shift register comprises: An input sub-circuit, an output sub-circuit, an operation sub-circuit and a clock driving sub-circuit; wherein, The input sub-circuit is configured to receive an input signal and pre-charge a pull-up node by the input signal; the pull-up node is a connecting node between the input sub-circuit and the output sub-circuit; The output sub-circuit is configured to output a first clock signal input to a first clock signal terminal through a signal output terminal under the control of a potential of the pull-up node; The operation sub-circuit is configured to compare a pixel voltage collected from the pixel driving circuit with a reference voltage to generate a first control signal; The clock driving sub-circuit is configured to input the first clock signal to the first clock signal terminal according to the first control signal.

2. The shift register of claim 1, wherein, The reference voltage is a sawtooth wave voltage.

3. The shift register of claim 1, wherein, The input sub-circuit comprises a first transistor and a second transistor; The control electrode of the first transistor is connected to a second clock signal terminal, the first electrode of the first transistor is connected to a signal input terminal, the second electrode of the first transistor is connected to the first electrode of the second transistor, the control electrode of the second transistor is connected to a first voltage terminal, and the second electrode of the second transistor is connected to a pull-up node.

4. The shift register of claim 3, wherein, Further comprising a voltage holding sub-circuit; The voltage holding sub-circuit is configured to store a second voltage under the control of the first clock signal and output the second voltage to the second electrode of the first transistor under the control of a potential of a pull-down node.

5. The shift register of claim 4, wherein, The voltage holding sub-circuit comprises a seventh transistor and an eighth transistor; The control electrode of the seventh transistor is connected to the first clock signal terminal, the first electrode of the seventh transistor is connected to the second electrode of the first transistor, the second electrode of the seventh transistor is connected to the first electrode of the eighth transistor, the control electrode of the eighth transistor is connected to the pull-down node, and the second electrode of the eighth transistor is connected to a second voltage terminal.

6. The shift register of claim 1, wherein, The output sub-circuit comprises a third transistor and a first capacitor; The control electrode of the third transistor is connected to the pull-up node, the first electrode of the third transistor is connected to the first clock signal terminal, the second electrode of the third transistor is connected to the signal output terminal, the first plate of the first capacitor is connected to the control electrode of the third transistor, and the second plate of the first capacitor is connected to the second electrode of the third transistor.

7. The shift register of claim 1, wherein, Further comprising a pull-down control sub-circuit; The pull-down control sub-circuit is configured to transmit a first voltage to the pull-down node under the control of a second clock signal and transmit the second clock signal to the pull-down node under the control of the potential of the pull-up node.

8. The shift register of claim 7, wherein, The pull-down control sub-circuit comprises a fourth transistor and a fifth transistor; The control electrode of the fourth transistor is connected to the second clock signal terminal, the first electrode of the fourth transistor is connected to the first voltage terminal, the second electrode of the fourth transistor is connected to the pull-down node, the control electrode of the fifth transistor is connected to the input sub-circuit, the first electrode of the fifth transistor is connected to the second clock signal terminal, and the second electrode of the fifth transistor is connected to the pull-down node.

9. The shift register of claim 1, wherein, Further comprising a pull-down sub-circuit; The pull-down sub-circuit is configured to transmit a second voltage to the signal output terminal under the control of the potential of the pull-down node.

10. The shift register of claim 9, wherein, The pull-down sub-circuit comprises a sixth transistor and a second capacitor; The control electrode of the sixth transistor is connected to a pull-down node, the first electrode of the sixth transistor is connected to a signal output end, and the second electrode of the sixth transistor is connected to a second voltage end; the first plate of the second capacitor is connected to the control electrode of the sixth transistor, and the second plate of the second capacitor is connected to the second electrode of the sixth transistor.

11. A gate drive circuit, characterized by comprising: The shift register comprises a plurality of cascaded shift registers as claimed in any one of claims 1-10; wherein, The signal input end of the first stage shift register is connected to a start signal end; In addition to the first stage shift register, the signal output end of the current stage shift register is connected to the reset signal end of the previous stage shift register and the signal input end of the next stage shift register.

12. A display device, characterized by comprising: The gate drive circuit comprises the shift register as claimed in claim 11.

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