Controller and method for off-line testing of train control and monitoring systems

Abstract

The application provides a controller for off-line test of a train control and monitoring system, comprising a core control module, a data processing module, a decoding control module, an information storage module and a display module; the core control module is connected with the data processing module, the decoding control module and the display module; the data processing module is connected with the decoding control module and the information storage module. The application can effectively test the whole system and can test the internal components of the control and monitoring system according to the maintenance requirement.

Description

Technical Field

[0001] This invention relates to the field of testing equipment technology, specifically to a controller and method for offline testing of train control and monitoring systems, and in particular to a method for overall offline testing of the train control and monitoring system enclosure and the status of each functional board. Background Technology

[0002] The electric train vehicle control and monitoring (train control module central bureau) system, as the heart of the electric train, is one of the key maintenance targets during major overhauls. To improve system stability, many critical components within the control and monitoring system require maintenance and testing during the overhaul process. To ensure the normal functioning and performance of the overall control and monitoring system, offline testing of the entire system is necessary. However, the original manufacturer has not provided system testing functionality, or has not provided all testing functionality. Existing testing primarily involves single-board testing in laboratories, which cannot provide effective overall system testing or allow for targeted testing of the control and monitoring system components according to maintenance needs.

[0003] Patent document CN113281596A discloses an offline testing system and method for an electric train traction system, including a controller power supply circuit, an FPGA logic control circuit, a DSP control chip, a processor module based on an ARM Cortex-A8 core, analog signal processing, analog signal sampling and threshold comparison circuits, digital signal input / output circuits, an 8-channel IGBT control circuit, and a traction motor speed detection circuit. The control method includes testing of traction system components and testing of the overall system function and performance. However, this patent document still has the drawback of not being able to perform effective overall testing of the system and not being able to perform targeted testing of the internal components of the control and monitoring system according to maintenance needs. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this invention is to provide a controller and method for offline testing of train control and monitoring systems.

[0005] According to the present invention, a controller for offline testing of a train control and monitoring system includes: a core control module, a data processing module, a decoding control module, an information storage module, and a display module;

[0006] The core control module is connected to the data processing module, the decoding control module, and the display module; the data processing module is connected to the decoding control module and the information storage module.

[0007] The core control module is embedded with a Linux operating system and is used to receive information transmitted from various modules of the entire controller; the data processing module is used for data decoding, data encoding, and data packet format processing; the decoding control module is used for address decoding, encoding frequency division, and timer timing of various modules of the entire controller; the information storage module is used to store train control module fault information; and the display module is a human-computer interaction module.

[0008] Preferably, the core control module adopts a Linux system core control board;

[0009] The Linux system core control board includes an AM335x-CPU processor, an EMMC-Flash memory chip, a DDR3-SDRAM chip, an Ethernet communication module, and an LCD touch screen interface.

[0010] The AM335x-CPU processor is connected to the EMMC-Flash memory chip, the DDR3-SDRAM chip, and the Ethernet communication module; the AM335x-CPU processor is connected to the display module through the LCD touch screen interface.

[0011] The EMMC-Flash storage chip is used to store the Linux embedded operating system, including the U-boot boot file, kernel, and file system; the DDR3-SDRAM chip is used as the system's running memory; the Ethernet communication module is used to implement IP allocation, network connection, data transmission, and subsequent system upgrades to a controller with an IoT module; the LCD touch screen interface is used to connect to the display module.

[0012] The AM335x-CPU processor is connected to the data control module and the information storage module.

[0013] Preferably, the data control module includes an MC68360 controller with an embedded HDLC controller, a communication module, a power management module, a Flash chip, and a first SRAM access memory.

[0014] The MC68360 controller is connected to the power management module and the communication module; the communication module is connected to the Flash chip and the first SRAM access memory.

[0015] The MC68360 controller with embedded HDLC controller is used to encode and decode HDLC frame format data; the power management module provides power to the entire data control module; the Flash chip is used to store the boot program for the MC68360 controller; the first SRAM access memory is used as the running memory of the MC68360 controller.

[0016] The communication module is used to send encoded HDLC frame format data to the train control module via RS-485 protocol or to decode data sent from the train control module via RS-485 protocol into HDLC frame format data.

[0017] The Flash chip and the first SRAM access memory are connected to the core control module, and the MC68360 controller is connected to the information storage module.

[0018] Preferably, the MC68360 controller is configured as a single unit;

[0019] The power management module is configured as one;

[0020] The communication module is configured as one, including 232 serial communication and 485 communication;

[0021] The Flash chip is configured as one, and the size of the Flash chip is 512KB;

[0022] The SRAM access memory is configured as two, and the size of the SRAM access memory is 4Mbit.

[0023] Preferably, the decoding control module uses an FPGA chip;

[0024] The FPGA chip is connected to the information storage module.

[0025] Preferably, the information storage module includes a second SRAM memory, a supercapacitor, and a button battery;

[0026] The supercapacitor is connected to the second SRAM access memory, and the button battery is connected to the second SRAM access memory;

[0027] The second SRAM memory is used to store the status information and fault information of each board in the train control module; the supercapacitor is used as a power supply to maintain the second SRAM memory in the event of power failure; the button battery is used to provide auxiliary power to the second SRAM memory.

[0028] The second SRAM access memory is connected to the decoding control module, the core control module, and the data control module.

[0029] Preferably, the second SRAM access memory is configured to have four SRAM access memories, and the size of the second SRAM access memory is 4 Mbit;

[0030] The supercapacitor is configured as one unit, and the capacitance of the supercapacitor is 0.1uF;

[0031] The button cell battery is configured as one, and the voltage of the button cell battery is 3.3V.

[0032] Preferably, the display module is an LCD touchscreen;

[0033] The LCD touchscreen includes a display, a power interface, and an LCD flexible flat cable interface; the display is connected to the power interface and the LCD flexible flat cable interface.

[0034] The display is used to show the startup information, time, temperature, and status of each board in the train control module of the entire system; the power interface is used to power the display; the LCD flexible flat cable interface is used to connect the display and the core control module, and the core control module sends the data processing results to the display through the LCD flexible flat cable.

[0035] Preferably, it also includes two DB9 serial ports and an HDLC interface;

[0036] The two DB9 serial ports are: one serial port as an RS232 serial port, used for offline testing of the train control and monitoring system, controller debugging, monitoring, software updates, and fault reading; and the other serial port as an RS-485 data transmission interface for the communication module within the data processing module.

[0037] The present invention also provides a control method for offline testing of a train control and monitoring system, based on the above-mentioned controller for offline testing of a train control and monitoring system, specifically including the following steps:

[0038] Step 1: Control, function, and data transmission and reading commands are issued through the LCD touch screen (which serves as the display module) and the Linux system core control board (which serves as the core control module);

[0039] Step 2: The corresponding board IDs in the train control module are sequentially decoded by the FPGA decoding module through the Linux core control board to form addresses and then sent to the MC68360 controller of the embedded HDLC controller in the data processing module.

[0040] Step 3: The MC68360 controller packages the obtained data into HDLC frame format data packets according to the HDLC communication protocol. After processing, the data is sent to the board in the train control system through the RS-485 serial port. Each data transmission is recorded once.

[0041] Step 4: If the corresponding ID in the train control system does not respond with any data, the packaged data is sent out again through the MC68360 controller. If there is still no response after 20 attempts, the data transmission is stopped. The MC68360 controller detects that the ID board has a communication fault and generates a new data packet. The data is then transmitted to the Linux system core control board, which processes the data and sends the processing result to the display module via the LCD flexible cable, displaying that the corresponding ID board has a communication failure.

[0042] Step 5: When the board in the train control system receives the instruction corresponding to its ID, it sends a feedback signal through the MC68360 controller. The MC68360 controller decodes the HDLC data frame in the feedback to extract the data.

[0043] Step 6: The decoded data is analyzed and processed by the MC68360 controller. Part of the data is stored in the second SRAM memory on the board, and part is transmitted to the Linux system core control board. After the data is processed and converted, it is displayed on the LCD touch screen that the board is communicating normally and can be tested internally.

[0044] Step 7: Select a test board with no communication faults to verify the internal ROM data. The LCD display will transmit the test board's internal ROM data verification command and the board ID command to the Linux system core control board. The Linux core control board will process the data and send it to the MC68360 controller of the embedded HDLC controller in the data processing module.

[0045] Step 8: The MC68360 controller packages the acquired data according to the HDLC communication protocol, forming a data packet in HDLC frame format, and sends it to the board in the train control module through the RS-485 serial port after processing.

[0046] Step 9: After the board in the train control system obtains the instruction corresponding to its ID, it makes the corresponding execution command according to the decoded data command, and sends the result obtained after the execution operation to the data processing module of the offline test controller of the train control and monitoring system through the RS-485 protocol.

[0047] Step 10: After the data is parsed and processed by the data processing module, it is sent to the Linux system core control board. The Linux core control board processes and calculates the data to obtain the verification and test results of the internal ROM data of the board, and transmits the results to the LCD touch screen for display.

[0048] Step 11: If the ROM data verification and test results are abnormal, the Linux system core control board will save the abnormal board ID and fault code into the second SRAM memory;

[0049] Step 12: Read the fault codes and IDs stored in the second SRAM through the RS-232 serial port to locate and maintain the faults;

[0050] Step 13: Test the SRAM inside the train control system board, read the board program version, the temperature sensor inside the board, the voltage and current sensor inside the board, etc. in sequence. The operation process is the same as steps 7 to 12.

[0051] Compared with the prior art, the present invention has the following beneficial effects:

[0052] 1. This invention can comprehensively test the functions of each board in the train control module system box in a static environment according to the HDLC encoding protocol, and intuitively reflect them on the LCD display screen. It can also further display the fault of a certain part of a faulty board and accurately locate the fault information point.

[0053] 2. This invention can greatly reduce the cost of major overhauls and maintenance of trains, and make the maintenance of train components more convenient and faster;

[0054] 3. This invention can perform effective overall testing of the system and can conduct targeted testing of internal components of the control and monitoring system according to maintenance needs;

[0055] 4. This invention can ensure the normal functioning of the central control unit of the train control module offline. Attached Figure Description

[0056] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0057] Figure 1 This is an overall structural block diagram of the controller for offline testing of the train control and monitoring system of the present invention;

[0058] Figure 2 This is a structural block diagram of the Linux system core control board of the present invention;

[0059] Figure 3 This is a system block diagram of the MC68360 controller with embedded HDLC controller of the present invention;

[0060] Figure 4 This is a structural block diagram of the information storage module of the present invention;

[0061] Figure 5 This is a flowchart of the system power-on self-test of the present invention;

[0062] Figure 6 This is a flowchart of the board function testing process of the present invention;

[0063] Figure 7 This is a flowchart illustrating the decoding process of the MC68360 controller function of the present invention.

[0064] Figure 8 This is a flowchart illustrating the coding process of the MC68360 controller function of the present invention. Detailed Implementation

[0065] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0066] Example 1

[0067] like Figures 1-8 As shown, this embodiment provides a controller for offline testing of a train control and monitoring system, including: a core control module, a data processing module, a decoding control module, an information storage module, and a display module. The core control module is connected to the data processing module, the decoding control module, and the display module; the data processing module is connected to the decoding control module and the information storage module; the core control module is embedded with a Linux operating system and is used to receive information transmitted from each module of the entire controller; the data processing module is used for data decoding, data encoding, and data packet format processing; the decoding control module is used for address decoding, encoding frequency division, and timer timing of each module of the entire controller; the information storage module is used to store fault information of the train control module; and the display module is a human-machine interaction module.

[0068] The offline test controller for the train control and monitoring system in this embodiment also includes two DB9 serial ports and an HDLC interface. The two DB9 serial ports are: one serial port as an RS232 serial port, used for offline testing of the train control and monitoring system, controller debugging, monitoring, software updates, and fault reading; and the other serial port as an RS-485 data transmission interface for the communication module within the data processing module.

[0069] The display module uses an LCD touch screen, which includes a display, a power interface, and an LCD flexible flat cable interface. The display is connected to the power interface and the LCD flexible flat cable interface. The display is used to display the startup information, time, temperature, and status of each board in the train control module of the entire system. The power interface is used to power the display. The LCD flexible flat cable interface is used to connect the display and the core control module. The core control module sends the data processing results to the display through the LCD flexible flat cable.

[0070] The data control module includes an MC68360 controller with an embedded HDLC controller, a communication module, a power management module, a Flash chip, and a first SRAM memory. The MC68360 controller is connected to the power management module and the communication module. The communication module is connected to the Flash chip and the first SRAM memory. The MC68360 controller with an embedded HDLC controller is used to encode and decode HDLC frame format data. The power management module provides power to the entire data control module. The Flash chip is used to store the boot program for starting the MC68360 controller. The first SRAM memory is used as the running memory of the MC68360 controller. The communication module is used to send the encoded HDLC frame format data to the train control module via RS-485 protocol or to decode the data sent by the train control module via RS-485 protocol into HDLC frame format data. The Flash chip and the first SRAM memory are connected to the core control module. The MC68360 controller is connected to the information storage module. The system consists of one MC68360 controller, one power management module, one communication module (including RS232 and RS485 communication), one 512KB Flash chip, and two 4Mbit SRAM memory modules.

[0071] The core control module uses a Linux system core control board, which includes an AM335x-CPU processor, an EMMC-Flash memory chip, a DDR3-SDRAM chip, an Ethernet communication module, and an LCD touchscreen interface. The AM335x-CPU processor connects to the EMMC-Flash memory chip, the DDR3-SDRAM chip, and the Ethernet communication module. The AM335x-CPU processor connects to the display module via the LCD touchscreen interface. The EMMC-Flash memory chip stores the Linux embedded operating system, including the U-boot boot file, kernel, and file system. The DDR3-SDRAM chip serves as the system's operating memory. The Ethernet communication module handles IP address allocation, network connectivity, data transmission, and future system upgrades to a controller with an IoT module. The LCD touchscreen interface connects to the display module. The AM335x-CPU processor also connects to the data control module and the information storage module.

[0072] The decoding control module uses an FPGA chip, which is connected to the information storage module. The information storage module includes a second SRAM memory, a supercapacitor, and a coin cell battery. Both the supercapacitor and the coin cell battery are connected to the second SRAM memory. The second SRAM memory stores status and fault information from various boards within the train control module. The supercapacitor serves as a power source for the second SRAM memory during power outages, and the coin cell battery provides auxiliary power. There are four second SRAM memories, each 4 Mbit in size. There is one supercapacitor with a capacitance of 0.1 μF, and one coin cell battery with a voltage of 3.3 V. The second SRAM memory connects to the decoding control module, the core control module, and the data control module.

[0073] Data transmission between the core control module and the data control module is achieved through the expansion of the external bus of the Am335x CPU processor, using a bus approach (address lines + parallel data lines + chip select, read enable, and write enable control lines) to access the data stored in the Flash chip and the first SRAM memory inside the data processing module.

[0074] The core control module and the information storage module access the second SRAM memory inside the information storage module through the expansion of the external bus of the Am335x CPU processor and the address of the FPGA chip of the decoding control module in a bus manner (address lines + parallel data lines + chip select, read enable, and write enable control lines).

[0075] The base plate pile head is allocated with the address lines + data bus + chip select, read enable, and write enable control lines after being decoded by the decoding control module.

[0076] The data control module and the information storage module communicate directly through the address bus, data bus, chip select, read enable, and write enable control lines (communication method: the MC68360 controller controls the first SRAM access memory and the second SRAM access memory to transmit data).

[0077] The entire device requires power from the power module. Since the data control module has high requirements for power quality, a separate power management module was added to the data control module because data processing and transmission require a very stable power supply.

[0078] This embodiment also provides a control method for offline testing of a train control and monitoring system, based on the aforementioned controller for offline testing of a train control and monitoring system, specifically including the following steps:

[0079] Step 1: Control, function, and data transmission and reading commands are issued through the LCD touch screen (which serves as the display module) and the Linux system core control board (which serves as the core control module);

[0080] Step 2: The corresponding board IDs in the train control module are sequentially decoded by the FPGA decoding module through the Linux core control board to form addresses and then sent to the MC68360 controller of the embedded HDLC controller in the data processing module.

[0081] Step 3: The MC68360 controller packages the obtained data into HDLC frame format data packets according to the HDLC communication protocol. After processing, the data is sent to the board in the train control system through the RS-485 serial port. Each data transmission is recorded once.

[0082] Step 4: If the corresponding ID in the train control system does not respond with any data, the packaged data is sent out again through the MC68360 controller. If there is still no response after 20 attempts, the data transmission is stopped. The MC68360 controller detects that the ID board has a communication fault and generates a new data packet. The data is then transmitted to the Linux system core control board, which processes the data and sends the processing result to the display module via the LCD flexible cable, displaying that the corresponding ID board has a communication failure.

[0083] Step 5: When the board in the train control system receives the instruction corresponding to its ID, it sends a feedback signal through the MC68360 controller. The MC68360 controller decodes the HDLC data frame in the feedback to extract the data.

[0084] Step 6: The decoded data is analyzed and processed by the MC68360 controller. Part of the data is stored in the second SRAM memory on the board, and part is transmitted to the Linux system core control board. After the data is processed and converted, it is displayed on the LCD touch screen that the board is communicating normally and can be tested internally.

[0085] Step 7: Select a test board with no communication faults to verify the internal ROM data. The LCD display will transmit the test board's internal ROM data verification command and the board ID command to the Linux system core control board. The Linux core control board will process the data and send it to the MC68360 controller of the embedded HDLC controller in the data processing module.

[0086] Step 8: The MC68360 controller packages the acquired data according to the HDLC communication protocol, forming a data packet in HDLC frame format, and sends it to the board in the train control module through the RS-485 serial port after processing.

[0087] Step 9: After the board in the train control system obtains the instruction corresponding to its ID, it makes the corresponding execution command according to the decoded data command, and sends the result obtained after the execution operation to the data processing module of the offline test controller of the train control and monitoring system through the RS-485 protocol.

[0088] Step 10: After the data is parsed and processed by the data processing module, it is sent to the Linux system core control board. The Linux core control board processes and calculates the data to obtain the verification and test results of the internal ROM data of the board, and transmits the results to the LCD touch screen for display.

[0089] Step 11: If the ROM data verification and test results are abnormal, the Linux system core control board will save the abnormal board ID and fault code into the second SRAM memory;

[0090] Step 12: Read the fault codes and IDs stored in the second SRAM through the RS-232 serial port to locate and maintain the faults;

[0091] Step 13: Test the SRAM inside the train control system board, read the board program version, the temperature sensor inside the board, the voltage and current sensor inside the board, etc. in sequence. The operation process is the same as steps 7 to 12.

[0092] Example 2

[0093] Those skilled in the art can understand this embodiment as a more specific description of Embodiment 1.

[0094] This embodiment provides a controller and method for offline testing of a train control and monitoring system, which can ensure the normal function of the central control station of the train control module offline.

[0095] The objective of this embodiment is achieved through the following technical solution:

[0096] A controller and method for offline testing of a train control and monitoring system include:

[0097] A core control board for a Linux system;

[0098] An HDLC controller MC68360 for serial data communication;

[0099] An address decoding, encoding, frequency division, and timing device;

[0100] A fault information storage device;

[0101] A 10.4-inch LCD touchscreen;

[0102] Two DB9 serial ports.

[0103] The core control board of the Linux system includes an AM335x CPU, an eMMC Flash memory chip for storing the Linux embedded operating system, a 4Gbit DDR3 SDRAM as the system's running memory, an Ethernet communication module for IP allocation, network connection and data transmission, and subsequent system upgrades to a controller with an IoT module, and an LCD touch screen interface for connecting an external 10.4-inch touch screen.

[0104] The HDLC controller MC68360 device for serial data communication includes one MC68360 chip, a power management module, a RS-485 serial communication module, a 512KB Flash memory for storing the boot program, and two 4Mbit SRAMs as the MC68360's operating memory. The various boards within the train control module communicate using the HDLC protocol; therefore, the MC68360, with its embedded HDLC controller, primarily encodes and decodes HDLC frame format data to ensure data recognition between modules. The power management module provides 5V, 3.3V, and 1.8V power to the entire device and provides power-down and overcurrent protection.

[0105] The address decoding, encoding, frequency division, and timing device is implemented using an FPGA. This device expands the memory space of the MC68360 processor and decodes and adapts the address lines and chip select lines of the MC68360 to accommodate more peripherals. The timing function serves as the clock for the entire system, allowing for timing and recording of information such as time.

[0106] The fault information storage device includes four 4Mbit static RAMs, a 0.1F supercapacitor, and a 3.3V button cell battery. The static RAM stores status and fault information from various boards within the train control module. The 0.1F supercapacitor serves as a backup power source for the static RAM. Even when the button cell battery is replaced or depleted, the data within the static RAM can still be retained for 30 minutes. The button cell battery primarily provides auxiliary power to the static RAM, ensuring that the train control module board information stored in the static RAM is not lost when the entire system is powered off.

[0107] The 10.4-inch LCD touchscreen includes a display, a power interface, and an LCD flexible flat cable interface. The display shows the system's startup information, time, temperature, and the status of each board within the train control module. The power interface supplies power to the display, and the LCD flexible flat cable connects the LCD to the Linux system's core control board.

[0108] One of the DB9 serial ports is the system debugging interface, which can also be connected to a PC to read fault information from the board inside the train control module.

[0109] One of the external communication RS-485 interfaces is mainly used to connect to other RS-485 interface boards outside the train control module system to facilitate external data communication.

[0110] Data transmission between the core control module and the data processing module is achieved through the expansion of the Am335x CPU's external bus, using a bus-like approach (address lines + parallel data lines + chip select, read enable, and write enable control lines) to access the data stored in the flash and SRAM within the data processing module. Similarly, the core control module and the status information power-down retention module also access the second SRAM within the status information power-down retention module through the expansion of the Am335x CPU's external bus and the address decoded by the FPGA, using a bus-like approach (address lines + parallel data lines + chip select, read enable, and write enable control lines). The baseboard pins are allocated with the address lines + data bus + chip select, read enable, and write enable control lines decoded by the FPGA decoding control module. The data processing module and the status information power-down retention module communicate directly through the address bus + data bus + chip select, read enable, and write enable control lines (communication method: MC68360 controls the data transmission between the first SRAM and the second SRAM).

[0111] The entire device requires power from the power module. However, because the data management and processing module has high requirements for power quality, a separate power management module was added to the data processing module because data processing and transmission require a very stable power supply.

[0112] The controller and method for offline testing of the train control and monitoring system in this embodiment include the following steps:

[0113] S1: Control, function, and data sending and reading commands are issued through the LCD touch screen as the display module and the Linux system core control board as the core control module;

[0114] S2: The Linux core control board sequentially decodes the corresponding board IDs in the train control module through the FPGA decoding module to form addresses and sends them to the MC68360 controller of the embedded HDLC controller in the data processing module.

[0115] S3: The MC68360 controller packages the acquired data according to the HDLC communication protocol, forming a data packet in HDLC frame format. After processing, it sends the data to the board in the train control system through the RS-485 serial port. Each data transmission is recorded once.

[0116] S4: If the corresponding board in the train control system does not provide any feedback, the MC68360 controller will send the packaged data again. If there is still no response after 20 attempts, the data transmission will stop. The MC68360 controller will detect the communication failure of the board and generate a new data packet. The data will be sent to the Linux system core control board. After processing the data, the Linux core control board will send the data processing result to the display module via the LCD flexible cable and display that the corresponding board has a communication failure.

[0117] S5: When the board in the train control system receives the instruction corresponding to its own ID, it sends a feedback signal to the MC68360 controller. The MC68360 controller decodes the HDLC data frame in the feedback signal to extract the data.

[0118] S6: The MC68360 controller analyzes and processes the decoded data. Part of the data is stored in the second SRAM on the substrate, and part is transmitted to the Linux core control board. After processing and conversion, the data is displayed on the LCD touch screen, indicating that the board's communication is normal and internal testing of the board can be performed.

[0119] S7: Select a board with no communication faults to test the internal ROM data checksum of the test board. The LCD display will transmit the test board's internal ROM data checksum command and the board ID command to the Linux core control board. The Linux core control board will process the data and send it to the MC68360 controller of the embedded HDLC controller in the data processing module.

[0120] S8: The MC68360 controller packages the acquired data according to the HDLC communication protocol, forming a data packet in HDLC frame format, and sends it to the board in the train control module through the RS-485 serial port after processing.

[0121] S9: When the board in the train control system obtains the instruction corresponding to its own ID, it makes the corresponding execution command based on the decoded data command, and sends the result obtained after the execution operation to the data processing module of the offline test controller of the train control and monitoring system through the RS-485 protocol.

[0122] S10: The data processing module parses and processes the data and then sends it to the Linux kernel control module. The Linux kernel control module then transmits the data to the LCD touch screen to display the board's internal ROM data verification and test results.

[0123] S11: If an abnormal test result appears on the LCD screen, save the abnormal board ID and fault code into the second SRAM access memory;

[0124] S12: Maintenance personnel can connect to the RS-232 serial port to read the fault codes and IDs stored in the second SRAM to locate and maintain the corresponding boards.

[0125] S13: Test the SRAM inside the train control system board in sequence, read the board program version, etc. The operation process is the same as S7 to S12. Among them, S7 is the test function of the board inside the train control module. For example, it can test whether there are bad blocks in the FLASH storage of the board, whether there are unreadable and writable areas in the SRAM of the board, whether the CPLD of the board is correctly decoded, and whether the AD and DA conversion functions of the board are normal, etc.

[0126] Example 3

[0127] Those skilled in the art can understand this embodiment as a more specific description of Embodiment 1.

[0128] The offline test controller for the train control and monitoring system in this embodiment comprises four main parts: a Linux system core board, an MC68360 controller with embedded HDLC, an address-encoded frequency divider and counter FPAG, a board information storage device, and an LCD display. The overall block diagram is shown below. Figure 1 As shown.

[0129] like Figure 2 As shown, this is the core board of the Linux system. After power-on and completing self-booting, the system autonomously identifies the board IDs within the train control module. This is primarily achieved by the Linux system core board sending a command to identify the board ID to the MC68360. The MC68360 decodes the command and extracts the valid data. According to the HDLC communication protocol, the data is encoded in HDLC frame format and sent to the train control module via the base plate header. If the board ID within the train control module receives the command, it sends a response to the MC68360. The MC68360 then parses the board ID and status data from the response and sends it to the Linux system core board, displaying the board ID and status information on the LCD screen. If the board within the train control module does not respond, the board ID command is resent. If no response is received after 20 repetitions, the MC68360 sends a communication failure message to the Linux system and displays "no communication" on the LCD screen. A rough execution flowchart is shown below. Figure 5 As shown.

[0130] Figure 3The diagram shows an overview of the MC68360 system with a built-in HDLC controller. Its main function is to encode command data sent from the upper-level Linux system and transmit it to the board within the train control module in HDLC communication protocol format. After receiving the data, the board executes the corresponding operation and sends the execution result back to the MC68360 in HDLC format. The MC68360 decodes the data to obtain the board's execution result and finally sends it back to the Linux system, displaying the board's test results on the LCD screen. This process is as follows... Figure 7 , Figure 8 As shown.

[0131] Figure 4 The diagram shows the fault information storage block. When the system detects a fault in the train control module board, the MC68360 decodes the data, which is then stored in SRAM. If the board is not faulty, the data is not stored. A PC can read the stored fault information via a serial port, providing a redundant solution for system fault information retrieval. The presence of supercapacitors and button batteries ensures that fault information can still be retained for a period of time after a power outage, allowing the system's operating environment to be adjusted appropriately.

[0132] Figure 6 The diagram shows the board function test flowchart. According to steps 2-5, the system has established a connection with the train control module board. By clicking the corresponding board on the LCD touch screen, you can enter the board function test interface. Click the corresponding function (e.g., ROM data verification and function test). The Linux system sends the test program data to the MC68360. The MC68360 encodes the data and sends it to the corresponding train control module board. After the board receives the data and completes the test function, it feeds back the test results to the Linux system and displays the test results on the LCD.

[0133] Example 4

[0134] Those skilled in the art can understand this embodiment as a more specific description of Embodiment 1.

[0135] This embodiment provides a controller for offline testing of a train control and monitoring system, including: a core control module, a data processing module, a decoding control module, an information storage module, and a display module. The core control module, embedded with a Linux operating system, receives information transmitted from various modules of the controller, analyzes and processes it, and generates corresponding processing results before transmitting the results back to each module. The data processing module is used for data decoding and encoding, and data packet format processing. The decoding control module is used for address decoding, encoding frequency division, and timer timing of various modules in the system. The information storage module stores fault information of the train control modules, such as the train 110V power supply module, the train controller digital input / output module, and the train control voltage and current sensor module. The display module is a human-machine interface module, allowing operators to view the status information of the train control modules.

[0136] The core control module uses a Linux system core control board. This board includes an AM335x CPU processor, eMMC Flash memory chip, DDR3 SDRAM chip, Ethernet communication module, and LCD touchscreen interface. The eMMC Flash memory chip stores the Linux embedded operating system, including the U-boot boot file, kernel, and file system. The DDR3 SDRAM chip serves as the system's operating memory. The Ethernet communication module handles IP address allocation, network connectivity, data transmission, and future system upgrades to a controller with an IoT module. The LCD touchscreen interface connects to the display module.

[0137] The data processing module includes an MC68360 controller with an embedded HDLC controller, a power management module, a communication module, a Flash chip, and a first SRAM memory. The MC68360 controller with the embedded HDLC controller is used to encode and decode data in HDLC frame format. The power management module provides a stable power supply to the entire data processing module, increasing the stability and reliability of data processing. The Flash chip stores the boot program for the MC68360. The first SRAM memory serves as the operating memory for the MC68360 controller. The communication module is used to send encoded HDLC frame format data to the train control module via RS-485 protocol or to decode data sent from the train control module via RS-485 protocol into HDLC frame format data.

[0138] The system consists of one MC68360 controller, one power management module, one communication module (including RS232 and RS485 communication), one 512KB Flash chip, and two 4Mbit SRAM memory modules.

[0139] The decoding control module uses an FPGA chip.

[0140] The information storage module includes a second SRAM (Secondary RAM Access Memory), a supercapacitor, and a button cell battery. The second SRAM stores status and fault information from various boards within the train control module. The supercapacitor serves as a power source for the second SRAM during power outages, ensuring that the stored status information remains intact for 30 minutes when the button cell battery is replaced after a power failure. The button cell battery provides auxiliary power to the second SRAM, ensuring that the stored status information is not lost after a power outage.

[0141] The second SRAM is configured with four modules, each with a size of 4 Mbit. A single supercapacitor with a capacitance of 0.1F and a single coin cell battery with a voltage of 3.3V are also included.

[0142] The display module uses an LCD touchscreen, which includes a display, a power interface, and an LCD flexible flat cable interface. The display shows the system's startup information, time, temperature, and the status of each board within the train control module; the power interface supplies power to the display; and the LCD flexible flat cable interface connects the display to the core control module, which sends data processing results to the display via the LCD flexible flat cable.

[0143] The offline test controller for the train control and monitoring system in this embodiment also includes two DB9 serial ports. One of the two DB9 serial ports is used as an RS232 serial port for debugging, monitoring, software updates, and fault reading of the offline test controller for the train control and monitoring system. The other serial port is used as an RS-485 data transmission interface for the communication module within the data processing module.

[0144] This embodiment also provides a control method for offline testing of a train control and monitoring system, based on the aforementioned controller for offline testing of a train control and monitoring system, specifically including the following steps:

[0145] Step 1: Control, function, and data transmission and reading commands are issued through the LCD touch screen (which serves as the display module) and the Linux system core control board (which serves as the core control module);

[0146] Step 2: The Linux core control board sequentially decodes the corresponding board IDs in the train control module through the FPGA decoding module to form addresses and sends them to the MC68360 controller of the embedded HDLC controller in the data processing module.

[0147] Step 3: The MC68360 controller packages the acquired data according to the HDLC communication protocol, forming a data packet in HDLC frame format. After processing, it sends the data to the board in the train control system through the RS-485 serial port. Each data transmission is recorded once.

[0148] Step 4: If the corresponding board in the train control system does not provide any feedback, the MC68360 controller will send the packaged data again. If there is still no response after 20 attempts, the data transmission will stop. The MC68360 controller will detect the communication failure of the board and generate a new data packet. The data will be sent to the Linux system core control board. After processing the data, the Linux core control board will send the data processing result to the display module via the LCD flexible cable and display that the corresponding board has a communication failure.

[0149] Step 5: When the board in the train control system receives the instruction corresponding to its own ID, it sends a feedback signal to the MC68360 controller. The MC68360 controller decodes the HDLC data frame in the feedback signal to extract the data.

[0150] Step 6: The MC68360 controller analyzes and processes the decoded data. Part of the data is stored in the second SRAM on the substrate, and part is transmitted to the Linux core control board. After processing and conversion, the data is displayed on the LCD touch screen, indicating that the board's communication is normal and internal testing of the board can be performed.

[0151] Step 7: Select a board with no communication faults to test the internal ROM data checksum. The LCD display will transmit the test board's internal ROM data checksum command and the board ID command to the Linux core control board. The Linux core control board will process the data and send it to the MC68360 controller of the embedded HDLC controller in the data processing module.

[0152] Step 8: The MC68360 controller packages the acquired data according to the HDLC communication protocol, forming a data packet in HDLC frame format, and sends it to the board in the train control module through the RS-485 serial port after processing.

[0153] Step 9: After the board in the train control system obtains the instruction corresponding to its own ID, it makes the corresponding execution command according to the decoded data command, and sends the result obtained after the execution operation to the data processing module of the offline test controller of the train control and monitoring system through the RS-485 protocol.

[0154] Step 10: The data processing module parses and processes the data and sends it to the Linux kernel control module. The Linux kernel control module then transmits the data to the LCD touch screen to display the ROM data verification and test results of the board.

[0155] Step 11: If the test results are abnormal on the LCD screen, save the abnormal board ID and fault code into the second SRAM memory;

[0156] Step 12: The maintenance personnel connect to the RS-232 serial port and read the fault codes and IDs stored in the second SRAM to locate and maintain the corresponding boards.

[0157] Step 13: Test the SRAM inside the train control system board and read the board program version in sequence. The operation process is the same as steps 7 to 12.

[0158] This invention can comprehensively test the functions of each board in the train control module system box in a static environment according to the HDLC encoding protocol, and intuitively reflect them on the LCD display screen. It can also further display that a certain part of a faulty board has failed, and accurately locate the fault information point.

[0159] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A control method for implementing a controller used in offline testing of a train control and monitoring system, characterized in that, The controller for offline testing of the train control and monitoring system includes: a core control module, a data processing module, a decoding control module, an information storage module, and a display module; The core control module is connected to the data processing module, the decoding control module, and the display module; the data processing module is connected to the decoding control module and the information storage module. The core control module is embedded with a Linux operating system and is used to receive information transmitted from various modules of the entire controller; the data processing module is used for data decoding, data encoding, and data packet format processing; the decoding control module is used for address decoding, encoding frequency division, and timer timing of various modules of the entire controller; the information storage module is used to store train control module fault information; and the display module is a human-computer interaction module. The data processing module includes an MC68360 controller with an embedded HDLC controller, a power management module, a communication module, a Flash chip, and a first SRAM access memory. The MC68360 controller is connected to the power management module and the communication module; the communication module is connected to the Flash chip and the first SRAM access memory. The MC68360 controller with embedded HDLC controller is used to encode and decode HDLC frame format data; the power management module provides power to the entire data processing module; the Flash chip is used to store the boot program for the MC68360 controller; the first SRAM access memory is used as the running memory of the MC68360 controller. The communication module is used to send encoded HDLC frame format data to the train control module via RS-485 protocol or to decode data sent from the train control module via RS-485 protocol into HDLC frame format data. The Flash chip and the first SRAM access memory are connected to the core control module, and the MC68360 controller is connected to the information storage module; The control method specifically includes the following steps: Step 1: Control, function, and data transmission and reading commands are issued through the LCD touch screen (which serves as the display module) and the Linux system core control board (which serves as the core control module); Step 2: The corresponding board IDs in the train control module are sequentially decoded by the FPGA decoding module through the Linux core control board to form addresses and then sent to the MC68360 controller of the embedded HDLC controller in the data processing module. Step 3: The MC68360 controller packages the obtained data into HDLC frame format data packets according to the HDLC communication protocol. After processing, the data is sent to the board in the train control module via RS-485 serial port. Each data transmission is recorded once. Step 4: If the corresponding ID card in the train control module does not provide any feedback, the packaged data is sent out again via the MC68360 controller. If there is still no response after 20 attempts, data transmission is stopped. The MC68360 controller detects that the ID card has a communication failure and generates a new data packet. The data is then transmitted to the Linux system core control board, which processes the data and sends the processing result to the display module via the LCD flexible cable, displaying that the corresponding ID card has a communication failure. Step 5: When the board in the train control module receives the instruction with the corresponding ID, it sends a feedback signal through the MC68360 controller. The MC68360 controller decodes the HDLC data frame from the feedback data. Step 6: The decoded data is analyzed and processed by the MC68360 controller. Part of the data is stored in the second SRAM memory on the board, and part is transmitted to the Linux system core control board. After the data is processed and converted, it is displayed on the LCD touch screen that the board communication is normal and the internal board test can be performed. Step 7: Select a test board with no communication faults to verify the internal ROM data. The LCD display will transmit the test board's internal ROM data verification command and the board ID command to the Linux system core control board. The Linux core control board will process the data and send it to the MC68360 controller of the embedded HDLC controller in the data processing module. Step 8: The MC68360 controller packages the acquired data according to the HDLC communication protocol, forming a data packet in HDLC frame format, and sends it to the board in the train control module through the RS-485 serial port after processing. Step 9: After the board in the train control module obtains the instruction corresponding to its ID, it makes the corresponding execution command according to the decoded data command, and sends the result obtained after the execution operation to the data processing module of the offline test controller of the train control and monitoring system through the RS-485 protocol. Step 10: After the data is parsed and processed by the data processing module, it is sent to the Linux system core control board. The Linux core control board processes and calculates the data to obtain the verification and test results of the internal ROM data of the board, and transmits the results to the LCD touch screen for display. Step 11: If the ROM data verification and test results are abnormal, the Linux system core control board will save the abnormal board ID and fault code into the second SRAM memory; Step 12: Read the fault codes and IDs stored in the second SRAM through the RS-232 serial port to locate and maintain the faults; Step 13: Test the SRAM inside the train control module board, read the board program version, the temperature sensor inside the board, and the voltage and current sensors inside the board in sequence. The operation process is the same as steps 7 to 12.

2. The control method for implementing an offline test controller for a train control and monitoring system according to claim 1, characterized in that, The core control module uses a Linux system core control board; The Linux system core control board includes an AM335x-CPU processor, an EMMC-Flash memory chip, a DDR3-SDRAM chip, an Ethernet communication module, and an LCD touch screen interface. The AM335x-CPU processor is connected to the EMMC-Flash memory chip, the DDR3-SDRAM chip, and the Ethernet communication module; the AM335x-CPU processor is connected to the display module through the LCD touch screen interface. The EMMC-Flash storage chip is used to store the Linux embedded operating system, including the U-boot boot file, kernel, and file system; the DDR3-SDRAM chip is used as the system's running memory; the Ethernet communication module is used to implement IP allocation, network connection, data transmission, and subsequent system upgrades to a controller with an IoT module; the LCD touch screen interface is used to connect to the display module. The AM335x-CPU processor is connected to the data processing module and the information storage module.

3. The control method for implementing an offline test controller for a train control and monitoring system according to claim 1, characterized in that, The MC68360 controller is configured as one; The power management module is configured as one; The communication module is configured as one, including 232 serial communication and 485 communication; The Flash chip is configured as one, and the size of the Flash chip is 512KB; The SRAM access memory is configured as two, and the size of the SRAM access memory is 4Mbit.

4. The control method for implementing an offline test controller for a train control and monitoring system according to claim 1, characterized in that, The decoding control module uses an FPGA chip; The FPGA chip is connected to the information storage module.

5. The control method for implementing an offline test controller for a train control and monitoring system according to claim 1, characterized in that, The information storage module includes a second SRAM memory, a supercapacitor, and a button battery; The supercapacitor is connected to the second SRAM access memory, and the button battery is connected to the second SRAM access memory; The second SRAM memory is used to store the status information and fault information of each board in the train control module; the supercapacitor is used as a power supply to maintain the second SRAM memory in the event of power failure; the button battery is used to provide auxiliary power to the second SRAM memory. The second SRAM access memory is connected to the decoding control module, the core control module, and the data processing module.

6. The control method for implementing an offline test controller for a train control and monitoring system according to claim 5, characterized in that, The second SRAM access memory is configured to have four SRAM access memories, and the size of the second SRAM access memory is 4 Mbit; The supercapacitor is configured as one unit, and the capacitance of the supercapacitor is 0.1uF; The button cell battery is configured as one, and the voltage of the button cell battery is 3.3V.

7. The control method for implementing an offline test controller for a train control and monitoring system according to claim 1, characterized in that, The display module uses an LCD touchscreen; The LCD touchscreen includes a display, a power interface, and an LCD flexible flat cable interface; the display is connected to the power interface and the LCD flexible flat cable interface. The display is used to show the startup information, time, temperature, and status of each board in the train control module of the entire system; the power interface is used to power the display. The LCD flexible flat cable interface is used to connect the display and the core control module. The core control module sends the data processing results to the display via the LCD flexible flat cable.

8. The control method for implementing an offline test controller for a train control and monitoring system according to claim 1, characterized in that, It also includes two DB9 serial ports and an HDLC interface; The two DB9 serial ports are: one serial port as an RS232 serial port, used for offline testing of the train control and monitoring system, controller debugging, monitoring, software updates, and fault reading; and the other serial port as an RS-485 data transmission interface for the communication module within the data processing module.

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