Data reading and writing method and device, electronic equipment and storage medium

Abstract

Embodiments of the present application provide a data read-write method and device, electronic equipment and storage medium, and relate to the technical field of display. The method comprises: determining a next write pointer address according to a current write pointer address, a current write pointer interval and a RAM depth of a dual-port RAM, and writing new display cache data in the RAM when there is a free storage address in the RAM; determining a next read pointer address according to a current read pointer address, a current read pointer interval and the RAM depth, and reading new display cache data from the RAM. The write pointer address of the Nth time of writing data can be the same as the read pointer address of the (N-D)th time of reading data, and D is the RAM depth, that is, one data can be read from one address of the RAM, and a new data can be immediately written in the address, thereby improving the utilization rate of the display cache and ensuring the continuity of display, and the capacity of the display cache does not need to be expanded.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a data reading and writing method, a data reading and writing device, an electronic device, and a storage medium. Background Technology

[0002] Computer display systems are a crucial component of many computer systems, including computers, mobile phones, and wearable devices. With increasingly higher monitor refresh rates, the memory access operations generated by the display controller reading pixel data from the frame buffer consume significant bus bandwidth and are also a major contributor to computer power consumption. Image compression has become an important method for reducing these overheads.

[0003] Image compression mode treats 16 (4×4) pixel tiles as a unit for compression processing, and then transmits them in tile mode. Unlike linear transmission, the pixel arrangement in tile transmission mode is no longer scanned row by row, but rather sent in a specific order within each tile. Since the display controller provides pixel data to the display device in linear mode, the display buffer inside the display controller needs to be optimized to convert the tile mode pixel data order to the linear mode pixel data order.

[0004] Normally, the size of the display buffer only needs to ensure that there are no conflicts between read and write operations and that the display data updates are continuous in time. However, in tile mode, the display data obtained by the display buffer from the upper-level module is in tile mode pixel data order, but the display buffer output data needs to be in linear mode pixel data order. Therefore, the order of reading and writing data in the display buffer is different, and the read and write logic and the size of the display buffer need to be specially designed.

[0005] In one approach, to ensure read and write operations do not conflict, the size of the display buffer needs to be increased so that read and write operations are performed on different tile rows (i.e., 4 rows of pixels). Since the pixel data output to the display device is scanned row by row, the capacity of the display buffer must at least guarantee the storage of pixel data for 4 rows of pixels. However, because this method requires read and write operations to be performed on different tile rows, the capacity of the display buffer must be increased to at least twice the minimum capacity, that is, at least the storage of pixel data for 8 rows of pixels must be guaranteed. This increases the display buffer area overhead.

[0006] In another approach, to maintain a constant display buffer capacity, it's necessary to wait until the last row of display buffer data is read before requesting data for the next tile. This method reduces display buffer utilization. Furthermore, if network latency is encountered when requesting data for the next tile row, there may be no new display buffer data available, negatively impacting display continuity. Therefore, this method amplifies the adverse effects of potential network latency on the display system. Summary of the Invention

[0007] In view of the above problems, embodiments of the present invention are proposed to provide a data read and write method that overcomes or at least partially solves the above problems, so as to solve the problem that the existing display buffer data read and write methods cannot simultaneously take into account the display buffer capacity, display buffer utilization, and display continuity.

[0008] Accordingly, embodiments of the present invention also provide a data read / write device, an electronic device, and a storage medium to ensure the implementation and application of the above methods.

[0009] To address the aforementioned problems, this invention discloses a data read / write method applied to a display controller. The display controller includes a display buffer, which includes a dual-port random access memory (RAM). The method includes:

[0010] Based on the current write pointer address of the dual-port RAM, the current write pointer spacing, and the depth of the dual-port RAM, determine the next write pointer address that needs to be written to the display cache data;

[0011] When there is a storage address in the dual-port RAM where the display cache data has already been read, the display cache data is written into the dual-port RAM according to the write pointer address of the next write operation that needs to be written to the display cache data.

[0012] Based on the current read pointer address of the dual-port RAM, the current read pointer spacing, and the depth of the dual-port RAM, determine the next read pointer address that needs to read the display cache data;

[0013] According to the read pointer address of the next required read, the display cache data is read from the dual-port RAM;

[0014] Wherein, the write pointer address corresponding to the Nth time the display cache data is written to the dual-port RAM is the same as the read pointer address corresponding to the (ND)th time the display cache data is read from the dual-port RAM; where D is the depth of the dual-port RAM.

[0015] Optionally, determining the next write pointer address to be written to the display cache based on the current write pointer address of the dual-port RAM, the current write pointer spacing, and the depth of the dual-port RAM includes:

[0016] When the current write pointer address is not the last storage address of the dual-port RAM, the sum of the quotient and remainder obtained by dividing the sum of the current write pointer address and the current write pointer distance by the depth of the dual-port RAM is determined as the next write pointer address that needs to be written to the display cache data.

[0017] When the current write pointer address is the last bit storage address of the dual-port RAM, the first bit storage address of the dual-port RAM is determined as the next write pointer address that needs to be written to the display cache data.

[0018] Optionally, determining the next read pointer address for reading the display cache data based on the current read pointer address of the dual-port RAM, the current read pointer spacing, and the depth of the dual-port RAM includes:

[0019] When the current read pointer address is not the last storage address of the dual-port RAM, the sum of the quotient and remainder obtained by dividing the sum of the current read pointer address and the current read pointer distance by the depth of the dual-port RAM is determined as the next read pointer address that needs to read the display cache data.

[0020] When the current read pointer address is the last bit storage address of the dual-port RAM, the first bit storage address of the dual-port RAM is determined as the next read pointer address that needs to read the display cache data.

[0021] Optionally, the method further includes:

[0022] When the current write pointer address is the last storage address of the dual-port RAM, the write pointer spacing corresponding to the next M writes of the display cache data into the dual-port RAM is determined based on the current write pointer spacing, the first constant, and the depth of the dual-port RAM.

[0023] Wherein, M is equal to the depth of the dual-port RAM.

[0024] Optionally, when the current write pointer address is the last storage address of the dual-port RAM, determining the write pointer interval for the subsequent M write operations of the display cache data into the dual-port RAM based on the current write pointer interval, the first constant, and the depth of the dual-port RAM includes:

[0025] The first preset value is used as the initial value of the write pointer spacing. When the first product of the current write pointer spacing and the first constant is less than the depth of the dual-port RAM, the first product is determined as the write pointer spacing corresponding to the next M writes of the display cache data into the dual-port RAM.

[0026] When the product of the current write pointer spacing and the first constant is greater than or equal to the depth of the dual-port RAM, the sum of the quotient and remainder obtained by dividing the first product by the depth of the dual-port RAM is determined as the write pointer spacing corresponding to the subsequent M writes of the display cache data into the dual-port RAM.

[0027] Optionally, the first constant is 4, and the first preset value is 1.

[0028] Optionally, the method further includes:

[0029] When the current read pointer address is the last storage address of the dual-port RAM, the read pointer spacing corresponding to the next M reads of the display cache data from the dual-port RAM is determined based on the current read pointer spacing, the second constant, and the depth of the dual-port RAM.

[0030] Wherein, M is equal to the depth of the dual-port RAM.

[0031] Optionally, when the current read pointer address is the last storage address of the dual-port RAM, determining the read pointer spacing for the subsequent M reads of the display cache data from the dual-port RAM based on the current read pointer spacing, the second constant, and the depth of the dual-port RAM includes:

[0032] Using a second preset value as the initial value of the read pointer spacing, when the second product of the current read pointer spacing and the second constant is less than the depth of the dual-port RAM, the second product is determined as the read pointer spacing corresponding to the subsequent M reads of the display cache data from the dual-port RAM;

[0033] When the second product of the current read pointer spacing and the second constant is greater than or equal to the depth of the dual-port RAM, the sum of the quotient and remainder obtained by dividing the second product by the depth of the dual-port RAM is determined as the read pointer spacing corresponding to the subsequent M reads of the display cache data from the dual-port RAM.

[0034] Optionally, the second constant is 4, and the second preset value is 4.

[0035] This invention also discloses a data read / write device, which is applied to a display controller. The display controller includes a display buffer, which includes a dual-port random access memory (RAM). The device includes:

[0036] The write pointer determination module is used to determine the next write pointer address that needs to be written to the display cache based on the current write pointer address of the dual-port RAM, the current write pointer spacing, and the depth of the dual-port RAM.

[0037] The data writing module is used to write the display cache data into the dual-port RAM according to the write pointer address of the next display cache data to be written when there is a storage address in the dual-port RAM where the display cache data has been read;

[0038] The read pointer determination module is used to determine the next read pointer address that needs to read the display cache data based on the current read pointer address of the dual-port RAM, the current read pointer spacing, and the depth of the dual-port RAM.

[0039] The data reading module is used to read the display cache data from the dual-port RAM according to the read pointer address that needs to be read next;

[0040] Wherein, the write pointer address corresponding to the Nth time the display cache data is written to the dual-port RAM is the same as the read pointer address corresponding to the (ND)th time the display cache data is read from the dual-port RAM; where D is the depth of the dual-port RAM.

[0041] Optionally, the write pointer determination module includes:

[0042] The first write pointer determination submodule is used to determine the next write pointer address that needs to be written to the display cache data when the current write pointer address is not the last storage address of the dual-port RAM by dividing the sum of the sum of the current write pointer address and the current write pointer distance by the depth of the dual-port RAM.

[0043] The second write pointer determination submodule is used to determine the initial storage address of the dual-port RAM as the next write pointer address that needs to be written to the display cache data when the current write pointer address is the last storage address of the dual-port RAM.

[0044] Optionally, the read pointer determination module includes:

[0045] The first read pointer determination submodule is used to determine the next read pointer address that needs to read the display cache data when the current read pointer address is not the last storage address of the dual-port RAM by dividing the sum of the sum of the current read pointer address and the current read pointer distance by the depth of the dual-port RAM.

[0046] The second read pointer determination submodule is used to determine the initial storage address of the dual-port RAM as the next read pointer address that needs to read the display cache data when the current read pointer address is the last storage address of the dual-port RAM.

[0047] Optionally, the device further includes:

[0048] The write pointer spacing determination module is used to determine the write pointer spacing corresponding to the next M writes of the display cache data into the dual-port RAM based on the current write pointer spacing, a first constant, and the depth of the dual-port RAM when the current write pointer address is the last storage address of the dual-port RAM.

[0049] Wherein, M is equal to the depth of the dual-port RAM.

[0050] Optionally, the write pointer spacing determination module includes:

[0051] The first write pointer spacing determination submodule is used to take a first preset value as the initial value of the write pointer spacing. When the first product of the current write pointer spacing and the first constant is less than the depth of the dual-port RAM, the first product is determined as the write pointer spacing corresponding to the next M writes of the display cache data into the dual-port RAM.

[0052] The second write pointer spacing determination submodule is used to determine the sum of the quotient and remainder obtained by dividing the first product of the current write pointer spacing and the first constant by the depth of the dual-port RAM as the write pointer spacing corresponding to the M subsequent writes of the display cache data into the dual-port RAM when the product of the current write pointer spacing and the first constant is greater than or equal to the depth of the dual-port RAM.

[0053] Optionally, the first constant is 4, and the first preset value is 1.

[0054] Optionally, the device further includes:

[0055] The read pointer spacing determination module is used to determine the read pointer spacing corresponding to the next M reads of the display cache data from the dual-port RAM based on the current read pointer spacing, the second constant, and the depth of the dual-port RAM when the current read pointer address is the last storage address of the dual-port RAM.

[0056] Wherein, M is equal to the depth of the dual-port RAM.

[0057] Optionally, the read pointer spacing determination module includes:

[0058] The first read pointer spacing determination submodule is used to take a second preset value as the initial value of the read pointer spacing. When the second product of the current read pointer spacing and the second constant is less than the depth of the dual-port RAM, the second product is determined as the read pointer spacing corresponding to the M subsequent reads of the display cache data from the dual-port RAM.

[0059] The second read pointer spacing determination submodule is used to determine the sum of the quotient and remainder obtained by dividing the second product of the current read pointer spacing and the second constant by the depth of the dual-port RAM as the read pointer spacing corresponding to the M subsequent reads of the display cache data from the dual-port RAM.

[0060] Optionally, the second constant is 4, and the second preset value is 4.

[0061] This invention also discloses an electronic device including a memory and one or more programs, wherein one or more programs are stored in the memory and configured to be executed by one or more display buffers. The one or more programs contain instructions for performing the following operations:

[0062] Based on the current write pointer address of the dual-port RAM, the current write pointer spacing, and the depth of the dual-port RAM, determine the next write pointer address that needs to be written to the display cache data;

[0063] When there is a storage address in the dual-port RAM where the display cache data has already been read, the display cache data is written into the dual-port RAM according to the write pointer address of the next write operation that needs to be written to the display cache data.

[0064] Based on the current read pointer address of the dual-port RAM, the current read pointer spacing, and the depth of the dual-port RAM, determine the next read pointer address that needs to read the display cache data;

[0065] According to the read pointer address of the next required read, the display cache data is read from the dual-port RAM;

[0066] Wherein, the write pointer address corresponding to the Nth time the display cache data is written to the dual-port RAM is the same as the read pointer address corresponding to the (ND)th time the display cache data is read from the dual-port RAM; where D is the depth of the dual-port RAM.

[0067] This invention also discloses a readable storage medium, which, when the instructions in the storage medium are executed by the display buffer of an electronic device, enables the electronic device to execute one or more of the data read / write methods described in this invention.

[0068] The embodiments of the present invention have the following advantages:

[0069] In this embodiment of the invention, the display buffer can determine the next write pointer address for writing display buffer data based on the current write pointer address, the current write pointer spacing, and the depth of the dual-port RAM, and write new display buffer data when there is free storage address in the dual-port RAM. Conversely, the display buffer can determine the next read pointer address for reading display buffer data based on the current read pointer address, the current read pointer spacing, and the depth of the dual-port RAM, and read new display buffer data from the dual-port RAM. The write pointer address for the Nth write of display buffer data can be the same as the read pointer address for the (ND)th read of display buffer data, where D is the depth of the dual-port RAM. This means that every time data is read from an address in the dual-port RAM, new data can be immediately written to that address, thereby improving the utilization rate of the display buffer, ensuring display continuity, and eliminating the need to increase the capacity of the display buffer. Attached Figure Description

[0070] Figure 1 This is a structural block diagram of a display architecture according to the present invention;

[0071] Figure 2 This is a schematic diagram illustrating the movement of a request read pointer in a FIFO queue according to the present invention;

[0072] Figure 3 This is a schematic diagram illustrating the movement of the decompression read pointer in a FIFO queue according to the present invention;

[0073] Figure 4 This is a schematic diagram of the pixel arrangement order in a tile transmission mode of the present invention;

[0074] Figure 5 This is a schematic diagram of the internal transmission sequence of decompressed image blocks according to the present invention;

[0075] Figure 6 This is a schematic diagram of the transmission order within the rearranged blocks according to the present invention;

[0076] Figure 7 This is a schematic diagram illustrating the data writing order of a dual-port RAM according to the present invention;

[0077] Figure 8 This is a flowchart illustrating the steps of an embodiment of the data reading and writing method of the present invention;

[0078] Figure 9 This is a schematic diagram of the data arrangement when a dual-port RAM is fully written in the first to third rounds according to the present invention;

[0079] Figure 10 This is a structural block diagram of an embodiment of a data read / write device according to the present invention;

[0080] Figure 11 This is a structural block diagram of an electronic device for reading and writing display data, according to an exemplary embodiment. Detailed Implementation

[0081] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0082] Before providing a detailed description of the embodiments of the present invention, the display architecture and display method used in the present invention will be introduced first.

[0083] Figure 1 A structural block diagram of a display architecture according to the present invention is shown, with reference to... Figure 1 The display architecture includes a display driver 10 and a display device 20. The display driver 10 includes a frame buffer 111 and a display controller 112. The display controller 112 may be configured with a graphics card chip 11. The frame buffer 111, also known as video memory, can be used to store rendering data processed or about to be retrieved by the graphics card chip 11. The display controller 112 can be used to retrieve frame buffer data from the frame buffer 111, process it, and then output it to the display device 20 for display. It should be noted that in practical applications, the display controller 112 may not necessarily be configured with a graphics card chip 11.

[0084] In practical applications, the display driver 10 and the display device 20 can be two separate devices, such as a host and a monitor. Of course, they can also be an integrated device, such as a host and monitor all-in-one computer. This embodiment of the invention does not specifically limit this. In practical applications, the graphics card chip 11 can be a system-on-a-chip (SoC).

[0085] Reference Figure 1 The display controller 112 may specifically include a Meta (pixel compression information) DMA (Direct Memory Access) module, a Pixel (pixel data) DMA module, a Pixel Dec (pixel data decompression) module, a tile sorting module, and a display buffer optimized for using tile transfer mode during decompression. Specifically, the Meta DMA module retrieves the compression information (hereinafter referred to as Meta information) required for pixel data decompression from the Meta frame buffer in the frame buffer 111; the Pixel DMA module retrieves the compressed pixel data from the Pixel frame buffer in the frame buffer 111; and the Pixel Dec module decompresses the compressed pixel data using the Meta information and provides it to the display buffer.

[0086] The display buffer may specifically include: a write data port, a read data port, a write pointer module, a read pointer module, and a dual-port RAM (Random Access Memory).

[0087] The write pointer module instructs the write data port to write the output of the tile sorting module to a specific location in the dual-port RAM. The read pointer module instructs the read data port to read data from a specific location in the dual-port RAM.

[0088] After data is read from the dual-port RAM, the corresponding storage space can be used to write new data. This can be understood as freeing up the storage space corresponding to the data, allowing new data to directly overwrite the original data in that space. When there is free storage space in the dual-port RAM, the display buffer can send a read request to the Pixel DMA module. The Pixel DMA module, combined with the Meta information previously obtained from the Meta DMA module, sends the read request to the Pixel frame buffer. The Meta information obtained by the Meta DMA module can be obtained beforehand from the Meta frame buffer. After obtaining the compressed pixel data from the Pixel frame buffer, the Pixel DMA module can send the compressed pixel data to the Pixel Dec module. Alternatively, after obtaining the Meta information, the Meta DMA module can also send the Meta information to the Pixel Dec module. The Pixel Dec module can decompress the compressed pixel data based on the Meta information and then send it to the tile sorting module. The decompressed pixel data is in tile format. The tile sorting module rearranges the tile pixel data received from the Pixel Dec module and sends it to the display buffer.

[0089] The image compression technology used by the display controller can compress a patch consisting of 16 (4×4) ARGB8888 or RGBA8888 color format pixels (each pixel occupies 4 bytes, representing 4 channels, each channel has 8 bits, 16 pixels for a total of 512 bits) into 0 bits, 256 bits, or 512 bits using a specific compression algorithm. 0 bits indicates the compressed patch is black or white; 256 bits indicates the compressed patch is a solid color or contains no more than 6 colors; 512 bits indicates the compressed patch is the original pixel data and has not been compressed. Meta information indicates the compression method of the patch, i.e., whether the patch is compressed to 0 bits, 256 bits, or 512 bits, with each patch corresponding to 4 bits of Meta information. The Meta information generated during compression will be used in the subsequent decompression process. The decompressed pixel data will be stored in the display buffer and then output to the display device.

[0090] The display controller provided by this invention reduces the number of memory access operations of the display controller by compressing image data, thereby reducing the bus load.

[0091] To save bandwidth, Meta information is used to change the length of pixel data read by the Pixel DMA module from the Pixel frame buffer. Meta information can also be used in the decompression process of the Pixel Dec module. The Meta DMA module is responsible for obtaining Meta information from the Meta frame buffer and providing it to the Pixel DMA module and Pixel Dec module respectively to coordinate the above operations.

[0092] Specifically, the basic working principle of the Meta DMA module is similar to a FIFO (First Input First Output) queue, the difference being that the Meta DMA module has two read pointers. The request read pointer (ReqPtr) is responsible for providing Meta information to the Pixel DMA module to determine the requested data length. The Meta DMA module can then send the Meta information indicated by the request read pointer (ReqPtr) to the Pixel DMA module. The decompression read pointer (DecPtr) is responsible for sending Meta information to the Pixel Dec module to complete the decompression work after the Pixel DMA module obtains the compressed pixel data. The Meta DMA module can then send the Meta information indicated by the decompression read pointer (DecPtr) to the Pixel DMA module.

[0093] In this invention, the FIFO queue is divided into two parts for ping-pong operation, and the Meta information is temporarily transferred through the register.

[0094] like Figure 2As shown, when the request read pointer (ReqPtr) moves to another area of ​​the FIFO queue, the Meta DMA module will move the Meta information currently pointed to by the request read pointer (ReqPtr) to another region. Figure 2 The middle part is Meta 2 1 The data is sent to the Pixel DMA module, and a read request is sent to the Meta frame buffer. The requested data length is 128 bits (i.e., 32 Meta messages). The 32 Meta messages returned by the Meta frame buffer are then stored in a register, awaiting later writing to the FIFO queue. Since the Meta DMA module can request 32 Meta messages at a time, a corresponding area of ​​the FIFO queue can include the storage space required for 32 Meta messages, as shown in the reference. Figure 2 Meta 1 1 -Meta 1 32 Occupies one region, Meta 2 1 -Meta2 32 Occupy another area.

[0095] like Figure 3 As shown, when the decompression read pointer (DecPtr) moves to another area of ​​the FIFO queue, the Meta DMA module will decompress the Meta information currently pointed to by the decompression read pointer (DecPtr). Figure 3 The middle is Meta 2 1 It sends the data to the Pixel Dec module and writes the 32 Meta information entries in the register into the FIFO queue.

[0096] It's important to note that each time the request read pointer (ReqPtr) moves, the currently indicated Meta information needs to be sent to the Pixel DMA module. However, only when crossing regions will a read request be sent to the Meta frame buffer simultaneously with sending Meta information to the Pixel DMA module. Similarly, each time the decompression read pointer (DecPtr) moves, the currently indicated Meta information needs to be sent to the Pixel Dec module. However, only when crossing regions will the Meta information be sent to the Pixel Dec module simultaneously with writing the Meta information temporarily stored in the registers into the FIFO queue.

[0097] This design allows the Pixel DMA module to acquire compressed pixel data synchronously with the Pixel Dec module to decompress the compressed pixel data, without waiting for the Meta information used for decompression to be sent and decompression to be completed before sending the next read request to the Meta frame buffer.

[0098] After obtaining the Meta information, the Pixel DMA module sends a read request to the Pixel frame buffer. The requested data length can be selected as 0 bits, 256 bits, or 512 bits, depending on the Meta information. In practical applications, the read request is transmitted from the lower layer of the Pixel DMA module to the upper layer. Specifically, when the requested data length is 0 bits, the upper layer of the Pixel DMA module intercepts the request upon receiving it and returns a virtual handshake signal to the lower layer of the Pixel DMA module. This makes the lower layer of the Pixel DMA module believe that it has successfully requested data from the Pixel frame buffer, without actually requesting data from the Pixel frame buffer, thus completing a virtual receive process. In this way, the consistency of the request and receive processes of the Pixel DMA module can be guaranteed without consuming bus bandwidth.

[0099] The Pixel Dec module can decompress the compressed pixel data obtained from the Pixel DMA module based on Meta information, and send the decompressed data to the tile sorting module. The decompression algorithm corresponds to the compression algorithm.

[0100] During the transmission of pixel data from the pixel frame buffer to the tile sorting module, the transmission is always performed in tile mode. The pixel arrangement order in tile transmission mode is as follows: Figure 4 As shown. The width of the dual-port RAM used by the display buffer can be designed to be 128 bits (4 pixels). Accordingly, the decompressed tiles can be divided into the following order according to the transmission sequence: Figure 5 The image shows four sub-tiles. During the transmission process prior to the tile sorting module, pixel data is transmitted in the order of tile 1 to tile n. Within each tile, data is sorted according to... Figure 5 The sequential transmission of sub-plots Data_dec 1 through Data_dec 4 is shown. Figure 5 Data_dec 1 in the middle includes Figure 4 Pixels 1, 2, 3, and 4 in Data_dec 2 include Figure 4 Pixels 5, 6, 7, and 8 in Data_dec 3 include Figure 4 Pixels 9, 10, 11, and 12 in Data_dec 4 include Figure 4 Pixels 13, 14, 15, and 16.

[0101] The tile sorting module can rearrange tiles according to the row of pixels, dividing them into categories such as... Figure 6 The four sub-tile data shown are sent to the display buffer in the order of tile 1-tile n, and sub-tiles Data_rod 1-Data_rod4 within each tile, for further processing. Figure 6 Data_rod 1 includes Figure 4 Pixels 1, 2, 5, and 6 in Data_rod 2 include Figure 4 Pixels 3, 4, 7, and 8 in Data_rod 3 include Figure 4 Pixels 9, 10, 13, and 14 in Data_rod4 include Figure 4 Pixels 11, 12, 15, and 16.

[0102] The display buffer is used to store reordered pixel data and to provide pixel data to the display device. Since the pixel data output to the display device is scanned line by line, to support 4K resolution, the capacity of the dual-port RAM in the display buffer should be at least 128 × 4096 bits (4 rows × 4096 pixels, a total of 1024 tiles), and correspondingly, the depth of the dual-port RAM should be at least 4096. The 1024 tiles are stored in the dual-port RAM in the write order of tile 1 to tile 1024, and the write order within a tile is sub-tiles Data_rod 1 to Data_rod 4. During pixel data read operations, pixel data with the same ordinal number among the sub-tiles within a tile are read first. Figure 7 Taking the write order shown as an example, the write order is 1. 1 ,2 1 3 1 4 1 1 2 ,2 2 3 2 4 2 , ..., 1 1024 ,2 1024 3 1024 4 1024 Accordingly, the reading order is 1. 1 1 2 , ..., 1 1024 ,2 1 ,2 2 , ..., 2 1024 3 1 3 2 , ..., 3 1024 4 1 4 2 …, 4 1024 The superscript number indicates the tile number.

[0103] Based on the above-described read / write method of dual-port RAM in the display buffer, this invention provides a data read / write method, apparatus, electronic device, and storage medium. One of the core concepts of this invention is that by adding a variable factor for the write pointer spacing when calculating the write pointer address of the dual-port RAM, and by adding a variable factor for the read pointer spacing when calculating the read pointer address of the dual-port RAM, the write pointer address corresponding to the Nth time display buffer data is written to the dual-port RAM is the same as the read pointer address corresponding to the (ND)th time display buffer data is read from the dual-port RAM, where D is the depth of the dual-port RAM. Thus, after each piece of data is read from the dual-port RAM, new data can be written to the address corresponding to that data. That is, the display buffer can immediately write the next piece of data whenever there is free space in the dual-port RAM, thereby improving the utilization rate of the display buffer, ensuring display continuity, and eliminating the need to increase the capacity of the display buffer.

[0104] Reference Figure 8 The diagram illustrates a flowchart of an embodiment of a data read / write method according to the present invention. This method can be applied to a display controller, which includes a display buffer and a dual-port RAM. Specifically, the method may include the following steps:

[0105] Step 801: Determine the next write pointer address that needs to be written to the display cache based on the current write pointer address of the dual-port RAM, the current write pointer spacing, and the depth of the dual-port RAM.

[0106] In this embodiment of the invention, a write pointer gap (WrPtrGap) register can be added. When it is necessary to determine the next write pointer address (NxtWrPtr) that needs to be written to the display cache, the current write pointer gap can be read from the write pointer gap (WrPtrGap) register. When the write pointer address (WrPtr) is updated, it can be incremented according to the corresponding write pointer gap (WrPtrGap).

[0107] When the write pointer address needs to be updated, the display buffer can determine the next write pointer address (NxtWrPtr) that needs to be written to the display buffer based on the current write pointer address (WrPtr) of the dual-port RAM, the current write pointer gap (WrPtrGap), and the depth (Depth) of the dual-port RAM.

[0108] Optionally, step 801 can be implemented in the following ways:

[0109] When the current write pointer address is not the last storage address of the dual-port RAM, the sum of the quotient and remainder obtained by dividing the sum of the current write pointer address and the current write pointer distance by the depth of the dual-port RAM is determined as the next write pointer address that needs to be written to the display cache.

[0110] When the current write pointer address is the last bit storage address of the dual-port RAM, the first bit storage address of the dual-port RAM is determined as the next write pointer address that needs to be written to the display cache.

[0111] The above steps can be represented by the following formula (1):

[0112]

[0113] In the above formula (1), rem represents the remainder symbol. In practical applications, since all parameters in formula (1) are non-negative, the rem symbol in formula (1) can also be replaced by the mod (modulo) symbol.

[0114] In practical applications, since the address of a dual-port RAM starts from 0, the last address of the dual-port RAM is (Depth-1). When the current write pointer address (WrPtr) is not located at the last position of the dual-port RAM, the next write pointer address (NxtWrPtr) is the sum of the quotient and remainder obtained by dividing the sum of the current write pointer address (WrPtr) and the current write pointer gap (WrPtrGap) by the depth (Depth) of the dual-port RAM; when the current write pointer address (WrPtr) is located at the last position of the dual-port RAM, the next write pointer address (NxtWrPtr) is the first position of the dual-port RAM.

[0115] Among them, the above formula (1) can construct the writing pattern of the display cache data, so that the write pointer address can be updated according to the current write pointer interval.

[0116] Optionally, the method further includes the following steps:

[0117] When the current write pointer address is the last storage address of the dual-port RAM, the write pointer spacing corresponding to the next M writes of the display cache data into the dual-port RAM is determined based on the current write pointer spacing, the first constant, and the depth of the dual-port RAM.

[0118] Where M equals the depth of the dual-port RAM.

[0119] In this embodiment of the invention, when the current write pointer address (WrPtr) is located at the last bit of the dual-port RAM, the current write pointer spacing (WrPtrGap) can be updated according to the current write pointer spacing (WrPtr), the first constant (k1), and the depth of the dual-port RAM (Depth) to obtain a new write pointer spacing (NxtWrPtrGap). The new write pointer spacing (NxtWrPtrGap) will be used for the subsequent M executions of step 801.

[0120] Here, M is the number of writes required to fill the display buffer once. Therefore, after each time the display buffer is filled, the write pointer spacing needs to be updated. By updating the write pointer spacing in each round, the pattern of writing data in this round can be matched with the pattern of reading data in the previous round. In this way, after reading each piece of display buffer data, a new piece of display buffer data can be written to the corresponding position of the display buffer data immediately.

[0121] Optionally, when the current write pointer address is the last storage address of the dual-port RAM, the step of determining the write pointer interval for the next M write operations of the display cache data to the dual-port RAM, based on the current write pointer spacing, the first constant, and the depth of the dual-port RAM, may specifically include:

[0122] The first preset value is used as the initial value of the write pointer spacing. When the product of the current write pointer spacing and the first constant is less than the depth of the dual-port RAM, the first product is determined as the write pointer spacing corresponding to the next M times when display cache data is written to the dual-port RAM.

[0123] When the current write pointer spacing and the first product of the first constant are greater than or equal to the depth of the dual-port RAM, the sum of the quotient and remainder obtained by dividing the first product by the depth of the dual-port RAM is determined as the write pointer spacing corresponding to the next M writes of display cache data to the dual-port RAM.

[0124] The above steps can be represented by the following formula (2):

[0125]

[0126] In practical applications, since all parameters in formula (2) are non-negative, the rem symbol in formula (2) can also be replaced with the mod symbol.

[0127] Thus, through the above formula (2), the spacing between the write pointers can be changed according to a certain pattern, so that it returns to the initial value. In this way, the data writing pattern forms a cycle and is offset by one step from the data reading pattern, which also forms a cycle. This achieves the goal of writing a new data at the corresponding position immediately after reading a data.

[0128] Optionally, the first constant (k1) can be 4, and the first preset value can be 1.

[0129] In practical applications, the initial value of the write pointer gap (WrPtrGap) can be 1. When the write pointer address (WrPtr) is located at the last bit of the dual-port RAM, if k1 times the write pointer gap (WrPtrGap) is less than the depth (Depth) of the dual-port RAM, then the write pointer gap (WrPtrGap) can be increased to k1 times the original value. If k1 times the write pointer gap (WrPtrGap) is greater than or equal to the depth (Depth) of the dual-port RAM, then the next write pointer gap (NxtWrPtrGap) is the sum of the quotient and remainder obtained by dividing k1 times the write pointer gap (WrPtrGap) by the depth (Depth) of the dual-port RAM.

[0130] Step 802: When there is a storage address in the dual-port RAM where display cache data has already been read, write the display cache data into the dual-port RAM according to the write pointer address of the next data to be written to the display cache.

[0131] In this step, when a storage address in the dual-port RAM has already contained read display cache data, it indicates that the display cache data corresponding to that address is used. Therefore, the display cache data at that address can be overwritten by new data, and the storage address can be considered a free location. The display cache can write the next display cache data to the storage address where the data has already been read; that is, the original display cache data at that address is overwritten by the new display cache data. In this embodiment of the invention, the next write pointer address (NxtWrPtr) that needs to be written to the display cache is the latest storage address where the display cache data has already been read.

[0132] Step 803: Determine the next read pointer address that needs to read display cache data based on the current read pointer address of the dual-port RAM, the current read pointer spacing, and the depth of the dual-port RAM.

[0133] In this embodiment of the invention, a read pointer spacing (RdPtrGap) register can be added. When it is necessary to determine the next read pointer address (NxtRdPtr) that needs to read display cache data, the current read pointer spacing can be read from the read pointer spacing (RdPtrGap) register. When the read pointer address (RdPtr) is updated, it can be incremented according to the corresponding read pointer spacing (RdPtrGap).

[0134] When the read pointer address needs to be updated, the display buffer can determine the next read pointer address (NxtRdPtr) that needs to read display buffer data based on the current read pointer address (RdPtr) of the dual-port RAM, the current read pointer gap (RdPtrGap), and the depth (Depth) of the dual-port RAM.

[0135] Optionally, step 803 can be implemented in the following ways:

[0136] When the current read pointer address is not the last storage address of the dual-port RAM, the sum of the quotient and remainder obtained by dividing the sum of the current read pointer address and the current read pointer distance by the depth of the dual-port RAM is determined as the next read pointer address that needs to read the display cache data.

[0137] When the current read pointer address is the last bit storage address of the dual-port RAM, the first bit storage address of the dual-port RAM is determined as the next read pointer address that needs to read the display cache data.

[0138] The above steps can be represented by the following formula (3):

[0139]

[0140] In practical applications, since all parameters in formula (3) are non-negative, the rem symbol in formula (3) can also be replaced with the mod symbol.

[0141] When the current read pointer address (RdPtr) is not located at the last bit of the dual-port RAM, the next read pointer address (NxtRdPtr) is the sum of the quotient and remainder obtained by dividing the sum of the current read pointer address (RdPtr) and the current read pointer gap (RdPtrGap) by the depth of the dual-port RAM; when the current read pointer address (RdPtr) is located at the last bit of the dual-port RAM, the next read pointer address (NxtRdPtr) is the first bit of the dual-port RAM.

[0142] Thus, the above formula (3) can construct the reading pattern of the display cache data, so that the read pointer address can be updated according to the current read pointer spacing. In this way, by adjusting the values ​​of the write pointer spacing and the degree pointer spacing, the goal of making the current round of data writing the same as the previous round of data reading can be achieved, so that after each display cache data is read, a new display cache data can be written at the corresponding position of the display cache data.

[0143] Step 804: Read the display cache data from the dual-port RAM according to the read pointer address of the next display cache data to be read.

[0144] Wherein, the write pointer address corresponding to the Nth time when display cache data is written to the dual-port RAM is the same as the read pointer address corresponding to the (ND)th time when display cache data is read from the dual-port RAM; D is the depth of the dual-port RAM.

[0145] In this embodiment of the invention, the write pointer address corresponding to the Nth write data operation is the same as the read pointer address corresponding to the (ND)th read data operation. That is, after the dual-port RAM is filled with data for the first time, each time data is read from the dual-port RAM, a free space is generated, and a new data can be written to the free space. This can improve the utilization rate of the display buffer and ensure the continuity of the display without expanding the capacity of the display buffer.

[0146] Optionally, the method further includes the following steps:

[0147] When the current read pointer address is the last storage address of the dual-port RAM, the read pointer spacing for the next M reads of display cache data from the dual-port RAM is determined based on the current read pointer spacing, the second constant, and the depth of the dual-port RAM.

[0148] Where M equals the depth of the dual-port RAM.

[0149] In this embodiment of the invention, when the current read pointer address (RdPtr) is located at the last bit of the dual-port RAM, the current read pointer spacing (RdPtrGap) can be updated according to the current read pointer spacing (RdPtr), the second constant (k2), and the depth of the dual-port RAM to obtain a new read pointer spacing (NxtRdPtrGap). The new read pointer spacing (NxtRdPtrGap) will be used for the subsequent M executions of step 803.

[0150] Here, M is the number of reads required to read data once in the display buffer. Therefore, after reading data once in the display buffer, the read pointer spacing needs to be updated. By updating the read pointer spacing in each round, the pattern of reading data in this round and writing data in the next round can be matched. In this way, after reading a piece of display buffer data, a new piece of display buffer data can be written to the corresponding position of the display buffer data immediately.

[0151] Optionally, when the current read pointer address is the last storage address of the dual-port RAM, the read pointer interval for the next M reads of display cache data from the dual-port RAM is determined based on the current read pointer interval, the second constant, and the depth of the dual-port RAM, including:

[0152] The second preset value is used as the initial value of the read pointer spacing. When the product of the current read pointer spacing and the second constant is less than the depth of the dual-port RAM, the second product is determined as the read pointer spacing corresponding to the next M reads of display cache data from the dual-port RAM.

[0153] When the current read pointer spacing and the second product of the second constant are greater than or equal to the depth of the dual-port RAM, the sum of the quotient and remainder obtained by dividing the second product by the depth of the dual-port RAM is determined as the read pointer spacing corresponding to the subsequent M reads of display cache data from the dual-port RAM.

[0154] The above steps can be represented by the following formula (4):

[0155]

[0156] In practical applications, since all parameters in formula (4) are non-negative, the rem symbol in formula (4) can also be replaced with the mod symbol.

[0157] Thus, through the above formula (4), the reading pointer spacing can be changed according to a certain pattern, so that it returns to the initial value. In this way, the data reading pattern forms a cycle and is offset one step from the data writing pattern that also forms a cycle, thereby achieving the purpose of writing a new data at the corresponding position immediately after reading a data.

[0158] Optionally, the second constant (k2) can be 4, and the second preset value can be 4.

[0159] In practical applications, the initial value of the read pointer gap (RdPtrGap) can be 4. When the read pointer address (RdPtr) is located at the last bit of the dual-port RAM, if k2 times the read pointer gap (RdPtrGap) is less than the depth of the dual-port RAM, then the read pointer gap (RdPtrGap) can be increased to k2 times the original value. If k2 times the read pointer gap (RdPtrGap) is greater than or equal to the depth of the dual-port RAM, then the next read pointer gap (NxtRdPtrGap) is the sum of the quotient and remainder obtained by dividing k2 times the read pointer gap (RdPtrGap) by the depth of the dual-port RAM.

[0160] Specifically, taking a dual-port RAM with a depth of 8, a first constant (k1) of 4, and a second constant (k2) of 4 as an example, a dual-port RAM with a depth of 8 can hold the data of two tiles. (Refer to...) Figure 9 (a) Figure 9 (b) and Figure 9 (c) From left to right, these are the arrangement of display cache data when the dual-port RAM is full in the first to third rounds of writing. The number to the left of the display cache data indicates the i-th write operation to the display cache in this round, and the number to the right of the display cache data indicates the i-th read operation from the display cache in this round.

[0161] The first round of writing process:

[0162] Reference Figure 9 (a) During the first 1-8 write operations, the write pointer spacing is initially set to 1. Based on formula (1) above, the write pointer addresses for the 1st-8th write operations to the display buffer are determined as 0, 1, 2, 3, 4, 5, 6, and 7 respectively. After the first round of writing is complete, the write pointer spacing can be updated from the initial value of 1 to 4 according to formula (2) above.

[0163] Reference Figure 9 (a) During the first 1-8 reads, the read pointer spacing is initially set to 4. Based on formula (3) above, the read pointer addresses for the 1-8 reads of the display cache data are determined as 0, 4, 1, 5, 2, 6, 3, and 7 respectively. After the first round of data is read, the read pointer spacing can be updated from the initial value of 4 to 2 according to formula (4) above.

[0164] The second round of writing process:

[0165] Reference Figure 9(b) During the 9th to 16th write operations, the write pointer interval is 4. Based on formula (1) above, the write pointer addresses for the 9th to 16th write operations to the display cache are determined as 0, 4, 1, 5, 2, 6, 3, and 7 respectively. It can be seen that the addresses of the 8 write operations in the second round correspond one-to-one with the addresses of the 8 read operations that filled the first round of data; that is, the addresses of the 9th to 16th write operations correspond one-to-one with the addresses of the 1st to 8th read operations. After the second round of data is filled, the write pointer interval can be updated from 4 to 2 according to formula (2) above.

[0166] Reference Figure 9 (b) During the 9th to 16th data reads, the read pointer spacing is 2. According to the above formula (3), the read pointer addresses for the 9th to 16th reads of the display cache data are determined as 0, 2, 4, 6, 1, 3, 5, and 7 respectively. After the data written in the second round is read, the read pointer spacing can be updated from 2 to 1 according to the above formula (4).

[0167] The third round of writing process:

[0168] Reference Figure 9 (c) During the 17th to 24th write operations, the write pointer interval is 2. According to formula (1) above, the write pointer addresses for the 17th to 24th write operations to the display cache are 0, 2, 4, 6, 1, 3, 5, and 7 respectively. It can be seen that the 8 write addresses in the third round correspond one-to-one with the 8 read addresses for the data filled in the second round, meaning the addresses for the 17th to 24th write operations correspond one-to-one with the addresses for the 9th to 16th read operations. After the third round of data is filled, the write pointer interval can be updated from 2 to 1 according to formula (2) above.

[0169] Reference Figure 9 (c) During the 17th to 24th data reads, the read pointer interval is 1. According to the above formula (3), the read pointer addresses for the 17th to 24th reads of the display cache data are determined as 0, 1, 2, 3, 4, 5, 6, and 7 respectively. After the data written in the third round is read, the read pointer interval can be updated from 1 to 4 according to the above formula (4).

[0170] At this point, the write pointer spacing returns to 1, and the read pointer spacing returns to 4. Therefore, the data read / write order of the fourth, fifth, and sixth rounds is consistent with the data read / write order of the first, second, and third rounds, and the data read / write order of the seventh, eighth, and ninth rounds is consistent with the data read / write order of the first, second, and third rounds, and so on. In other words, reading and writing the cached data will take three rounds as a cycle.

[0171] As shown in the above example, the address of the first data read in the first round is 0, and the address of the ninth data write in the second round is also 0. This means that reading data from address 0 immediately allows writing data to address 0. Similarly, the address of the second data read in the first round is 4, and the address of the tenth data write in the second round is also 4. This means that reading data from address 4 immediately allows writing data to address 4. And so on. Therefore, the data read / write method provided by this embodiment of the invention allows the display buffer to immediately write the next data whenever there is free space in the dual-port RAM. Compared to the existing first data read / write method, this saves 50% of RAM size without increasing RAM capacity, improving the utilization rate of the display buffer and reducing its area overhead. Furthermore, in the existing second method of reading and writing data, at least four sub-tiles (i.e., one tile) of display cache data must be read before four new sub-tiles of display cache data can be written. However, in the data reading and writing method provided in this embodiment of the invention, new sub-tile data can be written at the read position after each sub-tile data is read with an equal amount of display cache data. Therefore, even if network latency is encountered when requesting the writing of the next tile's data, there will still be three sub-tiles of display cache data available in the display cache. Thus, compared to the existing second method of reading and writing data, the tolerance for network latency can be increased by three times, ensuring the continuity of display.

[0172] In summary, the display cache provided by this invention saves 50% of RAM size compared to designs with the same performance, and can improve the tolerance for network latency by three times compared to designs with the same RAM size.

[0173] Finally, it should be noted that the present invention is not limited to the (4×4) pixel tile transmission mode; the specific values ​​of the first constant, the first preset value, the second constant, and the second preset value can be changed accordingly.

[0174] In this embodiment of the invention, the display buffer can determine the next write pointer address for writing display buffer data based on the current write pointer address, the current write pointer spacing, and the depth of the dual-port RAM, and write new display buffer data when there is free storage address in the dual-port RAM. Conversely, the display buffer can determine the next read pointer address for reading display buffer data based on the current read pointer address, the current read pointer spacing, and the depth of the dual-port RAM, and read new display buffer data from the dual-port RAM. The write pointer address for the Nth write of display buffer data can be the same as the read pointer address for the (ND)th read of display buffer data, where D is the depth of the dual-port RAM. This means that every time data is read from an address in the dual-port RAM, new data can be immediately written to that address, thereby improving the utilization rate of the display buffer, ensuring display continuity, and eliminating the need to increase the capacity of the display buffer.

[0175] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0176] Reference Figure 10 The diagram illustrates a structural block diagram of an embodiment of a data read / write device according to the present invention. The device 1000 is applied to a display controller, which includes a display cache, and the display cache includes a dual-port random access memory (RAM). Specifically, the device 1000 may include the following modules:

[0177] The write pointer determination module 1001 is used to determine the next write pointer address that needs to be written to the display cache based on the current write pointer address of the dual-port RAM, the current write pointer spacing, and the depth of the dual-port RAM.

[0178] The data writing module 1002 is used to write the display cache data into the dual-port RAM according to the write pointer address of the next display cache data to be written when there is a storage address in the dual-port RAM where the display cache data has been read;

[0179] The read pointer determination module 1003 is used to determine the next read pointer address that needs to read the display cache data based on the current read pointer address of the dual-port RAM, the current read pointer spacing, and the depth of the dual-port RAM.

[0180] The data reading module 1004 is used to read the display cache data from the dual-port RAM according to the read pointer address of the next display cache data to be read;

[0181] Wherein, the write pointer address corresponding to the Nth time the display cache data is written to the dual-port RAM is the same as the read pointer address corresponding to the (ND)th time the display cache data is read from the dual-port RAM; where D is the depth of the dual-port RAM.

[0182] Optionally, the write pointer determination module includes:

[0183] The first write pointer determination submodule is used to determine the next write pointer address that needs to be written to the display cache data when the current write pointer address is not the last storage address of the dual-port RAM by dividing the sum of the sum of the current write pointer address and the current write pointer distance by the depth of the dual-port RAM.

[0184] The second write pointer determination submodule is used to determine the initial storage address of the dual-port RAM as the next write pointer address that needs to be written to the display cache data when the current write pointer address is the last storage address of the dual-port RAM.

[0185] Optionally, the read pointer determination module includes:

[0186] The first read pointer determination submodule is used to determine the next read pointer address that needs to read the display cache data when the current read pointer address is not the last storage address of the dual-port RAM by dividing the sum of the sum of the current read pointer address and the current read pointer distance by the depth of the dual-port RAM.

[0187] The second read pointer determination submodule is used to determine the initial storage address of the dual-port RAM as the next read pointer address that needs to read the display cache data when the current read pointer address is the last storage address of the dual-port RAM.

[0188] Optionally, the device further includes:

[0189] The write pointer spacing determination module is used to determine the write pointer spacing corresponding to the next M writes of the display cache data into the dual-port RAM based on the current write pointer spacing, a first constant, and the depth of the dual-port RAM when the current write pointer address is the last storage address of the dual-port RAM.

[0190] Wherein, M is equal to the depth of the dual-port RAM.

[0191] Optionally, the write pointer spacing determination module includes:

[0192] The first write pointer spacing determination submodule is used to take a first preset value as the initial value of the write pointer spacing. When the first product of the current write pointer spacing and the first constant is less than the depth of the dual-port RAM, the first product is determined as the write pointer spacing corresponding to the next M writes of the display cache data into the dual-port RAM.

[0193] The second write pointer spacing determination submodule is used to determine the sum of the quotient and remainder obtained by dividing the first product of the current write pointer spacing and the first constant by the depth of the dual-port RAM as the write pointer spacing corresponding to the M subsequent writes of the display cache data into the dual-port RAM when the product of the current write pointer spacing and the first constant is greater than or equal to the depth of the dual-port RAM.

[0194] Optionally, the first constant is 4, and the first preset value is 1.

[0195] Optionally, the device further includes:

[0196] The read pointer spacing determination module is used to determine the read pointer spacing corresponding to the next M reads of the display cache data from the dual-port RAM based on the current read pointer spacing, the second constant, and the depth of the dual-port RAM when the current read pointer address is the last storage address of the dual-port RAM.

[0197] Wherein, M is equal to the depth of the dual-port RAM.

[0198] Optionally, the read pointer spacing determination module includes:

[0199] The first read pointer spacing determination submodule is used to take a second preset value as the initial value of the read pointer spacing. When the second product of the current read pointer spacing and the second constant is less than the depth of the dual-port RAM, the second product is determined as the read pointer spacing corresponding to the M subsequent reads of the display cache data from the dual-port RAM.

[0200] The second read pointer spacing determination submodule is used to determine the sum of the quotient and remainder obtained by dividing the second product of the current read pointer spacing and the second constant by the depth of the dual-port RAM as the read pointer spacing corresponding to the M subsequent reads of the display cache data from the dual-port RAM.

[0201] Optionally, the second constant is 4, and the second preset value is 4.

[0202] In this embodiment of the invention, the display buffer can determine the next write pointer address for writing display buffer data based on the current write pointer address, the current write pointer spacing, and the depth of the dual-port RAM, and write new display buffer data when there is free storage address in the dual-port RAM. Conversely, the display buffer can determine the next read pointer address for reading display buffer data based on the current read pointer address, the current read pointer spacing, and the depth of the dual-port RAM, and read new display buffer data from the dual-port RAM. The write pointer address for the Nth write of display buffer data can be the same as the read pointer address for the (ND)th read of display buffer data, where D is the depth of the dual-port RAM. This means that every time data is read from an address in the dual-port RAM, new data can be immediately written to that address, thereby improving the utilization rate of the display buffer, ensuring display continuity, and eliminating the need to increase the capacity of the display buffer.

[0203] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0204] Figure 11 This is a structural block diagram illustrating an electronic device 1100 for image filtering according to an exemplary embodiment. For example, the electronic device 1100 may be a computer, a server, etc.

[0205] Reference Figure 11 The electronic device 1100 may include one or more of the following components: a processing component 1102, a memory 1104, a power supply component 1106, a multimedia component 1108, an audio component 1110, an input / output (I / O) interface 1112, a sensor component 1114, and a communication component 1116.

[0206] Processing component 1102 typically controls the overall operation of electronic device 1100, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 1102 may include one or more processors 1120 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 1102 may include one or more modules to facilitate interaction between processing component 1102 and other components. For example, processing component 1102 may include a multimedia module to facilitate interaction between multimedia component 1108 and processing component 1102.

[0207] Memory 1104 is configured to store various types of data to support the operation of device 1100. Examples of this data include instructions for any application or method operating on electronic device 1100, contact data, phonebook data, messages, pictures, videos, etc. Memory 1104 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0208] Power supply component 1106 provides power to various components of electronic device 1100. Power supply component 1106 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 1100.

[0209] Multimedia component 1108 includes a screen that provides an output interface between the electronic device 1100 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 1108 includes a front-facing camera and / or a rear-facing camera. When the electronic device 1100 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities. The screen may be correspondingly configured with a display controller, which includes a display buffer for outputting display buffer data to the screen. The display buffer may store the display buffer data via dual-port random access memory (RAM).

[0210] Audio component 1110 is configured to output and / or input audio signals. For example, audio component 1110 includes a microphone (MIC) configured to receive external audio signals when electronic device 1100 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 1104 or transmitted via communication component 1116. In some embodiments, audio component 1110 also includes a speaker for outputting audio signals.

[0211] I / O interface 1112 provides an interface between processing component 1102 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0212] Sensor assembly 1114 includes one or more sensors for providing state assessments of various aspects of electronic device 1100. For example, sensor assembly 1114 may detect the on / off state of device 1100, the relative positioning of components such as the display and keypad of electronic device 1100, changes in position of electronic device 1100 or a component of electronic device 1100, the presence or absence of user contact with electronic device 1100, the orientation or acceleration / deceleration of electronic device 1100, and temperature changes of electronic device 1100. Sensor assembly 1114 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 1114 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 1114 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0213] Communication component 1116 is configured to facilitate wired or wireless communication between electronic device 1100 and other devices. Electronic device 1100 can access wireless networks based on communication standards, such as WiFi, 2G, or 3G, or combinations thereof. In one exemplary embodiment, communication component 1116 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 1116 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0214] In an exemplary embodiment, the electronic device 1100 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0215] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1104 including instructions, which can be executed by a processor 1120 of an electronic device 1100 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0216] A non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a display buffer of an electronic device, enables the electronic device to perform a data read / write method, the method comprising:

[0217] Based on the current write pointer address of the dual-port RAM, the current write pointer spacing, and the depth of the dual-port RAM, determine the next write pointer address that needs to be written to the display cache data;

[0218] When there is a storage address in the dual-port RAM where the display cache data has already been read, the display cache data is written into the dual-port RAM according to the write pointer address of the next write operation that needs to be written to the display cache data.

[0219] Based on the current read pointer address of the dual-port RAM, the current read pointer spacing, and the depth of the dual-port RAM, determine the next read pointer address that needs to read the display cache data;

[0220] According to the read pointer address of the next required read, the display cache data is read from the dual-port RAM;

[0221] Wherein, the write pointer address corresponding to the Nth time the display cache data is written to the dual-port RAM is the same as the read pointer address corresponding to the (ND)th time the display cache data is read from the dual-port RAM; where D is the depth of the dual-port RAM.

[0222] Optionally, determining the next write pointer address to be written to the display cache based on the current write pointer address of the dual-port RAM, the current write pointer spacing, and the depth of the dual-port RAM includes:

[0223] When the current write pointer address is not the last storage address of the dual-port RAM, the sum of the quotient and remainder obtained by dividing the sum of the current write pointer address and the current write pointer distance by the depth of the dual-port RAM is determined as the next write pointer address that needs to be written to the display cache data.

[0224] When the current write pointer address is the last bit storage address of the dual-port RAM, the first bit storage address of the dual-port RAM is determined as the next write pointer address that needs to be written to the display cache data.

[0225] Optionally, determining the next read pointer address for reading the display cache data based on the current read pointer address of the dual-port RAM, the current read pointer spacing, and the depth of the dual-port RAM includes:

[0226] When the current read pointer address is not the last storage address of the dual-port RAM, the sum of the quotient and remainder obtained by dividing the sum of the current read pointer address and the current read pointer distance by the depth of the dual-port RAM is determined as the next read pointer address that needs to read the display cache data.

[0227] When the current read pointer address is the last bit storage address of the dual-port RAM, the first bit storage address of the dual-port RAM is determined as the next read pointer address that needs to read the display cache data.

[0228] Optionally, the method further includes:

[0229] When the current write pointer address is the last storage address of the dual-port RAM, the write pointer spacing corresponding to the next M writes of the display cache data into the dual-port RAM is determined based on the current write pointer spacing, the first constant, and the depth of the dual-port RAM.

[0230] Wherein, M is equal to the depth of the dual-port RAM.

[0231] Optionally, when the current write pointer address is the last storage address of the dual-port RAM, determining the write pointer interval for the subsequent M write operations of the display cache data into the dual-port RAM based on the current write pointer interval, the first constant, and the depth of the dual-port RAM includes:

[0232] The first preset value is used as the initial value of the write pointer spacing. When the first product of the current write pointer spacing and the first constant is less than the depth of the dual-port RAM, the first product is determined as the write pointer spacing corresponding to the next M writes of the display cache data into the dual-port RAM.

[0233] When the product of the current write pointer spacing and the first constant is greater than or equal to the depth of the dual-port RAM, the sum of the quotient and remainder obtained by dividing the first product by the depth of the dual-port RAM is determined as the write pointer spacing corresponding to the subsequent M writes of the display cache data into the dual-port RAM.

[0234] Optionally, the first constant is 4, and the first preset value is 1.

[0235] Optionally, the method further includes:

[0236] When the current read pointer address is the last storage address of the dual-port RAM, the read pointer spacing corresponding to the next M reads of the display cache data from the dual-port RAM is determined based on the current read pointer spacing, the second constant, and the depth of the dual-port RAM.

[0237] Wherein, M is equal to the depth of the dual-port RAM.

[0238] Optionally, when the current read pointer address is the last storage address of the dual-port RAM, determining the read pointer spacing for the subsequent M reads of the display cache data from the dual-port RAM based on the current read pointer spacing, the second constant, and the depth of the dual-port RAM includes:

[0239] Using a second preset value as the initial value of the read pointer spacing, when the second product of the current read pointer spacing and the second constant is less than the depth of the dual-port RAM, the second product is determined as the read pointer spacing corresponding to the subsequent M reads of the display cache data from the dual-port RAM;

[0240] When the second product of the current read pointer spacing and the second constant is greater than or equal to the depth of the dual-port RAM, the sum of the quotient and remainder obtained by dividing the second product by the depth of the dual-port RAM is determined as the read pointer spacing corresponding to the subsequent M reads of the display cache data from the dual-port RAM.

[0241] Optionally, the second constant is 4, and the second preset value is 4.

[0242] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0243] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0244] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0245] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0246] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0247] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0248] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0249] The present invention has provided a detailed description of a data reading and writing method and apparatus, an electronic device, and a storage medium. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A data read / write method, characterized in that, The method is applied to a display controller, the display controller including a display buffer, the display buffer including a dual-port random access memory (RAM), the method comprising: Based on the current write pointer address of the dual-port RAM, the current write pointer spacing, and the depth of the dual-port RAM, the next write pointer address to be written to the display cache is determined, including: when the current write pointer address is not the last storage address of the dual-port RAM, an address offset operation is performed based on the current write pointer address and the current write pointer spacing, and an address constraint is applied to the offset address based on the depth of the dual-port RAM, and the result is determined as the next write pointer address to be written to the display cache; when the current write pointer address is the last storage address of the dual-port RAM, the first storage address of the dual-port RAM is determined as the next write pointer address to be written to the display cache. When there is a storage address in the dual-port RAM where the display cache data has already been read, the display cache data is written into the dual-port RAM according to the write pointer address of the next write operation that needs to be written to the display cache data. Based on the current read pointer address, the current read pointer spacing, and the depth of the dual-port RAM, the next read pointer address to read the display cache data is determined, including: when the current read pointer address is not the last storage address of the dual-port RAM, an address offset operation is performed based on the current read pointer address and the current read pointer spacing, and an address constraint is applied to the offset address based on the depth of the dual-port RAM, and the result is determined as the next read pointer address to read the display cache data; when the current read pointer address is the last storage address of the dual-port RAM, the first storage address of the dual-port RAM is determined as the next read pointer address to read the display cache data. According to the read pointer address of the next required read, the display cache data is read from the dual-port RAM; Wherein, the write pointer address corresponding to the Nth time the display cache data is written to the dual-port RAM is the same as the read pointer address corresponding to the (ND)th time the display cache data is read from the dual-port RAM; where D is the depth of the dual-port RAM.

2. The method according to claim 1, characterized in that, The step of performing an address offset operation based on the current write pointer address and the current write pointer distance, and performing address constraint processing on the offset address based on the depth of the dual-port RAM, and determining the result as the next write pointer address to be written to the display cache data, includes: The sum of the quotient and remainder obtained by dividing the sum of the current write pointer address and the current write pointer distance by the depth of the dual-port RAM is determined as the next write pointer address that needs to be written to the display cache data.

3. The method according to claim 1, characterized in that, The step of performing an address offset calculation based on the current read pointer address and the current read pointer distance, and performing address constraint processing on the offset address according to the depth of the dual-port RAM, and determining the result as the next read pointer address that needs to read the display cache data, includes: The sum of the quotient and remainder obtained by dividing the sum of the current read pointer address and the current read pointer distance by the depth of the dual-port RAM is determined as the next read pointer address that needs to read the display cache data.

4. The method according to claim 1, characterized in that, The method further includes: When the current write pointer address is the last storage address of the dual-port RAM, the write pointer spacing corresponding to the next M writes of the display cache data into the dual-port RAM is determined based on the current write pointer spacing, the first constant, and the depth of the dual-port RAM. Wherein, M is equal to the depth of the dual-port RAM.

5. The method according to claim 4, characterized in that, When the current write pointer address is the last storage address of the dual-port RAM, the write pointer spacing for the next M write operations of the display cache data into the dual-port RAM is determined based on the current write pointer spacing, a first constant, and the depth of the dual-port RAM, including: The first preset value is used as the initial value of the write pointer spacing. When the first product of the current write pointer spacing and the first constant is less than the depth of the dual-port RAM, the first product is determined as the write pointer spacing corresponding to the next M writes of the display cache data into the dual-port RAM. When the product of the current write pointer spacing and the first constant is greater than or equal to the depth of the dual-port RAM, the sum of the quotient and remainder obtained by dividing the first product by the depth of the dual-port RAM is determined as the write pointer spacing corresponding to the subsequent M writes of the display cache data into the dual-port RAM.

6. The method according to claim 5, characterized in that, The first constant is 4, and the first preset value is 1.

7. The method according to claim 1, characterized in that, The method further includes: When the current read pointer address is the last storage address of the dual-port RAM, the read pointer spacing corresponding to the next M reads of the display cache data from the dual-port RAM is determined based on the current read pointer spacing, the second constant, and the depth of the dual-port RAM. Wherein, M is equal to the depth of the dual-port RAM.

8. The method according to claim 7, characterized in that, When the current read pointer address is the last storage address of the dual-port RAM, the read pointer spacing for the subsequent M reads of the display cache data from the dual-port RAM is determined based on the current read pointer spacing, the second constant, and the depth of the dual-port RAM, including: Using a second preset value as the initial value of the read pointer spacing, when the second product of the current read pointer spacing and the second constant is less than the depth of the dual-port RAM, the second product is determined as the read pointer spacing corresponding to the subsequent M reads of the display cache data from the dual-port RAM; When the second product of the current read pointer spacing and the second constant is greater than or equal to the depth of the dual-port RAM, the sum of the quotient and remainder obtained by dividing the second product by the depth of the dual-port RAM is determined as the read pointer spacing corresponding to the subsequent M reads of the display cache data from the dual-port RAM.

9. The method according to claim 8, characterized in that, The second constant is 4, and the second preset value is 4.

10. A data read / write device, characterized in that, The device is applied to a display controller, the display controller including a display cache, the display cache including a dual-port random access memory (RAM), and the device comprising: The write pointer determination module is used to determine the next write pointer address that needs to be written to the display cache data based on the current write pointer address of the dual-port RAM, the current write pointer spacing, and the depth of the dual-port RAM; the data writing module is used to write the display cache data into the dual-port RAM based on the next write pointer address that needs to be written to the display cache data when there is a storage address in the dual-port RAM that has already read the display cache data. The read pointer determination module is used to determine the next read pointer address that needs to read the display cache data based on the current read pointer address of the dual-port RAM, the current read pointer spacing, and the depth of the dual-port RAM; the data reading module is used to read the display cache data from the dual-port RAM based on the next read pointer address that needs to read the display cache data. Wherein, the write pointer address corresponding to the Nth time the display cache data is written to the dual-port RAM is the same as the read pointer address corresponding to the (ND)th time the display cache data is read from the dual-port RAM; where D is the depth of the dual-port RAM; The write pointer determination module includes: The first write pointer determination submodule is used to perform address offset calculation based on the current write pointer address and the current write pointer distance when the current write pointer address is not the last storage address of the dual-port RAM, and to perform address constraint processing on the offset address based on the depth of the dual-port RAM, and determine the result as the next write pointer address that needs to be written to the display cache data. The second write pointer determination submodule is used to determine the initial storage address of the dual-port RAM as the next write pointer address that needs to be written to the display cache data when the current write pointer address is the last storage address of the dual-port RAM. The read pointer determination module includes: The first read pointer determination submodule is used to perform address offset calculation based on the current read pointer address and the current read pointer distance when the current read pointer address is not the last storage address of the dual-port RAM, and to perform address constraint processing on the offset address based on the depth of the dual-port RAM, and determine the result as the next read pointer address that needs to read the display cache data. The second read pointer determination submodule is used to determine the initial storage address of the dual-port RAM as the next read pointer address that needs to read the display cache data when the current read pointer address is the last storage address of the dual-port RAM.

11. The apparatus according to claim 10, characterized in that, The step of performing an address offset operation based on the current write pointer address and the current write pointer distance, and performing address constraint processing on the offset address based on the depth of the dual-port RAM, and determining the result as the next write pointer address to be written to the display cache data, includes: The sum of the quotient and remainder obtained by dividing the sum of the current write pointer address and the current write pointer distance by the depth of the dual-port RAM is determined as the next write pointer address that needs to be written to the display cache data.

12. The apparatus according to claim 10, characterized in that, The step of performing an address offset calculation based on the current read pointer address and the current read pointer distance, and performing address constraint processing on the offset address according to the depth of the dual-port RAM, and determining the result as the next read pointer address that needs to read the display cache data, includes: The sum of the quotient and remainder obtained by dividing the sum of the current read pointer address and the current read pointer distance by the depth of the dual-port RAM is determined as the next read pointer address that needs to read the display cache data.

13. The apparatus according to claim 10, characterized in that, The device further includes: The write pointer spacing determination module is used to determine the write pointer spacing corresponding to the next M writes of the display cache data into the dual-port RAM based on the current write pointer spacing, a first constant, and the depth of the dual-port RAM when the current write pointer address is the last storage address of the dual-port RAM. Wherein, M is equal to the depth of the dual-port RAM.

14. The apparatus according to claim 13, characterized in that, The write pointer spacing determination module includes: The first write pointer spacing determination submodule is used to take a first preset value as the initial value of the write pointer spacing. When the first product of the current write pointer spacing and the first constant is less than the depth of the dual-port RAM, the first product is determined as the write pointer spacing corresponding to the next M writes of the display cache data into the dual-port RAM. The second write pointer spacing determination submodule is used to determine the sum of the quotient and remainder obtained by dividing the first product of the current write pointer spacing and the first constant by the depth of the dual-port RAM as the write pointer spacing corresponding to the M subsequent writes of the display cache data into the dual-port RAM when the product of the current write pointer spacing and the first constant is greater than or equal to the depth of the dual-port RAM.

15. The apparatus according to claim 14, characterized in that, The first constant is 4, and the first preset value is 1.

16. The apparatus according to claim 10, characterized in that, The device further includes: The read pointer spacing determination module is used to determine the read pointer spacing corresponding to the next M reads of the display cache data from the dual-port RAM based on the current read pointer spacing, the second constant, and the depth of the dual-port RAM when the current read pointer address is the last storage address of the dual-port RAM. Wherein, M is equal to the depth of the dual-port RAM.

17. The apparatus according to claim 16, characterized in that, The read pointer spacing determination module includes: The first read pointer spacing determination submodule is used to take a second preset value as the initial value of the read pointer spacing. When the second product of the current read pointer spacing and the second constant is less than the depth of the dual-port RAM, the second product is determined as the read pointer spacing corresponding to the M subsequent reads of the display cache data from the dual-port RAM. The second read pointer spacing determination submodule is used to determine the sum of the quotient and remainder obtained by dividing the second product of the current read pointer spacing and the second constant by the depth of the dual-port RAM as the read pointer spacing corresponding to the M subsequent reads of the display cache data from the dual-port RAM.

18. The apparatus according to claim 17, characterized in that, The second constant is 4, and the second preset value is 4.

19. An electronic device, characterized in that, It includes memory and one or more programs, one or more of which are stored in memory and configured to be executed by one or more display buffers. The one or more programs contain instructions for performing the following operations: Based on the current write pointer address of the dual-port RAM, the current write pointer spacing, and the depth of the dual-port RAM, determine the next write pointer address that needs to be written to the display cache; this includes: when the current write pointer address is not the last storage address of the dual-port RAM, perform an address offset operation based on the current write pointer address and the current write pointer spacing, and perform address constraint processing on the offset address based on the depth of the dual-port RAM, and determine the result as the next write pointer address that needs to be written to the display cache; when the current write pointer address is the last storage address of the dual-port RAM, determine the first storage address of the dual-port RAM as the next write pointer address that needs to be written to the display cache. When there is a storage address in the dual-port RAM where the display cache data has already been read, the display cache data is written into the dual-port RAM according to the write pointer address of the next write operation that needs to be written to the display cache data. Based on the current read pointer address, the current read pointer spacing, and the depth of the dual-port RAM, determine the next read pointer address that needs to read the display cache data; this includes: when the current read pointer address is not the last storage address of the dual-port RAM, perform an address offset operation based on the current read pointer address and the current read pointer spacing, and perform address constraint processing on the offset address based on the depth of the dual-port RAM, and determine the result as the next read pointer address that needs to read the display cache data; when the current read pointer address is the last storage address of the dual-port RAM, determine the first storage address of the dual-port RAM as the next read pointer address that needs to read the display cache data. According to the read pointer address of the next required read, the display cache data is read from the dual-port RAM; Wherein, the write pointer address corresponding to the Nth time the display cache data is written to the dual-port RAM is the same as the read pointer address corresponding to the (ND)th time the display cache data is read from the dual-port RAM; where D is the depth of the dual-port RAM.

20. A readable storage medium, characterized in that, When the instructions in the storage medium are executed by the display buffer of the electronic device, the electronic device is able to perform one or more of the data read / write methods as described in claims 1-9.

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