A method for extracting single transistor interface state defects in an integrated circuit chip

By etching and testing capacitance-voltage and capacitance-frequency curves in silicon-based integrated circuit chips, and combining nonlinear fitting, the problems of accuracy and simplicity in extracting interface state defects of bipolar transistors are solved, thus improving testing precision and efficiency.

CN116859211BActive Publication Date: 2026-06-19XIDIAN UNIV
View PDF 0 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
XIDIAN UNIV
Filing Date
2023-05-26
Publication Date
2026-06-19

AI Technical Summary

Technical Problem

Existing technologies make it difficult to accurately and easily extract interface state defects of bipolar transistors in silicon-based integrated circuits, leading to chip performance degradation and failure. Furthermore, the testing methods are costly and have low accuracy.

Method used

The target transistor is obtained by etching the passivation layer and oxide layer of the bare chip. The capacitance-voltage and capacitance-frequency curves are tested using micro-nano probes. By combining nonlinear fitting, the time constant and concentration of interface state traps are determined, and the energy level of interface state traps is calculated.

Benefits of technology

This method enables rapid, sensitive, and convenient extraction of interface state defect information of transistors within bipolar integrated circuit chips, improving the accuracy of defect concentration and possessing significant practical value.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN116859211B_ABST
    Figure CN116859211B_ABST
Patent Text Reader

Abstract

This invention discloses a method for extracting interface state defects of a single transistor in an integrated circuit chip, comprising the following steps: Step 10, obtaining a bare die of a bipolar integrated circuit chip, etching the passivation layer and oxide layer of the bare die, and identifying the target transistor; Step 20, testing the target transistor using a micro-nano probe to obtain the capacitance-voltage curve and the turn-on voltage V. t Step 30, turn on voltage V t To test the initial DC bias voltage and multiple different DC bias voltages, the capacitance-frequency and resistance-frequency curves of the target transistor were measured, and the semiconductor capacitance value C was determined. s Step 40, determine R p The value of f and the determination of R p f-curve; Step 50, for R p The f-curve is nonlinearly fitted, and the interface state trap time constant τ is calculated. it and interface state trap concentration D it And calculate the interface state trap energy level E it This invention improves testing efficiency, reduces testing costs, provides high testing accuracy, and extracts comprehensive interface trap information.
Need to check novelty before this filing date? Find Prior Art