Data read / write circuits, methods and devices

Abstract

This application provides a data read / write circuit, method, and apparatus. The circuit includes a controller and a memory. The memory is used to decode instructions according to a first clock signal sent by the controller and to sample data according to a second clock signal sent by the controller. The memory includes a first storage module, a second storage module, and a mode register. The mode register stores a second synchronization parameter, and the second storage module is equipped with a second delay circuit. When reading from or writing to the first storage module, the controller synchronizes the first clock signal and the second clock signal using the first synchronization parameter. When reading from or writing to the second storage module, the controller performs a first synchronization of the first clock signal and the second clock signal using the first synchronization parameter. The memory performs a second synchronization of the first clock signal and the second clock signal using the second delay circuit and the second synchronization parameter. This application reduces clock synchronization complexity by superimposing clock synchronizations.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a data read / write circuit, method, and apparatus. Background Technology

[0002] In the semiconductor field, data is stored in memory, and data can be written to or read from memory. The data reading and writing process requires control by a controller, typically a system-on-a-chip (SoC). The controller relies on a clock signal WCK (write clock) for reading and writing, while the memory relies on another clock signal CK for executing read and write instructions. A significant time difference between these two clock signals can lead to read / write errors. To ensure correct read / write operations, these two clock signals need to be synchronized.

[0003] In existing technology, the controller synchronizes two clock signals in real time using a synchronization parameter. This synchronization parameter can be preset and represents the time deviation between the two clock signals. For example, if clock signal WCK is 5 nanoseconds ahead of clock signal CK, then 5 nanoseconds can be used as the synchronization parameter to delay WCK by 5 nanoseconds, or to speed up CK by 5 nanoseconds. Summary of the Invention

[0004] This application provides a data read / write circuit, method, and device to reduce clock synchronization complexity.

[0005] In a first aspect, embodiments of this application provide a data read / write circuit, including a controller and a memory connected to each other. The memory is used to receive a first clock signal and a second clock signal sent by the controller, and the memory is used to decode instructions based on the first clock signal and sample data based on the second clock signal.

[0006] The controller stores a first synchronization parameter. The memory includes a first storage module, a second storage module, and a mode register. The mode register stores a second synchronization parameter. The second storage module is equipped with a second delay circuit, which is connected to the mode register.

[0007] During the reading and writing process of the first storage module, the controller is used to synchronize the first clock signal and the second clock signal through the first synchronization parameter;

[0008] During the reading and writing process of the second storage module, the controller is used to perform a first synchronization of the first clock signal and the second clock signal using the first synchronization parameter, and the memory is used to perform a second synchronization of the first clock signal and the second clock signal sent by the controller using the second delay circuit and the second synchronization parameter.

[0009] Optionally, the first storage module is also provided with the second delay circuit, which is used to synchronize the first clock signal and the second clock signal sent by the controller through the second synchronization parameter corresponding to the first storage module.

[0010] Optionally, the second delay circuit is located on the transmission path of the first clock signal, and is used to receive the first clock signal sent by the controller, and to delay the received first clock signal based on the second synchronization parameter.

[0011] Optionally, the memory further includes: a deviation measurement circuit connected to the second delay circuit and the mode register respectively, for determining the time deviation between the first clock signal and the second clock signal, and adjusting the second synchronization parameter in the mode register according to the time deviation.

[0012] Optionally, the second delay circuit is located on the transmission path of the second clock signal, and is used to receive the second clock signal sent by the controller, and to delay the received second clock signal using the second synchronization parameter.

[0013] Optionally, the memory further includes: a deviation measurement circuit connected to the second delay circuit and the mode register respectively, for determining the time deviation between the first clock signal and the second clock signal, and adjusting the second synchronization parameter in the mode register according to the time deviation.

[0014] Optionally, the controller further includes a first delay circuit for synchronizing the first clock signal and the second clock signal using the first synchronization parameter, wherein the first delay circuit is located on the transmission path of the first clock signal or the second clock signal.

[0015] Optionally, the second delay circuit includes a decoding circuit, a delay processing circuit, and an output circuit. The decoding circuit is used to decode the second synchronization parameter to obtain N delay processing signals, one of which is in a valid state. The delay processing circuit is used to delay the target clock signal input to the second delay processing circuit through the valid delay processing signal. The output circuit is used to output the target clock signal after delay processing as the target clock signal, which is either the first clock signal or the second clock signal.

[0016] Optionally, the delay processing circuit includes: N AND gates, each AND gate corresponding to a delay processing signal, the input of each AND gate being the target clock signal and the corresponding delay processing signal, N-1 AND gates being connected to delay units with different delays, the delay units being used to delay the output signals of the AND gates, the effective delay processing signal corresponding to the target AND gate, and the output signal of the target AND gate or the output signal of the delay unit connected to the target AND gate serving as the target clock signal output by the delay processing circuit.

[0017] Secondly, embodiments of this application provide a data read / write method, applied in the data read / write circuit of the first aspect, the method comprising:

[0018] During the reading and writing process of the first storage module, the first clock signal and the second clock signal are synchronized through the first synchronization parameter;

[0019] During the reading and writing process of the second storage module, the first clock signal and the second clock signal are synchronized using the first synchronization parameter, and then the first clock signal and the second clock signal are synchronized again using the second synchronization parameter.

[0020] Optionally, synchronizing the first clock signal and the second clock signal using the second synchronization parameter includes:

[0021] The first clock signal is delayed by the second synchronization parameter, which is the difference between the time deviation corresponding to the second storage module and the time deviation corresponding to the first storage module. The time deviation corresponding to the first storage module refers to the time deviation between the first clock signal and the second clock signal during the reading and writing process of the first storage module. The time deviation corresponding to the second storage module refers to the time deviation between the first clock signal and the second clock signal during the reading and writing process of the second storage module.

[0022] Optionally, synchronizing the first clock signal and the second clock signal using the second synchronization parameter includes:

[0023] The second clock signal is delayed by the second synchronization parameter, which is the negative of the difference between the time deviation of the second storage module and the time deviation of the first storage module. The time deviation of the first storage module refers to the time deviation between the first clock signal and the second clock signal during the reading and writing process of the first storage module. The time deviation of the second storage module refers to the time deviation between the first clock signal and the second clock signal during the reading and writing process of the second storage module.

[0024] Optionally, synchronizing the first clock signal and the second clock signal using the first synchronization parameter includes:

[0025] The first clock signal is delayed by the first synchronization parameter, which is the time deviation of the first storage module.

[0026] Optionally, synchronizing the first clock signal and the second clock signal using the first synchronization parameter includes:

[0027] The second clock signal is delayed by the first synchronization parameter, which is the inverse of the time deviation of the first storage module.

[0028] Thirdly, embodiments of this application provide a data read / write method, applied in the data read / write circuit of the first aspect, the method comprising:

[0029] During the reading and writing process of the target storage module, the first clock signal and the second clock signal are synchronized by the first synchronization parameter, and the target storage module is either the first storage module or the second storage module.

[0030] After the first synchronization, the first clock signal and the second clock signal are synchronized again using the second synchronization parameters corresponding to the target storage module.

[0031] Optionally, the step of performing a second synchronization of the first clock signal and the second clock signal using the second synchronization parameter corresponding to the target storage module includes:

[0032] The first clock signal is delayed using the second synchronization parameter corresponding to the target storage module. If the target storage module has the largest time deviation, the second synchronization parameter of the target storage module is the absolute difference between the time deviation of the first storage module and the time deviation of the second storage module. If the target storage module has the smallest time deviation, the second synchronization parameter of the target storage module is 0. The time deviation of the storage module is the time deviation between the first clock signal and the second clock signal during the reading and writing process of the storage module.

[0033] Optionally, the step of performing a second synchronization of the first clock signal and the second clock signal using the second synchronization parameter corresponding to the target storage module includes:

[0034] The second clock signal is delayed using the second synchronization parameter corresponding to the target storage module. If the target storage module has the largest time deviation, the second synchronization parameter of the target storage module is the negative of the absolute difference between the time deviation of the first storage module and the time deviation of the second storage module. If the target storage module has the smallest time deviation, the second synchronization parameter of the target storage module is 0. The time deviation of the storage module is the time deviation between the first clock signal and the second clock signal during the reading and writing process of the storage module.

[0035] Optionally, the first synchronization of the first clock signal and the second clock signal using the first synchronization parameter includes:

[0036] The first clock signal is delayed by the first synchronization parameter, which is the minimum value between the time deviation corresponding to the first storage module and the time deviation corresponding to the second storage module.

[0037] Optionally, the first synchronization of the first clock signal and the second clock signal using the first synchronization parameter includes:

[0038] The second clock signal is delayed by the first synchronization parameter, which is the opposite of the minimum value of the time deviation corresponding to the first storage module and the time deviation corresponding to the second storage module.

[0039] Fourthly, embodiments of this application provide an electronic device, including the data read / write circuit of the first aspect.

[0040] The data read / write circuit, method, and apparatus provided in this application can achieve clock synchronization during the read / write of the first storage module using a first synchronization parameter, and achieve clock synchronization during the read / write of the second storage module using the superposition of the first and second synchronization parameters. In other words, the synchronization parameter used for reading and writing to the first storage module is the first synchronization parameter, and the synchronization parameter used for reading and writing to the second storage module is the superposition of the first and second synchronization parameters. Thus, the synchronization parameters for the two storage modules are different. This achieves clock synchronization of the first and second storage modules using synchronization parameters of different magnitudes. Therefore, after initially setting the first and second synchronization parameters for the first and second storage modules respectively, it is not necessary to modify the synchronization parameters when switching between storage modules being read and written, which helps reduce the complexity of clock synchronization. Attached Figure Description

[0041] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with those of this application and, together with the description, serve to explain the principles of the embodiments of this application.

[0042] Figure 1 This is a schematic diagram of the boundary metal wires connecting the clock signals of the two storage modules provided in this application embodiment;

[0043] Figure 2 This is a schematic diagram of a data read / write circuit provided in an embodiment of this application;

[0044] Figure 3 This is a schematic diagram of another data read / write circuit provided in an embodiment of this application;

[0045] Figure 4 This is a schematic diagram of a data read / write circuit structure provided in an embodiment of this application when the second delay circuit is located on the transmission path of the first clock signal;

[0046] Figure 5 This is a schematic diagram of a data read / write circuit structure provided in an embodiment of this application when the second delay circuit is located on the transmission path of the second clock signal;

[0047] Figure 6 This is a schematic diagram of the data read / write circuit structure when both second delay circuits provided in this application embodiment are located on the transmission path of the first clock signal;

[0048] Figure 7 and Figure 8 These are schematic diagrams of two data read / write circuit structures provided in this application embodiment when the two second delay circuits are located on different clock signal transmission paths;

[0049] Figure 9This is a schematic diagram of the data read / write circuit structure when both second delay circuits provided in this application embodiment are located on the transmission path of the second clock signal;

[0050] Figure 10 This is a schematic diagram of a second delay circuit structure provided in an embodiment of this application;

[0051] Figure 11 This is a schematic diagram of the structure of a delay processing circuit provided in an embodiment of this application;

[0052] Figure 12 and Figure 13 These are schematic diagrams of the internal structures of two controllers provided in the embodiments of this application;

[0053] Figure 14 and Figure 15 These are flowcharts illustrating the steps of two data read / write methods provided in the embodiments of this application.

[0054] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the embodiments of this application in any way, but rather to illustrate the concepts of the embodiments of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0055] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0056] The inventors of this disclosure have discovered that existing technologies suffer from high clock synchronization complexity when the memory comprises two memory modules. After analyzing the prior art, the inventors found that one reason for this technical problem is that the different lengths of the bounding wires of the different memory modules result in different time deviations between the two clock signals corresponding to the different memory modules. Therefore, different synchronization parameters are used when synchronizing the clocks of the different memory modules. Figure 1 This is a schematic diagram of the boundary metal wires connecting the clock signals of the two memory modules provided in this application embodiment. (Refer to...) Figure 1As shown, storage module R1 obtains a first clock signal through boundary metal wire W11, and storage module R2 obtains a second clock signal through boundary metal wire W12. Storage module R2 obtains a first clock signal through boundary metal wire W21, and storage module R2 obtains a second clock signal through boundary metal wire W22. Figure 1 As can be seen, the length difference between W11 and W12 is different from the length difference between W21 and W22, which results in the time deviation between the two clock signals corresponding to the first storage module being different from the time deviation between the two clock signals corresponding to the second storage module. Therefore, the synchronization parameters corresponding to the two storage modules are also different.

[0057] exist Figure 1 In the clock synchronization scenario shown, if reading and writing to one of the storage modules is required, the synchronization parameters for that storage module must first be set to synchronize its clock. When reading and writing to another storage module, the synchronization parameters need to be modified to synchronize the clock of the other storage module according to the modified parameters. It can be seen that if the data read / write process continuously switches between storage modules, the synchronization parameters need to be modified frequently, resulting in high clock synchronization complexity.

[0058] To address the aforementioned issues, this application embodiment considers the need to set different synchronization processes for the two storage modules. To achieve these different synchronization processes, clock synchronization between the two storage modules can be implemented using two synchronization parameters. Specifically, clock synchronization is performed during the read / write process of the first storage module using a first synchronization parameter, and clock synchronization is performed during the read / write process of the second storage module using both a first and a second synchronization parameter. In this way, the clock synchronization of the first and second storage modules uses different synchronization parameters. Since the first and second synchronization parameters only need to be set initially, there is no need to modify the first and second synchronization parameters when switching between storage modules that need to be read / written, effectively reducing the complexity of clock synchronization.

[0059] Figure 2 This is a schematic diagram of a data read / write circuit provided in an embodiment of this application. Please refer to... Figure 2 The aforementioned data read / write circuit 100 includes a controller 101 and a memory 102 connected to each other. The memory 102 is used to receive a first clock signal and a second clock signal sent by the controller 101, and to decode instructions based on the first clock signal and sample data based on the second clock signal.

[0060] The controller 101 stores a first synchronization parameter, which is used to synchronize the first clock signal and the second clock signal during the reading and writing process of any storage module. It is understood that the first clock signal and the second clock signal are generated by the controller 101. Due to transmission line and technical issues, the first clock signal and the second clock signal usually have a time deviation, thus requiring synchronization to minimize this time deviation and keep it within an acceptable range.

[0061] The aforementioned memory 102 includes a first storage module 1021 and a second storage module 1022. The second storage module 1022 includes a second delay circuit 10221 and a mode register 10222. The second delay circuit 10221 is connected to the mode register 10222, and the mode register 10222 stores a second synchronization parameter. The second delay circuit 10221 is used to synchronize the first clock signal and the second clock signal using the second synchronization parameter.

[0062] Based on the above Figure 2 The data read / write circuit shown in the diagram, during the reading and writing process of the first storage module 1021, uses the controller 101 to synchronize the first clock signal and the second clock signal through the first synchronization parameter. Reading and writing to the first storage module 1021 is equivalent to reading and writing to the storage array 10214 of the first storage module 1021.

[0063] During the reading and writing process of the second storage module 1022, the controller 101 performs first synchronization of the first clock signal and the second clock signal using the aforementioned first synchronization parameter, and the memory 102 performs second synchronization of the first clock signal and the second clock signal sent by the controller 101 using the second delay circuit 10221 and the second synchronization parameter. Reading and writing to the second storage module 1022 is equivalent to reading and writing to the storage array 10224 of the second storage module 1022.

[0064] It can be seen that during the read / write operation of the first storage module 1021, the controller 101 performs clock synchronization only once. During the read / write operation of the second storage module 1022, in addition to the clock synchronization performed by the controller 101, the memory 102 also requires the second delay circuit 10221 to perform clock synchronization again. The first synchronization parameter used by the controller 101 for synchronization is the same during the read / write operation of either the first storage module 1021 or the second storage module 1022.

[0065] Optionally, refer to Figure 3As shown, the first storage module 1021 may also be provided with a second delay circuit 10211 and a mode register 10212. The first storage module 1021 and the second storage module 1022 have the same structure, and the corresponding second delay circuits have the same structure. Accordingly, the mode register 10212 of the first storage module 1021 is used to store the second synchronization parameters of the first storage module 1021, and the mode register 10222 of the second storage module 1022 is used to store the second synchronization parameters of the second storage module 1022. This allows the first storage module 1021 to synchronize the first clock signal and the second clock signal sent by the controller 101 using the second synchronization parameters of the first storage module 1021; or, the second storage module 1022 to synchronize the first clock signal and the second clock signal sent by the controller 101 using the second synchronization parameters of the second storage module 1022.

[0066] It can be seen that, based on Figure 3 In the data read / write circuit shown, for the first storage module 1021 and the second storage module 1022, the controller 101 uses the same first synchronization parameter, but the first storage module 1021 and the second storage module 1022 each use a second synchronization parameter. When both the first synchronization parameter and the second synchronization parameter corresponding to the first storage module 1021 exist and are not zero, the clock synchronization during the read / write process of the first storage module 1021 is the superposition of the clock synchronization performed by the controller 101 and the clock synchronization performed by the memory 102. When both the first synchronization parameter and the second synchronization parameter corresponding to the second storage module 1022 exist and are not zero, the clock synchronization during the read / write process of the second storage module 1022 is the superposition of the clock synchronization performed by the controller 101 and the clock synchronization performed by the memory 102.

[0067] It should be noted that, due to Figure 2 and Figure 3 The circuit structures shown are different, therefore, Figure 2 The circuit uses the first synchronization parameter and Figure 3 The first synchronization parameters used in the circuits can be different. Accordingly, Figure 2 The circuit uses the second synchronization parameter and Figure 3 The second synchronization parameter used in the circuit can also be different. The process of setting the first and second synchronization parameters can be referred to the detailed description of the method embodiments below.

[0068] The second delay circuit 10211 corresponding to the first storage module 1021 or the second delay circuit 10221 corresponding to the second storage module 1022 are both used to synchronize the first clock signal and the second clock signal. The delay principle of the two delay circuits is the same.

[0069] Specifically, during the reading and writing process of the first storage module 1021, the second delay circuit 10211 corresponding to the first storage module 1021 can be used to delay either the first clock signal or the second clock signal. When the second delay circuit 10211 corresponding to the first storage module 1021 is located on the transmission path of the first clock signal, it receives the first clock signal sent by the controller 101 and delays the received first clock signal based on the second synchronization parameter. When the second delay circuit 10211 corresponding to the first storage module 1021 is located on the transmission path of the second clock signal, it receives the second clock signal sent by the controller 101 and delays the received second clock signal based on the second synchronization parameter.

[0070] Similarly, during the reading and writing process of the second storage module 1022, the second delay circuit 10221 corresponding to the second storage module 1022 can be used to delay either the first clock signal or the second clock signal. When the second delay circuit 10221 corresponding to the second storage module 1022 is located on the transmission path of the first clock signal, it receives the first clock signal sent by the controller 101 and delays the received first clock signal based on the second synchronization parameter. When the second delay circuit 10221 corresponding to the second storage module 1022 is located on the transmission path of the second clock signal, it receives the second clock signal sent by the controller 101 and delays the received second clock signal based on the second synchronization parameter.

[0071] As can be seen, the second delay circuit in this embodiment can be flexibly configured. Thus, depending on the actual application scenario, the second delay circuit can be placed in the transmission path of the first clock signal or the transmission path of the second clock signal. For example, the second delay circuit 10211 corresponding to the first storage module 1021 can be placed in the transmission path of the first clock signal, and the second delay circuit 10221 corresponding to the second storage module 1022 can be placed in the transmission path of the second clock signal.

[0072] based on Figure 2 The data read / write circuit shown is Figure 4 This is a schematic diagram of a data read / write circuit structure provided in an embodiment of this application when the second delay circuit is located on the transmission path of the first clock signal. (Refer to...) Figure 4As shown, the second delay circuit 10221 is located in the transmission path of the first clock signal. It is used to delay the first clock signal during the reading and writing process of the second storage module 1022, thereby achieving clock synchronization between the first and second clock signals. The first storage module 1021 also includes a storage array 10214 and an instruction decoding circuit 10215. Correspondingly, the second storage module 1022 also includes a storage array 10224 and an instruction decoding circuit 10225, with the instruction decoding circuit 10225 connected to the second delay circuit 10221. The storage array is used to sample data and read / write data using the second clock signal. The instruction decoding circuit is used to decode instructions using the second clock signal.

[0073] based on Figure 4 The circuit shown, during the reading and writing process of the second storage module 1022, may include the following steps: First, the controller 101 sends the first clock signal to the second delay circuit 10221; then, the second delay circuit 10221 delays the first clock signal using a second synchronization parameter; finally, the second delay circuit 10221 sends the delayed first clock signal to the instruction decoding circuit 10225 of the second storage module 1022, so that the instruction decoding circuit 10225 of the second storage module 1022 decodes the instruction according to the first clock signal.

[0074] based on Figure 4 In the circuit shown, during the reading and writing process of the second storage module 1022, the transmission process of the second clock signal can be as follows: the controller 101 sends the second clock signal to the storage array 10224 of the second storage module 1022, so that the storage array 10224 of the second storage module 1022 samples data according to the second clock signal.

[0075] based on Figure 2 The data read / write circuit shown is Figure 5 This is a schematic diagram of a data read / write circuit structure provided in an embodiment of this application when the second delay circuit is located on the transmission path of the second clock signal. (Refer to...) Figure 5 As shown, the second delay circuit 10221 is located in the transmission path of the second clock signal. It is used to delay the second clock signal during the reading and writing process of the second storage module 1022, so as to realize the clock synchronization of the first clock signal and the second clock signal.

[0076] based on Figure 5In the circuit shown, during the reading and writing process of the second storage module 1022, the transmission process of the first clock signal can be as follows: the controller 101 sends the first clock signal to the second storage module 1022 of the memory 102, so that the second storage module 1022 receives the code instruction according to the first clock signal.

[0077] based on Figure 5 The circuit shown, during the reading and writing process of the second storage module 1022, includes the following steps for transmitting the second clock signal: First, the controller 101 sends the second clock signal to the second delay circuit 10221; then, the second delay circuit 10221 delays the second clock signal using a second synchronization parameter; finally, the second delay circuit 10221 sends the delayed second clock signal to the storage array 10224 of the second storage module 1022, so that the storage array 10224 of the second storage module 1022 samples data according to the second clock signal.

[0078] Furthermore, based on Figure 4 or Figure 5 In the circuit shown, during the reading and writing process of the first storage module 1021, the controller 101 sends the first clock signal to the instruction decoding circuit 10215 of the first storage module 1021 so that it can decode the first clock signal. The controller 101 sends the second clock signal to the storage array 10214 of the first storage module 1021 so that it can sample data according to the second clock signal.

[0079] based on Figure 3 The data read / write circuit shown is Figure 6 This is a schematic diagram of the data read / write circuit structure when both second delay circuits provided in this application are located on the transmission path of the first clock signal. (Refer to...) Figure 6 As shown, the second delay circuits are all located in the transmission path of the first clock signal, and are used to delay the first clock signal during the reading and writing process of the first storage module 1021 or the second storage module 1022, so as to realize the clock synchronization of the first clock signal and the second clock signal.

[0080] based on Figure 6The circuit shown, during the reading and writing process of the first storage module 1021, includes the following steps for transmitting the first clock signal: First, the controller 101 sends the first clock signal to the second delay circuit 10211 corresponding to the first storage module 1021; then, the second delay circuit 10211 of the first storage module 1021 delays the first clock signal using the second synchronization parameter corresponding to the first storage module 1021; finally, the second delay circuit 10211 of the first storage module 1021 sends the delayed first clock signal to the instruction decoding circuit 10215 of the first storage module 1021, so that the instruction decoding circuit 10215 of the first storage module 1021 decodes the instruction according to the first clock signal.

[0081] based on Figure 6 The circuit shown, during the reading and writing process of the second storage module 1022, includes the following steps for transmitting the first clock signal: First, the controller 101 sends the first clock signal to the second delay circuit 10221 corresponding to the second storage module 1022; then, the second synchronization parameter corresponding to the second storage module 1022 delays the first clock signal; finally, the second delay circuit 10221 of the second storage module 1022 sends the delayed first clock signal to the instruction decoding circuit 10225 of the second storage module 1022, so that the instruction decoding circuit 10225 of the second storage module 1022 decodes the instruction according to the first clock signal.

[0082] based on Figure 6 In the circuit shown, during the reading and writing process of the first storage module 1021, the controller 101 sends a second clock signal to the storage array 10214 of the first storage module 1021 so that the storage array 10214 of the first storage module 1021 samples data according to the second clock signal.

[0083] based on Figure 6 In the circuit shown, during the reading and writing process of the second storage module 1022, the controller 101 sends a second clock signal to the storage array 10224 of the second storage module 1022, so that the storage array 10224 of the second storage module 1022 samples data according to the second clock signal.

[0084] based on Figure 3 The data read / write circuit shown is Figure 7 This is a schematic diagram of a data read / write circuit structure provided in this application embodiment when the two second delay circuits are located on different clock signal transmission paths. (Refer to...) Figure 7As shown, the second delay circuit 10211 of the first storage module 1021 is located in the transmission path of the first clock signal. It is used to delay the first clock signal during the reading and writing process of the first storage module 1021, thereby achieving clock synchronization between the first and second clock signals. The second delay circuit 10221 of the second storage module 1022 is located in the transmission path of the second clock signal. It is used to delay the second clock signal during the reading and writing process of the second storage module 1022, thereby achieving clock synchronization between the first and second clock signals.

[0085] based on Figure 7 The circuit shown, during the reading and writing process of the first storage module 1021, includes the following steps for transmitting the first clock signal: First, the controller 101 sends the first clock signal to the second delay circuit 10211 corresponding to the first storage module 1021; then, the second delay circuit 10211 of the first storage module 1021 delays the first clock signal using the second synchronization parameter corresponding to the first storage module 1021; finally, the second delay circuit 10211 of the first storage module 1021 sends the delayed first clock signal to the instruction decoding circuit 10215 of the first storage module 1021, so that the instruction decoding circuit 10215 of the first storage module 1021 decodes the instruction according to the first clock signal.

[0086] based on Figure 7 The circuit shown, during the reading and writing process of the second storage module 1022, includes the following steps for transmitting the second clock signal: First, the controller 101 sends the second clock signal to the second delay circuit 10221 corresponding to the second storage module 1022; then, the second synchronization parameter corresponding to the second storage module 1022 delays the second clock signal; finally, the second delay circuit 10221 of the second storage module 1022 sends the delayed second clock signal to the storage array 10224 of the second storage module 1022, so that the storage array 10224 of the second storage module 1022 samples data according to the second clock signal.

[0087] based on Figure 7 In the circuit shown, during the reading and writing process of the first storage module 1021, the controller 101 sends a second clock signal to the storage array 10214 of the first storage module 1021 so that the storage array 10214 of the first storage module 1021 samples data according to the second clock signal.

[0088] based on Figure 7In the circuit shown, during the reading and writing process of the second storage module 1022, the controller 101 sends a first clock signal to the instruction decoding circuit 10225 of the second storage module 1022, so that the instruction decoding circuit 10225 of the second storage module 1022 decodes the instruction according to the first clock signal.

[0089] based on Figure 3 The data read / write circuit shown is Figure 8 This is a schematic diagram of another data read / write circuit structure when the two second delay circuits provided in this application are located on different clock signal transmission paths. (Refer to...) Figure 8 As shown, the second delay circuit 10211 of the first storage module 1021 is located in the transmission path of the second clock signal. It is used to delay the second clock signal during the reading and writing process of the first storage module 1021, thereby achieving clock synchronization between the first and second clock signals. The second delay circuit 10221 of the second storage module 1022 is located in the transmission path of the first clock signal. It is used to delay the first clock signal during the reading and writing process of the second storage module 1022, thereby achieving clock synchronization between the first and second clock signals.

[0090] based on Figure 8 The circuit shown, during the reading and writing process of the first storage module 1021, includes the following steps for transmitting the second clock signal: First, the controller 101 sends the second clock signal to the second delay circuit 10211 corresponding to the first storage module 1021; then, the second synchronization parameter corresponding to the first storage module 1021 delays the second clock signal; finally, the second delay circuit 10211 of the first storage module 1021 sends the delayed second clock signal to the storage array 10214 of the first storage module 1021, so that the storage array 10214 of the first storage module 1021 samples data according to the second clock signal.

[0091] based on Figure 8 The circuit shown, during the reading and writing process of the second storage module 1022, includes the following steps for transmitting the first clock signal: First, the controller 101 sends the first clock signal to the second delay circuit 10221 corresponding to the second storage module 1022; then, the second delay circuit 10221 of the second storage module 1022 delays the first clock signal using the second synchronization parameter corresponding to the second storage module 1022; finally, the second delay circuit 10221 of the second storage module 1022 sends the delayed first clock signal to the instruction decoding circuit 10225 of the second storage module 1022, so that the instruction decoding circuit 10225 of the second storage module 1022 decodes the instruction according to the first clock signal.

[0092] based on Figure 8 In the circuit shown, during the reading and writing process of the first storage module 1021, the controller 101 sends a first clock signal to the instruction decoding circuit 10215 of the first storage module 1021, so that the instruction decoding circuit 10215 of the first storage module 1021 decodes the instruction according to the first clock signal.

[0093] based on Figure 8 In the circuit shown, during the reading and writing process of the second storage module 1022, the controller 101 sends a second clock signal to the storage array 10224 of the second storage module 1022, so that the storage array 10224 of the second storage module 1022 samples data according to the second clock signal.

[0094] based on Figure 3 The data read / write circuit shown is Figure 9 This is a schematic diagram of the data read / write circuit structure when both second delay circuits provided in this application are located on the transmission path of the second clock signal. (Refer to...) Figure 9 As shown, both second delay circuits are located in the transmission path of the second clock signal. They are used to delay the second clock signal during the reading and writing process of the first storage module 1021 or the second storage module 1022, so as to achieve clock synchronization between the first clock signal and the second clock signal.

[0095] based on Figure 9 The circuit shown, during the reading and writing process of the first storage module 1021, includes the following steps for transmitting the second clock signal: First, the controller 101 sends the second clock signal to the second delay circuit 10211 corresponding to the first storage module 1021; then, the second synchronization parameter corresponding to the first storage module 1021 delays the second clock signal; finally, the second delay circuit 10211 of the first storage module 1021 sends the delayed second clock signal to the storage array 10214 of the first storage module 1021, so that the storage array 10214 of the first storage module 1021 samples data according to the second clock signal.

[0096] based on Figure 9The circuit shown, during the reading and writing process of the second storage module 1022, includes the following steps for transmitting the first clock signal: First, the controller 101 sends the second clock signal to the second delay circuit 10221 corresponding to the second storage module 1022; then, the second synchronization parameter corresponding to the second storage module 1022 delays the second clock signal; finally, the second delay circuit 10221 of the second storage module 1022 sends the delayed second clock signal to the storage array 10224 of the second storage module 1022, so that the storage array 10224 of the second storage module 1022 samples data according to the second clock signal.

[0097] based on Figure 9 In the circuit shown, during the reading and writing process of the first storage module 1021, the controller 101 sends a first clock signal to the instruction decoding circuit 10215 of the first storage module 1021, so that the instruction decoding circuit 10215 of the first storage module 1021 decodes the instruction according to the first clock signal.

[0098] based on Figure 9 In the circuit shown, during the reading and writing process of the second storage module 1022, the controller 101 sends a first clock signal to the instruction decoding circuit 10225 of the second storage module 1022, so that the instruction decoding circuit 10225 of the second storage module 1022 decodes the instruction according to the first clock signal.

[0099] It should be noted that, in the above Figures 2 to 9 In the data read / write circuit shown, the second synchronization parameter of the first storage module 1021 or the second synchronization parameter of the second storage module 1022 may be 0. Therefore, when the second synchronization parameter is 0, the second delay circuit of the corresponding storage module can determine that the first clock signal does not need to be delayed by the second synchronization parameter that is 0.

[0100] Of course, the corresponding mode register can also be empty, meaning there is no second synchronization parameter. In this case, it represents a scenario where the second synchronization parameter is 0. Under these circumstances, the corresponding second delay circuit does not delay the first clock signal by default.

[0101] In the above Figures 2 to 9 During the operation of the circuit shown, it is also necessary to measure the time deviation between the first clock signal and the second clock signal in order to adjust the first synchronization parameter and the second synchronization parameter according to the time deviation. Therefore, the above... Figures 2 to 9The circuit shown can also include a deviation measurement circuit to determine the time deviation between the first clock signal and the second clock signal, and adjust the second synchronization parameter in the mode register according to the time deviation. Thus, embodiments of this disclosure can dynamically adjust the second synchronization parameter through the deviation measurement circuit to improve the accuracy of the second synchronization parameter, thereby improving the accuracy of clock synchronization.

[0102] Reference Figure 2 As shown, the second storage module 1022 includes a deviation measurement circuit 10223, which is connected to the second delay circuit 10221. Of course, the first storage module 1021 can also include a deviation measurement circuit; however, for simplicity... Figure 2 Not in Figure 2 As shown in the image. Figure 4 , Figure 5 You can follow Figure 2 The deviation measurement circuit is set up in this way.

[0103] Reference Figure 3 As shown, the first storage module 1021 and the second storage module 1022 are respectively provided with a deviation measurement circuit 10213 and a deviation measurement circuit 10223, which are respectively connected to the corresponding second delay circuit. Figure 4 , Figure 5 You can follow Figure 2 The deviation measurement circuit is set up in this way. Figures 6 to 9 You can follow Figure 3 The deviation measurement circuit is set up in this way.

[0104] against Figure 2 , Figure 4 or Figure 5 The circuit shown includes a deviation measurement circuit 10213 in the first storage module 1021 that can be connected to the controller 101. This circuit is used to receive a first clock signal and a second clock signal sent by the controller 101 during the reading and writing process of the first storage module 1021, and to measure the time deviation between the first clock signal and the second clock signal.

[0105] against Figure 4 In the circuit shown, the deviation measurement circuit 10223 in the second storage module 1022 is connected to the second delay circuit 10221 and the controller 101 respectively. It is used to receive the first clock signal delayed by the second delay circuit 10221 and the second clock signal sent by the controller 101 during the reading and writing process of the second storage module 1022, and to measure the time deviation between the first clock signal delayed by the second delay circuit 10221 and the second clock signal sent by the controller 101.

[0106] against Figure 5In the circuit shown, the deviation measurement circuit 10223 in the second storage module 1022 is connected to the second delay circuit 10221 and the controller 101 respectively. It is used to receive the second clock signal delayed by the second delay circuit 10221 and the first clock signal sent by the controller 101 during the reading and writing process of the second storage module 1022, and to measure the time deviation between the second clock signal delayed by the second delay circuit 10221 and the first clock signal sent by the controller 101.

[0107] against Figure 6 In the circuit shown, in each storage module, the deviation measurement circuit is connected to the controller 101 and the corresponding second delay circuit. During the reading and writing process of the first storage module 1021 or the second storage module 1022, the corresponding deviation measurement circuit is used to receive the first clock signal delayed by the second delay circuit and the second clock signal sent by the controller 101, and to measure the time deviation between the first clock signal delayed by the second delay circuit and the second clock signal sent by the controller 101.

[0108] against Figure 7 In the circuit shown, in each storage module, the deviation measurement circuit is connected to the controller 101 and the corresponding second delay circuit. The deviation measurement circuit 10213 of the first storage module 1021 is used to receive the delayed first clock signal from the second delay circuit 10211 and the second clock signal sent by the controller 101 during the read / write operation of the first storage module 1021, and to measure the time deviation between the delayed first clock signal from the second delay circuit 10211 and the second clock signal sent by the controller 101. Similarly, the deviation measurement circuit 10223 of the second storage module 1022 is used to receive the delayed second clock signal from the second delay circuit 10221 and the first clock signal sent by the controller 101 during the read / write operation of the second storage module 1022, and to measure the time deviation between the delayed second clock signal from the second delay circuit 10221 and the first clock signal sent by the controller 101.

[0109] against Figure 8In the circuit shown, in each storage module, the deviation measurement circuit is connected to the controller 101 and the corresponding second delay circuit. The deviation measurement circuit 10213 of the first storage module 1021 is used to receive the delayed second clock signal from the second delay circuit 10211 and the first clock signal sent by the controller 101 during the read / write operation of the first storage module 1021, and to measure the time deviation between the delayed second clock signal from the second delay circuit 10211 and the first clock signal sent by the controller 101. Similarly, the deviation measurement circuit 10223 of the second storage module 1022 is used to receive the delayed first clock signal from the second delay circuit 10221 and the second clock signal sent by the controller 101 during the read / write operation of the second storage module 1022, and to measure the time deviation between the delayed first clock signal from the second delay circuit 10221 and the second clock signal sent by the controller 101.

[0110] against Figure 9 In the circuit shown, in each storage module, the deviation measurement circuit is connected to the controller 101 and the corresponding second delay circuit. During the reading and writing process of the first storage module 1021 or the second storage module 1022, the corresponding deviation measurement circuit is used to receive the second clock signal delayed by the second delay circuit and the first clock signal sent by the controller 101, and to measure the time deviation between the second clock signal delayed by the second delay circuit and the first clock signal sent by the controller 101.

[0111] In addition, for Figures 2 to 9 In any of the circuits shown, the deviation measurement circuits in the first storage module 1021 and the second storage module 1022 can share one. In this way, two time deviations can be measured with a single deviation measurement circuit, which helps to minimize the circuit size while ensuring the accuracy of clock synchronization.

[0112] As can be seen, the second delay circuit described above is used to delay the input target clock signal, which can be either the first clock signal or the second clock signal described above.

[0113] Figure 10 This is a schematic diagram of a second delay circuit structure provided in an embodiment of this application. (Refer to...) Figure 10 As shown, the second delay circuit may include a decoding circuit, a delay processing circuit, and an output circuit. The decoding circuit decodes the second synchronization parameter to obtain N delay processing signals, one of which is in a valid state. The delay processing circuit uses the valid delay processing signal to delay the target clock signal and outputs the delayed target clock signal as a new target clock signal.

[0114] Figure 11 This is a schematic diagram of a delay processing circuit provided in an embodiment of this application. When the valid signal is high, refer to... Figure 11 As shown, the aforementioned delay processing circuit includes N AND gates, each corresponding to a delay processing signal. The input to each AND gate is the target clock signal and the corresponding delay processing signal. The N-1 AND gates are connected to delay circuits with different delay times. Each delay circuit is used to delay the output signal of the AND gate. The active delay processing signal corresponds to the target AND gate, and the output signal of the target AND gate or the output signal of the delay circuit connected to the target AND gate serves as the target clock signal output by the delay processing circuit.

[0115] The different delay units mentioned above correspond to different levels of delay, and different levels of delay can be achieved in two ways.

[0116] In the first approach, different delayers may include a delay unit, and the delay unit included in different delayers corresponds to different delay durations.

[0117] In the second approach, different delayers can include different numbers of delay units, each with the same delay duration. In other words, different delayers achieve different levels of delay by varying the number of delay units.

[0118] As can be seen, the foregoing process details the connection relationship between the second delay circuit in memory 102 and the other circuits in memory 102. In practical applications, the controller 101 may also contain a first delay circuit, used to synchronize the first clock signal and the second clock signal using the aforementioned first synchronization parameter.

[0119] Figure 12 This is a schematic diagram of the internal structure of a controller 101 provided in an embodiment of this application. (Refer to...) Figure 12 As shown, the aforementioned first delay circuit is located on the transmission path of the first clock signal. Specifically, refer to... Figure 12 As shown, after the oscillator generates a clock signal, it undergoes phase-locked loop (PLL) processing. The resulting clock signal is the first clock signal. A first delay circuit can be connected to both the PLL and the third drive circuit. Thus, the first delay circuit can delay the first clock signal obtained from the PLL processing using a first synchronization parameter, enabling the third drive circuit to send the delayed first clock signal to the memory 102.

[0120] Figure 13 This is a schematic diagram of the internal structure of another controller 101 provided in an embodiment of this application. (Refer to...) Figure 13 As shown, the first delay circuit is located on the transmission path of the second clock signal. Specifically, refer to... Figure 13As shown, after the oscillator generates a clock signal, it undergoes phase-locked loop (PLL) processing, resulting in a first clock signal. A frequency divider divides the first clock signal to obtain a second clock signal. A first delay circuit can be connected in series between the frequency divider and the second drive circuit. Thus, the first delay circuit can delay the second clock signal obtained from the frequency division using a first synchronization parameter, enabling the second drive circuit to send the delayed second clock signal to the memory 102.

[0121] Of course, the first delay circuit can also be placed before the frequency divider, so that the second clock signal is obtained by delaying the signal before frequency division.

[0122] In addition, refer to Figure 12 As shown in Figure 13, the controller 101 also includes a trigger and a first driving circuit. The trigger is used to temporarily store commands and send the temporarily stored commands to the first driving circuit according to the second clock signal, so that the first driving circuit sends the commands to the memory 102.

[0123] Corresponding to the above circuit embodiment, Figure 14 This is a flowchart illustrating the steps of a data read / write method provided in an embodiment of this application. Figure 14 The method shown corresponds to the one described above. Figure 2 , Figure 4 and Figure 5 The circuit shown is a method for a second delay circuit. Please refer to... Figure 14 The above data read and write method may include steps S201 and S202.

[0124] S201: During the reading and writing process of the first storage module, the first clock signal and the second clock signal are synchronized through the first synchronization parameter.

[0125] Specifically, the first delay circuit can synchronize the first clock signal and the second clock signal using a first synchronization parameter. Synchronizing the first clock signal and the second clock signal can include two methods: delaying the first clock signal using the first synchronization parameter, or delaying the second clock signal using the first clock signal.

[0126] Of course, the first synchronization parameter when delaying the first clock signal is different from the first synchronization parameter when delaying the second clock signal.

[0127] When the first clock signal is delayed, the first synchronization parameter can be the time deviation corresponding to the first storage module. This time deviation is the time difference between the first clock signal and the second clock signal during the reading and writing process of the first storage module. When the second clock signal is delayed, the first synchronization parameter can be the negative of the time deviation corresponding to the first storage module.

[0128] S202: During the reading and writing process of the second storage module, after synchronizing the first clock signal and the second clock signal through the first synchronization parameter, the first clock signal and the second clock signal are synchronized again through the second synchronization parameter.

[0129] Specifically, during the reading and writing process of the second storage module, firstly, the first delay circuit in the controller uses the same process as in S201 to delay the first clock signal or the second clock signal; then, the controller sends the first clock signal and the delayed second clock signal to the memory, or sends the second clock signal and the delayed first clock signal to the memory; finally, the second delay circuit in the memory can delay the first clock signal or the second clock signal through the second synchronization parameter.

[0130] Of course, the second synchronization parameters when delaying the first clock signal are different from those when delaying the second clock signal.

[0131] When the first clock signal is delayed using the second synchronization parameter, the second synchronization parameter is the difference between the time deviation corresponding to the second storage module and the time deviation corresponding to the first storage module. When the second clock signal is delayed using the second synchronization parameter, the second synchronization parameter is the negative of the difference between the time deviation of the second storage module and the time deviation corresponding to the first storage module. The time deviation corresponding to the second storage module refers to the time deviation between the first clock signal and the second clock signal during the read / write operation of the second storage module. This time deviation can be as described above. Figure 2 The deviation was measured by the deviation measurement circuit in the middle.

[0132] This application embodiment can achieve clock synchronization using a first synchronization parameter and a second synchronization parameter. As illustrated below, the time difference between the first clock signal and the second clock signal can be defined as the time deviation between the first clock signal and the second clock signal. That is, if the first clock signal is earlier than the second clock signal, then the time deviation is greater than 0. If the first clock signal is later than the second clock signal, then the time deviation is less than 0. If the first clock signal and the second clock signal are synchronized, then the time deviation is 0.

[0133] For example, when the time deviation corresponding to the first storage module is 4 nanoseconds and the time deviation corresponding to the second storage module is 5 nanoseconds, the first synchronization parameter can be set to 4 nanoseconds and the second synchronization parameter can be set to 5-4=1 nanoseconds.

[0134] During the reading and writing process of the first storage module, the first delay circuit delays the first clock signal by 4 nanoseconds using the first synchronization parameter. Since the first clock signal is 4 nanoseconds earlier than the second clock signal before clock synchronization, the first clock signal and the second clock signal are synchronized after synchronization.

[0135] During the read / write operation of the second storage module, firstly, the first delay circuit delays the first clock signal by 4 nanoseconds using the first synchronization parameter. Then, the second delay circuit delays the first clock signal by another 1 nanosecond using the second synchronization parameter, for a total delay of 5 nanoseconds. Since the first clock signal is 5 nanoseconds ahead of the second clock signal before clock synchronization, the first and second clock signals are synchronized after synchronization.

[0136] For example, when the time deviation corresponding to the first storage module is 5 nanoseconds and the time deviation corresponding to the second storage module is 4 nanoseconds, the first synchronization parameter can be set to -5 nanoseconds and the second synchronization parameter can be set to the opposite of 4-5, 1 nanosecond.

[0137] During the reading and writing process of the first storage module, the first delay circuit advances the second clock signal by 5 nanoseconds using the first synchronization parameter. Since the first clock signal is 5 nanoseconds ahead of the second clock signal before clock synchronization, the first clock signal and the second clock signal are synchronized after synchronization.

[0138] During the read / write operation of the second storage module, firstly, the first delay circuit advances the second clock signal by 5 nanoseconds using the first synchronization parameter. Then, the second delay circuit delays the second clock signal by another 1 nanosecond using the second synchronization parameter. In other words, the second clock signal is first advanced by 5 nanoseconds and then delayed by 1 nanosecond, for a total advancement of 4 nanoseconds. Since the first clock signal is 4 nanoseconds ahead of the second clock signal before clock synchronization, after synchronization, the first and second clock signals are in a synchronized state.

[0139] In summary, during the read / write operation of the first storage module, the time deviation between the first clock signal and the second clock signal is eliminated through the first synchronization parameter and the first delay circuit, ensuring that the first clock signal and the second clock signal are synchronized, which helps improve the read / write accuracy of the first storage module. Similarly, during the read / write operation of the second storage module, the time deviation between the first clock signal and the second clock signal is eliminated through the first synchronization parameter, the first delay circuit, the second synchronization parameter, and the second delay circuit, ensuring that the first clock signal and the second clock signal are synchronized, which also helps improve the read / write accuracy of the second storage module.

[0140] As can be seen, through the above process, after setting the first synchronization parameter and the second synchronization parameter, whether reading or writing to the first storage module or the second storage module, the first synchronization parameter and the second synchronization parameter do not need to be modified, thus reducing the clock synchronization complexity.

[0141] Corresponding to the above circuit embodiment, Figure 15 This is a flowchart illustrating the steps of another data read / write method provided in an embodiment of this application. Figure 15 The method shown corresponds to the one described above. Figure 3 , Figures 6 to 9 The circuit shown is the method for two second delay circuits. Please refer to... Figure 15 The above data read and write method may include steps S301 and S302.

[0142] S301: During the reading and writing process of the target storage module, the first clock signal and the second clock signal are synchronized by the first synchronization parameter, and the target storage module is the first storage module or the second storage module.

[0143] S302: After the first synchronization, the first clock signal and the second clock signal are synchronized again by using the second synchronization parameters corresponding to the target storage module.

[0144] It should be noted that the controller uses the same first synchronization parameter during the read / write operation of either the first or second storage module. The first storage module has a corresponding second synchronization parameter for synchronization during read / write operations. The second storage module has a separate second synchronization parameter for synchronization during read / write operations of the first storage module. It can be seen that in this embodiment, when both the first and second synchronization parameters exist and are not zero, two clock synchronizations are required for both read / write operations on the first and second storage modules. The first synchronization is performed by the first delay circuit using the first synchronization parameter, and the second synchronization is performed by the second delay circuit using the second synchronization parameter.

[0145] The first delay circuit performs first synchronization using a first synchronization parameter in two ways: delaying the first clock signal using the first synchronization parameter, and delaying the second clock signal using the first clock signal. Similarly, the second delay circuit performs second synchronization using a second synchronization parameter, which includes: delaying the first clock signal using the second synchronization parameter, and delaying the second clock signal using the second synchronization parameter.

[0146] Of course, the first synchronization parameter when delaying the first clock signal is different from the first synchronization parameter when delaying the second clock signal. Similarly, the second synchronization parameter when delaying the first clock signal is also different from the second synchronization parameter when delaying the second clock signal.

[0147] When the first clock signal is delayed using the first synchronization parameter, the first synchronization parameter is the minimum of the time deviations corresponding to the first and second storage modules. When the second clock signal is delayed using the first synchronization parameter, the first synchronization parameter is the negative of the minimum of the time deviations corresponding to the first and second storage modules.

[0148] When delaying the first clock signal using the second synchronization parameter, the second synchronization parameter for each storage module needs to be set according to the time deviation between the two storage modules. The second synchronization parameter for the storage module with the largest time deviation between the first and second storage modules is the absolute difference between their time deviations; that is, the absolute value of the difference between their time deviations. The second synchronization parameter for the storage module with the smallest time deviation between the first and second storage modules is 0. For the target storage module, if it has the largest time deviation, its second synchronization parameter is the absolute difference between the time deviation of the first storage module and the time deviation of the second storage module. If the target storage module has the smallest time deviation, its second synchronization parameter is 0.

[0149] When delaying the second clock signal using the second synchronization parameter, the second synchronization parameter for each storage module also needs to be set according to the time deviation between the two storage modules. The second synchronization parameter for the storage module with the largest time deviation between the first and second storage modules is the inverse of the absolute difference between their time deviations. The second synchronization parameter for the storage module with the smallest time deviation between the first and second storage modules is 0. For the target storage module, if it has the largest time deviation, its second synchronization parameter is the inverse of the absolute difference between the time deviation of the first and second storage modules. If it has the smallest time deviation, its second synchronization parameter is 0. The time deviation here can be as described above. Figure 3 The deviation was measured by the deviation measurement circuit in the middle.

[0150] This application embodiment can achieve clock synchronization using one first synchronization parameter and two second synchronization parameters. As illustrated below, similarly, the time difference between the first clock signal and the second clock signal can be defined as the time deviation between the first clock signal and the second clock signal. That is, if the first clock signal is earlier than the second clock signal, then the time deviation is greater than 0. If the first clock signal is later than the second clock signal, then the time deviation is less than 0. If the first clock signal and the second clock signal are synchronized, then the time deviation is 0.

[0151] For example, when the time deviation corresponding to the first storage module is 4 nanoseconds and the time deviation corresponding to the second storage module is 5 nanoseconds, the first synchronization parameter can be set to the minimum value of 4 and 5, which is 4 nanoseconds. The second synchronization parameter of the second storage module with the larger time deviation can be set to the absolute difference between 4 and 5, which is 1 nanosecond. The second synchronization parameter of the first storage module with the smaller time deviation can be set to 0.

[0152] During the read / write operation of the first storage module, the first delay circuit delays the first clock signal by 4 nanoseconds using the first synchronization parameter. Since the second synchronization parameter of the first storage module is 0, the second delay circuit no longer delays it, which can also be understood as a 0 nanosecond delay. Therefore, the first clock signal is delayed by a total of 4 nanoseconds during this process. Because the first clock signal is 4 nanoseconds ahead of the second clock signal before clock synchronization, the first and second clock signals are synchronized after synchronization.

[0153] During the read / write operation of the second storage module, the first delay circuit delays the first clock signal by 4 nanoseconds using the first synchronization parameter. Then, the second delay circuit delays the first clock signal by 1 nanosecond using the second synchronization parameter of the second storage module. Thus, the first clock signal is delayed by a total of 5 nanoseconds. Since the first clock signal is 5 nanoseconds ahead of the second clock signal before clock synchronization, the first and second clock signals are synchronized after synchronization.

[0154] For example, when the time deviation corresponding to the first storage module is 5 nanoseconds and the time deviation corresponding to the second storage module is 4 nanoseconds, the first synchronization parameter can be set to the opposite of the minimum value of 4 nanoseconds (4 nanoseconds) - 4 nanoseconds, and the second synchronization parameter of the first storage module with the larger time deviation can be set to the opposite of the absolute difference of 4 and 5 (1 nanoseconds) - 1 nanosecond, and the second synchronization parameter of the second storage module with the smaller time deviation can be set to 0.

[0155] During the read / write operation of the first storage module, the first delay circuit advances the second clock signal by 4 nanoseconds using the first synchronization parameter -4 nanoseconds. Then, the second delay circuit advances the second clock signal by 1 nanosecond using the second synchronization parameter of the second storage module -1 nanoseconds. Thus, the second clock signal is advanced by a total of 5 nanoseconds during this process. Since the first clock signal was 5 nanoseconds ahead of the second clock signal before clock synchronization, the first and second clock signals are synchronized after synchronization.

[0156] During the read / write operation of the second storage module, the first delay circuit advances the second clock signal by 4 nanoseconds using the first synchronization parameter of -4 nanoseconds. Since the second synchronization parameter of the second storage module is 0, the second delay circuit no longer delays it, which can be understood as a 0 nanosecond delay. Therefore, in this process, the second clock signal is advanced by a total of 4 nanoseconds. Because the first clock signal is 4 nanoseconds ahead of the second clock signal before clock synchronization, after synchronization, the first and second clock signals are in a synchronized state.

[0157] It should be noted that the above examples are merely illustrative. In practical applications, the first synchronization parameter and the second synchronization parameter can both be positive, both can be negative, or one can be positive and the other negative. This application does not impose any restrictions on these.

[0158] The two method embodiments described above are embodiments corresponding to the aforementioned circuit embodiments and have the same technical effects as the circuit embodiments. A detailed description of this device embodiment can be found in the detailed description of the aforementioned method embodiments, and will not be repeated here.

[0159] This application also provides an electronic device, including the aforementioned data read / write circuit.

[0160] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0161] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0162] The above are merely preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structural or procedural transformations made using the description and drawings of the present application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present application.

Claims

1. A data read / write circuit, characterized by, It includes an interconnected controller and a memory, the memory being used to receive a first clock signal and a second clock signal sent by the controller, the memory being used to decode instructions based on the first clock signal, and to sample data based on the second clock signal; The controller stores a first synchronization parameter. The memory includes a first storage module, a second storage module, and a mode register. The mode register stores a second synchronization parameter. The second storage module is equipped with a second delay circuit, which is connected to the mode register. During the reading and writing process of the first storage module, the controller is used to synchronize the first clock signal and the second clock signal through the first synchronization parameter; During the reading and writing process of the second storage module, the controller is used to perform a first synchronization of the first clock signal and the second clock signal using the first synchronization parameter, and the memory is used to perform a second synchronization of the first clock signal and the second clock signal sent by the controller using the second delay circuit and the second synchronization parameter.

2. The data read / write circuit of claim 1, wherein, The first storage module is also provided with the second delay circuit, which is used to synchronize the first clock signal and the second clock signal sent by the controller through the second synchronization parameter corresponding to the first storage module.

3. The data read / write circuit according to claim 1 or 2, characterized in that, The second delay circuit is located on the transmission path of the first clock signal and is used to receive the first clock signal sent by the controller and perform delay processing on the received first clock signal based on the second synchronization parameter.

4. The data read / write circuit according to claim 3, characterized in that, The memory further includes a deviation measurement circuit connected to the second delay circuit and the mode register respectively, for determining the time deviation between the first clock signal and the second clock signal, and adjusting the second synchronization parameter in the mode register according to the time deviation.

5. The data read / write circuit according to claim 1 or 2, characterized in that, The second delay circuit is located on the transmission path of the second clock signal and is used to receive the second clock signal sent by the controller and to delay the received second clock signal using the second synchronization parameter.

6. The data read / write circuit according to claim 5, characterized in that, The memory further includes a deviation measurement circuit connected to the second delay circuit and the mode register respectively, for determining the time deviation between the first clock signal and the second clock signal, and adjusting the second synchronization parameter in the mode register according to the time deviation.

7. The data read / write circuit according to claim 1 or 2, characterized in that, The controller further includes a first delay circuit for synchronizing the first clock signal and the second clock signal using the first synchronization parameter. The first delay circuit is located on the transmission path of the first clock signal or the transmission path of the second clock signal.

8. The data read / write circuit according to claim 1 or 2, characterized in that, The second delay circuit includes a decoding circuit, a delay processing circuit, and an output circuit. The decoding circuit is used to decode the second synchronization parameter to obtain N delay processing signals, one of which is in an active state. The delay processing circuit is used to delay the target clock signal input to the second delay circuit using the active delay processing signal. The output circuit is used to output the delayed target clock signal as the target clock signal, which is either the first clock signal or the second clock signal.

9. The data read / write circuit according to claim 8, characterized in that, The delay processing circuit includes: N AND gates, each AND gate corresponding to a delay processing signal. The input of each AND gate is the target clock signal and the corresponding delay processing signal. N-1 AND gates are respectively connected to delay units with different delays. The delay units are used to delay the output signals of the AND gates. The effective delay processing signal corresponds to the target AND gate. The output signal of the target AND gate or the output signal of the delay unit connected to the target AND gate serves as the target clock signal output by the delay processing circuit.

10. A data read / write method, characterized in that, Applied to the data read / write circuit as described in claim 1, the method includes: During the reading and writing process of the first storage module, the first clock signal and the second clock signal are synchronized through the first synchronization parameter; During the reading and writing process of the second storage module, the first clock signal and the second clock signal are synchronized using the first synchronization parameter, and then the first clock signal and the second clock signal are synchronized again using the second synchronization parameter.

11. The method according to claim 10, characterized in that, The step of synchronizing the first clock signal and the second clock signal using the second synchronization parameter includes: The first clock signal is delayed by the second synchronization parameter, which is the difference between the time deviation corresponding to the second storage module and the time deviation corresponding to the first storage module. The time deviation corresponding to the first storage module refers to the time deviation between the first clock signal and the second clock signal during the reading and writing process of the first storage module. The time deviation corresponding to the second storage module refers to the time deviation between the first clock signal and the second clock signal during the reading and writing process of the second storage module.

12. The method according to claim 10, characterized in that, The step of synchronizing the first clock signal and the second clock signal using the second synchronization parameter includes: The second clock signal is delayed by the second synchronization parameter, which is the negative of the difference between the time deviation of the second storage module and the time deviation of the corresponding first storage module. The time deviation of the corresponding first storage module refers to the time deviation between the first clock signal and the second clock signal during the reading and writing process of the first storage module. The time deviation of the corresponding second storage module refers to the time deviation between the first clock signal and the second clock signal during the reading and writing process of the second storage module.

13. The method according to claim 11 or 12, characterized in that, The step of synchronizing the first clock signal and the second clock signal using the first synchronization parameter includes: The first clock signal is delayed by the first synchronization parameter, which is the time deviation of the first storage module.

14. The method according to claim 11 or 12, characterized in that, The step of synchronizing the first clock signal and the second clock signal using the first synchronization parameter includes: The second clock signal is delayed by the first synchronization parameter, which is the inverse of the time deviation of the first storage module.

15. A data read / write method, characterized in that, Applied to the data read / write circuit as described in claim 2, the method includes: During the reading and writing process of the target storage module, the first clock signal and the second clock signal are synchronized by the first synchronization parameter, and the target storage module is either the first storage module or the second storage module. After the first synchronization, the first clock signal and the second clock signal are synchronized again using the second synchronization parameters corresponding to the target storage module.

16. The method according to claim 15, characterized in that, The step of synchronizing the first clock signal and the second clock signal using the second synchronization parameter corresponding to the target storage module includes: The first clock signal is delayed using the second synchronization parameter corresponding to the target storage module. If the target storage module has the largest time deviation, the second synchronization parameter of the target storage module is the absolute difference between the time deviation of the first storage module and the time deviation of the second storage module. If the target storage module has the smallest time deviation, the second synchronization parameter of the target storage module is 0. The time deviation of the storage module is the time deviation between the first clock signal and the second clock signal during the reading and writing process of the storage module.

17. The method according to claim 15, characterized in that, The step of synchronizing the first clock signal and the second clock signal using the second synchronization parameter corresponding to the target storage module includes: The second clock signal is delayed using the second synchronization parameter corresponding to the target storage module. If the target storage module has the largest time deviation, the second synchronization parameter of the target storage module is the negative of the absolute difference between the time deviation of the first storage module and the time deviation of the second storage module. If the target storage module has the smallest time deviation, the second synchronization parameter of the target storage module is 0. The time deviation of the storage module is the time deviation between the first clock signal and the second clock signal during the reading and writing process of the storage module.

18. The method according to claim 16 or 17, characterized in that, The step of synchronizing the first clock signal and the second clock signal using the first synchronization parameter includes: The first clock signal is delayed by the first synchronization parameter, which is the minimum value between the time deviation corresponding to the first storage module and the time deviation corresponding to the second storage module.

19. The method according to claim 16 or 17, characterized in that, The step of synchronizing the first clock signal and the second clock signal using the first synchronization parameter includes: The second clock signal is delayed by the first synchronization parameter, which is the opposite of the minimum value of the time deviation corresponding to the first storage module and the time deviation corresponding to the second storage module.

20. An electronic device, characterized in that, Includes the data read / write circuit as described in any one of claims 1 to 9.

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