Memory devices and their operation methods

Abstract

This disclosure provides a memory device and its operation method. The memory device includes a memory controller, a buffer, and a memory array. The buffer is coupled to or embedded in the memory controller. The storage space of the buffer is configured by the memory controller to include multiple groups. The memory array is coupled to the memory controller and includes multiple memory blocks. Each group corresponds one-to-one with a memory block. Each group is used to store data to be written to the corresponding memory block. The memory controller performs write operations on a group-by-group basis.

Description

Technical Field

[0001] This disclosure relates to a memory device and a method of operating the same. Background Technology

[0002] Three-dimensional (3D) or non-orbit (NOR) flash memory has the characteristic that read latency is much lower than write latency. Improving the data write efficiency of 3D NOR flash memory is a key research focus. On the other hand, managing write disturbances is also an important issue for 3D NOR flash memory. Summary of the Invention

[0003] One embodiment of this disclosure discloses a memory device including a memory controller, a buffer, and a memory array. The buffer is coupled to or embedded in the memory controller. The storage space of the buffer is configured by the memory controller to include multiple groups. The memory array is coupled to the memory controller and includes multiple memory blocks. Each group corresponds one-to-one with a memory block. Each group is used to store data to be written to the corresponding memory block. The memory controller performs write operations on a group-by-group basis.

[0004] Another embodiment of this disclosure discloses a method of operating a memory device, including: configuring a buffer storage space to include a plurality of groups; and mapping the plurality of groups one-to-one to a plurality of memory blocks of a memory array. Each group is used to store data to be written to the corresponding memory block, and write operations are performed on a group-by-group basis.

[0005] Another embodiment of this disclosure discloses a method for operating a memory device, including:

[0006] Multiple write count values ​​and multiple write-not-write record tables are established in a buffer; multiple write interval record tables are established in a memory array. The multiple write count values ​​correspond one-to-one with multiple memory blocks in the memory array. Each write count value records the number of write operations performed on the corresponding memory block. Each write count value has a start value and an upper limit value, and is divided into multiple intervals from the start value to the upper limit value. The multiple write-not-write record tables record whether multiple pages of the multiple memory blocks have been written to the multiple intervals corresponding to the multiple write count values. The multiple write interval record tables correspond one-to-one with the multiple memory blocks, and each write interval record table records the interval in which the multiple pages of the corresponding memory block were last written to.

[0007] To provide a better understanding of the above and other aspects of this disclosure, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1 A block diagram of a calculator system according to an embodiment of the present disclosure is shown;

[0009] Figure 2 A block diagram of a memory device according to an embodiment of the present disclosure is shown;

[0010] Figure 3 A flowchart illustrating an operation method of a memory device according to an embodiment of the present disclosure is shown;

[0011] Figures 4A-4B A flowchart illustrating an operation method of a memory device according to another embodiment of the present disclosure is shown;

[0012] Figure 5 A schematic diagram illustrating the operation of a memory device according to an embodiment of the present disclosure is shown;

[0013] Figure 6 A table showing the correspondence between write count values ​​and intervals according to an embodiment of the present disclosure is illustrated;

[0014] Figure 7 A write interval record table according to an embodiment of the present disclosure is illustrated;

[0015] Figures 8-10 A write / not write record table is illustrated according to an embodiment of the present disclosure;

[0016] Figure 11 A write-on / off record table according to another embodiment of this disclosure is illustrated;

[0017] Figure 12 A write interval record table according to another embodiment of the present disclosure is illustrated;

[0018] Figure 13 A write-on / off record table is illustrated according to yet another embodiment of this disclosure;

[0019] Figure 14 A write interval record table according to yet another embodiment of the present disclosure is illustrated;

[0020] Explanation of reference numerals in the attached figures:

[0021] 10: Calculator system;

[0022] 110: Central Processing Unit;

[0023] 112: Linear address converter;

[0024] 114: Dynamic Random Access Memory;

[0025] 116: Flash memory device;

[0026] 118: L3 Cache;

[0027] 20: Memory device;

[0028] 210: Memory controller;

[0029] 220: Buffer;

[0030] 230: Memory array;

[0031] 510: group;

[0032] S301~S310, S401~S413: Steps;

[0033] P1~P4: Data. Detailed Implementation

[0034] Please refer to Figure 1 , Figure 1 A block diagram of a calculator system according to an embodiment of the present disclosure is illustrated. The calculator system 10 includes a central processing unit (CPU) 110, a linear address converter 112, a dynamic random access memory (DRAM) 114, and a flash memory device 116. The CPU 110 may include an L3 cache 118. The DRAM 114 and the flash memory device 116 are coupled to the CPU 110 via the linear address converter 112. The linear address converter 112 can be used to map logical addresses used by the CPU 110 to physical addresses in the DRAM 114 and the flash memory device 116. Figure 1 The embodiments can illustrate how the flash memory device 116 can be used as hardware in a calculator system.

[0035] Please refer to Figure 2 , Figure 2 A block diagram of a flash memory device according to an embodiment of the present disclosure is shown. The flash memory device 20 includes a memory controller 210, a buffer 220, and a memory array 230.

[0036] Buffer 220 may be a storage device with high read / write speeds, such as static random access memory (SRAM). Buffer 220 may be integrated into memory controller 210 or externally connected to memory controller 210. Memory array 230 is coupled to memory controller 210. Memory controller 210 is used to control and operate memory array 230. In one embodiment, memory array 230 is a 3D NOR flash memory array.

[0037] In one embodiment, the memory array 230 includes a plurality of chips. A chip includes a plurality of memory tiles. A memory tile includes a plurality of memory sectors. A memory sector includes a plurality of pages. A page includes a plurality of memory cells.

[0038] In one embodiment, the size of a page is variable and has a maximum page size. The maximum amount of data written in a single write operation performed by the memory controller 210 on the memory array 230 is a maximum write size. In one embodiment, the size of a page can be 64 bytes (B), 128B, or 256B (i.e., the maximum page size is 256B). A single write operation can write 64B, 128B, or 256B of data (i.e., the maximum write size is 256B).

[0039] To reduce the number of times the memory controller 210 actually performs write operations on the memory array 230, the memory controller 210 may operate according to a first write policy and a second write policy.

[0040] The first write strategy involves configuring buffer 220 such that its storage space comprises multiple groups, each group corresponding (e.g., one-to-one) to a plurality of memory blocks in the memory array. Data to be written is stored in the group corresponding to the memory block to which it is to be written, and write operations are performed on a group-by-group basis. For example, if memory array 230 has X memory blocks, memory controller 210 configures buffer 220 such that its storage space comprises X groups corresponding to X memory blocks, where X is a positive integer. The group corresponding to the first memory block stores data to be written to the first memory block, the group corresponding to the second memory block stores data to be written to the second memory block, and so on. Performing write operations on a group-by-group basis means that memory controller 210 schedules write operations for data within the same group to be performed together in time. Performing write operations on a group-by-group basis increases the probability that the pages to be written are contiguous. Contiguous pages refer to contiguous page addresses. When the pages to be written are contiguous and the size of each page is smaller than the maximum page size, the memory controller 210 can combine multiple write operations into a single write operation. For example, if four 64-byte data entries need to be written to four consecutive 64-byte pages, the memory controller 210 can achieve the same result as four 64-byte write operations with a single 256-byte write operation. In one embodiment, the memory controller 210 can calculate a hash value corresponding to the physical address of a page using a hash function. The hash function is designed so that the physical addresses of pages belonging to the same memory block correspond to the same hash value. Pages corresponding to the same hash value will be grouped together.

[0041] The second write strategy is to determine whether the number of actual write operations can be reduced by reading some data from the target storage block into the buffer 220 before performing a write operation on a target storage block, based on the data stored in the group corresponding to the target storage block. If the determination is yes, then some data from the target storage block is read into the buffer 220 and then the write operation is performed based on the group corresponding to the target storage block.

[0042] For example, such as Figure 5As shown, assuming the maximum allowed data size for a single write operation is 256 bytes, and group 510 of the target memory block stores data P1, P3, and P4 to be written to the first, third, and fourth pages of the target memory block, with each page being 64 bytes in size. Without the second write strategy, the memory controller 210 would need to perform a 64-byte write operation to write data P1 and a 128-byte write operation to write the consecutive data P3 and P4. However, based on the second write strategy, the memory controller 210 determines that by reading data P2 stored on the second page of the target memory block into group 510, the four pages to be written to P1 through P4 will be consecutive. In other words, after the memory controller 210 performs a read operation to read data P2 from the target memory block of the memory array 230 into group 510 of the buffer 220, it can then perform a single 256-byte write operation to write data P1 through P4 to the target memory block. This effectively saves the latency of a write operation by incurring the latency of a read operation. Since the memory device 20 has a read latency that is much smaller than the write latency (for example, the read latency is one-thousandth of the write latency), it is worthwhile to spend one or even more read operations to save more than one write operation.

[0043] To manage write interference, the memory controller 210 may be used to store multiple write interval record tables in the memory array 230, and multiple write count values ​​and multiple write-on / off record tables in the buffer 220. In one embodiment, the write count values, write-on / off record tables, and write interval record tables may be created and modified by the memory controller 210.

[0044] The write count values ​​correspond to the plurality of storage blocks. For each storage block, the corresponding write count value represents the number of times a write operation has been performed on that storage block. When any page in that storage block is written, the write count value corresponding to that storage block is incremented by one. For example, assuming the memory array 230 includes X storage blocks, the buffer 220 will store X write count values ​​corresponding to the X storage blocks. The write count value has an initial value and an upper limit value. When the write count value reaches the upper limit value, it is reset to the initial value before the next increment. In one embodiment, the initial value is 0. The upper limit value can be determined based on the number of write interferences tolerated. Write interference refers to the impact on data stored in nearby pages when a page is written. The data stored in a page may be corrupted as the number of write interferences increases. The number of write interferences a page can tolerate against write interference can be obtained through experiments and statistics; that is, when the number of write interferences exceeds the tolerance number, the data in the page may be corrupted. In one embodiment, the upper limit value is equal to the tolerance number. For ease of explanation, the upper limit and the number of tolerances will be assumed to be 100,000 (one hundred thousand) in the following text.

[0045] The write count value is divided into multiple intervals from the initial value to the upper limit value. In one embodiment, the range from 0 to 100k (hundred thousand) is divided into ten intervals S0 to S9, as follows. Figure 6 As shown. The first interval S0 is from 0 to 10k (ten thousand), the second interval S1 is from 10001 to 20k (twenty thousand), and so on.

[0046] In one embodiment, the number of write interval record tables is equal to the number of memory blocks in the memory array 230. Each write interval record table corresponds one-to-one with one of the multiple memory blocks and records the interval at which the corresponding memory block's multiple pages were last written. For example, assuming the memory array 230 has X memory blocks and each memory block has Y pages, the memory array 230 will store X write interval record tables corresponding to the X memory blocks. Each write interval record table includes Y fields corresponding to the Y pages of that memory block, and these fields are used to record the interval at which the corresponding page was last written, where Y is a positive integer. Figure 7 This example shows a write interval record table corresponding to a memory block containing 4096 pages. In this example, intervals S0 to S9 can be represented using four bits of binary data. For example, intervals S0 to S9 are represented by binary 0 to 9, i.e., 0000 represents interval S0, 0001 represents interval S1, 0010 represents interval S2, and so on.

[0047] In one embodiment, the number of write-in / write-out record tables is equal to the number of memory blocks in the memory array 230. Each write-in / write-out record table corresponds one-to-one with the plurality of memory blocks and records whether the plurality of pages of the corresponding memory block have been written to within the interval corresponding to the write count value of that memory block. When the interval corresponding to the write count value of a memory block in the write-in / write-out record table changes, the memory controller 210 updates the write interval record table corresponding to the same memory block according to the write-in / write-out record table and then resets it. In one embodiment, assuming the memory array has a total of X memory blocks and each memory block has Y pages, the buffer 220 stores X write-in / write-out record tables corresponding to the X memory blocks. Each write-in / write-out record table includes Y fields corresponding to the Y pages of that memory block. Each field can be a one-bit binary data to record whether the corresponding page has been written to within the interval corresponding to the write count value of that memory block, where 0 represents no writing and 1 represents writing. When the write-in / write-out record table is reset, the values ​​of all fields are reset to 0. Figures 8-10 This displays an example of a write / notification record table corresponding to a specific storage block. When the write count is 0, the value of the field corresponding to all pages in the write / notification record table is 0, such as... Figure 8As shown. When the write count is 1, assuming page #1 is written, the value of the field corresponding to page code #1 will be set to 1, such as... Figure 9 As shown. When the write count is 2, assuming page #3 is written, the value of the field corresponding to page code #3 will be set to 1, such as... Figure 10 As shown. When the write count is 3, assuming page #1 is written, the value of the field corresponding to page code #1 will remain 1. The record table is the same whether a write occurs or not. Figure 10 As shown. When the write count reaches 10k, the write-or-not-write record table will be reset before the write count becomes 10001, and the values ​​of the fields corresponding to all pages will be reset to 0.

[0048] When the memory controller 210 updates the corresponding write interval record table based on the write / not write record table for a certain interval, it performs the following: (1) scans the write / not write record table to find pages that have been written in that interval; (2) changes the field in the corresponding write interval record table corresponding to the pages that have been written in that interval to that interval. For example, suppose the write / not write record table corresponds to the write / not write record table when the write count value of a certain memory block reaches 80k (the end of interval S8). Figure 11 As shown, the corresponding write interval record table before the update is as follows: Figure 7 As shown, the memory controller 210 according to Figure 11 The write / not-write record table update is shown. Figure 7 The table of records to be written in the specified range will yield the following result: Figure 12 The table showing the write interval records is shown. From... Figure 11 It can be seen that pages #1 and #3 of this storage block were written in interval S8, therefore Figure 12 The fields corresponding to page numbers #1 and #3 are updated to 1000, representing interval S8. Fields corresponding to pages not written to within interval S8 remain unchanged.

[0049] In another embodiment, the number of write-not-record tables is less than the number of memory blocks in the memory array 230. Each write-not-record table dynamically corresponds to one of a plurality of memory blocks. For example, assuming the memory array 230 has X memory blocks and Z write-not-record tables, each write-not-record table can dynamically correspond to one of (X / Z) memory blocks, where Z is a positive integer. For example, suppose a certain write-not-record table dynamically corresponds to memory block #1 and memory block #2. When the memory controller 210 performs a write operation on memory block #1, the memory controller 210 maps the write-not-record table to memory block #1 and uses the write-not-record table to record whether the page of memory block #1 has been written to in that interval. When the memory controller 210 switches to performing a write operation on memory block #2, the memory controller 210 first updates the write interval record table in the memory array 230 corresponding to memory block #1 according to the current write / not write record table (please refer to the previous text for the update method), then resets the write / not write record table and maps it to memory block #2 to record whether the page in memory block #2 has been written to in that interval. This operation is equivalent to "replacing" the write / not write record table used to record memory block #1 with the write / not write record table used to record memory block #2.

[0050] In one embodiment, the write / notification record table of the replaced memory block will not be "replaced" again before the transition to the next interval, to avoid frequent changes in the memory block corresponding to the write / notification record table. For example, suppose a certain write / notification record table dynamically corresponds to memory block #1 and memory block #2. Suppose that in interval S2, the object of the write operation performed by the memory controller 210 changes from memory block #1 to memory block #2, and then from memory block #2 back to memory block #1. After the memory controller 210 replaces the write / notification record table used to record memory block #1 with the write / notification record table used to record memory block #2, the memory controller 210 will not use that write / notification record table to record memory block #1 again until the interval changes from S2 to S3. In one embodiment, if the memory controller 210 performs a write operation on memory block #1 while the write record table used to record whether memory block #1 is written is being replaced, the memory controller 210 can directly modify the write interval record table in the memory array 230 corresponding to memory block #1.

[0051] In one embodiment, a write-or-not-write record table may correspond to more than two storage blocks. For example, Figure 13A write / not-write record table is displayed, corresponding to two memory blocks. The first 2048 fields of the write / not-write record table correspond to pages #1 to #2048 of memory block #0, and the last 2048 fields correspond to pages #2049 to #4096 of memory block #4. In this embodiment, the memory controller 210 needs to add multiple bits of label to the write / not-write record table to represent the memory block corresponding to each field. Figure 13 For example, the memory controller 210 adds a three-bit label 000 to the write-or-not-write record table to indicate that the field corresponding to page codes #1 to #2048 is used to record memory block #0, and adds a three-bit label 100 to indicate that the field corresponding to page codes #2049 to #4096 is used to record memory block #4.

[0052] The following will explain how the memory controller 210 uses a write interval record table, a write status record table, and a write counter value to prevent stored data from being damaged by write interference.

[0053] For each memory block, the memory controller 210 can be configured with a check cycle. When the write count value of a memory block reaches the check cycle, the memory controller 210 performs a check operation on that memory block. Performing a check operation on a memory block involves checking, according to the write interval record table corresponding to the memory block, whether there are any pages in the memory block that require a data flush. A data flush on a page means that the memory controller 210 rewrites the data corresponding to that page stored in the buffer 220 back to the page to maintain the correctness of the data stored on that page. The data corresponding to that page can be the same data currently stored on that page that was already stored in the buffer 220 before the data flush was triggered, or it can be read from that page and stored in the buffer 220 after the data flush was triggered.

[0054] In one embodiment, the check cycle is fixed. For example, the memory controller 210 may fix the check cycle to the beginning or end of intervals S2, S5, S8.

[0055] In one embodiment, the check period is dynamically adjustable. For each memory block, after each check operation is performed on that memory block, the memory controller 210 can set the new check period to be recorded in the field of the write interval record table corresponding to that memory block, which is the next interval closest to the current interval. The so-called next interval refers to the interval after the current interval. For example, the next intervals of interval S0, in descending order of proximity, are S1, S2, S3, S4, S5, S6, S7, S8, and S9. For another example, the next intervals of interval S5, in descending order of proximity, are S6, S7, S8, S9, S0, S1, S2, S3, and S4. For example, suppose the initial check period is set to the start of the next interval S0. For a certain memory block, the first check operation will be triggered after the corresponding write count value reaches 100k. After the check operation is triggered, the memory controller 210 can update the corresponding write interval record table according to the corresponding write status record table (interval S9) and then load the corresponding write interval record table into the buffer 220. Assuming the corresponding write range record table is as follows: Figure 14 As shown. When interval S9 ends and interval S0 begins, the memory block has already undergone 100k write operations, meaning that if a page was last written to interval S0, that page has been subjected to 100k write interruptions (the tolerance count) in the worst case. During the check operation, the memory controller 210 identifies a field that records the same interval as the current interval (S0 in this example). Figure 14 In the record, the field corresponding to page codes #1 and #4096 contains 0000 representing S0. Therefore, the memory controller 210 determines that pages #1 and #4096 need to be refreshed. Next, the memory controller 210 determines the next check cycle. The memory controller 210 finds the closest subsequent interval to the current interval from the corresponding write interval record table. Figure 14 In this context, assuming there is no field record for interval S1 (0001), the closest subsequent interval is interval S2 (0010) corresponding to the field record for page number #2. The memory controller 210 will then set the next check cycle to interval S2.

[0056] Please refer to Figure 3 , Figure 3 A flowchart illustrating an operation method of a memory device according to an embodiment of the present disclosure is shown. Figure 3 The flowchart can be executed by the memory controller 210 in response to each write request from the central processing unit 110.

[0057] In step S301, it is determined whether a data refresh should be triggered. If the determination is yes, step S302 is executed; if the determination is no, step S303 is executed. In one embodiment, when new data (e.g., from the central processing unit 110) is to be written and the storage space of buffer 220 is full, the memory controller 210 may determine to trigger a data refresh. In one embodiment, when the data to be written is an old version of data already stored in buffer 220 or the storage space of buffer 220 is not full, the memory controller 210 may determine not to trigger a data refresh.

[0058] In step S302, the old version data in buffer 220 is updated to the memory array 230, and the new data is written to buffer 2220. For example, when the new data is to be written to a target memory block, the memory controller 210 refreshes the target memory block according to the old version data corresponding to the target memory block in buffer 220, and overwrites the old version data corresponding to the target memory block in buffer 220 with the new data.

[0059] In step S303, data is written to memory array 230. For example, new data from central processing unit 110 is written to buffer 220, and then the new data in buffer 220 is written to memory array 230, or memory array 230 is updated according to the old version data in buffer 220.

[0060] In step S304, the write count value and the write status record table are updated. For example, after data is refreshed on the target storage block, the write count value and the write status record table corresponding to the target storage block are updated.

[0061] In step S305, it is determined whether the write count value has reached the next interval, for example, whether the write count value updated in S304 has reached the next interval. If the determination is yes, proceed to S306; if the determination is no, end the process.

[0062] In step S306, the corresponding write interval record table is updated based on the write count value updated in S304 and the write status record table.

[0063] In step S307, it is determined whether a check operation should be triggered based on the updated write count value and the check cycle. If the determination is yes, proceed to step S308; if the determination is no, end the process.

[0064] In step S308, the write interval record table of the corresponding storage block (e.g., the target storage block) is loaded into the buffer 220, and the write interval record table loaded into the buffer 220 is scanned to check if there are any pages that need to be refreshed. If it is determined that there are, the pages that need to be refreshed are refreshed and the write count value is reset.

[0065] In step S310, the write count value and the write status record table are updated.

[0066] Please refer to Figures 4A-4B , Figures 4A-4B A flowchart illustrating an operation method of a memory device according to another embodiment of the present disclosure is shown. Figures 4A-4B The operation method can be performed by the memory controller 210 in response to each request from the central processing unit 110, wherein the request can be a write request or a read request.

[0067] In step S401, the type of request is determined. If it is a read request, proceed to step S402; if it is a write request, proceed to step S403.

[0068] In step S402, data is read from buffer 220 or memory array 230.

[0069] In step S403, the write-to-write record table is queried to facilitate the execution of S404.

[0070] Steps S404 to S413 are similar to steps S301 to S310. Details of steps S404 to S413 can be found in the previous description and will not be repeated here.

[0071] This disclosure reduces the number of actual write operations and effectively manages write interference, preventing data corruption due to write interference.

[0072] In summary, although this disclosure has been presented above with reference to embodiments, it is not intended to limit this disclosure. Those skilled in the art to which this disclosure pertains can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. A memory device, characterized in that, include: A memory controller; A buffer, coupled to or embedded in the memory controller, the storage space of the buffer being configured by the memory controller to include multiple groups; and A memory array, coupled to the memory controller, and comprising multiple memory blocks. The plurality of groups correspond one-to-one with the plurality of storage blocks, and each group is used to store data to be written to the corresponding storage block. The memory controller performs write operations on a group-by-group basis. The buffer includes multiple write count values ​​and multiple write-not-write record tables. The multiple write count values ​​correspond one-to-one with the multiple storage blocks. Each write count value is used to record the number of times the corresponding storage block is written. The multiple write count values ​​have a start value and an upper limit value. The range from the start value to the upper limit value is divided into multiple intervals. The multiple write-not-write record tables are used to record whether multiple pages of the multiple storage blocks have been written to the multiple intervals corresponding to the multiple write count values. The memory array includes multiple write interval record tables, each of which corresponds one-to-one with the multiple memory blocks. Each write interval record table is used to record the multiple intervals on the multiple pages of the corresponding memory block where a write operation was last performed.

2. The memory device of claim 1, wherein the memory controller uses a hash function to map multiple entity addresses of multiple pages of each memory block to the same hash value.

3. The memory device of claim 1, wherein before performing a plurality of write operations on one of the plurality of memory blocks, the memory controller determines, based on the data stored in the group corresponding to the memory block, whether the number of actual write operations can be reduced by reading a portion of the data stored in the memory block into the buffer; if the determination is yes, then the portion of the data stored in the memory block is read into the buffer, and then one or more write operations are performed based on the group corresponding to the memory block.

4. The memory device according to claim 1, wherein when the interval corresponding to the write count value of each memory block changes, the memory controller updates the corresponding write interval record table according to the corresponding write / not write record table.

5. The memory device according to claim 1, wherein the memory controller sets a check cycle for each of the memory blocks, and when the write count value corresponding to each of the memory blocks reaches the check cycle, the memory controller determines whether to trigger a data refresh based on the write cycle record table corresponding to each of the memory blocks and the check cycle.

6. A method of operating a memory device, characterized in that, include: Configure the storage space of a buffer to include multiple groups; as well as The multiple groups are mapped one-to-one to multiple memory blocks of a memory array. Each group is used to store the data to be written to the corresponding storage block, and write operations are performed on a group-by-group basis. The buffer includes multiple write count values ​​and multiple write-not-write record tables. The multiple write count values ​​correspond one-to-one with the multiple storage blocks. Each write count value is used to record the number of times the corresponding storage block is written. The multiple write count values ​​have a start value and an upper limit value. The range from the start value to the upper limit value is divided into multiple intervals. The multiple write-not-write record tables are used to record whether multiple pages of the multiple storage blocks have been written to the multiple intervals corresponding to the multiple write count values. The memory array includes multiple write interval record tables, each of which corresponds one-to-one with the multiple memory blocks. Each write interval record table is used to record the multiple intervals on the multiple pages of the corresponding memory block where a write operation was last performed.

7. The operating method according to claim 6 further includes: Before performing multiple write operations on one of the plurality of storage blocks, it is determined whether the number of actual write operations can be reduced by reading a portion of the data stored in the storage block into the buffer, based on the data stored in the group corresponding to the storage block. If the determination is yes, then the portion of the data stored in the storage block is read into the buffer, and then one or more write operations are performed based on the group corresponding to the storage block.

8. A method of operating a memory device, characterized in that, include: Create multiple write counter values ​​and multiple write-not-write record tables in a buffer; as well as Create multiple write interval record tables in a memory array. The plurality of write count values ​​correspond one-to-one with the plurality of memory blocks of the memory array. Each write count value is used to record the number of times the corresponding memory block has been written. The plurality of write count values ​​are divided into a starting value and an upper limit value, and are divided into a plurality of intervals from the starting value to the upper limit value. The plurality of write / not write record tables are used to record whether the plurality of pages of the plurality of memory blocks have been written to the plurality of intervals corresponding to the plurality of write count values. The plurality of write interval record tables correspond one-to-one with the plurality of memory blocks. Each write interval record table is used to record the interval in which the plurality of pages of the corresponding memory block were last written.

9. The operating method according to claim 8, further comprising: For each write interval record table, when the interval corresponding to the write count value of the corresponding storage block changes, the write interval record table is updated according to the write status record table and the write count value corresponding to the corresponding storage block.

10. The operating method according to claim 8, further comprising: For each storage block, a check cycle is set; For each storage block, determine whether the corresponding write count value has reached the check cycle; as well as For each storage block, determine whether to trigger a check operation based on the corresponding check cycle and the write count value; In response to the determination that triggers the check operation, a decision is made, based on the corresponding write interval record table and the interval corresponding to the write count value, whether to perform a data refresh operation on one or more of the plurality of pages of the storage block.

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