Circuit and method for increasing refresh rate of LED display screen

Abstract

The application relates to a circuit and method for improving the refresh rate of an LED display screen. The circuit for improving the refresh rate of the LED display screen comprises a data processing module and a PWM control unit, wherein the analog constant current source module is used for reducing the current according to the required refresh rate, and the PWM control unit is used for transforming the PWM grayscale data to reduce the PWM period. The method for improving the refresh rate of the LED display screen is as follows: reducing the current according to the required refresh rate, and then proportionally adjusting the PWM grayscale data according to the required PWM period. By reducing the output current of the analog constant current source, the grayscale value is proportionally reduced under the same current equivalent value, and the display period of the PWM can be reduced, so that the refresh rate of the LED display screen can be improved under the premise of fixed scanning number.

Description

Circuits and methods for improving the refresh rate of LED displays Technical Field

[0001] This invention relates to the field of LED display technology, and in particular to a circuit and method for improving the refresh rate of an LED display. Background Technology

[0002] With the continuous development of LED display driving technology, LED displays are being used more and more widely, and users' requirements for the display effect of LED displays are also getting higher and higher. Currently, the pixel density of LED displays is increasing daily, which means that LED constant current driver chips must be able to drive as many pixels as possible. To achieve this goal, most small-pitch LED displays on the market currently use solutions that increase column drive channels and increase the number of row scans. However, in LED display technology, factors affecting display effect include the number of scans, refresh rate, and grayscale bit depth, and these three factors are interdependent. The refresh rate of an LED display refers to the number of times the image displayed on the LED display is repeated per second. Therefore, with a fixed refresh rate, as the number of row scans increases, the conduction time of each row will shorten, thus limiting the frequency of the PWM clock and making it impossible to meet high grayscale levels. Summary of the Invention

[0003] To address some or all of the problems in the existing technology, and in order to achieve a higher scan number without increasing the GCLK clock frequency and reducing the PWM grayscale level, the first aspect of this invention provides a circuit for improving the refresh rate of an LED display screen, comprising:

[0004] A simulated constant current source module is used to reduce current according to the required refresh rate; and

[0005] The PWM control unit is used to transform the PWM grayscale data to shorten the PWM cycle.

[0006] Furthermore, the PWM control unit includes a data processing unit.

[0007] Furthermore, the simulated constant current source module includes an input reference current module, wherein the input reference current comprises multiple current mirrors, and the magnitude of the input current of any one current mirror is I / 2. j Where I is the standard output current value of the analog constant current source module, and 2 j This is the current reduction factor.

[0008] Furthermore, the analog constant current source module includes multiple output transistors, which reduce the output current by 2%. j times.

[0009] Furthermore, the analog constant current source module adopts a sump-type structure, including an output module OUT_DAC, an input module I_DAC, an operational amplifier, three transistors, a PWM data port, and an IOUT port. The input module I_DAC and the output module OUT_DAC may include multiple sets of transistors and ports corresponding to each set of transistors, which are used to adjust the input current and the amplification ratio between the input and output transistors.

[0010] Furthermore, the analog constant current source module adopts a pull-out structure, including an output module OUT_DAC, an input module I_DAC, two operational amplifiers, two transistors, and an IOUT port. The input module I_DAC and the output module OUT_DAC may include multiple sets of transistors and ports corresponding to each set of transistors, which are used to adjust the input current and the amplification ratio between the input and output transistors.

[0011] Based on the driving circuit described above, a second aspect of the present invention provides a method for improving the refresh rate of an LED display screen, comprising:

[0012] Reduce current consumption based on the required refresh rate; and

[0013] Adjust the PWM grayscale data proportionally according to the required PWM period.

[0014] Furthermore, proportionally reducing the current includes:

[0015] Select input current as I / 2 j The current mirror is used as the reference current input, where I is the standard output current value of the analog constant current source module, and 2 j This is the current reduction factor.

[0016] Furthermore, proportionally reducing the current includes:

[0017] Select a reduction ratio of 2 j The output tube.

[0018] Furthermore, proportionally adjusting the PWM grayscale data includes:

[0019] Shift the PWM grayscale data that is greater than the preset value to the right by j bits, where 2 j This is the factor by which the PWM period is reduced.

[0020] The present invention provides a circuit and method for improving the refresh rate of an LED display screen. By reducing the output current of the analog constant current source, the grayscale value is proportionally reduced under the same current equivalent value, thereby reducing the display cycle of the PWM. Thus, the refresh rate of the LED display screen can be improved under the premise of a fixed number of scans. Attached Figure Description

[0021] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0022] Figure 1 is a schematic diagram of a circuit for improving the refresh rate of an LED display screen according to an embodiment of the present invention;

[0023] Figure 2 is a schematic diagram of the circuit structure of an analog constant current source module according to an embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of the circuit structure of an analog constant current source module according to another embodiment of the present invention;

[0025] Figure 4 is a schematic diagram of the circuit structure of the output module of the simulated constant current source of the present invention in a first embodiment.

[0026] Figure 5 is a schematic diagram of the circuit structure of the output module of the simulated constant current source of the present invention in a second embodiment;

[0027] Figure 6 is a schematic diagram of the circuit structure of the output module of the simulated constant current source of the present invention in a third embodiment;

[0028] Figure 7 is a schematic diagram of the circuit structure of the present invention for adjusting the output current of the simulated constant current source;

[0029] Figure 8 is a schematic diagram of the circuit structure of the first embodiment of the present invention, which simulates a constant current source to regulate the output current.

[0030] Figure 9 is a schematic diagram of the circuit structure of the second embodiment of the present invention, which simulates the constant current source regulating the output current.

[0031] Figure 10 is a schematic diagram of the circuit structure of the third embodiment of the present invention, which simulates the regulation of output current by a constant current source.

[0032] Figure 11 is a schematic diagram of the circuit structure of the fourth embodiment of the present invention, which simulates the regulation of output current by a constant current source.

[0033] Figure 12 is a flowchart illustrating a method for improving the refresh rate of an LED display screen according to an embodiment of the present invention. Detailed Implementation

[0034] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or in conjunction with other alternatives and / or additional methods or components. In other instances, well-known structures or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific numbers and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0035] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0036] It should be noted that the embodiments of the present invention describe the method steps in a specific order; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0037] For LED displays, there is an interdependent relationship between the scan count, refresh rate, and grayscale bit depth. To increase pixel density, the scan count typically needs to be increased. However, if the refresh rate remains constant, the grayscale level increases, leading to a decrease in image sharpness and a deterioration in display quality. To solve this problem, the inventors discovered that, assuming the complete PWM grayscale data for each pixel has n bits, its data is [P...]. n-1 ,P n-2 [P2, P1, P0], after data processing, the number of grayscale bits required to display in each row is m, and its data is [P m-1 ,P m-2 Let I be the output current of the analog constant current source, S be the number of line scans, GCLK be the PWM clock, f be the frequency, and t be the period. Then, the time required for each line of PWM grayscale display is t*2. m The display time for each subframe is T*=S*t*2 m And the refresh rate of this subframe is A complete frame requires time T = (2 n-m )*S*t*2 m =S*t*2 nFurthermore, since the frame rate of most current video sources is greater than or equal to 60Hz, this means that the time required for a complete frame must satisfy T≤1 / 60≈16.67ms. Therefore, it can be seen that as the number of line scans S increases, the GCLK period t and the PWM grayscale level 2 must be adjusted accordingly. n The reduction in period t requires a higher GCLK frequency, but increasing the frequency will cause waveform distortion and a series of problems; while the PWM grayscale level 2 n Lowering the refresh rate means a decrease in the sharpness of the displayed image and a deterioration in the display effect. Further research by the inventors revealed that because the human eye's sensitivity to LED brightness is non-linear, the actual displayed grayscale value follows an exponential curve (gamma transformation). Therefore, decreasing or increasing high grayscale values ​​by a few points has almost no impact on the display effect. Based on this, this invention provides a circuit and method for improving the refresh rate of an LED display screen. It improves the refresh rate by enhancing the mixed-signal design without increasing the GCLK clock frequency or reducing the PWM grayscale level.

[0038] The present invention will be further described below with reference to the accompanying drawings of the embodiments.

[0039] Figure 1 is a schematic diagram of a circuit for improving the refresh rate of an LED display screen according to an embodiment of the present invention.

[0040] As shown in Figure 1, a circuit for improving the refresh rate of an LED display screen includes a data processing module 101, an analog constant current source module 102, and a PWM control unit 103. The data processing module 101 converts the completed PWM grayscale data into grayscale data for each line to be displayed. After processing, the PWM values ​​are sent to the analog constant current source module 102 and the PWM control unit 103 for current reduction and data reduction, respectively, to reduce the PWM period and improve the refresh rate.

[0041] Since the LED display screen refreshes line by line, a complete PWM grayscale value for a single pixel needs to be converted into grayscale data for each line by the data processing module 101. For a PWM-controlled LED scanning screen, the refresh rate depends on the number of scan lines and the display time for each line. Given a fixed number of scans, increasing the refresh rate can only be achieved by reducing the display time for each line. In one embodiment of the invention, the grayscale data to be displayed for each line uses 8 bits of data.

[0042] The analog constant current source module 102 is used to adjust the output current according to the required refresh rate, i.e., the PWM cycle. Since the purpose of this invention is to improve the refresh rate, the analog constant current source module 102 is used to reduce the output current of the corresponding grayscale data. In embodiments of this invention, the analog constant current source module 102 can adopt a sinking structure or a pull-out structure. The sinking structure means that the current flows from the output terminal to the input terminal of the analog constant current source module 102, i.e., it absorbs the load current through the output terminal. The pull-out structure means that the current flows from the input terminal to the output terminal of the analog constant current source module 102 and is delivered to the load to provide current to the load. In embodiments of this invention, the analog constant current source module 102 can achieve current reduction through structures such as a current mirror.

[0043] Figure 2 is a schematic diagram of the circuit structure of an analog constant current source module according to an embodiment of the present invention. Figure 2 shows an analog constant current source module with a cascading structure. As shown in Figure 2, the analog constant current source module includes an output module OUT_DAC, an input module I_DAC, an operational amplifier 201, transistors M21, M22, and M23, a PWM data port, and an IOUT port. The output module OUT_DAC includes 6 transistors and 3 ports, and the input module I_DAC includes 7 transistors and 3 ports. However, those skilled in the art should understand that the scope of protection of the present invention is not limited to the specific number of transistors and ports described above. The input module I_DAC and the output module OUT_DAC may include multiple sets of transistors and corresponding ports for each set of transistors, as needed, for adjusting the input current and the amplification ratio between the input and output transistors. As shown in Figure 2, the negative feedback terminal of operational amplifier 201 is connected to the drain of transistor M22, the positive feedback terminal is connected to the source of transistor M23, and the output terminal is connected to the gate of transistor M21. The drain of transistor M21 is connected to the gate of transistor M22, the drain of transistor M216 in the input module I_DAC, and the gates of M25, M27, and M29 in the output module OUT_DAC. The source of transistor M21 is connected to the drain of transistor M22, and the source of transistor M22 is connected to the sources of transistors M25, M27, and M29 in the output module OUT_DAC. The gate of transistor M23 is connected to the PWM data port, and the drain of transistor M23 is connected to the IOUT port. As shown in Figure 2, the output module OUT_DAC includes 6 transistors and 3 ports. The gates of transistors M24, M26, and M28 are respectively connected to the port OUT_DAC. <1> OUT_DAC <2> OUT_DAC <3> The drain of transistor M24 is connected to the drains of transistors M26 and M28 and the source of transistor M23. The sources of transistors M24, M26, and M28 are connected to the drains of transistors M25, M27, and M29, respectively. Port OUT_DAC <1> OUT_DAC <2> OUT_DAC <3> It is connected to an external control circuit.As shown in Figure 2, the input module I_DAC includes 7 transistors and 3 ports. Transistors M211, M212, M213, M214, M215, and M216 form a current mirror structure. The gates of transistors M212, M214, and M216 are respectively connected to port I_DAC. <1> I_DAC <2> I_DAC <3> The sources of transistors M212, M214, and M216 are connected to the drains of transistors M211, M213, and M215, respectively. The drains of transistors M212, M214, and M216 are connected to the drain of transistor M21. The sources of transistors M210, M212, M214, and M216 are connected together. The gates of transistors M210, M212, M214, and M216 are connected to the drain of M210 and then to I_in. The other end of I_in is grounded. Port I_DAC <1> I_DAC <2> I_DAC <3> It is connected to an external control circuit. As shown in the figure, the input module I_DAC may include a multi-stage current mirror structure, which reduces the current through the input of each current mirror. Specifically, the input current of the current mirror is I / 2j, where I is the standard output current value of the analog constant current source module, and 2j is the current reduction factor. Furthermore, in one embodiment of the invention, current reduction can also be achieved through the output module OUT_DAC. Specifically, as shown in the figure, the output module OUT_DAC includes multiple transistors, which can also reduce the current.

[0044] Figure 3 is a schematic diagram of the circuit structure of an analog constant current source module according to another embodiment of the present invention. As shown in Figure 3, it is an analog constant current source module with a pull-out structure. As shown in Figure 3, the analog constant current source module includes an output module OUT_DAC, an input module I_DAC, a first operational amplifier 301, a second operational amplifier 302, a transistor M31, a transistor M34, and an IOUT port. As shown in Figure 3, the negative feedback terminal of the first operational amplifier 301 is connected to the drain of transistor M33 and the source of transistor M34. The positive feedback terminal of the first operational amplifier 301 is connected to the drain of transistor M32, the source of transistor M31, and the positive feedback terminal of the second operational amplifier 302. The output terminal of the first operational amplifier 301 is connected to the gate of transistor M34, and the drain of transistor M34 is connected to the IOUT port. The negative feedback terminal of the second operational amplifier 302 is connected to the VSET port, and the output terminal of the second operational amplifier 302 is connected to the gate of transistor M31. The drain of transistor M31 is connected to the drain of transistor M311 in the input module I_DAC, and the gates of M32 and M33 in the output module OUT_DAC. As shown in Figure 3, the output module OUT_DAC includes two transistors, with the sources of transistors M32 and M33 connected together and grounded. As shown in Figure 3, the input module I_DAC includes 6 transistors and 3 ports. Transistors M36, M37, M38, M39, M310, and M311 form a current mirror structure. The gates of transistors M37, M39, and M311 are respectively connected to port I_DAC. <1> I_DAC <2> I_DAC <3> The sources of transistors M37, M39, and M311 are connected to the drains of transistors M36, M38, and M310, respectively. The drains of transistors M37, M39, and M311 are connected to the drain of transistor M31. The sources of transistors M35, M36, M38, and M310 are connected together. The gates of M35, M36, M38, and M310 are connected to I_in, and the other end of I_in is grounded. Port I_DAC <1> I_DAC <2> I_DAC <3> It is connected to an external control circuit. However, those skilled in the art should understand that the scope of protection of this invention is not limited to the specific number of transistors and ports mentioned above. The input module I_DAC and the output module OUT_DAC can include multiple sets of transistors and ports corresponding to each set of transistors as needed, for adjusting the input current and the amplification ratio of the input and output transistors. As shown in the figure, the input module I_DAC includes a multi-stage current mirror structure, which reduces the current through the input of each stage of the current mirror. Specifically, the magnitude of the input current of the current mirror is I / 2j, where I is the standard output current value of the analog constant current source module, and 2j is the current reduction factor. In addition, in one embodiment of this invention, the current reduction can also be achieved through the output module OUT_DAC.Specifically, as shown in the figure, the output module OUT_DAC includes multiple transistors, which can also reduce the current.

[0045] The output module OUT_DAC can be placed on the output structure side. Figure 4 is a schematic diagram of the circuit structure of the first embodiment of the output module of the analog constant current source of the present invention. As shown in Figure 4, the output module includes 7 transistors and 6 ports. The gates of transistors M42, M44, and M46 are respectively connected to port DAC1. <1> DAC1 <2> DAC1 <3> The drains of transistors M42, M44, and M46 are connected to the IOUT port. The sources of transistors M42, M44, and M46 are connected to the drains of transistors M43, M45, and M47, respectively. The gates of transistors M43, M45, and M47 are connected to the VBAIS port and the gate of transistor M41. The sources of transistors M43, M45, and M47 are connected to the source of transistor M41 and grounded. The drain of transistor M41 is connected to the IBAIS port. Port DAC1 <1> DAC1 <2> DAC1 <3> It is connected to an external control circuit.

[0046] The output module OUT_DAC can also be placed on the input structure side. Figure 5 is a circuit structure diagram of the second embodiment of the output module of the analog constant current source of the present invention. As shown in Figure 5, the output module includes 7 transistors and 6 ports. The gates of transistors M52, M54, and M56 are respectively connected to port DAC2. <1> DAC2 <2> DAC2 <3> The drains of transistors M52, M54, and M56 are connected to the IBAIS port. The sources of transistors M52, M54, and M56 are connected to the drains of transistors M53, M55, and M57, respectively. The gates of transistors M53, M55, and M57 are connected to the VBAIS port and the gate of transistor M51. The sources of transistors M53, M55, and M57 are connected to the source of transistor M51 and grounded. The drain of transistor M51 is connected to the IOUT port. Port DAC2 <1> DAC2 <2> DAC2 <3> It is connected to an external control circuit.

[0047] The output module OUT_DAC can also be placed on both the input and output structures. Figure 6 is a schematic diagram of the circuit structure of the third embodiment of the output module of the analog constant current source of the present invention. As shown in Figure 6, the output module includes 12 transistors and 9 ports. The gates of transistors M61, M63, M65, M67, M69, and M611 are respectively connected to port DAC3. <3> DAC3 <2> DAC3 <1> DAC4 <1> DAC4 <2> DAC4 <3> The sources of transistors M61, M63, M65, M67, M69, and M611 are connected to the drains of transistors M62, M64, M66, M68, M610, and M612, respectively. The drains of transistors M61, M63, and M65 are connected to the IBAIS port, and the drains of transistors M67, M69, and M611 are connected to the IOUT port. The gates of transistors M62, M64, M66, M68, M610, and M612 are connected to the VBAIS port, and the sources of transistors M62, M64, M66, M68, M610, and M612 are grounded. Port DAC3 <3> DAC3 <2> DAC3 <1> DAC4 <1> DAC4 <2> DAC4 <3> It is connected to an external control circuit.

[0048] To better understand the current reduction method, an example is given below. Figure 7 is a schematic diagram of the circuit structure of the simulated constant current source regulating the output current of the present invention. As shown in Figure 7, the circuit structure of the simulated constant current source regulating the output current includes an output module OUT_DAC, an operational amplifier 701, a transistor M71, an IDAC port, and an IOUT port. The output module OUT_DAC includes two transistors and one grounded terminal. As shown in Figure 7, the positive feedback terminal of the operational amplifier 701 is connected to the drain of transistor M73 and the IOUT port, the negative feedback terminal of the operational amplifier is connected to the source of transistor M71 and the drain of M72, the output terminal of the operational amplifier is connected to the gate of transistor M71, the drain of transistor M71 is connected to the IDAC port, and the gates of transistors M72 and M73. The sources of transistors M72 and M73 are grounded, and I_IN is the input current value of the simulated constant current source module.

[0049] Figure 8 is a schematic diagram of the circuit structure of the first embodiment of the present invention for regulating the output current using a simulated constant current source. I_IN is the input current value of the simulated constant current source module. The amplification ratio of the output transistor to the input transistor is set to N:M, and the PWM duty cycle of the output is D. Therefore, the equivalent value of the output current is: D*(N / M)*I_IN. As shown in Figure 8, the circuit structure of the first embodiment of the simulated constant current source for regulating the output current includes an operational amplifier 801, 20 transistors, and 10 ports. As shown in Figure 8, the positive feedback terminal of operational amplifier 201 is connected to the drains of transistors M87, M89, and M811 and the IOUT port. The negative feedback terminal of operational amplifier is connected to the drains of transistors M81, M83, and M85 and the source of transistor M80. The output terminal of operational amplifier is connected to the gate of transistor M80. The drain of transistor M80 is connected to the drains of transistors M815, M817, and M819, and the gates of transistors M82, M84, M86, M88, M810, and M812. The gates of transistors M81, M83, M85, M87, M89, and M811 are respectively connected to port DAC5. <1> DAC5 <2> DAC5 <3> DAC6 <1> DAC6 <2> DAC6 <3> The sources of transistors M81, M83, M85, M87, M89, and M811 are connected to the drains of transistors M82, M84, M86, M88, M810, and M812, respectively. The sources of transistors M82, M84, M86, M88, M810, and M812 are connected together and grounded. The gates of transistors M815, M817, and M819 are connected to port I_DAC. <1> I_DAC <2> I_DAC <3> The sources of transistors M815, M817, and M819 are connected to the drains of transistors M814, M816, and M818, respectively. The sources of transistors M813, M814, M816, and M818 are connected together. The gates of transistors M813, M814, M816, and M818 are connected to the drain of M813 and then to I_in. The other end of I_in is grounded. Port I_DAC <1> I_DAC <2> I_DAC <3> These correspond to input currents I_IN / 4, I_IN / 2, and I_IN, respectively, and port DAC5. <1> DAC5 <2> DAC5 <3> DAC6 <1> DAC6 <2> DAC6 <3> The corresponding amplification factors for the transistors are 4M, 2M, M, N, N / 2, and N / 4, respectively. If the duty cycle D remains unchanged, the input current I_IN and the output transistor N and input transistor M remain constant; that is, only I_IN, M, and N are conducting, while the other paths are disconnected.

[0050] Assuming the duty cycle is increased to four times its original value, in order to keep the equivalent value of the output current unchanged, (N / M)*I needs to be reduced to 1 / 4 of its original value. There are several ways to achieve this. Figures 9, 10, and 11 are circuit structure diagrams of the second, third, and fourth embodiments of the present invention for simulating constant current source adjustment of output current. The circuit structure is the same as that in Figure 8, the difference being the different conduction paths. Figure 9 shows a schematic diagram of the circuit structure of the second embodiment of the present invention for simulating constant current source adjustment of output current. As shown in Figure 9, the input current I_IN is reduced to I / 4, while N / M remains unchanged. That is, only the I_IN / 4, M, and N paths are conducted, and the other paths are disconnected. Figure 10 shows a schematic diagram of the circuit structure of the third embodiment of the present invention for simulating constant current source adjustment of output current. As shown in Figure 10, the input current I_IN remains unchanged, the input transistor becomes 4M, and the output constant current transistor N remains unchanged. That is, only the I_IN, 4M, and N paths are conducted, and the other paths are disconnected. Figure 11 shows a schematic diagram of the circuit structure of the fourth embodiment of the present invention for simulating constant current source adjustment of output current. As shown in Figure 11, the input current I_IN remains unchanged, the input transistor M remains unchanged, and the output constant current transistor N is reduced to N / 4. That is, only the I_IN, M, and N / 4 paths are conducted, and the other paths are disconnected. In addition, multiple variables can be changed simultaneously, and the current reduction can be achieved by mixed control of the output module OUT_DAC and the input module I_DAC. For example, reduce I_IN to I_IN / 2, keep M unchanged, and reduce N to N / 2; or reduce I_IN to I_IN / 2, keep N unchanged, and increase M to 2M.

[0051] It should be understood that in other embodiments of the present invention, the current can also be increased by other current adjustment structures commonly used in the art, which will not be described in detail in this application.

[0052] For an LED scanning screen controlled by PWM, its refresh rate depends on the number of scan lines and the display time required for each line. Given a fixed number of scan lines, increasing the refresh rate can only be achieved by reducing the display time for each line. Therefore, after reducing the output current, the PWM grayscale data needs to be proportionally reduced to generate the final PWM control signal. The PWM control unit 103 is used to transform the PWM grayscale data to achieve the required PWM cycle. For example, for 10-bit PWM grayscale data, if the PWM grayscale data range needs to be reduced from (000000 0000)-(11 1111 1111)1024 states to (0000 0000)-(1111 1111)256 states. For the low grayscale (00 0000 0000)-(00 1111 1111) portion of the original data, the PWM data value remains unchanged, but the bit width becomes 8 bits (0000 0000)-(1111 1111), and the current value is reduced from I to I / 4. Therefore, the current corresponding to each grayscale value is 0, 0.25I / 256, 2*0.25I / 256, ..., 255*0.25I / 256, which equals 0, I / 1024, 2I / 1024, ..., 255I / 1024. Under the same PWM clock operating conditions, the PWM period is reduced from the original 1024 clock cycles to 256 clock cycles, thus increasing the refresh rate to 4 times the original. Based on this, in one embodiment of the present invention, the PWM control unit 103 includes a shift unit, which is used to perform a right shift operation on the received PWM grayscale data, converting it to 1 / 2 of its original value. j times, of which 2 j This is the factor by which the refresh rate is increased, which is also the factor by which the current is reduced.

[0053] Based on the driving circuit described above, Figure 12 is a flowchart illustrating a method for improving the refresh rate of an LED display screen according to an embodiment of the present invention. As shown in Figure 12, a method for improving the refresh rate of an LED display screen includes:

[0054] First, in step 1201, data processing. After the driver chip receives the PWM grayscale data, it first converts it into the PWM grayscale data that needs to be displayed for each line;

[0055] Next, in step 1202, current reduction occurs. After the PWM grayscale data processing is complete, it is sent to the analog constant current source module, which performs corresponding current reduction. Specifically, if it is desired to increase the current by 2... j For a refresh rate that is twice the normal value, the low grayscale output current should be reduced by 2 times. j The multiple was adjusted to 1 / 2. jFor example, if the refresh rate is expected to increase to four times its original value, the low grayscale output current should be reduced by a factor of four, adjusted to I / 4. As mentioned earlier, the current reduction can be operated at the input terminal of the analog constant current source module or at its output terminal. Taking the embodiment shown in Figure 2 as an example, this can be achieved by selecting an input current of I / 2. j A current mirror is used as a reference current input to achieve current reduction 2. j The ratio can be increased by 1 / 2. j Output tube output reduction 2 j The current is times that of the analog constant current source module, where I is the standard output current value of the analog constant current source module, and 2 j This is the current reduction factor;

[0056] Finally, in step 1203, the data is reduced. After the PWM grayscale data processing is completed, it is also sent to the PWM control unit for data reduction to generate a PWM control signal. The data is processed according to the expected refresh rate increase factor. As mentioned above, in the embodiments of the present invention, the data reduction is actually a shifting process of the larger data values ​​to make its period smaller. For example, for 10-bit PWM grayscale data, if the PWM period needs to be reduced to one-quarter of the original, the PWM grayscale data range needs to be reduced from (00 0000 0000)-(11 1111 1111)1024 states to (000000000)-(1111 1111)256 states. The specific operation is as follows: First, the PWM data values ​​in the range (00 0000 0000)-(001111 1111) of the original data remain unchanged, but the bit width becomes 8 bits. The current values ​​in the range (0000 0000)-(1111 1111) are reduced from I to I / 4. Therefore, the current corresponding to each grayscale value is 0, 0.25I / 256, 2*0.25I / 256, ..., 255*0.25I / 256, which equals 0, I / 1024, 2I / 1024, ..., 255I / 1024. Second, the data in the range (01 00000000)-(01 1111 1111) of the original data are shifted one bit to the right, and the bit width also becomes 8 bits (1000 0000000)-(001111 1111). The current value is reduced from I to I / 2 in the range (0000)-(11111111). Therefore, the current corresponding to each grayscale value in this range is 128*0.5I / 256, 129*0.5I / 256, ..., 255*0.5I / 256, which equals 256I / 1024, 258I / 1024, ..., 510I / 1024. Finally, the data in the range (10 00000000)-(11 1111 1111) in the original data is shifted two bits to the right, and the bit width becomes 8 bits (1000 0000)-(1111). If the current value I remains constant, then the current corresponding to each grayscale value within this range is 128*I / 256, 129*I / 256, ..., 255*I / 256, which equals 512I / 1024, 516I / 1024, ..., 1020I / 1024. Under the same PWM clock operating conditions, the PWM cycle is reduced from the original 1024 clock cycles to 256 clock cycles, thus increasing the refresh rate to 4 times the original, and so on.

[0057] Furthermore, in one embodiment of the present invention, in order to solve the problem of low grayscale consistency, after increasing the refresh rate, the low grayscale data can be further modified and the current reduced proportionally to increase the duty cycle of the low grayscale data, reduce the proportion of error caused by analog circuit response time in the entire display cycle, thereby improving low grayscale consistency.

[0058] By using the aforementioned driving method, reducing the current for low gray values ​​and proportionally reducing the data, the PWM cycle can be effectively reduced, thereby reducing the time required to display each line and improving the refresh rate.

[0059] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A circuit for improving the refresh rate of an LED display screen, characterized in that, include: The analog constant current source module is configured to reduce current according to the required refresh rate; And a PWM control unit, configured to proportionally reduce PWM grayscale data according to the current reduction factor, generating a PWM control signal with a reduced clock count; wherein, proportionally reducing the PWM grayscale data includes: shifting PWM grayscale data greater than a preset value to the right by j bits, where 2 j This is the factor by which the number of PWM clock cycles is reduced.

2. The circuit as described in claim 1, characterized in that, The PWM control unit includes a data processing unit.

3. The circuit as described in claim 1, characterized in that, The simulated constant current source module includes an input reference current module, which comprises multiple current mirrors, wherein the magnitude of the input current of any one current mirror is I / 2. j Where I is the standard output current value of the analog constant current source module, and 2 j This is the current reduction factor.

4. The circuit as described in claim 1, characterized in that, The simulated constant current source module includes multiple output transistors, which reduce the output current by 2%. j times.

5. The circuit as described in claim 1, characterized in that, The analog constant current source module adopts a sump-type structure, including an output module OUT_DAC, an input module I_DAC, an operational amplifier, three transistors, a PWM data port, and an IOUT port. The input module I_DAC and the output module OUT_DAC may include multiple sets of transistors and corresponding ports for each set of transistors, which are used to adjust the input current and the amplification ratio between the input and output transistors.

6. The circuit as described in claim 1, characterized in that, The analog constant current source module adopts a pull-out structure, including an output module OUT_DAC, an input module I_DAC, two operational amplifiers, two transistors, and an IOUT port. The input module I_DAC and the output module OUT_DAC may include multiple sets of transistors and a corresponding port for each set of transistors, which are used to adjust the input current and the amplification ratio between the input and output transistors.

7. A method for improving the refresh rate of an LED display screen, characterized in that, The steps include: reducing the current according to the required refresh rate; and proportionally reducing the PWM grayscale data according to the current reduction factor to obtain the required number of PWM clock cycles; wherein, proportionally reducing the PWM grayscale data includes: shifting PWM grayscale data greater than a preset value to the right by j bits, where 2 j This is the factor by which the number of PWM clock cycles is reduced.

8. The method as described in claim 7, characterized in that, Reducing current involves the following steps: Selecting an input current of I / 2 j The current mirror is used as the reference current input, where I is the standard output current value of the analog constant current source module, and 2 j This is the current reduction factor.

9. The method as described in claim 7, characterized in that, The current reduction includes the following steps: Select a reduction ratio of 2. j The output tube.

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