Array substrate, driving method and display device

Abstract

The application provides an array substrate, a driving method and a display device. The array substrate comprises a driving module, a plurality of rows and columns of sub-pixels, a plurality of columns of data lines and a plurality of rows of scanning lines; one frame time comprises at least two sub-frames; the driving module provides scanning signals to the scanning lines, controls the plurality of rows of scanning lines to be opened in turn in the sub-frames, and controls the sub-pixels corresponding to the same color and electrically connected to the opened scanning lines and the same data line in the sub-frames; in the sub-frames, there are overlapping time periods and non-overlapping time periods between effective time periods of scanning signals provided by at least two adjacent scanning lines in the plurality of rows of scanning lines opened in turn; and data voltages received by the data line in at least part of the overlapping time periods are the same as data voltages received by the data line in at least part of the non-overlapping time periods. The application can improve the charging time of at least part of the sub-pixels, improve the charging rate and the refresh rate, and improve the display quality.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to an array substrate, a driving method, and a display device. Background Technology

[0002] In related technologies, pixel structures using a Dual Gate (DG) driving architecture can reduce display costs by reducing the number of data signal lines and thus the number of channels in the source driver chip. As display panels move towards larger sizes and higher resolutions, the display industry is constantly exploring how to balance cost and ensure display charging efficiency. Summary of the Invention

[0003] The main objective of this invention is to provide an array substrate, a driving method, and a display device that solve the problem of improving the charging rate of pixel structures in dual-gate architecture.

[0004] In one aspect, embodiments of the present invention provide an array substrate, including a driving module, multiple rows and columns of subpixels, multiple columns of data lines, and multiple rows of scan lines; one frame time includes at least two subframes; the subpixels are electrically connected to the scan lines and the data lines respectively, and are used to receive data voltages provided by the data lines under the control of scan signals provided by the scan lines;

[0005] The driving module is used to provide scanning signals to the scanning lines to control multiple rows of the scanning lines to open sequentially within the subframe, and to control the subpixels that are electrically connected to the opened scanning lines and electrically connected to the same data line within the subframe to have the same color.

[0006] Within the subframe, there are overlapping and non-overlapping time periods among the effective time periods of the scan signals provided by at least two adjacent scan lines in a series of sequentially opened scan lines;

[0007] The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0008] Optionally, one frame time includes N subframes, where N is an integer greater than 1; the driving module includes multi-level driving circuits and N initial voltage lines, the multi-level driving circuits include multi-level display driving circuits; the display driving circuits are used to provide scanning signals for the scan lines;

[0009] The nth initial voltage line is electrically connected to the input terminal of the nth level display driving circuit included in the driving module, and is used to provide an input signal to the nth level display driving circuit;

[0010] n is a positive integer less than or equal to N.

[0011] Optionally, the display driving circuit provides input signals to the adjacent N-level display driving circuits through its output terminal;

[0012] The display driving circuit provides a reset signal to the adjacent 2N-level display driving circuits through its output terminal.

[0013] Optionally, the multi-level driving circuit may further include a multi-level virtual driving circuit;

[0014] The virtual driving circuit is used to provide a reset signal to the corresponding level display driving circuit in the multi-level display driving circuit;

[0015] At least a portion of the N initial voltage lines are electrically connected to the reset terminal of the corresponding virtual drive circuit, for providing a reset signal to the corresponding virtual drive circuit.

[0016] Optionally, the multi-level driving circuit includes an M-level display driving circuit and a 2N-level virtual driving circuit; M is an integer greater than 1.

[0017] The a-level virtual driving circuit is used to provide a reset signal for the M-2N+a-level display driving circuit;

[0018] a is a positive integer less than or equal to 2N.

[0019] Optionally, one frame time includes four subframes; the driving module includes a multi-level driving circuit and four initial voltage lines; the multi-level driving circuit includes M levels of display driving circuit; M is an integer greater than 1;

[0020] The first initial voltage line is electrically connected to the input terminal of the first-stage display driver circuit and is used to provide an input signal to the first-stage display driver circuit.

[0021] The second initial voltage line is electrically connected to the input terminal of the second-stage display driver circuit and is used to provide input signals to the second-stage display driver circuit.

[0022] The third initial voltage line is electrically connected to the input terminal of the third-level display driver circuit and is used to provide an input signal to the third-level display driver circuit.

[0023] The fourth initial voltage line is electrically connected to the input terminal of the fourth-level display driver circuit, and is used to provide an input signal to the fourth-level display driver circuit.

[0024] Optionally, the m-th display driver circuit provides an input signal to the (m+4)-th display driver circuit through its output terminal; m is a positive integer, and m+4 is less than or equal to M;

[0025] The b-th display driver circuit provides a reset signal to the b-8th display driver circuit through its output terminal;

[0026] b is an integer greater than 8, and b is less than or equal to M.

[0027] Optionally, the drive module further includes an eight-level virtual drive circuit;

[0028] The first-level virtual driving circuit provides a reset signal to the M-7 level display driving circuit through its output terminal;

[0029] The second-level virtual drive circuit provides a reset signal to the M-6 level display drive circuit through its output terminal;

[0030] The third-level virtual drive circuit provides a reset signal to the M-5 level display drive circuit through its output terminal;

[0031] The fourth-level virtual drive circuit provides a reset signal to the M-4 level display drive circuit through its output terminal;

[0032] The fifth-level virtual drive circuit provides a reset signal to the M-3 level display drive circuit through its output terminal;

[0033] The sixth-level virtual drive circuit provides a reset signal to the M-2 level display drive circuit through its output terminal;

[0034] The seventh-level virtual drive circuit provides a reset signal to the (M-1)th-level display drive circuit through its output terminal;

[0035] The eighth-level virtual drive circuit provides a reset signal to the M-level display drive circuit through its output terminal.

[0036] Optionally, the second initial voltage line provides reset signals to the first-stage virtual drive circuit and the fifth-stage virtual drive circuit, respectively;

[0037] The third initial voltage line provides reset signals to the second-stage virtual drive circuit and the sixth-stage virtual drive circuit, respectively.

[0038] The fourth initial voltage line provides reset signals to the third-stage virtual drive circuit and the seventh-stage virtual drive circuit, respectively.

[0039] Optionally, the first initial voltage line provides reset signals to the fourth-level virtual drive circuit and the eighth-level virtual drive circuit, respectively.

[0040] Optionally, the array substrate described in at least one embodiment of the present invention further includes twelve clock signal lines; c is a positive integer;

[0041] The 12c-11 stage driver circuit is electrically connected to the first clock signal line; the 12c-10 stage driver circuit is electrically connected to the second clock signal line; the 12c-9 stage driver circuit is electrically connected to the third clock signal line; the 12c-8 stage driver circuit is electrically connected to the fourth clock signal line; the 12c-7 stage driver circuit is electrically connected to the fifth clock signal line; the 12c-6 stage driver circuit is electrically connected to the sixth clock signal line; the 12c-5 stage driver circuit is electrically connected to the seventh clock signal line; the 12c-4 stage driver circuit is electrically connected to the eighth clock signal line; the 12c-3 stage driver circuit is electrically connected to the ninth clock signal line; the 12c-2 stage driver circuit is electrically connected to the tenth clock signal line; the 12c-1 stage driver circuit is electrically connected to the eleventh clock signal line; and the 12c stage driver circuit is electrically connected to the twelfth clock signal line.

[0042] Optionally, a portion of the subpixels located in the same row are electrically connected to a row of scan lines for receiving scan signals from the scan lines;

[0043] Another portion of the subpixels located in the same row is electrically connected to the other row of scan lines for receiving scan signals from the other row of scan lines.

[0044] Optionally, the display driving circuit includes an input terminal, a carry output terminal, a drive output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit, and a drive output circuit.

[0045] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0046] The first reset circuit is electrically connected to the reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal input to the reset terminal; the reset terminal is electrically connected to the output terminal of the adjacent lower 2N stage drive circuit.

[0047] The second reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0048] The first node control circuit is electrically connected to the first node, the second node, and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0049] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0050] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0051] The carry-out circuit is electrically connected to the first node, the second node, the carry-out terminal, the first clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry-out terminal and the first clock signal terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node.

[0052] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0053] Optionally, at least some of the virtual driving circuits in the multi-level virtual driving circuit are first-type virtual driving circuits, which include an input terminal, a carry output terminal, a drive output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit, and a drive output circuit.

[0054] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0055] The first reset circuit is electrically connected to the reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal input to the reset terminal; the reset terminal is electrically connected to the corresponding initial voltage line.

[0056] The second reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0057] The first node control circuit is electrically connected to the first node, the second node, and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0058] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0059] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0060] The carry-out circuit is electrically connected to the first node, the second node, the carry-out terminal, the first clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry-out terminal and the first clock signal terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node.

[0061] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0062] Optionally, all of the multi-level virtual driving circuits are of the first type of virtual driving circuit.

[0063] Optionally, some of the virtual driving circuits in the multi-level virtual driving circuit are second-type virtual driving circuits. The second-type virtual driving circuit includes an input terminal, a carry output terminal, a drive output terminal, an input circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit, and a drive output circuit.

[0064] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0065] The second reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0066] The first node control circuit is electrically connected to the first node, the second node, and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0067] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0068] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0069] The carry-out circuit is electrically connected to the first node, the second node, the carry-out terminal, the first clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry-out terminal and the first clock signal terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node.

[0070] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0071] Optionally, some of the virtual driving circuits in the multi-level virtual driving circuit are first-type virtual driving circuits, and the other part of the virtual driving circuits in the multi-level virtual driving circuit are second-type virtual driving circuits.

[0072] The first type of virtual driving circuit includes an input terminal, a carry output terminal, a drive output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit, and a drive output circuit.

[0073] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0074] The first reset circuit is electrically connected to the reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal input to the reset terminal; the reset terminal is electrically connected to the corresponding initial voltage line.

[0075] The second reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0076] The first node control circuit is electrically connected to the first node, the second node, and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0077] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0078] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0079] The carry-out circuit is electrically connected to the first node, the second node, the carry-out terminal, the first clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry-out terminal and the first clock signal terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node.

[0080] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal, and the second voltage terminal, respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0081] The second type of virtual driving circuit includes an input terminal, a carry output terminal, a drive output terminal, an input circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit, and a drive output circuit.

[0082] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0083] The second reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0084] The first node control circuit is electrically connected to the first node, the second node, and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0085] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0086] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0087] The carry-out circuit is electrically connected to the first node, the second node, the carry-out terminal, the first clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry-out terminal and the first clock signal terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node.

[0088] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0089] In a second aspect, embodiments of the present invention provide a driving method applied to the above-mentioned array substrate, wherein a frame time includes at least two subframes; within the subframe, there are overlapping time periods and non-overlapping time periods among the effective time periods of the scan signals provided by at least two adjacent scan lines in a series of sequentially opened scan lines;

[0090] The driving method includes:

[0091] Within the subframe, the driving module provides a scanning signal to the scan line to control multiple rows of the scan line to open sequentially, and controls the subpixel that is electrically connected to the opened scan line and has the same color as the subpixel electrically connected to the same data line.

[0092] The data voltage of the data line is the same for at least a portion of the overlapping time period as the data voltage received by the data line for at least a portion of the non-overlapping time period.

[0093] Optionally, one frame time includes N subframes; adjacent N rows of scan lines in a multi-row scan line are set as a scan line group; the driving method includes:

[0094] Within the nth subframe, the driving module provides a scanning signal to the nth row of scan lines in the scan line group to control the nth row of scan lines to open;

[0095] N is an integer greater than 1, and n is a positive integer less than or equal to N.

[0096] In a third aspect, embodiments of the present invention provide a display device including the array substrate described above.

[0097] The embodiments of the present invention can realize the HSR (Hardware SuperResulation) function of the pixel structure of the dual gate architecture, so as to reduce costs while improving the charging time of at least some sub-pixels, thereby improving the charging rate and refresh rate and improving display quality. Attached Figure Description

[0098] Figure 1 This is a structural diagram of the pixel structure in the array substrate according to at least one embodiment of the present invention;

[0099] Figure 2 yes Figure 1 Timing diagram of at least one embodiment of the pixel structure shown;

[0100] Figure 3 yes Figure 1 Timing diagram of at least one embodiment of the pixel structure shown;

[0101] Figure 4 yes Figure 1 Timing diagram of at least one embodiment of the pixel structure shown;

[0102] Figure 5 yes Figure 1 Timing diagram of at least one embodiment of the pixel structure shown;

[0103] Figure 6 yes Figure 1 Timing diagram of at least one embodiment of the pixel structure shown;

[0104] Figure 7A This is a structural diagram of the first part of the driving module in the array substrate according to at least one embodiment of the present invention;

[0105] Figure 7B This is a structural diagram of the first part of the driving module in the array substrate according to at least one embodiment of the present invention;

[0106] Figure 8A This is a structural diagram of the second part of the driving module in the array substrate according to at least one embodiment of the present invention;

[0107] Figure 8B This is a structural diagram of the second part of the driving module in the array substrate according to at least one embodiment of the present invention;

[0108] Figure 9 This is a structural diagram of the first part of the driving module in the array substrate according to at least one embodiment of the present invention;

[0109] Figure 10 This is a timing diagram of the operation of the driving module in the array substrate according to at least one embodiment of the present invention;

[0110] Figure 11 This is a structural diagram of the display driving circuit in the array substrate according to at least one embodiment of the present invention;

[0111] Figure 12 This is a circuit diagram of the display driving circuit in the array substrate according to at least one embodiment of the present invention;

[0112] Figure 13 This is a structural diagram of the virtual driving circuit in the array substrate according to at least one embodiment of the present invention;

[0113] Figure 14 This is a circuit diagram of the virtual driving circuit in the array substrate according to at least one embodiment of the present invention;

[0114] Figure 15 This is a structural diagram of the virtual driving circuit in the array substrate according to at least one embodiment of the present invention;

[0115] Figure 16 This is a circuit diagram of the virtual driving circuit in the array substrate according to at least one embodiment of the present invention. Detailed Implementation

[0116] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0117] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal, and the other as the second terminal.

[0118] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0119] The array substrate described in this embodiment of the invention is characterized by comprising a driving module, multiple rows and columns of sub-pixels, multiple columns of data lines, and multiple rows of scan lines; one frame time includes at least two sub-frames; the sub-pixels are electrically connected to the scan lines and the data lines respectively, and are used to receive the data voltage provided by the data lines under the control of the scan signal provided by the scan lines;

[0120] The driving module provides scanning signals to the scan lines to control the sequential opening of multiple scan lines within the subframe. It also controls the subpixels electrically connected to the opened scan lines and to the same data line within the subframe to correspond to the same color. Here, "same color" refers to subpixels corresponding to color resists of different colors (e.g., red, green, and blue resists) when the display panel containing the array substrate is a liquid crystal display panel. The color resists can be located on one side of the array substrate or on one side of the color filter substrate included in the liquid crystal display panel (opposite to the array substrate). When the display panel containing the array substrate is an organic light-emitting diode (OLED) display panel, "same color" refers to subpixels emitting the same color light.

[0121] Within the subframe, there are overlapping and non-overlapping time periods among the effective time periods of the scan signals provided by at least two adjacent scan lines in a series of sequentially opened scan lines;

[0122] The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0123] In related technologies, pixel structures using a Dual Gate driving architecture suffer from horizontal and vertical stripe quality issues in large-size display products. This invention employs a Z-architecture dual-gate driving pixel structure (Z-architecture refers to pixel electrodes arranged in a Z-shape) to improve these issues. Simultaneously, to enhance charging efficiency and meet high-resolution display requirements, a High-Speed ​​Refresh Rate (HSR) function is utilized. In other words, this invention can implement the HSR function of a Z-architecture dual-gate driving pixel structure, thereby improving the charging time of at least some sub-pixels, increasing charging rate and refresh rate, and ultimately enhancing display quality.

[0124] In at least one embodiment of the present invention, within the subframe, the multiple rows of scan lines that open sequentially are a portion of the scan lines in the array substrate that correspond to the subframe. For example, when a frame time includes two subframes, in the first subframe, a portion of the scan lines in the array substrate that open sequentially, and in the second subframe, another portion of the scan lines in the array substrate that open sequentially.

[0125] In at least one embodiment of the present invention, the effective time period of the scan signal provided by the scan line refers to the time period during which the scan signal provided by the scan line is a valid scan signal;

[0126] At least two adjacent scan lines in a series of scan lines that are opened sequentially can refer to at least two scan lines that are opened at adjacent times.

[0127] The overlapping time period between the effective time period of the scan signal provided by the first scan line and the effective time period of the scan signal provided by the second scan line can refer to the time period during which both the scan signal provided by the first scan line and the scan signal provided by the second scan line are effective scan signals.

[0128] During the non-overlapping time period between the effective time period of the scan signal provided by the first scan line and the effective time period of the scan signal provided by the second scan line, the scan signal provided by the first scan line and / or the scan signal provided by the second scan line are not valid scan signals.

[0129] In at least one embodiment of the present invention, the subpixel may include a switching transistor and a pixel electrode, wherein the gate of the switching transistor is electrically connected to the scan line, the first electrode of the switching element is electrically connected to the data line, and the second electrode of the switching element is electrically connected to the pixel electrode.

[0130] When the switching transistor is an n-type transistor, the potential of the effective scan signal can be a high voltage;

[0131] When the switching transistor is a p-type transistor, the potential of the effective scan signal can be a low voltage.

[0132] In specific implementation, when a frame time includes four subframes, within the first subframe, the first scan line, the fifth scan line, the ninth scan line, and the thirteenth scan line are turned on sequentially. An overlapping time period and a non-overlapping time period can be set between the time period during which the first scan line outputs a valid scan signal and the time period during which the fifth scan line outputs a valid scan signal. During the overlapping time period, the data voltage provided by the data line can be the same as the data voltage provided by the data line for at least a portion of the time during the non-overlapping time period.

[0133] In at least one embodiment of the present invention, a frame time includes N subframes, where N is an integer greater than 1; the driving module includes a multi-level driving circuit and N initial voltage lines, the multi-level driving circuit includes a multi-level display driving circuit; the display driving circuit is used to provide scanning signals for the scan lines;

[0134] The nth initial voltage line is electrically connected to the input terminal of the nth level display driving circuit included in the driving module, and is used to provide an input signal to the nth level display driving circuit;

[0135] n is a positive integer less than or equal to N.

[0136] In a specific implementation, when a frame time includes N subframes, the driving module may include a multi-level driving circuit and N initial voltage lines. The multi-level driving circuit may include a multi-level display driving circuit; the nth initial voltage line provides an input signal to the nth level display driving circuit.

[0137] Optionally, the display driving circuit provides input signals to the adjacent N-level display driving circuits through its output terminal;

[0138] The display driving circuit provides a reset signal to the adjacent 2N-level display driving circuits through its output terminal.

[0139] In specific implementation, the output terminal can be a drive output terminal or a carry output terminal for cascading. In at least one embodiment of the present invention, the carry output terminal is used as an example for explanation.

[0140] In at least one embodiment of the present invention, the multi-level driving circuit further includes a multi-level virtual driving circuit;

[0141] The virtual driving circuit is used to provide a reset signal to the corresponding level display driving circuit in the multi-level display driving circuit;

[0142] At least a portion of the N initial voltage lines are electrically connected to the reset terminal of the corresponding virtual drive circuit, for providing a reset signal to the corresponding virtual drive circuit.

[0143] In specific implementations, the multi-level driving circuit may further include multi-level virtual driving circuits. These virtual driving circuits can provide reset signals to corresponding display driving circuits within the multi-level display driving circuit. At least a portion of the N initial voltage lines provide reset signals to the corresponding virtual driving circuits. In actual operation, initial voltage lines can be reused to provide reset signals to the corresponding virtual driving circuits, or a dedicated reset signal line can be used. Reusing initial voltage lines has the advantage of reducing the number of signal lines used.

[0144] In at least one embodiment of the present invention, the multi-level driving circuit includes an M-level display driving circuit and a 2N-level virtual driving circuit; M is an integer greater than 1.

[0145] The a-level virtual driving circuit is used to provide a reset signal for the M-2N+a-level display driving circuit;

[0146] a is a positive integer less than or equal to 2N.

[0147] Optionally, one frame time includes four subframes; the driving module includes a multi-level driving circuit and four initial voltage lines; the multi-level driving circuit includes M levels of display driving circuit; M is an integer greater than 1;

[0148] The first initial voltage line is electrically connected to the input terminal of the first-stage display driver circuit and is used to provide an input signal to the first-stage display driver circuit.

[0149] The second initial voltage line is electrically connected to the input terminal of the second-stage display driver circuit and is used to provide input signals to the second-stage display driver circuit.

[0150] The third initial voltage line is electrically connected to the input terminal of the third-level display driver circuit and is used to provide an input signal to the third-level display driver circuit.

[0151] The fourth initial voltage line is electrically connected to the input terminal of the fourth-level display driver circuit, and is used to provide an input signal to the fourth-level display driver circuit.

[0152] In specific implementation, the first frame time may include four subframes, and the driving module may include four initial voltage lines. The first initial voltage line provides input signals to the first-level display driving circuit, the second initial voltage line provides input signals to the second-level display driving circuit, the third initial voltage line provides input signals to the third-level display driving circuit, and the fourth initial voltage line provides input signals to the fourth-level display driving circuit.

[0153] Optionally, the m-th display driver circuit sends an input signal to the (m+4)-th display driver circuit through its output terminal; m is a positive integer, and m+4 is less than or equal to M;

[0154] The b-th display driver circuit provides a reset signal to the b-8th display driver circuit through its output terminal;

[0155] b is an integer greater than 8, and b is less than or equal to M.

[0156] In at least one embodiment of the present invention, the driving module further includes an eight-level virtual driving circuit;

[0157] The first-level virtual driving circuit provides a reset signal to the M-7 level display driving circuit through its output terminal;

[0158] The second-level virtual drive circuit provides a reset signal to the M-6 level display drive circuit through its output terminal;

[0159] The third-level virtual drive circuit provides a reset signal to the M-5 level display drive circuit through its output terminal;

[0160] The fourth-level virtual drive circuit provides a reset signal to the M-4 level display drive circuit through its output terminal;

[0161] The fifth-level virtual drive circuit provides a reset signal to the M-3 level display drive circuit through its output terminal;

[0162] The sixth-level virtual drive circuit provides a reset signal to the M-2 level display drive circuit through its output terminal;

[0163] The seventh-level virtual drive circuit provides a reset signal to the (M-1)th-level display drive circuit through its output terminal;

[0164] The eighth-level virtual drive circuit provides a reset signal to the M-level display drive circuit through its output terminal.

[0165] In a specific implementation, when a frame time includes four subframes, the driving module may include eight levels of virtual driving circuits, each of which provides a reset signal to the corresponding display driving circuit.

[0166] Optionally, the second initial voltage line provides reset signals to the first-stage virtual drive circuit and the fifth-stage virtual drive circuit, respectively;

[0167] The third initial voltage line provides reset signals to the second-stage virtual drive circuit and the sixth-stage virtual drive circuit, respectively.

[0168] The fourth initial voltage line provides reset signals to the third-stage virtual drive circuit and the seventh-stage virtual drive circuit, respectively.

[0169] Optionally, the first initial voltage line provides reset signals to the fourth-level virtual drive circuit and the eighth-level virtual drive circuit, respectively.

[0170] In practical implementation, the first initial voltage line can provide reset signals to the fourth-level virtual drive circuit and the eighth-level virtual drive circuit respectively, but this is not a limitation. In actual operation, the fourth-level virtual drive circuit and the eighth-level virtual drive circuit may also not receive reset signals.

[0171] The array substrate described in at least one embodiment of the present invention further includes twelve clock signal lines; c is a positive integer;

[0172] The 12c-11 stage driver circuit is electrically connected to the first clock signal line; the 12c-10 stage driver circuit is electrically connected to the second clock signal line; the 12c-9 stage driver circuit is electrically connected to the third clock signal line; the 12c-8 stage driver circuit is electrically connected to the fourth clock signal line; the 12c-7 stage driver circuit is electrically connected to the fifth clock signal line; the 12c-6 stage driver circuit is electrically connected to the sixth clock signal line; the 12c-5 stage driver circuit is electrically connected to the seventh clock signal line; the 12c-4 stage driver circuit is electrically connected to the eighth clock signal line; the 12c-3 stage driver circuit is electrically connected to the ninth clock signal line; the 12c-2 stage driver circuit is electrically connected to the tenth clock signal line; the 12c-1 stage driver circuit is electrically connected to the eleventh clock signal line; and the 12c stage driver circuit is electrically connected to the twelfth clock signal line.

[0173] In a specific implementation, when a frame time includes four subframes, the array substrate may include a twelfth clock signal line, and each stage of the driving circuit is electrically connected to the corresponding clock signal line to receive the corresponding clock signal.

[0174] Optionally, a portion of the subpixels located in the same row are electrically connected to a row of scan lines for receiving scan signals from the scan lines;

[0175] Another portion of the subpixels located in the same row is electrically connected to the other row of scan lines for receiving scan signals from the other row of scan lines.

[0176] In a specific implementation, the one row of scan lines and the other row of scan lines can be set on opposite sides of sub-pixels located in the same row, and two columns of sub-pixels can be set between two adjacent columns of data lines.

[0177] The array substrate described in at least one embodiment of the present invention may include multiple rows of sub-pixels, multiple rows of scan lines, and multiple columns of data lines;

[0178] exist Figure 1 The image shows at least one embodiment of the array substrate comprising four rows of twelve columns of sub-pixels, a first row of scan lines G1, a second row of scan lines G2, a third row of scan lines G3, a fourth row of scan lines G4, a fifth row of scan lines G5, a sixth row of scan lines G6, a seventh row of scan lines G7, an eighth row of scan lines G8, a ninth row of scan lines G9, a tenth row of scan lines G10, an eleventh row of scan lines G11, a twelfth row of scan lines G12, a thirteenth row of scan lines G13, a fourteenth row of scan lines G14, a fifteenth row of scan lines G15, a sixteenth row of scan lines G16, a first column of data lines D1, a second column of data lines D2, a third column of data lines D3, a fourth column of data lines D4, a fifth column of data lines D5, a sixth column of data lines D6, and a seventh column of data lines D7.

[0179] The first row of scan lines G1 and the second row of scan lines G2 are located above and below the first row of subpixels, respectively.

[0180] The third scan line G3 and the fourth scan line G4 are located above and below the sub-pixels of the second row, respectively;

[0181] The fifth scan line G5 and the sixth scan line G6 are located above and below the sub-pixels of the third row, respectively;

[0182] The seventh scan line G7 and the eighth scan line G8 are located above and below the sub-pixels of the fourth row, respectively;

[0183] D1 is positioned to the left of the first column of subpixels; D2 is positioned between the second and third columns of subpixels; D3 is positioned between the fourth and fifth columns of subpixels; D4 is positioned between the sixth and seventh columns of subpixels; D5 is positioned between the eighth and ninth columns of subpixels; D6 is positioned between the tenth and eleventh columns of subpixels; and D7 is positioned to the right of the twelfth column of subpixels.

[0184] Two rows of scan lines are provided between every two rows of subpixels, and two data lines are provided between every two columns of subpixels. In this case, the subpixel includes a pixel electrode and a transistor, wherein the data lines are electrically connected through the transistor and the pixel electrode, and the scan lines are electrically connected to the gate of the transistor.

[0185] The first row, first column, red subpixel R11 is electrically connected to the first row scan line G1 and the first column data line D1, respectively; the first row, second column, green subpixel G12 is electrically connected to the second row scan line G2 and the first column data line D1, respectively; the first row, third column, blue subpixel B13 is electrically connected to the first row scan line G1 and the second column data line D2, respectively; the first row, fourth column, red subpixel R14 is electrically connected to the second row scan line G2 and the second column data line D2, respectively; the first row, fifth column, green subpixel G15 is electrically connected to the first row scan line G1 and the third column data line D3, respectively; the first row, sixth column, blue subpixel B16 is electrically connected to the second row scan line G2 and the third column data line D3, respectively; the first... The red subpixel R17 in the seventh column of the first row is electrically connected to the first row scan line G1 and the fourth column data line D4, respectively; the green subpixel G18 in the eighth column of the first row is electrically connected to the second row scan line G2 and the fourth column data line D4, respectively; the blue subpixel B19 in the ninth column of the first row is electrically connected to the first row scan line G1 and the fifth column data line D5, respectively; the red subpixel R110 in the tenth column of the first row is electrically connected to the second row scan line G2 and the fifth column data line D5, respectively; the green subpixel G111 in the eleventh column of the first row is electrically connected to the first row scan line G1 and the sixth column data line D6, respectively; the blue subpixel B112 in the twelfth column of the first row is electrically connected to the second row scan line G2 and the sixth column data line D6, respectively.

[0186] The second row, first column, red subpixel R21 is electrically connected to the third row scan line G3 and the second column data line D2; the second row, second column, green subpixel G22 is electrically connected to the fourth row scan line G4 and the second column data line D2; the second row, third column, blue subpixel B23 is electrically connected to the third row scan line G3 and the third column data line D3; the second row, fourth column, red subpixel R24 is electrically connected to the fourth row scan line G4 and the third column data line D3; the second row, fifth column, green subpixel G25 is electrically connected to the third row scan line G3 and the fourth column data line D4; the second row, sixth column, blue subpixel B26 is electrically connected to the fourth row scan line G4 and the fourth column data line D4; the second row... The red subpixel R27 in the seventh column of the second row is electrically connected to the scan line G3 in the third row and the data line D5 in the fifth column; the green subpixel G28 in the eighth column of the second row is electrically connected to the scan line G4 in the fourth row and the data line D5 in the fifth column; the blue subpixel B29 in the ninth column of the second row is electrically connected to the scan line G3 in the third row and the data line D6 in the sixth column; the red subpixel R210 in the tenth column of the second row is electrically connected to the scan line G4 in the fourth row and the data line D6 in the sixth column; the green subpixel G211 in the eleventh column of the second row is electrically connected to the scan line G3 in the third row and the data line D7 in the seventh column; the blue subpixel B212 in the twelfth column of the second row is electrically connected to the scan line G4 in the fourth row and the data line D7 in the seventh column.

[0187] The red subpixel R31 in the first column of the third row is electrically connected to the fifth row scan line G5 and the first column data line D1, respectively; the green subpixel G32 in the second column of the third row is electrically connected to the sixth row scan line G6 and the first column data line D1, respectively; the blue subpixel B33 in the third column of the third row is electrically connected to the fifth row scan line G5 and the second column data line D2, respectively; the red subpixel R34 in the fourth column of the third row is electrically connected to the sixth row scan line G6 and the second column data line D2, respectively; the green subpixel G35 in the fifth column of the third row is electrically connected to the fifth row scan line G5 and the third column data line D3, respectively; the blue subpixel B36 in the sixth column of the third row is electrically connected to the sixth row scan line G6 and the third column data line D3, respectively; the third... The red subpixel R37 in the seventh column of the third row is electrically connected to the scan line G5 in the fifth row and the data line D4 in the fourth column; the green subpixel G38 in the eighth column of the third row is electrically connected to the scan line G6 in the sixth row and the data line D4 in the fourth column; the blue subpixel B39 in the ninth column of the third row is electrically connected to the scan line G5 in the fifth row and the data line D5 in the fifth column; the red subpixel R310 in the tenth column of the third row is electrically connected to the scan line G6 in the sixth row and the data line D5 in the fifth column; the green subpixel G311 in the eleventh column of the third row is electrically connected to the scan line G5 in the fifth row and the data line D6 in the sixth column; the blue subpixel B312 in the twelfth column of the third row is electrically connected to the scan line G6 in the sixth row and the data line D6 in the sixth column.

[0188] Other row pixel references Figure 1 The connection method will not be elaborated here.

[0189] exist Figure 1 In the image, R41 represents the red subpixel in the first column of the fourth row; G7 represents the seventh scan line; G42 represents the green subpixel in the second column of the fourth row; and G8 represents the eighth scan line. B43 represents the blue subpixel in the third column of the fourth row; R44 represents the red subpixel in the fourth column of the fourth row; G45 represents the green subpixel in the fifth column of the fourth row; and B46 represents the blue subpixel in the sixth column of the fourth row. R47 represents the red subpixel in the seventh column of the fourth row; G48 represents the green subpixel in the eighth column of the fourth row; and B49 represents the blue subpixel in the ninth column of the fourth row. R410 represents the red subpixel in the tenth column of the fourth row; G411 represents the green subpixel in the eleventh column of the fourth row; and B412 represents the blue subpixel in the twelfth column of the fourth row.

[0190] The subpixels labeled R51 are red subpixels in the first column of the fifth row; G9 is the ninth scan line; G52 is the second green subpixel in the second column of the fifth row; and G10 is the tenth scan line. The subpixels labeled B53 are blue subpixels in the third column of the fifth row; R54 is red subpixels in the fourth column of the fifth row; G55 is green subpixels in the fifth column of the fifth row; and B56 is blue subpixels in the sixth column of the fifth row. The subpixels labeled R57 are red subpixels in the seventh column of the fifth row; G58 is green subpixels in the eighth column of the fifth row; and B59 is blue subpixels in the ninth column of the fifth row. The subpixels labeled R510 are red subpixels in the tenth column of the fifth row; G511 is green subpixels in the eleventh column of the fifth row; and B512 is blue subpixels in the twelfth column of the fifth row.

[0191] The subpixels labeled R61 are red subpixels in the first column of the sixth row; G11 is the eleventh row scan line; G62 is the second green subpixel in the second column of the sixth row; and G12 is the twelfth row scan line. The subpixels labeled B63 are blue subpixels in the third column of the sixth row; R64 are red subpixels in the fourth column of the sixth row; G65 are green subpixels in the fifth column of the sixth row; and B66 are blue subpixels in the sixth column of the sixth row. The subpixels labeled R67 are red subpixels in the seventh column of the sixth row; G68 are green subpixels in the eighth column of the sixth row; and B69 are blue subpixels in the ninth column of the sixth row. The subpixels labeled R610 are red subpixels in the tenth column of the sixth row; G611 are green subpixels in the eleventh column of the sixth row; and B612 are blue subpixels in the twelfth column of the sixth row.

[0192] The subpixels labeled R71 are red subpixels in the first column of the seventh row; G13 is the thirteenth scan line; G72 is the second green subpixel in the seventh row; and G14 is the fourteenth scan line. The subpixels labeled B73 are blue subpixels in the third column of the seventh row; R74 is red subpixels in the fourth column of the seventh row; G75 is green subpixels in the fifth column of the seventh row; and B76 is blue subpixels in the sixth column of the seventh row. The subpixels labeled R77 are red subpixels in the seventh column of the seventh row; G78 is green subpixels in the eighth column of the seventh row; and B79 is blue subpixels in the ninth column of the seventh row. The subpixels labeled R710 are red subpixels in the tenth column of the seventh row; G711 is green subpixels in the eleventh column of the seventh row; and B712 is blue subpixels in the twelfth column of the seventh row.

[0193] The subpixels labeled R81 are red subpixels in the first column of the eighth row; G15 is the fifteenth scan line; G82 is the second green subpixel in the second column of the eighth row; and G16 is the sixteenth scan line. The subpixels labeled B83 are blue subpixels in the third column of the eighth row; R84 are red subpixels in the fourth column of the eighth row; G85 are green subpixels in the fifth column of the eighth row; and B86 are blue subpixels in the sixth column of the eighth row. The subpixels labeled R87 are red subpixels in the seventh column of the eighth row; G88 are green subpixels in the eighth column of the eighth row; and B89 are blue subpixels in the ninth column of the eighth row. The subpixels labeled R810 are red subpixels in the tenth column of the eighth row; G811 are green subpixels in the eleventh column of the eighth row; and B812 are blue subpixels in the twelfth column of the eighth row.

[0194] This invention Figure 1 In at least one embodiment of the array substrate shown, when in operation, one frame time may include four subframes;

[0195] Within the first subframe, scan lines such as the first scan line G1, the fifth scan line G5, the ninth scan line G9, and the thirteenth scan line G13 are scanned sequentially until the scan lines corresponding to the first subframe of the display panel are scanned.

[0196] Within the second subframe, scan lines such as the second scan line G2, the sixth scan line G6, the tenth scan line G10, and the fourteenth scan line G14 are scanned sequentially until the scan lines corresponding to the second subframe of the display panel are scanned.

[0197] Within the third subframe, scan lines such as the third scan line G3, the seventh scan line G7, the eleventh scan line G11, and the fifteenth scan line G15 are scanned sequentially until the scan lines corresponding to the third subframe of the display panel are scanned.

[0198] Within the fourth subframe, scan lines G4 (fourth row), G8 (eighth row), G12 (twelfth row), and G16 (sixteenth row) are scanned sequentially until the scan lines corresponding to the fourth subframe of the display panel are scanned.

[0199] The subframes are scanned sequentially, that is, after the first subframe is scanned, the second subframe is scanned, after the second subframe is scanned, the third subframe is scanned, and after the third subframe is scanned, the fourth subframe is scanned.

[0200] In at least one embodiment of the present invention, multiple scan lines can be grouped. The number of scan line groups can be the same as the number of subframes included in one frame. For example, when the number of scan line groups is 4, the first group of scan lines can be scanned sequentially in the first subframe. The first group of scan lines may include the first row scan line G1, the fifth row scan line G5, the ninth row scan line G9, the thirteenth row scan line G13, and the 4F-3 row scan line. In the second subframe, the second group of scan lines is scanned sequentially. The second group of scan lines may include the second row scan line G2, the sixth row scan line G13, and the 4F-3 row scan line G14. 6. The tenth scan line G10, the fourteenth scan line G14, and the 4F-2 scan line; in the third subframe, the third group of scan lines is scanned sequentially, which may include the third scan line G3, the seventh scan line G7, the eleventh scan line G11, the fifteenth scan line G15, and the 4F-1 scan line; in the fourth subframe, the fourth group of scan lines is scanned sequentially, which may include the fourth scan line G4, the eighth scan line G8, the twelfth scan line G12, the sixteenth scan line G16, and the 4F scan line;

[0201] F can be an integer greater than 4.

[0202] like Figure 2 As shown, F1 represents one frame, F11 represents the first subframe, F12 represents the second subframe, F13 represents the third subframe, and F14 represents the fourth subframe.

[0203] In the first subframe F11, G1, G5, G9 and G13 sequentially provide valid scan signals and high voltage signals (valid scan signals refer to signals that can turn on the transistors in the display area. When the transistors in the display area are n-type transistors, the valid scan signal is a high voltage signal, and when the transistors in the display area are p-type transistors, the valid scan signal is a low voltage signal. In this case, we take an example where the transistors in the display area are n-type transistors).

[0204] In the second subframe F12, G2, G6, G10 and G14 sequentially provide high voltage signals;

[0205] In the third subframe F13, G3, G7, G11 and G15 sequentially provide high voltage signals;

[0206] In the fourth subframe F14, G4, G8, G12 and G16 sequentially provide high voltage signals.

[0207] exist Figure 2 In at least one of the embodiments shown, for example, the duration of F1 can be 8.33 ms, and the durations of F11, F12, F13 and F14 can all be 2.08 ms.

[0208] like Figure 3 As shown, in the first subframe,

[0209] G1, G5, G9 and G13 provide valid scan signals in sequence;

[0210] There is a first overlapping time period J1 between the effective time period of the first scan signal provided by G1 and the effective time period of the fifth scan signal provided by G5;

[0211] During the first overlapping time period J1, the first data line D1 can provide the first data voltage Vd1;

[0212] During the first non-overlapping time period B1, the potential of the first scan signal is low voltage, and the potential of the fifth scan signal is high voltage, that is, the fifth scan signal is a valid scan signal, and the first column data line D1 can provide the first data voltage Vd1;

[0213] There is a second overlapping time period J2 between the effective time period of the ninth scan signal provided by G9 and the effective time period of the thirteenth scan signal provided by G13;

[0214] During the second overlapping time period J2, the first data line D1 can provide the second data voltage Vd2;

[0215] During the second non-overlapping time period B2, the potential of the ninth scan signal is low, the potential of the thirteenth scan signal is high, and the first column data line D1 can provide the second data voltage Vd2.

[0216] Through such Figure 3 The timing control shown can improve the charging time of the fifth and ninth row subpixels, ensuring the charging rate while increasing the refresh rate.

[0217] exist Figure 3 In at least one of the embodiments shown, providing a valid scan signal for each scan line means that the scan signal provided by each scan line is a high voltage signal.

[0218] It should be noted that in this case, the first overlapping time period J1 and the second overlapping time period J2 can both be 1H, which is the charging time of one row. The first non-overlapping time period B1 and the second non-overlapping time period B2 can both be 1H or greater than 1H. That is, this case can achieve that at least some rows of subpixels can have a charging time greater than 1H. For example, when the G5 scan line is turned on, the first data voltage Vd1 can be used to charge some subpixels of the third row for a time of, for example, 2H, thereby improving the charging time of subpixels and improving the display quality for high-resolution products.

[0219] like Figure 4 As shown, in the second subframe,

[0220] G2, G6, G10 and G14 provide valid scan signals in sequence;

[0221] There is a third overlapping time period J3 between the effective time period of the second scan signal provided by G2 and the effective time period of the sixth scan signal provided by G6;

[0222] During the third overlapping time period J3, the first data line D1 can provide the third data voltage Vd3;

[0223] During the third non-overlapping time period B3, the potential of the second scan signal is low voltage, the potential of the sixth scan signal is high voltage, and the first column data line D1 can provide the third data voltage Vd3;

[0224] There is a fourth overlapping time period J4 between the effective time period of the tenth scan signal provided by G10 and the effective time period of the fourteenth scan signal provided by G14;

[0225] During the fourth overlapping time period J4, the first data line D1 can provide the fourth data voltage Vd4;

[0226] During the fourth non-overlapping time period B4, the potential of the tenth scan signal is low, and the potential of the fourteenth scan signal is high. The first data line D1 can provide the fourth data voltage Vd4. Figure 5 As shown, in the third subframe,

[0227] G3, G7, G11 and G15 provide valid scan signals in sequence;

[0228] There is a fifth overlapping time period J5 between the effective time period of the third scan signal provided by G3 and the effective time period of the seventh scan signal provided by G7;

[0229] During the fifth overlapping time period J5, the first data line D1 can provide the fifth data voltage Vd5;

[0230] During the fifth non-overlapping time period B5, the potential of the third scan signal is low voltage, the potential of the seventh scan signal is high voltage, and the first column data line D1 can provide the fifth data voltage Vd5.

[0231] There is a sixth overlapping time period J6 between the effective time period of the eleventh scan signal provided by G11 and the effective time period of the fifteenth scan signal provided by G15;

[0232] During the sixth overlapping time period J6, the first data line D1 can provide the sixth data voltage Vd6;

[0233] During the sixth non-overlapping time period B6, the potential of the eleventh scan signal is low, and the potential of the fifteenth scan signal is high. The first data line D1 can provide the sixth data voltage Vd6.

[0234] like Figure 6 As shown, in the fourth subframe,

[0235] G4, G8, G12 and G16 provide valid scan signals in sequence;

[0236] There is a seventh overlapping time period J7 between the effective time period of the fourth scan signal provided by G4 and the effective time period of the eighth scan signal provided by G8.

[0237] During the seventh overlapping time period J7, the first data line D1 can provide the seventh data voltage Vd7;

[0238] During the seventh non-overlapping time period B7, the potential of the fourth scan signal is low voltage, the potential of the eighth scan signal is high voltage, and the first column data line D1 can provide the seventh data voltage Vd7.

[0239] There is an eighth overlapping time period J8 between the effective time period of the twelfth scan signal provided by G12 and the effective time period of the sixteenth scan signal provided by G16;

[0240] During the eighth overlapping time period J8, the first data line D1 can provide the eighth data voltage Vd8;

[0241] During the eighth non-overlapping time period B8, the potential of the twelfth scan signal is low, the potential of the sixteenth scan signal is high, and the first column data line D1 can provide the eighth data voltage Vd8.

[0242] It should be noted that, in this case, the third overlapping time period J3, the fourth overlapping time period J4, the fifth overlapping time period J5, the sixth overlapping time period J6, the seventh overlapping time period J7, and the eighth overlapping time period J8 can all be 1 hour, i.e., the charging time of one line. The third non-overlapping time period B3, the fourth non-overlapping time period B4, the fifth non-overlapping time period B5, the sixth non-overlapping time period B6, the seventh non-overlapping time period B7, and the eighth non-overlapping time period B8 can all be 1 hour or longer, and no limitation is made here.

[0243] like Figures 3-6 As shown, within each subframe, there are overlapping and non-overlapping time periods between the effective time periods of the scan signals provided by at least two adjacent scan lines in the sequentially opened multi-row scan lines; the data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period, so as to realize the HSR function.

[0244] In an exemplary embodiment of the present invention, the array substrate may include twelve clock signal lines, 2160 levels of display driving circuits, and 8 levels of virtual driving circuits (the specific number of clock signal lines, display driving circuits, and virtual driving circuits can be set according to actual needs and is not limited here).

[0245] exist Figure 7A In the diagram, OC is the carry signal output terminal of each level of the display driver circuit, I1 is the input terminal of each level of the display driver circuit, R1 is the reset terminal of each level of the display driver circuit, CLK is the clock signal terminal, and TRST is the frame reset terminal of each level of the display driver circuit.

[0246] like Figure 7A As shown, the first-level display driver circuit GA1 is electrically connected to the first clock signal line CLK1, the input terminal of the first-level display driver circuit GA1 is electrically connected to the first initial voltage line STVA, and the reset terminal of the first-level display driver circuit GA1 is electrically connected to the carry output terminal of the ninth-level display driver circuit GA9.

[0247] The second-level display driver circuit GA2 is electrically connected to the second clock signal line CLK2. The input terminal of the second-level display driver circuit GA2 is electrically connected to the second initial voltage line STVB. The reset terminal of the second-level display driver circuit GA2 is electrically connected to the carry signal output terminal of the tenth-level display driver circuit GA10.

[0248] The third-level display driver circuit GA3 is electrically connected to the third clock signal line CLK3. The input terminal of the third-level display driver circuit GA3 is electrically connected to the third initial voltage line STVC. The reset terminal of the third-level display driver circuit GA3 is electrically connected to the carry output terminal of the eleventh-level display driver circuit GA11.

[0249] The fourth-level display driver circuit GA4 is electrically connected to the fourth clock signal line CLK4, the input terminal of the fourth-level display driver circuit GA4 is electrically connected to the fourth initial voltage line STVD, and the reset terminal of the fourth-level display driver circuit GA4 is electrically connected to the carry signal output terminal of the twelfth-level display driver circuit GA12.

[0250] The fifth-level display driver circuit GA5 is electrically connected to the fifth clock signal line CLK5. The input terminal of the fifth-level display driver circuit GA5 is electrically connected to the carry output terminal of the first-level display driver circuit GA1. The reset terminal of the fifth-level display driver circuit GA5 is electrically connected to the carry signal output terminal of the thirteenth-level display driver circuit GA13.

[0251] The sixth-level display driver circuit GA6 is electrically connected to the sixth clock signal line CLK6. The input terminal of the sixth-level display driver circuit GA6 is electrically connected to the carry output terminal of the second-level display driver circuit GA2. The reset terminal of the sixth-level display driver circuit GA6 is electrically connected to the carry signal output terminal of the fourteenth-level display driver circuit GA14.

[0252] The seventh-level display driver circuit GA7 is electrically connected to the seventh clock signal line CLK7. The input terminal of the seventh-level display driver circuit GA7 is electrically connected to the carry output terminal of the third-level display driver circuit GA3. The reset terminal of the seventh-level display driver circuit GA7 is electrically connected to the carry signal output terminal of the fifteenth-level display driver circuit GA15.

[0253] The eighth-level display driver circuit GA8 is electrically connected to the eighth clock signal line CLK8. The input terminal of the eighth-level display driver circuit GA8 is electrically connected to the carry output terminal of the fourth-level display driver circuit GA4. The reset terminal of the eighth-level display driver circuit GA8 is electrically connected to the carry signal output terminal of the sixteenth-level display driver circuit GA16.

[0254] The ninth-level display driver circuit GA9 is electrically connected to the ninth clock signal line CLK9. The input terminal of the ninth-level display driver circuit GA9 is electrically connected to the carry output terminal of the fifth-level display driver circuit GA5. The reset terminal of the ninth-level display driver circuit GA9 is electrically connected to the carry signal output terminal of the seventeenth display driver circuit.

[0255] The tenth-level display driver circuit GA10 is electrically connected to the tenth clock signal line CLK10. The input terminal of the tenth-level display driver circuit GA10 is electrically connected to the carry output terminal of the sixth-level display driver circuit GA6. The reset terminal of the tenth-level display driver circuit GA10 is electrically connected to the carry signal output terminal of the eighteenth display driver circuit.

[0256] The eleventh-level display driver circuit GA11 is electrically connected to the eleventh clock signal line CLK11. The input terminal of the eleventh-level display driver circuit GA11 is electrically connected to the carry output terminal of the seventh-level display driver circuit GA7. The reset terminal of the eleventh-level display driver circuit GA11 is electrically connected to the carry signal output terminal of the nineteenth display driver circuit.

[0257] The 12th-level display driver circuit GA12 is electrically connected to the 12th clock signal line CLK12. The input terminal of the 12th-level display driver circuit GA12 is electrically connected to the carry output terminal of the 8th-level display driver circuit GA8. The reset terminal of the 12th-level display driver circuit GA12 is electrically connected to the carry signal output terminal of the 20th display driver circuit.

[0258] The thirteenth-level display driver circuit GA13 is electrically connected to the first clock signal line CLK1. The input terminal of the thirteenth-level display driver circuit GA13 is electrically connected to the carry output terminal of the ninth-level display driver circuit GA9. The reset terminal of the thirteenth-level display driver circuit GA13 is electrically connected to the carry signal output terminal of the twenty-first display driver circuit.

[0259] The fourteenth-level display driver circuit GA14 is electrically connected to the second clock signal line CLK2. The input terminal of the fourteenth-level display driver circuit GA14 is electrically connected to the carry output terminal of the tenth-level display driver circuit GA10. The reset terminal of the fourteenth-level display driver circuit GA14 is electrically connected to the carry signal output terminal of the twenty-second display driver circuit.

[0260] The fifteenth-level display driver circuit GA15 is electrically connected to the third clock signal line CLK3. The input terminal of the fifteenth-level display driver circuit GA15 is electrically connected to the carry output terminal of the eleventh-level display driver circuit GA11. The reset terminal of the fifteenth-level display driver circuit GA15 is electrically connected to the carry signal output terminal of the twenty-third display driver circuit.

[0261] The sixteenth-level display driver circuit GA16 is electrically connected to the fourth clock signal line CLK4. The input terminal of the sixteenth-level display driver circuit GA16 is electrically connected to the carry output terminal of the twelfth-level display driver circuit GA12. The reset terminal of the sixteenth-level display driver circuit GA16 is electrically connected to the carry signal output terminal of the twenty-fourth display driver circuit.

[0262] In at least one embodiment of the present invention, the carry signal output terminal of the (n-4)th level display driving circuit provides an input signal to the nth level display driving circuit, and the carry signal output terminal of the (n+8)th level display driving circuit provides a reset signal to the nth level display driving circuit; n is a positive integer.

[0263] exist Figure 7A In the diagram, CLK is the clock signal terminal, I1 is the input terminal, R1 is the reset terminal, OC is the carry output terminal, and TRST is the frame reset terminal.

[0264] like Figure 7B As shown, in Figure 7A Based on at least one embodiment of the driving module shown, a driving output terminal G0, illustrating each stage of the display driving circuit, is added.

[0265] like Figure 8A As shown, the 2157th level display driver circuit GA2157 is electrically connected to the first clock signal line CLK1, the input terminal of the 2157th level display driver circuit GA2157 is electrically connected to the carry output terminal of the 2153rd level display driver circuit, and the reset terminal of the 2157th level display driver circuit GA2157 is electrically connected to the carry output terminal of the fifth level virtual driver circuit GR5.

[0266] The 2158th level display driver circuit GA2158 is electrically connected to the second clock signal line CLK2. The input terminal of the 2158th level display driver circuit GA2158 is electrically connected to the carry output terminal of the 2154th level display driver circuit. The reset terminal of the 2158th level display driver circuit GA2158 is electrically connected to the carry output terminal of the sixth level virtual driver circuit GR6.

[0267] The 2159th level display driver circuit GA2159 is electrically connected to the third clock signal line CLK3. The input terminal of the 2159th level display driver circuit GA2159 is electrically connected to the carry output terminal of the 2155th level display driver circuit. The reset terminal of the 2159th level display driver circuit GA2159 is electrically connected to the carry output terminal of the seventh level virtual driver circuit GR7.

[0268] The 2160th level display driver circuit GA2160 is electrically connected to the fourth clock signal line CLK4. The input terminal of the 2160th level display driver circuit GA2160 is electrically connected to the carry output terminal of the 2156th level display driver circuit. The reset terminal of the 2160th level display driver circuit GA2160 is electrically connected to the carry output terminal of the eighth level virtual driver circuit GR8.

[0269] The first-level virtual drive circuit GR1 is electrically connected to the fifth clock signal line CLK5. The input terminal of the first-level virtual drive circuit GR1 is electrically connected to the carry output terminal of the 2157th level display drive circuit GA2157. The reset terminal of the first-level virtual drive circuit GR1 is electrically connected to the second initial voltage line STVB.

[0270] The second-level virtual drive circuit GR2 is electrically connected to the sixth clock signal line CLK6. The input terminal of the second-level virtual drive circuit GR2 is electrically connected to the carry output terminal of the 2158th level display drive circuit GA2158. The reset terminal of the second-level virtual drive circuit GR2 is electrically connected to the third initial voltage line STVC.

[0271] The third-level virtual drive circuit GR3 is electrically connected to the seventh clock signal line CLK7. The input terminal of the third-level virtual drive circuit GR3 is electrically connected to the carry output terminal of the 2159th level display drive circuit GA2159. The reset terminal of the third-level virtual drive circuit GR3 is electrically connected to the fourth initial voltage line STVD.

[0272] The fourth-level virtual drive circuit GR4 is electrically connected to the eighth clock signal line CLK8. The input terminal of the fourth-level virtual drive circuit GR4 is electrically connected to the carry output terminal of the 2160th-level display drive circuit GA2160. The reset terminal of the fourth-level virtual drive circuit GR4 is not connected to a signal.

[0273] The fifth-stage virtual drive circuit GR5 is electrically connected to the ninth clock signal line CLK9. The input terminal of the fifth-stage virtual drive circuit GR5 is electrically connected to the carry output terminal of the first-stage virtual drive circuit GR1. The reset terminal of the fifth-stage virtual drive circuit GR5 is electrically connected to the second initial voltage line STVB.

[0274] The sixth-level virtual drive circuit GR6 is electrically connected to the tenth clock signal line CLK10. The input terminal of the sixth-level virtual drive circuit GR6 is electrically connected to the carry output terminal of the second-level virtual drive circuit GR2. The reset terminal of the sixth-level virtual drive circuit GR6 is electrically connected to the third initial voltage line STVC.

[0275] The seventh-level virtual drive circuit GR7 is electrically connected to the eleventh clock signal line CLK11. The input terminal of the seventh-level virtual drive circuit GR7 is electrically connected to the carry output terminal of the third-level virtual drive circuit GR3. The reset terminal of the seventh-level virtual drive circuit GR7 is electrically connected to the fourth initial voltage line STVD.

[0276] The eighth-level virtual drive circuit GR8 is electrically connected to the twelfth clock signal line CLK12. The input terminal of the eighth-level virtual drive circuit GR8 is electrically connected to the carry output terminal of the fourth-level virtual drive circuit GR4. The reset terminal of the eighth-level virtual drive circuit GR8 is not connected to a signal.

[0277] exist Figure 8A In the diagram, CLK is the clock signal terminal, I1 is the input terminal, R1 is the reset terminal, and OC is the carry output terminal.

[0278] exist Figure 8A In at least one embodiment shown, the fourth-level virtual drive circuit GR4 may include a first reset circuit, which may not be electrically connected to the first initial voltage line; or, the fourth-level virtual drive circuit GR4 may not include a first reset circuit.

[0279] The eighth-level virtual drive circuit GR8 may include a first reset circuit, which may not be electrically connected to the first initial voltage line; or, the eighth-level virtual drive circuit GR8 may not include a first reset circuit.

[0280] In at least one embodiment of the present invention, the reset terminals of the fourth-level virtual drive circuit GR4 and the eighth-level virtual drive circuit GR8 may also be electrically connected to the first initial voltage line STVA to receive the first initial voltage from the first initial voltage line STVA.

[0281] like Figure 8B As shown, in Figure 8A Based on at least one embodiment of the driving module shown, a driving output terminal G0, illustrating each stage of the display driving circuit, is added.

[0282] Figure 9 and Figure 8A The difference is that the reset terminal of the fourth-level virtual drive circuit GR4 is electrically connected to the first initial voltage line STVA, while the reset terminal of the eighth-level virtual drive circuit GR8 is electrically connected to the first initial voltage line STVA.

[0283] In at least one embodiment of the present invention, the GOA (Gate On Array, gate driving circuit disposed on the array substrate) input signal is divided into four parts: the first initial voltage line STVA, the second initial voltage line STVB, the third initial voltage line STVC, and the fourth initial voltage line STVD. At this time, the number of clock signal lines used by the array substrate is a multiple of 4. The present invention is illustrated using multiple driving circuits and 12 clock signal lines as an example, and correspondingly uses an eight-level virtual driving circuit to provide a reset signal for the last eight levels of the multi-level display driving circuit. All display driving circuits and all virtual driving circuits are electrically connected to the frame reset line STV0, and finally, all levels of driving circuits are reset by the frame reset signal provided by the frame reset line STV0.

[0284] like Figure 10As shown, when the multi-level driving circuit in the array substrate described in at least one embodiment of the present invention operates at 120Hz, the duration of one frame is 8.33ms. This can be achieved by splitting the GOA input signal into four parts, dividing the sub-pixel scan of the entire surface into four sub-frames, each lasting approximately 2.08ms. In the first scan, STVA provides a first initial voltage to the input terminal of GA1, and the first-level display driving circuit, the fifth-level display driving circuit, the ninth-level display driving circuit, the thirteenth-level display driving circuit, ..., the 2157th-level display driving circuit are sequentially turned on. After scanning the 2157th-level display driving circuit, STVB provides a second initial voltage to the input terminal of GA2, and the second-level display driving circuit, the sixth-level display driving circuit, the tenth-level display driving circuit, and the fourteenth-level display driving circuit are sequentially turned on. The 2158th level display driver circuit is turned on sequentially. After scanning the 2158th level display driver circuit, STVC provides the third initial voltage to the input of GA3, and the third, seventh, eleventh, fifteenth, ..., 2159th level display driver circuits are turned on sequentially. After scanning the 2159th level display driver circuit, STVD provides the fourth initial voltage to the input of GA4, and the fourth, eighth, twelfth, sixteenth, ..., 2160th level display driver circuits are turned on sequentially. After scanning the 2160th level display driver circuit, the frame reset line STV0 provides a frame reset signal to reset all driver circuits.

[0285] By adopting the above scheme, low voltage signals are provided for CLK2, CLK3, CLK4, CLK6, CLK7, CLK8, CLK10, CLK11 and CLK12 in the first subframe. This can reduce the current flowing through the above clock signal lines, reduce the corner temperature of the display panel PLG (Propel Link Gate), and solve the problem of excessive PLG temperature caused by high frequency.

[0286] In the second subframe, CLK1, CLK3, CLK4, CLK5, CLK7, CLK8, CLK9, CLK11 and CLK12 all provide low voltage signals, which can reduce the current flowing through the above clock signal lines, reduce the temperature of the PLG corner of the display panel, and solve the problem of excessive PLG temperature caused by high frequency.

[0287] In the third subframe, CLK1, CLK2, CLK4, CLK5, CLK6, CLK8, CLK9, CLK10 and CLK12 all provide low voltage signals, which can reduce the current flowing through the above clock signal lines, reduce the temperature of the PLG corner of the display panel, and solve the problem of excessive PLG temperature caused by high frequency.

[0288] In the fourth subframe, CLK1, CLK2, CLK3, CLK5, CLK6, CLK7, CLK9, CLK10 and CLK11 all provide low voltage signals. This reduces the current flowing through the above clock signal lines, lowers the PLG corner temperature of the display panel, and solves the problem of excessive PLG temperature caused by high frequency.

[0289] In related technologies, only the frame reset line is used to reset the eight-level virtual driving circuit. This reset method has the following problems: In the first subframe, after scanning the corresponding display driving circuit, the first-level virtual driving circuit and the fifth-level virtual driving circuit cannot be reset; in the second subframe, after scanning the corresponding display driving circuit, the first-level, second-level, fifth-level, and sixth-level virtual driving circuits cannot be reset; in the third subframe, after scanning the corresponding display driving circuit, the first-level, second-level, third-level, fifth-level, sixth-level, and seventh-level virtual driving circuits cannot be reset; in the fourth subframe, after scanning the corresponding display driving circuit, the frame reset line STV0 resets each level of the driving circuit. At this time, all eight levels of virtual driving circuits can be reset. However, since the first-level, second-level, third-level, fifth-level, sixth-level, and seventh-level virtual driving circuits have not been reset for a long time, the transistors they contain are easily damaged. Based on this, in at least one embodiment of the present invention, the reset terminal of the first-level virtual driving circuit GR1 is electrically connected to the second initial voltage line STVB; the reset terminal of the second-level virtual driving circuit GR2 is electrically connected to the third initial voltage line STVC; the reset terminal of the third-level virtual driving circuit GR3 is electrically connected to the fourth initial voltage line STVD; the reset terminal of the fifth-level virtual driving circuit GR5 is electrically connected to the second initial voltage line STVB; the reset terminal of the sixth-level virtual driving circuit GR6 is electrically connected to the third initial voltage line STVC; and the reset terminal of the seventh-level virtual driving circuit GR7 is electrically connected to the fourth initial voltage line STVD. In this way, after scanning the corresponding display driving circuit in each subframe, the corresponding virtual driving circuit can be reset without affecting the normal operation of the driving module including multiple driving circuits. Furthermore, in this invention, the virtual driving circuit and the initial four-level driving circuit share STVA, STVB, STVC, and STVD, or STVB, STVC, and STVD, which not only ensures normal virtual driving reset but also reduces peripheral signal lines, achieving a narrow bezel effect.

[0290] In at least one embodiment of the present invention, the frequency of the clock signal provided by each clock signal line can be up-frequencyed to 480Hz, so that the display frequency can reach 120Hz and the SOC (System-on-a-Chip) can output a data voltage of 60Hz.

[0291] In at least one embodiment of the present invention, the display driving circuit includes an input terminal, a carry output terminal, a drive output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit, and a drive output circuit.

[0292] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0293] The first reset circuit is electrically connected to the reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal input to the reset terminal; the reset terminal is electrically connected to the output terminal of the adjacent lower 2N stage drive circuit.

[0294] The second reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0295] The first node control circuit is electrically connected to the first node, the second node, and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0296] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0297] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0298] The carry-out circuit is electrically connected to the first node, the second node, the carry-out terminal, the first clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry-out terminal and the first clock signal terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node.

[0299] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0300] In at least one embodiment of the present invention, the first clock signal terminal and the second clock signal terminal may be the same clock signal terminal and connected to the same clock signal; or, the first clock signal terminal and the second clock signal terminal may be electrically connected to each other.

[0301] Optionally, the first clock signal terminal and the second clock signal terminal can also be different clock signal terminals, connected to different clock signals.

[0302] In practical implementation, in the display driving circuit, the reset terminal can be electrically connected to the output terminal of the adjacent lower 2N-level driving circuit to receive the reset signal from the adjacent lower 2N-level driving circuit.

[0303] Optionally, the output terminal can be a drive output terminal or a carry output terminal. In at least one embodiment of the present invention, the output terminal is described as a carry output terminal.

[0304] like Figure 11 As shown, at least one embodiment of the display driving circuit includes an input terminal I1, a carry output terminal OC, a drive output terminal G0, a reset terminal R1, an input circuit 11, a first reset circuit 12, a second reset circuit 13, a first node control circuit 14, a second node control circuit 15, an energy storage circuit 16, a carry output circuit 17, and a drive output circuit 18.

[0305] The input circuit 11 is electrically connected to the input terminal I1 and the first node PU respectively, and is used to control the potential of the first node PU according to the input signal connected to the input terminal I1;

[0306] The first reset circuit 12 is electrically connected to the reset terminal R1, the first node PU, and the first voltage terminal V1, respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the reset signal connected to the reset terminal R1; the reset terminal R1 is electrically connected to the carry output terminal of the adjacent lower 2N stage drive circuit.

[0307] The second reset circuit 13 is electrically connected to the frame reset terminal TRST, the first node PU, and the first voltage terminal V1, respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0308] The first node control circuit 14 is electrically connected to the first node PU, the first second node PD1, the second second node PD2 and the first voltage terminal V1 respectively. It is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the potential of the first second node PD1, and to control the connection between the first node PU and the first voltage terminal V1 under the control of the potential of the second second node PD2.

[0309] The second node control circuit 15 is electrically connected to the first control voltage terminal VDDO, the second control voltage terminal VDDE, the first node PU, the first second node PD1, the second second node PD2 and the first voltage terminal V1, respectively. It is used to control the potential of the first second node PD1 under the control of the first control voltage provided by the first control voltage terminal VDDO and the potential of the first node PU, and to control the potential of the second second node PD2 under the control of the second control voltage provided by the second control voltage terminal VDDE and the potential of the first node PU.

[0310] The energy storage circuit 16 is electrically connected to the first node PU and is used to store electrical energy.

[0311] The carry output circuit 17 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the carry output terminal OC, the clock signal terminal CLK, and the first voltage terminal V1, respectively. It is used to control the connection between the carry output terminal OC and the clock signal terminal CLK under the control of the potential of the first node PU, control the connection between the carry output terminal OC and the first voltage terminal V1 under the control of the potential of the first second node PD1, and control the connection between the carry output terminal OC and the first voltage terminal V1 under the control of the potential of the second second node PD2.

[0312] The drive output circuit 18 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the drive output terminal G0, the clock signal terminal CLK, and the second voltage terminal V2, respectively. It is used to control the connection between the drive output terminal G0 and the clock signal terminal CLK under the control of the potential of the first node PU, control the connection between the drive output terminal G0 and the second voltage terminal V2 under the control of the potential of the first second node PD1, and control the connection between the drive output terminal G0 and the second voltage terminal V2 under the control of the potential of the second second node PD2.

[0313] Optionally, the first voltage terminal can be a first low voltage terminal, and the second voltage terminal can be a second low voltage terminal.

[0314] like Figure 12 As shown, in Figure 11 Based on at least one embodiment of the display driving circuit shown, the input circuit may include a first transistor M1; the first reset circuit may include a second transistor M2, the second reset circuit 13 may include a third transistor M3, the first node control circuit may include a fourth transistor M4 and a fifth transistor M5; the second node control circuit may include a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15; the energy storage circuit includes a storage capacitor C; the carry output circuit includes a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18; and the drive output circuit includes a nineteenth transistor M19, a twentieth transistor M20, and a twenty-first transistor M21.

[0315] The gate and source of M1 are both electrically connected to the input terminal I1, and the drain of M1 is electrically connected to the first node PU.

[0316] The gate of M2 is electrically connected to the reset terminal R1, the source of M2 is electrically connected to the first node PU, and the drain of M2 is electrically connected to the first low voltage terminal LVGL.

[0317] The gate of M3 is electrically connected to the frame reset terminal TRST, the source of M3 is electrically connected to the first node PU, and the drain of M3 is electrically connected to the first low voltage terminal LVGL.

[0318] The gate of M4 is electrically connected to the first second node PD1, the source of M4 is electrically connected to the first node PU, and the drain of M4 is electrically connected to the first low voltage terminal LVGL.

[0319] The gate of M5 is electrically connected to the second node PD2, the source of M5 is electrically connected to the first node PU, and the drain of M5 is electrically connected to the first low voltage terminal LVGL.

[0320] The gate and source of M6 are both electrically connected to the first control voltage terminal VDDO, and the drain of M6 is electrically connected to the first pull-down control node PDCN1.

[0321] The gate of M7 is electrically connected to the first node PU, the source of M7 is electrically connected to the first pull-down control node PDCN1, and the drain of M7 is electrically connected to the first low voltage terminal LVGL.

[0322] The gate of M8 is electrically connected to the first pull-down control node PDCN1, the source of M8 is electrically connected to the first control voltage terminal VDDO, and the drain of M8 is electrically connected to the first second node PD1.

[0323] The gate of M9 is electrically connected to the first node PU, the source of M9 is electrically connected to the first second node PD1, and the drain of M9 is electrically connected to the first low voltage terminal LVGL.

[0324] The gate of M10 is electrically connected to the input terminal I1, the source of M10 is electrically connected to the first second node PD1, and the drain of M10 is electrically connected to the first low voltage terminal LVGL.

[0325] The gate and source of M11 are both electrically connected to the second control voltage terminal VDDE, and the drain of M11 is electrically connected to the second pull-down control node PDCN2.

[0326] The gate of M12 is electrically connected to the first node PU, the source of M12 is electrically connected to the second pull-down control node PDCN2, and the drain of M12 is electrically connected to the first low voltage terminal LVGL.

[0327] The gate of M13 is electrically connected to the second pull-down control node PDCN2, the source of M13 is electrically connected to the second control voltage terminal VDDE, and the drain of M13 is electrically connected to the second node PD2.

[0328] The gate of M14 is electrically connected to the first node PU, the source of M14 is electrically connected to the second node PD2, and the drain of M14 is electrically connected to the first low voltage terminal LVGL.

[0329] The gate of M15 is electrically connected to the input terminal I1, the source of M15 is electrically connected to the second node PD2, and the drain of M15 is electrically connected to the first low voltage terminal LVGL.

[0330] The first end of the storage capacitor C is electrically connected to the first node PU, and the second end of the storage capacitor C is electrically connected to the drive output terminal G0.

[0331] The gate of M16 is electrically connected to the first node PU, the source of M16 is electrically connected to the clock signal terminal CLK, and the drain of M16 is electrically connected to the carry output terminal OC.

[0332] The gate of M17 is electrically connected to the first second node PD1, the source of M17 is electrically connected to the carry output terminal OC, and the drain of M17 is electrically connected to the first low voltage terminal LVGL.

[0333] The gate of M18 is electrically connected to the second node PD2, the source of M18 is electrically connected to the carry output terminal OC, and the drain of M18 is electrically connected to the first low voltage terminal LVGL.

[0334] The gate of M19 is electrically connected to the first node PU, the source of M19 is electrically connected to the clock signal terminal CLK, and the drain of M19 is electrically connected to the drive output terminal G0.

[0335] The gate of M20 is electrically connected to the first second node PD1, the source of M20 is electrically connected to the drive output terminal G0, and the drain of M20 is electrically connected to the second low voltage terminal VGL.

[0336] The gate of M21 is electrically connected to the second node PD2, the source of M21 is electrically connected to the drive output terminal G0, and the drain of M21 is electrically connected to the second low voltage terminal VGL.

[0337] exist Figure 12 In at least one embodiment of the display driving circuit shown, all transistors are n-type transistors, but this is not a limitation.

[0338] In at least one embodiment of the present invention, the gate and source of M1 may be electrically connected to each other, but this is not a limitation. In actual operation, the gate of M1 may also be disconnected from the source of M1, and the source of M1 may be electrically connected to a low-voltage terminal.

[0339] In at least one embodiment of the present invention, at least a portion of the virtual driving circuits in the multi-level virtual driving circuit can be a first type of virtual driving circuit, which includes an input terminal, a carry output terminal, a drive output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit, and a drive output circuit.

[0340] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0341] The first reset circuit is electrically connected to the reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal input to the reset terminal; the reset terminal is electrically connected to the corresponding initial voltage line.

[0342] The second reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0343] The first node control circuit is electrically connected to the first node, the second node, and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0344] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0345] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0346] The carry-out circuit is electrically connected to the first node, the second node, the carry-out terminal, the first clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry-out terminal and the first clock signal terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node.

[0347] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0348] In at least one embodiment of the present invention, in the virtual drive circuit, the reset terminal may be electrically connected to the corresponding initial voltage line.

[0349] like Figure 13 As shown, at least one embodiment of the virtual driving circuit includes an input terminal I1, a carry output terminal OC, a drive output terminal G0, a reset terminal, an input circuit 11, a first reset circuit 12, a second reset circuit 13, a first node control circuit 14, a second node control circuit 15, an energy storage circuit 16, a carry output circuit 17, and a drive output circuit 18.

[0350] The input circuit 11 is electrically connected to the input terminal I1 and the first node PU respectively, and is used to control the potential of the first node PU according to the input signal connected to the input terminal I1;

[0351] The first reset circuit 12 is electrically connected to the reset terminal, the first node PU, and the first voltage terminal V1, respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the reset signal input to the reset terminal; the reset terminal is electrically connected to the initial voltage line STVX;

[0352] The second reset circuit 13 is electrically connected to the frame reset terminal TRST, the first node PU, and the first voltage terminal V1, respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0353] The first node control circuit 14 is electrically connected to the first node PU, the first second node PD1, the second second node PD2 and the first voltage terminal V1 respectively. It is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the potential of the first second node PD1, and to control the connection between the first node PU and the first voltage terminal V1 under the control of the potential of the second second node PD2.

[0354] The second node control circuit 15 is electrically connected to the first control voltage terminal VDDO, the second control voltage terminal VDDE, the first node PU, the first second node PD1, the second second node PD2 and the first voltage terminal V1, respectively. It is used to control the potential of the first second node PD1 under the control of the first control voltage provided by the first control voltage terminal VDDO and the potential of the first node PU, and to control the potential of the second second node PD2 under the control of the second control voltage provided by the second control voltage terminal VDDE and the potential of the first node PU.

[0355] The energy storage circuit 16 is electrically connected to the first node PU and is used to store electrical energy.

[0356] The carry output circuit 17 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the carry output terminal OC, the clock signal terminal CLK, and the first voltage terminal V1, respectively. It is used to control the connection between the carry output terminal OC and the clock signal terminal CLK under the control of the potential of the first node PU, control the connection between the carry output terminal OC and the first voltage terminal V1 under the control of the potential of the first second node PD1, and control the connection between the carry output terminal OC and the first voltage terminal V1 under the control of the potential of the second second node PD2.

[0357] The drive output circuit 18 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the drive output terminal G0, the clock signal terminal CLK, and the second voltage terminal V2, respectively. It is used to control the connection between the drive output terminal G0 and the clock signal terminal CLK under the control of the potential of the first node PU, control the connection between the drive output terminal G0 and the second voltage terminal V2 under the control of the potential of the first second node PD1, and control the connection between the drive output terminal G0 and the second voltage terminal V2 under the control of the potential of the second second node PD2.

[0358] Optionally, the initial voltage line can be one of the following: a first initial voltage line STVA, a second initial voltage line STVB, a third initial voltage line STVC, and a fourth initial voltage line STVD.

[0359] like Figure 14 As shown, in Figure 13 Based on at least one embodiment of the display driving circuit shown, the input circuit may include a first transistor M1; the first reset circuit may include a second transistor M2, the second reset circuit 13 may include a third transistor M3, the first node control circuit may include a fourth transistor M4 and a fifth transistor M5; the second node control circuit may include a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15; the energy storage circuit includes a storage capacitor C; the carry output circuit includes a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18; and the drive output circuit includes a nineteenth transistor M19, a twentieth transistor M20, and a twenty-first transistor M21.

[0360] The gate and source of M1 are both electrically connected to the input terminal I1, and the drain of M1 is electrically connected to the first node PU.

[0361] The gate of M2 is electrically connected to the initial voltage line STVX, the source of M2 is electrically connected to the first node PU, and the drain of M2 is electrically connected to the first low voltage terminal LVGL.

[0362] The gate of M3 is electrically connected to the frame reset terminal TRST, the source of M3 is electrically connected to the first node PU, and the drain of M3 is electrically connected to the first low voltage terminal LVGL.

[0363] The gate of M4 is electrically connected to the first second node PD1, the source of M4 is electrically connected to the first node PU, and the drain of M4 is electrically connected to the first low voltage terminal LVGL.

[0364] The gate of M5 is electrically connected to the second node PD2, the source of M5 is electrically connected to the first node PU, and the drain of M5 is electrically connected to the first low voltage terminal LVGL.

[0365] The gate and source of M6 are both electrically connected to the first control voltage terminal VDDO, and the drain of M6 is electrically connected to the first pull-down control node PDCN1.

[0366] The gate of M7 is electrically connected to the first node PU, the source of M7 is electrically connected to the first pull-down control node PDCN1, and the drain of M7 is electrically connected to the first low voltage terminal LVGL.

[0367] The gate of M8 is electrically connected to the first pull-down control node PDCN1, the source of M8 is electrically connected to the first control voltage terminal VDDO, and the drain of M8 is electrically connected to the first second node PD1.

[0368] The gate of M9 is electrically connected to the first node PU, the source of M9 is electrically connected to the first second node PD1, and the drain of M9 is electrically connected to the first low voltage terminal LVGL.

[0369] The gate of M10 is electrically connected to the input terminal I1, the source of M10 is electrically connected to the first second node PD1, and the drain of M10 is electrically connected to the first low voltage terminal LVGL.

[0370] The gate and source of M11 are both electrically connected to the second control voltage terminal VDDE, and the drain of M11 is electrically connected to the second pull-down control node PDCN2.

[0371] The gate of M12 is electrically connected to the first node PU, the source of M12 is electrically connected to the second pull-down control node PDCN2, and the drain of M12 is electrically connected to the first low voltage terminal LVGL.

[0372] The gate of M13 is electrically connected to the second pull-down control node PDCN2, the source of M13 is electrically connected to the second control voltage terminal VDDE, and the drain of M13 is electrically connected to the second node PD2.

[0373] The gate of M14 is electrically connected to the first node PU, the source of M14 is electrically connected to the second node PD2, and the drain of M14 is electrically connected to the first low voltage terminal LVGL.

[0374] The gate of M15 is electrically connected to the input terminal I1, the source of M15 is electrically connected to the second node PD2, and the drain of M15 is electrically connected to the first low voltage terminal LVGL.

[0375] The first end of the storage capacitor C is electrically connected to the first node PU, and the second end of the storage capacitor C is electrically connected to the drive output terminal G0.

[0376] The gate of M16 is electrically connected to the first node PU, the source of M16 is electrically connected to the clock signal terminal CLK, and the drain of M16 is electrically connected to the carry output terminal OC.

[0377] The gate of M17 is electrically connected to the first second node PD1, the source of M17 is electrically connected to the carry output terminal OC, and the drain of M17 is electrically connected to the first low voltage terminal LVGL.

[0378] The gate of M18 is electrically connected to the second node PD2, the source of M18 is electrically connected to the carry output terminal OC, and the drain of M18 is electrically connected to the first low voltage terminal LVGL.

[0379] The gate of M19 is electrically connected to the first node PU, the source of M19 is electrically connected to the clock signal terminal CLK, and the drain of M19 is electrically connected to the drive output terminal G0.

[0380] The gate of M20 is electrically connected to the first second node PD1, the source of M20 is electrically connected to the drive output terminal G0, and the drain of M20 is electrically connected to the second low voltage terminal VGL.

[0381] The gate of M21 is electrically connected to the second node PD2, the source of M21 is electrically connected to the drive output terminal G0, and the drain of M21 is electrically connected to the second low voltage terminal VGL.

[0382] exist Figure 14 In at least one embodiment of the virtual driving circuit shown, all transistors are n-type transistors, but this is not a limitation.

[0383] In at least one embodiment of the present invention, at least a portion of the virtual driving circuits in the multi-level virtual driving circuits are second-type virtual driving circuits. The second-type virtual driving circuits include an input terminal, a carry output terminal, a drive output terminal, an input circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit, and a drive output circuit.

[0384] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0385] The second reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0386] The first node control circuit is electrically connected to the first node, the second node, and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0387] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0388] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0389] The carry-out circuit is electrically connected to the first node, the second node, the carry-out terminal, the first clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry-out terminal and the first clock signal terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node.

[0390] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0391] In specific implementations, in at least one embodiment of the virtual drive circuit, a reset circuit may not be provided.

[0392] like Figure 15 As shown, at least one embodiment of the virtual driving circuit includes an input terminal I1, a carry output terminal OC, a drive output terminal G0, an input circuit 11, a second reset circuit 13, a first node control circuit 14, a second node control circuit 15, an energy storage circuit 16, a carry output circuit 17, and a drive output circuit 18.

[0393] The input circuit 11 is electrically connected to the input terminal I1 and the first node PU respectively, and is used to control the potential of the first node PU according to the input signal connected to the input terminal I1;

[0394] The second reset circuit 13 is electrically connected to the frame reset terminal TRST, the first node PU, and the first voltage terminal V1, respectively, and is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the frame reset signal provided by the frame reset terminal TRST.

[0395] The first node control circuit 14 is electrically connected to the first node PU, the first second node PD1, the second second node PD2 and the first voltage terminal V1 respectively. It is used to control the connection between the first node PU and the first voltage terminal V1 under the control of the potential of the first second node PD1, and to control the connection between the first node PU and the first voltage terminal V1 under the control of the potential of the second second node PD2.

[0396] The second node control circuit 15 is electrically connected to the first control voltage terminal VDDO, the second control voltage terminal VDDE, the first node PU, the first second node PD1, the second second node PD2 and the first voltage terminal V1, respectively. It is used to control the potential of the first second node PD1 under the control of the first control voltage provided by the first control voltage terminal VDDO and the potential of the first node PU, and to control the potential of the second second node PD2 under the control of the second control voltage provided by the second control voltage terminal VDDE and the potential of the first node PU.

[0397] The energy storage circuit 16 is electrically connected to the first node PU and is used to store electrical energy.

[0398] The carry output circuit 17 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the carry output terminal OC, the clock signal terminal CLK, and the first voltage terminal V1, respectively. It is used to control the connection between the carry output terminal OC and the clock signal terminal CLK under the control of the potential of the first node PU, control the connection between the carry output terminal OC and the first voltage terminal V1 under the control of the potential of the first second node PD1, and control the connection between the carry output terminal OC and the first voltage terminal V1 under the control of the potential of the second second node PD2.

[0399] The drive output circuit 18 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the drive output terminal G0, the clock signal terminal CLK, and the second voltage terminal V2, respectively. It is used to control the connection between the drive output terminal G0 and the clock signal terminal CLK under the control of the potential of the first node PU, control the connection between the drive output terminal G0 and the second voltage terminal V2 under the control of the potential of the first second node PD1, and control the connection between the drive output terminal G0 and the second voltage terminal V2 under the control of the potential of the second second node PD2.

[0400] like Figure 16 As shown, in Figure 15Based on at least one embodiment of the display driving circuit shown, the input circuit may include a first transistor M1; the second reset circuit 13 may include a third transistor M3; the first node control circuit may include a fourth transistor M4 and a fifth transistor M5; the second node control circuit may include a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15; the energy storage circuit includes a storage capacitor C; the carry output circuit includes a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18; and the drive output circuit includes a nineteenth transistor M19, a twentieth transistor M20, and a twenty-first transistor M21.

[0401] The gate and source of M1 are both electrically connected to the input terminal I1, and the drain of M1 is electrically connected to the first node PU.

[0402] The gate of M3 is electrically connected to the frame reset terminal TRST, the source of M3 is electrically connected to the first node PU, and the drain of M3 is electrically connected to the first low voltage terminal LVGL.

[0403] The gate of M4 is electrically connected to the first second node PD1, the source of M4 is electrically connected to the first node PU, and the drain of M4 is electrically connected to the first low voltage terminal LVGL.

[0404] The gate of M5 is electrically connected to the second node PD2, the source of M5 is electrically connected to the first node PU, and the drain of M5 is electrically connected to the first low voltage terminal LVGL.

[0405] The gate and source of M6 are both electrically connected to the first control voltage terminal VDDO, and the drain of M6 is electrically connected to the first pull-down control node PDCN1.

[0406] The gate of M7 is electrically connected to the first node PU, the source of M7 is electrically connected to the first pull-down control node PDCN1, and the drain of M7 is electrically connected to the first low voltage terminal LVGL.

[0407] The gate of M8 is electrically connected to the first pull-down control node PDCN1, the source of M8 is electrically connected to the first control voltage terminal VDDO, and the drain of M8 is electrically connected to the first second node PD1.

[0408] The gate of M9 is electrically connected to the first node PU, the source of M9 is electrically connected to the first second node PD1, and the drain of M9 is electrically connected to the first low voltage terminal LVGL.

[0409] The gate of M10 is electrically connected to the input terminal I1, the source of M10 is electrically connected to the first second node PD1, and the drain of M10 is electrically connected to the first low voltage terminal LVGL.

[0410] The gate and source of M11 are both electrically connected to the second control voltage terminal VDDE, and the drain of M11 is electrically connected to the second pull-down control node PDCN2.

[0411] The gate of M12 is electrically connected to the first node PU, the source of M12 is electrically connected to the second pull-down control node PDCN2, and the drain of M12 is electrically connected to the first low voltage terminal LVGL.

[0412] The gate of M13 is electrically connected to the second pull-down control node PDCN2, the source of M13 is electrically connected to the second control voltage terminal VDDE, and the drain of M13 is electrically connected to the second node PD2.

[0413] The gate of M14 is electrically connected to the first node PU, the source of M14 is electrically connected to the second node PD2, and the drain of M14 is electrically connected to the first low voltage terminal LVGL.

[0414] The gate of M15 is electrically connected to the input terminal I1, the source of M15 is electrically connected to the second node PD2, and the drain of M15 is electrically connected to the first low voltage terminal LVGL.

[0415] The first end of the storage capacitor C is electrically connected to the first node PU, and the second end of the storage capacitor C is electrically connected to the drive output terminal G0.

[0416] The gate of M16 is electrically connected to the first node PU, the source of M16 is electrically connected to the clock signal terminal CLK, and the drain of M16 is electrically connected to the carry output terminal OC.

[0417] The gate of M17 is electrically connected to the first second node PD1, the source of M17 is electrically connected to the carry output terminal OC, and the drain of M17 is electrically connected to the first low voltage terminal LVGL.

[0418] The gate of M18 is electrically connected to the second node PD2, the source of M18 is electrically connected to the carry output terminal OC, and the drain of M18 is electrically connected to the first low voltage terminal LVGL.

[0419] The gate of M19 is electrically connected to the first node PU, the source of M19 is electrically connected to the clock signal terminal CLK, and the drain of M19 is electrically connected to the drive output terminal G0.

[0420] The gate of M20 is electrically connected to the first second node PD1, the source of M20 is electrically connected to the drive output terminal G0, and the drain of M20 is electrically connected to the second low voltage terminal VGL.

[0421] The gate of M21 is electrically connected to the second node PD2, the source of M21 is electrically connected to the drive output terminal G0, and the drain of M21 is electrically connected to the second low voltage terminal VGL.

[0422] exist Figure 16 In at least one embodiment of the virtual driving circuit shown, all transistors are n-type transistors, but this is not a limitation.

[0423] Optionally, some of the virtual driving circuits in the multi-level virtual driving circuit are first-type virtual driving circuits, and the other part of the virtual driving circuits in the multi-level virtual driving circuit are second-type virtual driving circuits.

[0424] The first type of virtual driving circuit includes an input terminal, a carry output terminal, a drive output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit, and a drive output circuit.

[0425] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0426] The first reset circuit is electrically connected to the reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal input to the reset terminal; the reset terminal is electrically connected to the corresponding initial voltage line.

[0427] The second reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0428] The first node control circuit is electrically connected to the first node, the second node, and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0429] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0430] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0431] The carry-out circuit is electrically connected to the first node, the second node, the carry-out terminal, the first clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry-out terminal and the first clock signal terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node.

[0432] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal, and the second voltage terminal, respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0433] The second type of virtual driving circuit includes an input terminal, a carry output terminal, a drive output terminal, an input circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit, and a drive output circuit.

[0434] The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal;

[0435] The second reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal;

[0436] The first node control circuit is electrically connected to the first node, the second node, and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node;

[0437] The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node;

[0438] The energy storage circuit is electrically connected to the first node and is used to store electrical energy;

[0439] The carry-out circuit is electrically connected to the first node, the second node, the carry-out terminal, the first clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry-out terminal and the first clock signal terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node.

[0440] The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

[0441] In specific implementation, some of the virtual driving circuits in the multi-level virtual driving circuit can be first-type virtual driving circuits, and the other part of the virtual driving circuits in the multi-level virtual driving circuit can be second-type virtual driving circuits.

[0442] In at least one embodiment of the present invention, the array substrate may include a plurality of virtual driving circuits, and the structures of the plurality of virtual driving circuits may all be as follows: Figure 13 As shown, or, the structure of some of the multiple virtual drive circuits is as follows: Figure 13 As shown, the structure of another part of the multiple virtual drive circuits can be as follows: Figure 15 As shown.

[0443] The driving method described in this embodiment of the invention is applied to the array substrate described above. One frame time includes at least two subframes. Within the subframe, there are overlapping time periods and non-overlapping time periods among the effective time periods of the scan signals provided by at least two adjacent scan lines in the multiple scan lines that are opened sequentially.

[0444] The driving method includes:

[0445] Within the subframe, the driving module provides a scanning signal to the scan line to control multiple rows of the scan line to open sequentially, and controls the subpixel that is electrically connected to the opened scan line and has the same color as the subpixel electrically connected to the same data line.

[0446] The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0447] In at least one embodiment of the present invention, a frame time includes N subframes; adjacent N rows of scan lines in a multi-row scan line group are set as a scan line group; the driving method includes:

[0448] Within the nth subframe, the driving module provides a scanning signal to the nth row of scan lines in the scan line group to control the nth row of scan lines to open;

[0449] N is an integer greater than 1, and n is a positive integer less than or equal to N.

[0450] The display device described in this embodiment of the invention includes the array substrate described above. The display device may include a display panel, which further includes a counter substrate disposed opposite to the array substrate. When the display device is a liquid crystal display panel, a liquid crystal layer is disposed between the counter substrate and the array substrate. The counter substrate may include a black matrix and a color resist layer (e.g., red, green, and blue resists), or the color resist layer may be disposed on one side of the array substrate. The display panel may be a liquid crystal display panel, an organic light-emitting diode display panel (OLED), a micro-light-emitting diode display panel, or an electrophoretic display, etc., and is not limited thereto.

[0451] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that, It includes a driving module, multiple rows and columns of subpixels, multiple columns of data lines, and multiple rows of scan lines; one frame time includes at least two subframes; the subpixels are electrically connected to the scan lines and the data lines respectively, and are used to receive the data voltage provided by the data lines under the control of the scan signal provided by the scan lines; The driving module is used to provide scanning signals to the scanning lines to control multiple rows of the scanning lines to open sequentially within the subframe, and to control the subpixels that are electrically connected to the opened scanning lines and electrically connected to the same data line within the subframe to have the same color. Within the subframe, there are overlapping and non-overlapping time periods among the effective time periods of the scan signals provided by at least two adjacent scan lines in a series of sequentially opened scan lines; The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period. One frame time includes N subframes, where N is an integer greater than 1; the driving module includes a multi-level driving circuit and N initial voltage lines, the multi-level driving circuit includes a multi-level display driving circuit; the display driving circuit is used to provide scanning signals for the scan lines; The nth initial voltage line is electrically connected to the input terminal of the nth level display driving circuit included in the driving module, and is used to provide an input signal to the nth level display driving circuit; n is a positive integer less than or equal to N; The frame time comprises four subframes. In the first subframe, the first, fifth, ninth, and thirteenth scan lines are scanned sequentially until the scan lines of the first subframe corresponding to the display panel are completed. In the second subframe, the second, sixth, tenth, and fourteenth scan lines are scanned sequentially until the scan lines of the first subframe corresponding to the display panel are completed. In the third subframe, the third, seventh, eleventh, and fifteenth scan lines are scanned sequentially until the scan lines of the first subframe corresponding to the display panel are completed. In the fourth subframe, the fourth, eighth, twelfth, and sixteenth scan lines are scanned sequentially until the scan lines of the first subframe corresponding to the display panel are completed. There is a first overlapping time period between the effective time period of the first scan signal provided by the first scan line and the effective time period of the fifth scan signal provided by the fifth scan line, and a first non-overlapping time period adjacent to the first overlapping time period; there is a second overlapping time period between the effective time period of the ninth scan signal provided by the ninth scan line and the effective time period of the thirteenth scan signal provided by the thirteenth scan line, and a second non-overlapping time period adjacent to the second overlapping time period; The duration of both the first overlapping time period and the second overlapping time period is 1 hour, where 1 hour is the charging time for one row; the duration of both the first non-overlapping time period and the second non-overlapping time period is 1 hour; during the first overlapping time period included in the effective time period of the first row scan signal, the data line provides a first data voltage, and the first overlapping time period corresponding to the first row scan signal is adjacent to the invalid time period of the first row scan signal; during the first overlapping time period and the first non-overlapping time period corresponding to the fifth row scan signal, the data line provides the first data voltage; during the second overlapping time period included in the effective time period of the ninth row scan signal, the data line provides a second data voltage, and the second overlapping time period corresponding to the ninth row scan signal is adjacent to the invalid time period of the ninth row scan signal; during the second overlapping time period and the second non-overlapping time period corresponding to the thirteenth row scan signal, the data line provides the second data voltage; There is a third overlapping time period between the effective time period of the second scan signal provided by the second scan line and the effective time period of the sixth scan signal provided by the sixth scan line, and a third non-overlapping time period adjacent to the third overlapping time period; there is a fourth overlapping time period between the effective time period of the tenth scan signal provided by the tenth scan line and the effective time period of the fourteenth scan signal provided by the fourteenth scan line, and a fourth non-overlapping time period adjacent to the fourth overlapping time period; The duration of the third overlapping time period and the duration of the fourth overlapping time period are both 1 hour; the duration of the third non-overlapping time period and the duration of the fourth non-overlapping time period are both 1 hour. During the third overlapping time period included in the valid time period of the second row scan signal, the data line provides a third data voltage, and the third overlapping time period corresponding to the second row scan signal is adjacent to the invalid time period of the second row scan signal; during the third overlapping time period and the third non-overlapping time period corresponding to the sixth row scan signal, the data line provides the third data voltage; during the fourth overlapping time period included in the valid time period of the tenth row scan signal, the data line provides a fourth data voltage, and the fourth overlapping time period corresponding to the tenth row scan signal is adjacent to the invalid time period of the tenth row scan signal; during the fourth overlapping time period and the fourth non-overlapping time period corresponding to the fourteenth row scan signal, the data line provides the fourth data voltage; There is a fifth overlapping time period between the effective time period of the third scan signal provided by the third scan line and the effective time period of the seventh scan signal provided by the seventh scan line, and a fifth non-overlapping time period adjacent to the fifth overlapping time period; there is a sixth overlapping time period between the effective time period of the eleventh scan signal provided by the eleventh scan line and the effective time period of the fifteenth scan signal provided by the fifteenth scan line, and a sixth non-overlapping time period adjacent to the sixth overlapping time period; The duration of the fifth overlapping time period and the duration of the sixth overlapping time period are both 1 hour; the duration of the fifth non-overlapping time period and the duration of the sixth non-overlapping time period are both 1 hour. During the fifth overlapping time period included in the valid time period of the third row scan signal, the data line provides a fifth data voltage, and the fifth overlapping time period corresponding to the third row scan signal is adjacent to the invalid time period of the third row scan signal; during the fifth overlapping time period and the fifth non-overlapping time period corresponding to the seventh row scan signal, the data line provides the fifth data voltage; during the sixth overlapping time period included in the valid time period of the eleventh row scan signal, the data line provides a sixth data voltage, and the sixth overlapping time period corresponding to the eleventh row scan signal is adjacent to the invalid time period of the eleventh row scan signal; during the sixth overlapping time period and the sixth non-overlapping time period corresponding to the fifteenth row scan signal, the data line provides the sixth data voltage; There is a seventh overlapping time period between the effective time period of the fourth scan signal provided by the fourth scan line and the effective time period of the eighth scan signal provided by the eighth scan line, and a seventh non-overlapping time period adjacent to the seventh overlapping time period; there is an eighth overlapping time period between the effective time period of the twelfth scan signal provided by the twelfth scan line and the effective time period of the sixteenth scan signal provided by the sixteenth scan line, and an eighth non-overlapping time period adjacent to the eighth overlapping time period; The duration of the seventh overlapping time period and the duration of the eighth overlapping time period are both 1 hour; the duration of the seventh non-overlapping time period and the duration of the eighth non-overlapping time period are both 1 hour; During the seventh overlapping time period included in the valid time period of the fourth scan signal, the data line provides a seventh data voltage, and the seventh overlapping time period corresponding to the fourth scan signal is adjacent to the invalid time period of the fourth scan signal; during the seventh overlapping time period and the seventh non-overlapping time period corresponding to the eighth scan signal, the data line provides the seventh data voltage; during the eighth overlapping time period included in the valid time period of the twelfth scan signal, the data line provides an eighth data voltage, and the eighth overlapping time period corresponding to the twelfth scan signal is adjacent to the invalid time period of the twelfth scan signal; during the eighth overlapping time period and the eighth non-overlapping time period corresponding to the sixteenth scan signal, the data line provides the eighth data voltage; The multi-level driving circuit also includes a multi-level virtual driving circuit; The virtual driving circuit is used to provide a reset signal to the corresponding level display driving circuit in the multi-level display driving circuit; At least a portion of the N initial voltage lines are electrically connected to the reset terminal of the corresponding virtual drive circuit, for providing a reset signal to the corresponding virtual drive circuit; The reset terminal of the first-stage virtual drive circuit is electrically connected to the second initial voltage line; the reset terminal of the second-stage virtual drive circuit is electrically connected to the third initial voltage line; the reset terminal of the third-stage virtual drive circuit is electrically connected to the fourth initial voltage line; the reset terminal of the fifth-stage virtual drive circuit is electrically connected to the second initial voltage line; the reset terminal of the sixth-stage virtual drive circuit is electrically connected to the third initial voltage line; and the reset terminal of the seventh-stage virtual drive circuit is electrically connected to the fourth initial voltage line.

2. The array substrate as described in claim 1, characterized in that, The display driving circuit provides input signals to the adjacent N-level display driving circuits through its output terminal; The display driving circuit provides a reset signal to the adjacent 2N-level display driving circuits through its output terminal.

3. The array substrate as described in claim 1, characterized in that, The multi-level driving circuit includes an M-level display driving circuit and 2N-level virtual driving circuits; M is an integer greater than 1. The a-level virtual driving circuit is used to provide a reset signal for the M-2N+a-level display driving circuit; a is a positive integer less than or equal to 2N.

4. The array substrate as described in claim 1, characterized in that, One frame time includes four subframes; the driving module includes a multi-level driving circuit and four initial voltage lines; the multi-level driving circuit includes M levels of display driving circuit; M is an integer greater than 1; The first initial voltage line is electrically connected to the input terminal of the first-stage display driver circuit and is used to provide an input signal to the first-stage display driver circuit. The second initial voltage line is electrically connected to the input terminal of the second-stage display driver circuit and is used to provide input signals to the second-stage display driver circuit. The third initial voltage line is electrically connected to the input terminal of the third-level display driver circuit and is used to provide an input signal to the third-level display driver circuit. The fourth initial voltage line is electrically connected to the input terminal of the fourth-level display driver circuit, and is used to provide an input signal to the fourth-level display driver circuit.

5. The array substrate as described in claim 4, characterized in that, The m-th display driver circuit provides an input signal to the (m+4)-th display driver circuit through its output terminal; m is a positive integer, and m+4 is less than or equal to M. The b-th display driver circuit provides a reset signal to the b-8th display driver circuit through its output terminal; b is an integer greater than 8, and b is less than or equal to M.

6. The array substrate as described in claim 4, characterized in that, The drive module also includes an eight-level virtual drive circuit; The first-level virtual driving circuit provides a reset signal to the M-7 level display driving circuit through its output terminal; The second-level virtual drive circuit provides a reset signal to the M-6 level display drive circuit through its output terminal; The third-level virtual drive circuit provides a reset signal to the M-5 level display drive circuit through its output terminal; The fourth-level virtual drive circuit provides a reset signal to the M-4 level display drive circuit through its output terminal; The fifth-level virtual drive circuit provides a reset signal to the M-3 level display drive circuit through its output terminal; The sixth-level virtual drive circuit provides a reset signal to the M-2 level display drive circuit through its output terminal; The seventh-level virtual drive circuit provides a reset signal to the (M-1)th-level display drive circuit through its output terminal; The eighth-level virtual drive circuit provides a reset signal to the M-level display drive circuit through its output terminal.

7. The array substrate as described in claim 6, characterized in that, The second initial voltage line provides reset signals to the first-stage virtual drive circuit and the fifth-stage virtual drive circuit, respectively. The third initial voltage line provides reset signals to the second-stage virtual drive circuit and the sixth-stage virtual drive circuit, respectively. The fourth initial voltage line provides reset signals to the third-stage virtual drive circuit and the seventh-stage virtual drive circuit, respectively.

8. The array substrate as claimed in claim 7, characterized in that, The first initial voltage line provides reset signals to the fourth-level virtual drive circuit and the eighth-level virtual drive circuit, respectively.

9. The array substrate according to any one of claims 4 to 8, characterized in that, It also includes twelve clock signal lines; c is a positive integer; The 12c-11 stage driver circuit is electrically connected to the first clock signal line; the 12c-10 stage driver circuit is electrically connected to the second clock signal line; the 12c-9 stage driver circuit is electrically connected to the third clock signal line; the 12c-8 stage driver circuit is electrically connected to the fourth clock signal line; the 12c-7 stage driver circuit is electrically connected to the fifth clock signal line; the 12c-6 stage driver circuit is electrically connected to the sixth clock signal line; the 12c-5 stage driver circuit is electrically connected to the seventh clock signal line; the 12c-4 stage driver circuit is electrically connected to the eighth clock signal line; the 12c-3 stage driver circuit is electrically connected to the ninth clock signal line; the 12c-2 stage driver circuit is electrically connected to the tenth clock signal line; the 12c-1 stage driver circuit is electrically connected to the eleventh clock signal line; and the 12c stage driver circuit is electrically connected to the twelfth clock signal line.

10. The array substrate according to any one of claims 1 to 8, characterized in that, A portion of the subpixels located in the same row are electrically connected to a row of scan lines for receiving scan signals from the scan lines; Another portion of the subpixels located in the same row is electrically connected to the other row of scan lines for receiving scan signals from the other row of scan lines.

11. The array substrate according to any one of claims 1 to 8, characterized in that, The display driving circuit includes an input terminal, a carry output terminal, a drive output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit, and a drive output circuit. The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal; The first reset circuit is electrically connected to the reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal input to the reset terminal; the reset terminal is electrically connected to the output terminal of the adjacent lower 2N stage drive circuit. The second reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal; The first node control circuit is electrically connected to the first node, the second node, and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node; The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node; The energy storage circuit is electrically connected to the first node and is used to store electrical energy; The carry-out circuit is electrically connected to the first node, the second node, the carry-out terminal, the first clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry-out terminal and the first clock signal terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node. The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

12. The array substrate as described in claim 1, 3, 6, 7 or 8, characterized in that, At least some of the virtual driving circuits in the multi-level virtual driving circuits are first-type virtual driving circuits. The first-type virtual driving circuit includes an input terminal, a carry output terminal, a drive output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit, and a drive output circuit. The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal; The first reset circuit is electrically connected to the reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal input to the reset terminal; the reset terminal is electrically connected to the corresponding initial voltage line. The second reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal; The first node control circuit is electrically connected to the first node, the second node, and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node; The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node; The energy storage circuit is electrically connected to the first node and is used to store electrical energy; The carry-out circuit is electrically connected to the first node, the second node, the carry-out terminal, the first clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry-out terminal and the first clock signal terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node. The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

13. The array substrate as claimed in claim 12, characterized in that, All of the multi-level virtual driving circuits are of the first type.

14. The array substrate as described in claim 1, 3, 6, 7 or 8, characterized in that, Some of the virtual driving circuits in the multi-level virtual driving circuit are second-type virtual driving circuits. The second-type virtual driving circuit includes an input terminal, a carry output terminal, a drive output terminal, an input circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit, and a drive output circuit. The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal; The second reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal; The first node control circuit is electrically connected to the first node, the second node, and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node; The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node; The energy storage circuit is electrically connected to the first node and is used to store electrical energy; The carry-out circuit is electrically connected to the first node, the second node, the carry-out terminal, the first clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry-out terminal and the first clock signal terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node. The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

15. The array substrate according to claim 1, 3, 6, 7 or 8, characterized in that, The virtual driving circuits in the multi-level virtual driving circuits are of the first type, and the other part of the virtual driving circuits in the multi-level virtual driving circuits are of the second type. The first type of virtual driving circuit includes an input terminal, a carry output terminal, a drive output terminal, a reset terminal, an input circuit, a first reset circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit, and a drive output circuit. The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal; The first reset circuit is electrically connected to the reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the reset signal input to the reset terminal; the reset terminal is electrically connected to the corresponding initial voltage line. The second reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal; The first node control circuit is electrically connected to the first node, the second node, and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node; The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node; The energy storage circuit is electrically connected to the first node and is used to store electrical energy; The carry-out circuit is electrically connected to the first node, the second node, the carry-out terminal, the first clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry-out terminal and the first clock signal terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node. The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal, and the second voltage terminal, respectively, and is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node. The second type of virtual driving circuit includes an input terminal, a carry output terminal, a drive output terminal, an input circuit, a second reset circuit, a first node control circuit, a second node control circuit, an energy storage circuit, a carry output circuit, and a drive output circuit. The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node according to the input signal connected to the input terminal; The second reset circuit is electrically connected to the frame reset terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal; The first node control circuit is electrically connected to the first node, the second node, and the first voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the potential of the second node; The second node control circuit is electrically connected to the control voltage terminal, the first node, the second node, and the first voltage terminal, respectively, and is used to control the potential of the second node under the control of the control voltage provided by the control voltage terminal and the potential of the first node; The energy storage circuit is electrically connected to the first node and is used to store electrical energy; The carry-out circuit is electrically connected to the first node, the second node, the carry-out terminal, the first clock signal terminal, and the first voltage terminal, respectively, and is used to control the connection between the carry-out terminal and the first clock signal terminal under the control of the potential of the first node, and to control the connection between the carry-out terminal and the first voltage terminal under the control of the potential of the second node. The drive output circuit is electrically connected to the first node, the second node, the drive output terminal, the second clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the first node, and to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the second node.

16. A driving method applied to an array substrate as described in any one of claims 1 to 15, characterized in that, A frame time includes at least two subframes; within the subframe, there are overlapping and non-overlapping time periods among the effective time periods of the scan signals provided by at least two adjacent scan lines in a series of sequentially opened scan lines; The driving method includes: Within the subframe, the driving module provides a scanning signal to the scan line to control multiple rows of the scan line to open sequentially, and controls the subpixel that is electrically connected to the opened scan line and has the same color as the subpixel electrically connected to the same data line. The data voltage of the data line is the same for at least a portion of the overlapping time period as the data voltage received by the data line for at least a portion of the non-overlapping time period. The frame time includes four sub-frames; the driving method further includes: Within the first subframe, the first, fifth, ninth, and thirteenth scan lines are scanned sequentially until the scan lines of the first subframe corresponding to the display panel are completed. Within the second subframe, the second, sixth, tenth, and fourteenth scan lines are scanned sequentially until the scan lines of the first subframe corresponding to the display panel are completed. Within the third subframe, the third, seventh, eleventh, and fifteenth scan lines are scanned sequentially until the scan lines of the first subframe corresponding to the display panel are completed. Within the fourth subframe, the fourth, eighth, twelfth, and sixteenth scan lines are scanned sequentially until the scan lines of the first subframe corresponding to the display panel are completed. There is a first overlapping time period between the effective time period of the first scan signal provided by the first scan line and the effective time period of the fifth scan signal provided by the fifth scan line, and a first non-overlapping time period adjacent to the first overlapping time period; there is a second overlapping time period between the effective time period of the ninth scan signal provided by the ninth scan line and the effective time period of the thirteenth scan signal provided by the thirteenth scan line, and a second non-overlapping time period adjacent to the second overlapping time period; The duration of both the first overlapping time period and the second overlapping time period is 1 hour, where 1 hour is the charging time for one row; the duration of both the first non-overlapping time period and the second non-overlapping time period is 1 hour; during the first overlapping time period included in the effective time period of the first row scan signal, the data line provides a first data voltage, and the first overlapping time period corresponding to the first row scan signal is adjacent to the invalid time period of the first row scan signal; during the first overlapping time period and the first non-overlapping time period corresponding to the fifth row scan signal, the data line provides the first data voltage; during the second overlapping time period included in the effective time period of the ninth row scan signal, the data line provides a second data voltage, and the second overlapping time period corresponding to the ninth row scan signal is adjacent to the invalid time period of the ninth row scan signal; during the second overlapping time period and the second non-overlapping time period corresponding to the thirteenth row scan signal, the data line provides the second data voltage; There is a third overlapping time period between the effective time period of the second scan signal provided by the second scan line and the effective time period of the sixth scan signal provided by the sixth scan line, and a third non-overlapping time period adjacent to the third overlapping time period; there is a fourth overlapping time period between the effective time period of the tenth scan signal provided by the tenth scan line and the effective time period of the fourteenth scan signal provided by the fourteenth scan line, and a fourth non-overlapping time period adjacent to the fourth overlapping time period; The duration of the third overlapping time period and the duration of the fourth overlapping time period are both 1 hour; the duration of the third non-overlapping time period and the duration of the fourth non-overlapping time period are both 1 hour. During the third overlapping time period included in the valid time period of the second row scan signal, the data line provides a third data voltage, and the third overlapping time period corresponding to the second row scan signal is adjacent to the invalid time period of the second row scan signal; during the third overlapping time period and the third non-overlapping time period corresponding to the sixth row scan signal, the data line provides the third data voltage; during the fourth overlapping time period included in the valid time period of the tenth row scan signal, the data line provides a fourth data voltage, and the fourth overlapping time period corresponding to the tenth row scan signal is adjacent to the invalid time period of the tenth row scan signal; during the fourth overlapping time period and the fourth non-overlapping time period corresponding to the fourteenth row scan signal, the data line provides the fourth data voltage; There is a fifth overlapping time period between the effective time period of the third scan signal provided by the third scan line and the effective time period of the seventh scan signal provided by the seventh scan line, and a fifth non-overlapping time period adjacent to the fifth overlapping time period; there is a sixth overlapping time period between the effective time period of the eleventh scan signal provided by the eleventh scan line and the effective time period of the fifteenth scan signal provided by the fifteenth scan line, and a sixth non-overlapping time period adjacent to the sixth overlapping time period; The duration of the fifth overlapping time period and the duration of the sixth overlapping time period are both 1 hour; the duration of the fifth non-overlapping time period and the duration of the sixth non-overlapping time period are both 1 hour. During the fifth overlapping time period included in the valid time period of the third row scan signal, the data line provides a fifth data voltage, and the fifth overlapping time period corresponding to the third row scan signal is adjacent to the invalid time period of the third row scan signal; during the fifth overlapping time period and the fifth non-overlapping time period corresponding to the seventh row scan signal, the data line provides the fifth data voltage; during the sixth overlapping time period included in the valid time period of the eleventh row scan signal, the data line provides a sixth data voltage, and the sixth overlapping time period corresponding to the eleventh row scan signal is adjacent to the invalid time period of the eleventh row scan signal; during the sixth overlapping time period and the sixth non-overlapping time period corresponding to the fifteenth row scan signal, the data line provides the sixth data voltage; There is a seventh overlapping time period between the effective time period of the fourth scan signal provided by the fourth scan line and the effective time period of the eighth scan signal provided by the eighth scan line, and a seventh non-overlapping time period adjacent to the seventh overlapping time period; there is an eighth overlapping time period between the effective time period of the twelfth scan signal provided by the twelfth scan line and the effective time period of the sixteenth scan signal provided by the sixteenth scan line, and an eighth non-overlapping time period adjacent to the eighth overlapping time period; The duration of the seventh overlapping time period and the duration of the eighth overlapping time period are both 1 hour; the duration of the seventh non-overlapping time period and the duration of the eighth non-overlapping time period are both 1 hour. During the seventh overlapping time period included in the valid time period of the fourth scan signal, the data line provides a seventh data voltage, and the seventh overlapping time period corresponding to the fourth scan signal is adjacent to the invalid time period of the fourth scan signal; during the seventh overlapping time period and the seventh non-overlapping time period corresponding to the eighth scan signal, the data line provides the seventh data voltage; during the eighth overlapping time period included in the valid time period of the twelfth scan signal, the data line provides an eighth data voltage, and the eighth overlapping time period corresponding to the twelfth scan signal is adjacent to the invalid time period of the twelfth scan signal; during the eighth overlapping time period and the eighth non-overlapping time period corresponding to the sixteenth scan signal, the data line provides the eighth data voltage.

17. A display device, characterized in that, Includes the array substrate as described in any one of claims 1 to 15.

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