A shift register, a gate driving circuit and a driving method of the shift register

Abstract

A shift register, a gate driving circuit, and a driving method for a shift register. The shift register includes: a cascaded output sub-circuit, an output control sub-circuit, and a scan output sub-circuit; the cascaded output sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a cascaded output terminal under the control of signals of an input terminal, a first clock signal terminal, a second clock signal terminal, a first node, a second node, and a third node; the output control sub-circuit is configured to provide a signal of the first node to a fourth node and a signal of the second node to a fifth node under the control of signals of the first node, the third node, and first to third control signal terminals; the scan output sub-circuit is configured to output a signal of the first power supply terminal or the second power supply terminal to a scan signal output terminal under the control of signals of the fourth node and the fifth node.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, display technologies, and particularly to a shift register, a gate driving circuit, and a driving method for a shift register. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technologies, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistors (TFTs) have become the mainstream products in the current display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in the present disclosure. This overview is not intended to limit the scope of protection of the claims.

[0004] In a first aspect, an embodiment of the present disclosure provides a shift register, including: a cascaded output sub-circuit, an output control sub-circuit, and a scan output sub-circuit;

[0005] The cascaded output sub-circuit is electrically connected to an input terminal, a first clock signal terminal, a second clock signal line, a first power supply terminal, a second power supply terminal, a cascaded output terminal, a first node, a second node, and a third node respectively, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the cascaded output terminal under the control of signals of the input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the second node, and the third node;

[0006] The output control sub-circuit is electrically connected to a first control signal terminal to a third control signal terminal, the first node, the second node, the third node, a fourth node, and a fifth node respectively, and is configured to provide a signal of the first node to the fourth node and a signal of the second node to the fifth node under the control of signals of the first node, the third node, and the first control signal terminal to the third control signal terminal;

[0007] The scan output sub-circuit is electrically connected to the fourth node, the fifth node, a scan signal output terminal, the first power supply terminal, and the second power supply terminal respectively, and is configured to output a signal of the first power supply terminal or the second power supply terminal to the scan signal output terminal under the control of signals of the fourth node and the fifth node.

[0008] In some possible implementation manners, the output control sub - circuit includes: a first control sub - circuit, a second control sub - circuit, and a third control sub - circuit;

[0009] The first control sub - circuit is electrically connected to the first node, the third node, the sixth node, and the first control signal terminal to the third control signal terminal respectively, and is configured to provide the signal of the second control signal terminal or the third control signal terminal to the sixth node under the control of the signals of the first node, the third node, and the first control signal terminal;

[0010] The second control sub - circuit is electrically connected to the first node, the fourth node, and the sixth node respectively, and is configured to provide the signal of the first node to the fourth node under the control of the signal of the sixth node;

[0011] The third control sub - circuit is electrically connected to the second node, the fifth node, and the sixth node respectively, and is configured to provide the signal of the second node to the fifth node under the control of the signal of the sixth node.

[0012] In some possible implementation manners, the first control sub - circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor;

[0013] The control electrode of the first transistor is electrically connected to the first control signal terminal, the first pole of the first transistor is electrically connected to the second pole of the second transistor, and the second pole of the first transistor is electrically connected to the third control signal terminal;

[0014] The control electrode of the second transistor is electrically connected to the third node, and the first pole of the second transistor is electrically connected to the sixth node;

[0015] The control electrode of the third transistor is electrically connected to the first control signal terminal, the first pole of the third transistor is electrically connected to the second control signal terminal, and the second pole of the third transistor is electrically connected to the first pole of the fourth transistor;

[0016] The control electrode of the fourth transistor is electrically connected to the first node, and the second pole of the fourth transistor is electrically connected to the sixth node.

[0017] In some possible implementation manners, the second control sub - circuit includes: a fifth transistor;

[0018] The control electrode of the fifth transistor is electrically connected to the sixth node, the first pole of the fifth transistor is electrically connected to the first node, and the second pole of the fifth transistor is electrically connected to the fourth node.

[0019] In some possible implementation manners, the third control sub - circuit includes: a sixth transistor;

[0020] The control electrode of the sixth transistor is electrically connected to the sixth node, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the fifth node.

[0021] In some possible implementation manners, the output control sub-circuit further includes: a storage sub-circuit;

[0022] The storage sub-circuit, which is electrically connected to the fourth node and the sixth node respectively, is configured to store the voltage difference between the signals of the sixth node and the fourth node.

[0023] In some possible implementation manners, the storage sub-circuit includes: a first capacitor, and the first capacitor includes a first electrode plate and a second electrode plate;

[0024] The first electrode plate of the first capacitor is electrically connected to the sixth node, and the second electrode plate of the first capacitor is electrically connected to the fourth node.

[0025] In some possible implementation manners, the scan output sub-circuit includes: a seventh transistor and an eighth transistor;

[0026] The control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode of the seventh transistor is electrically connected to the first power supply terminal, and the second electrode of the seventh transistor is electrically connected to the scan signal output terminal;

[0027] The control electrode of the eighth transistor is electrically connected to the fifth node, the first electrode of the eighth transistor is electrically connected to the scan signal output terminal, and the second electrode of the eighth transistor is electrically connected to the second power supply terminal.

[0028] In some possible implementation manners, the scan output sub-circuit further includes: a second capacitor, and the second capacitor includes a first electrode plate and a second electrode plate;

[0029] The first electrode plate of the second capacitor is electrically connected to the fourth node, and the second electrode plate of the second capacitor is electrically connected to the first power supply terminal.

[0030] In some possible implementation manners, the cascade output sub-circuit includes: the ninth transistor to the twenty-fifth transistor, and the third capacitor to the sixth capacitor;

[0031] The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth transistor is electrically connected to the cascade output terminal;

[0032] The control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the cascade output terminal;

[0033] The control electrode of the eleventh transistor is electrically connected to the second power supply terminal, the first electrode of the eleventh transistor is electrically connected to the seventh node, and the second electrode of the eleventh transistor is electrically connected to the ninth node;

[0034] The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the second node, and the second electrode of the twelfth transistor is electrically connected to the third node;

[0035] The control electrode of the thirteenth transistor is electrically connected to the third power supply terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the second node;

[0036] The control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the input terminal, and the second electrode of the fourteenth transistor is electrically connected to the eighth node;

[0037] The control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, the first electrode of the fifteenth transistor is electrically connected to the eighth node, and the second electrode of the fifteenth transistor is electrically connected to the twelfth node;

[0038] The control electrode of the sixteenth transistor is electrically connected to the twelfth node, the first electrode of the sixteenth transistor is electrically connected to the third node, and the second electrode of the sixteenth transistor is electrically connected to the twelfth node;

[0039] The control electrode of the seventeenth transistor is electrically connected to the first clock signal terminal, the first electrode of the seventeenth transistor is electrically connected to the input terminal, and the second electrode of the seventeenth transistor is electrically connected to the second node;

[0040] The control electrode of the eighteenth transistor is electrically connected to the second node, the first electrode of the eighteenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the eighteenth transistor is electrically connected to the seventh node;

[0041] The control electrode of the nineteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the nineteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the nineteenth transistor is electrically connected to the seventh node;

[0042] The control electrode of the twentieth transistor is electrically connected to the second node, the first electrode of the twentieth transistor is electrically connected to the second clock signal terminal, and the second electrode of the twentieth transistor is electrically connected to the eleventh node;

[0043] The control electrode of the twenty-first transistor is electrically connected to the seventh node, the first electrode of the twenty-first transistor is electrically connected to the first power supply terminal, and the second electrode of the twenty-first transistor is electrically connected to the eleventh node;

[0044] The control electrode of the twenty-second transistor is electrically connected to the ninth node, the first electrode of the twenty-second transistor is electrically connected to the second clock signal terminal, and the second electrode of the twenty-second transistor is electrically connected to the tenth node;

[0045] The control electrode of the twenty-third transistor is electrically connected to the second clock signal terminal, the first electrode of the twenty-third transistor is electrically connected to the tenth node, and the second electrode of the twenty-third transistor is electrically connected to the first node;

[0046] The control electrode of the twenty-fourth transistor is electrically connected to the second node, the first electrode of the twenty-fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the twenty-fourth transistor is electrically connected to the first node;

[0047] The control electrode of the twenty-fifth transistor is electrically connected to the twelfth node, the first electrode of the twenty-fifth transistor is electrically connected to the twelfth node, and the second electrode of the twenty-fifth transistor is electrically connected to the fifth node;

[0048] The third capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the third capacitor is electrically connected to the third node, and the second electrode plate of the third capacitor is electrically connected to the eleventh node;

[0049] The fourth capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the fourth capacitor is electrically connected to the second power supply terminal, and the second electrode plate of the fourth capacitor is electrically connected to the cascaded output terminal;

[0050] The fifth capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the fifth capacitor is electrically connected to the ninth node, and the second electrode plate of the fifth capacitor is electrically connected to the tenth node;

[0051] The sixth capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the sixth capacitor is electrically connected to the first node, and the second electrode plate of the sixth capacitor is electrically connected to the first power supply terminal.

[0052] In some possible implementation manners, the cascaded output sub-circuit includes: the ninth transistor to the twenty-fifth transistor, the third capacitor to the sixth capacitor; the output control sub-circuit includes: the first transistor to the sixth transistor and the first capacitor; the scan output sub-circuit includes: the seventh transistor, the eighth transistor and the second capacitor;

[0053] The control electrode of the first transistor is electrically connected to the first control signal terminal, the first electrode of the first transistor is electrically connected to the second electrode of the second transistor, and the second electrode of the first transistor is electrically connected to the third control signal terminal;

[0054] The control electrode of the second transistor is electrically connected to the third node, and the first electrode of the second transistor is electrically connected to the sixth node;

[0055] The control electrode of the third transistor is electrically connected to the first control signal terminal, the first electrode of the third transistor is electrically connected to the second control signal terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor;

[0056] The control electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the sixth node;

[0057] The control electrode of the fifth transistor is electrically connected to the sixth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the fourth node;

[0058] The control electrode of the sixth transistor is electrically connected to the sixth node, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the fifth node;

[0059] The control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode of the seventh transistor is electrically connected to the first power supply terminal, and the second electrode of the seventh transistor is electrically connected to the scan signal output terminal;

[0060] The control electrode of the eighth transistor is electrically connected to the fifth node, the first electrode of the eighth transistor is electrically connected to the scan signal output terminal, and the second electrode of the eighth transistor is electrically connected to the second power supply terminal;

[0061] The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth transistor is electrically connected to the cascade output terminal;

[0062] The control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the cascade output terminal;

[0063] The control electrode of the eleventh transistor is electrically connected to the second power supply terminal, the first electrode of the eleventh transistor is electrically connected to the seventh node, and the second electrode of the eleventh transistor is electrically connected to the ninth node;

[0064] The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the second node, and the second electrode of the twelfth transistor is electrically connected to the third node;

[0065] The control electrode of the thirteenth transistor is electrically connected to the third power supply terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the second node;

[0066] The control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the input terminal, and the second electrode of the fourteenth transistor is electrically connected to the eighth node;

[0067] The control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, the first electrode of the fifteenth transistor is electrically connected to the eighth node, and the second electrode of the fifteenth transistor is electrically connected to the twelfth node;

[0068] The control electrode of the sixteenth transistor is electrically connected to the twelfth node, the first electrode of the sixteenth transistor is electrically connected to the third node, and the second electrode of the sixteenth transistor is electrically connected to the twelfth node;

[0069] The control electrode of the seventeenth transistor is electrically connected to the first clock signal terminal, the first electrode of the seventeenth transistor is electrically connected to the input terminal, and the second electrode of the seventeenth transistor is electrically connected to the second node;

[0070] The control electrode of the eighteenth transistor is electrically connected to the second node, the first electrode of the eighteenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the eighteenth transistor is electrically connected to the seventh node;

[0071] The control electrode of the nineteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the nineteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the nineteenth transistor is electrically connected to the seventh node;

[0072] The control electrode of the twentieth transistor is electrically connected to the second node, the first electrode of the twentieth transistor is electrically connected to the second clock signal terminal, and the second electrode of the twentieth transistor is electrically connected to the eleventh node;

[0073] The control electrode of the twenty-first transistor is electrically connected to the seventh node, the first electrode of the twenty-first transistor is electrically connected to the first power supply terminal, and the second electrode of the twenty-first transistor is electrically connected to the eleventh node;

[0074] The control electrode of the twenty-second transistor is electrically connected to the ninth node, the first electrode of the twenty-second transistor is electrically connected to the second clock signal terminal, and the second electrode of the twenty-second transistor is electrically connected to the tenth node;

[0075] The control electrode of the twenty-third transistor is electrically connected to the second clock signal terminal, the first electrode of the twenty-third transistor is electrically connected to the tenth node, and the second electrode of the twenty-third transistor is electrically connected to the first node;

[0076] The control electrode of the twenty-fourth transistor is electrically connected to the second node, the first electrode of the twenty-fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the twenty-fourth transistor is electrically connected to the first node;

[0077] The control electrode of the twenty-fifth transistor is electrically connected to the twelfth node, the first electrode of the twenty-fifth transistor is electrically connected to the twelfth node, and the second electrode of the twenty-fifth transistor is electrically connected to the fifth node;

[0078] The first capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the first capacitor is electrically connected to the sixth node, and the second electrode plate of the first capacitor is electrically connected to the fourth node;

[0079] The second capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the second capacitor is electrically connected to the fourth node, and the second electrode plate of the second capacitor is electrically connected to the first power supply terminal;

[0080] The third capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the third capacitor is electrically connected to the third node, and the second electrode plate of the third capacitor is electrically connected to the eleventh node;

[0081] The fourth capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the fourth capacitor is electrically connected to the second power supply terminal, and the second electrode plate of the fourth capacitor is electrically connected to the cascaded output terminal;

[0082] The fifth capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the fifth capacitor is electrically connected to the ninth node, and the second electrode plate of the fifth capacitor is electrically connected to the tenth node;

[0083] The sixth capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the sixth capacitor is electrically connected to the first node, and the second electrode plate of the sixth capacitor is electrically connected to the first power supply terminal.

[0084] In some possible implementation manners, the shift register is disposed on a display substrate. The display substrate includes: a plurality of scan signal lines. The working process of the display substrate includes: a display stage and a blank stage located between the display stages; the display substrate includes: a plurality of display regions. The refresh frequencies of different display regions include a first refresh frequency and a second refresh frequency, and the first refresh frequency is greater than the second refresh frequency;

[0085] When the signal of the first control signal terminal is a low-level signal in a state where the working process of the display substrate is in the blank stage, the signals of the second control signal terminal and the third control signal terminal are low-level signals;

[0086] When the signal of the first control signal terminal is a low-level signal in a state where the working process of the display substrate is in the display stage and the shift register is connected to the scan signal line of the display region with the first refresh frequency, the signals of the second control signal terminal and the third control signal terminal are low-level signals;

[0087] When the signal of the first control signal terminal is a low-level signal in a state where the working process of the display substrate is in the display stage, the shift register is connected to the scan signal line of the display region with the second refresh frequency, and the cascaded output terminal of the shift register outputs a low-level signal, the signal of the second control signal terminal is a high-level signal, and the signal of the third control signal terminal is a low-level signal;

[0088] When the display substrate is in the display stage, the shift register is connected to the scan signal lines of the display area at the second refresh frequency, and the cascaded output terminal of the shift register outputs a high-level signal, if the signal at the first control signal terminal is a low-level signal, the signal at the second control signal terminal is a high-level signal, and the signal at the third control signal terminal is a low-level signal;

[0089] When the display substrate is in the display stage, the shift register is connected to the scan signal lines of the display area at the second refresh frequency, and the cascaded output terminal of the shift register outputs a low-level signal, if the signal at the first control signal terminal is a low-level signal, the signal at the second control signal terminal is a high-level signal, and the signal at the third control signal terminal is a low-level signal;

[0090] The duration for which the signal at the first control signal terminal is at a low level is less than the duration for which the signal at any one of the second control signal terminal and the third control signal terminal is at a low level.

[0091] In a second aspect, an embodiment of the present disclosure provides a gate driving circuit, including: a plurality of cascaded shift registers as described in any one of the first aspect;

[0092] The cascaded output terminal of the i-th stage shift register is electrically connected to the input terminal of the (i + 1)-th stage shift register, where 1 ≤ i ≤ M - 1 and M is the total number of stages of the shift register.

[0093] In a third aspect, an embodiment of the present disclosure provides a method for driving a shift register, configured to drive the shift register as described in any one of the first aspect, the method including:

[0094] The cascaded output sub-circuit provides the signal of the first power supply terminal or the second power supply terminal to the cascaded output terminal under the control of the signals at the input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the second node, and the third node;

[0095] The output control sub-circuit provides the signal of the first node to the fourth node and the signal of the second node to the fifth node under the control of the signals at the first node, the third node, and the first control signal terminal to the third control signal terminal;

[0096] The scan output sub-circuit outputs the signal of the first power supply terminal or the second power supply terminal to the scan signal output terminal under the control of the signals at the fourth node and the fifth node.

[0097] Other aspects can be understood after reading and understanding the drawings and the detailed description. Description of the Drawings

[0098] The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure.

[0099] Figure 1A Schematic structural diagram of a shift register provided for an exemplary embodiment of the present disclosure;

[0100] Figure 1B Schematic structural diagram of a shift register provided for an exemplary embodiment of the present disclosure;

[0101] Figure 2 Equivalent circuit diagram of an output control sub - circuit provided for an exemplary embodiment;

[0102] Figure 3 Equivalent circuit diagram of a first control sub - circuit provided for an exemplary embodiment;

[0103] Figure 4 Equivalent circuit diagram of a second control sub - circuit provided for an exemplary embodiment;

[0104] Figure 5 Equivalent circuit diagram of a third control sub - circuit provided for an exemplary embodiment;

[0105] Figure 6 Equivalent circuit diagram of an output control sub - circuit provided for an exemplary embodiment;

[0106] Figure 7 Equivalent circuit diagram of a storage sub - circuit provided for an exemplary embodiment;

[0107] Figure 8 Equivalent circuit diagram of a scan output sub - circuit provided for an exemplary embodiment;

[0108] Figure 9 Equivalent circuit diagram of a scan output sub - circuit provided for an exemplary embodiment;

[0109] Figure 10 Equivalent circuit diagram of a cascade output sub - circuit provided for an exemplary embodiment;

[0110] Figure 11 Equivalent circuit diagram of a shift register provided for an exemplary embodiment;

[0111] Figure 12A Working timing diagram of a shift register provided for an exemplary embodiment;

[0112] Figure 12B Working timing diagram of a shift register provided for an exemplary embodiment;

[0113] Figure 13 Output waveform diagram of a shift register provided for an exemplary embodiment;

[0114] Figure 14 Operating timing diagram of a cascaded output sub - circuit provided for an exemplary embodiment;

[0115] Figure 15A Equivalent circuit schematic diagram of a pixel circuit;

[0116] Figure 15B For Figure 15A Operating timing diagram of the pixel circuit provided;

[0117] Figure 16A Equivalent circuit schematic diagram of another pixel circuit;

[0118] Figure 16B For Figure 16A Operating timing diagram of the pixel circuit provided. Detailed implementation manners

[0119] To make the objectives, technical solutions and advantages of the present disclosure clearer and more understandable, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation manners can be implemented in multiple different forms. It is easy for those of ordinary skill in the art to understand the fact that the manners and contents can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined arbitrarily with each other. To keep the following description of the embodiments of the present disclosure clear and concise, the detailed descriptions of some known functions and known components are omitted. The accompanying drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0120] The drawing ratios in the present disclosure can be used as a reference in actual processes, but are not limited thereto. For example: the width - length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub - pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in the present disclosure are only schematic diagrams, and one manner of the present disclosure is not limited to the shapes or values shown in the drawings.

[0121] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of components, rather than to limit in terms of quantity.

[0122] In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of the components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of the components is appropriately changed according to the directions describing the components. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the circumstances.

[0123] In this specification, unless otherwise clearly defined and limited, the terms "mounted", "connected", and "coupled" shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0124] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0125] In this specification, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes switch with each other. Therefore, in this specification, the "source electrode" and "drain electrode" can be switched with each other.

[0126] In this specification, "electrically connected" includes the case where components are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0127] In this specification, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°. Therefore, it also includes the state where the angle is more than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°. Therefore, it also includes the state where the angle is more than 85° and less than 95°.

[0128] In this specification, "film" and "layer" can be interchanged with each other. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0129] In this specification, the "same-layer setting" adopted means a structure formed by patterning two (or more than two) structures through the same patterning process, and their materials can be the same or different. For example, the materials of the precursors for forming multiple structures with the same-layer setting are the same, and the finally formed materials can be the same or different.

[0130] Triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not strictly defined and can be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There can be some small deformations caused by tolerances, and there can be chamfers, arc edges, and deformations, etc.

[0131] "About" in this disclosure means not strictly defining the boundary and allowing values within the process and measurement error ranges.

[0132] OLED display technology has advantages such as high contrast, fast response, and low power consumption. In order to reduce power consumption, a display technology of low temperature polycrystalline oxide (LTPO for short) is achieved by combining low temperature poly-silicon (abbreviated as LTPS) and indium gallium zinc oxide (abbreviated as IGZO). LTPO can achieve low frame rate display and reduce the driving power consumption by reducing the repeated refreshing of static pictures. However, when updating the picture of an OLED display, it is necessary to initialize and write the voltages of all pixels within one frame. And in some special pictures, such as always-on display (AOD for short), static pictures, or pictures with less updates, etc., the voltages of most pixels on the entire screen do not need to be updated. At this time, the repeated writing of these pixels makes the power consumption of the display relatively large.

[0133] Figure 1A It is a schematic structural diagram of a shift register provided for an exemplary embodiment of this disclosure. Figure 1B It is a schematic structural diagram of a shift register provided for an exemplary embodiment of this disclosure. AsFigure 1A and Figure 1B As shown in Figure 1B , the shift register provided by the embodiments of the present disclosure may include: a cascaded output sub-circuit GOA, an output control sub-circuit HRD, and a scan output sub-circuit NGOA.

[0134] The cascaded output sub-circuit is respectively electrically connected to an input terminal SIN, a first clock signal terminal CK1, a second clock signal line CK2, a first power supply terminal V1, a second power supply terminal V2, a cascaded output terminal SOUT, a first node N1, a second node N2, and a third node N3, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the cascaded output terminal under the control of signals of the input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the second node, and the third node.

[0135] The output control sub-circuit is respectively electrically connected to a first control signal terminal MS1 to a third control signal terminal MS3, the first node N1, the second node N2, the third node N3, a fourth node N4, and a fifth node N5, and is configured to provide a signal of the first node to the fourth node and a signal of the second node to the fifth node under the control of signals of the first node, the third node, and the first control signal terminal to the third control signal terminal.

[0136] The scan output sub-circuit is respectively electrically connected to the fourth node N4, the fifth node N5, a scan signal output terminal OUT, the first power supply terminal V1, and the second power supply terminal V2, and is configured to output a signal of the first power supply terminal or the second power supply terminal to the scan signal output terminal under the control of signals of the fourth node and the fifth node.

[0137] The cascaded output sub-circuit GOA outputs a signal of the cascaded output terminal SOUT under the control of the input terminal SIN, the first clock signal terminal CK1, and the second clock signal line CK2, where the signal of the cascaded output terminal SOUT is the first power supply terminal V1 or the second power supply terminal V2. The output control sub-circuit HRD may select whether to transfer a signal of the first power supply terminal V1 or the second power supply terminal V2 under the control of the first control signal terminal MS1 to the third control signal terminal MS3. If it is selected to transfer the signal of the first power supply terminal V1 under the control of the first control signal terminal MS1 to the third control signal terminal MS3, the signal of the first power supply terminal V1 is input to the scan output sub-circuit NGOA, and the signal of the scan signal output terminal OUT output by the scan output sub-circuit NGOA is the first power supply terminal V1. If it is selected to transfer the signal of the second power supply terminal V2 under the control of the first control signal terminal MS1 to the third control signal terminal MS3, the cascaded output terminal SOUT signal of the second power supply terminal V2 is input to the scan output sub-circuit NGOA, and the signal of the scan signal output terminal OUT output by the scan output sub-circuit NGOA is the second power supply terminal V2.

[0138] In an exemplary embodiment, the first power supply terminal V1 continuously provides a high-level signal, and the second power supply terminal V2 continuously provides a low-level signal.

[0139] In an exemplary embodiment, the first clock signal terminal CK1 and the second clock signal line CK2 can be periodic pulse signals.

[0140] The shift register provided by the embodiment of the present disclosure includes: a cascaded output sub-circuit, an output control sub-circuit, and a scan output sub-circuit. The shift register is electrically connected to the input terminal SIN, the first clock signal terminal CK1, the second clock signal line CK2, the first power supply terminal V1, the second power supply terminal V2, the scan signal output terminal OUT, the first control signal terminal MS1 to the third control signal terminal MS3. The cascaded output sub-circuit provides the signal of the first power supply terminal or the second power supply terminal to the cascaded output terminal under the control of the signals of the input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the second node, and the third node. The output control sub-circuit provides the signal of the first node to the fourth node and the signal of the second node to the fifth node under the control of the signals of the first node, the third node, and the first control signal terminal to the third control signal terminal. The scan output sub-circuit outputs the signal of the first power supply terminal or the second power supply terminal to the scan signal output terminal under the control of the signals of the fourth node and the fifth node. By setting the output control sub-circuit in the embodiment of the present disclosure, it is possible to control whether the scan signal output terminal of the scan output sub-circuit outputs, thereby reducing power consumption.

[0141] Figure 2 It is an equivalent circuit diagram of the output control sub-circuit provided for an exemplary embodiment. As Figure 2 shown, in an exemplary embodiment, the output control sub-circuit may include: a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit.

[0142] In an exemplary embodiment, as Figure 2 shown, the first control sub-circuit is electrically connected to the first node N1, the third node N3, the sixth node N6, and the first control signal terminal MS1 to the third control signal terminal MS3 respectively, and is configured to provide the signal of the second control signal terminal MS2 or the third control signal terminal MS3 to the sixth node under the control of the signals of the first node, the third node, and the first control signal terminal. The second control sub-circuit is electrically connected to the first node N1, the fourth node N4, and the sixth node N6 respectively, and is configured to provide the signal of the first node to the fourth node under the control of the signal of the sixth node. The third control sub-circuit is electrically connected to the second node N2, the fifth node N5, and the sixth node N6 respectively, and is configured to provide the signal of the second node to the fifth node under the control of the signal of the sixth node.

[0143] Figure 2An exemplary structure of the output control sub-circuit is shown. It is easy for those skilled in the art to understand that the implementation manner of the output control sub-circuit is not limited to this.

[0144] Figure 3 The equivalent circuit diagram of the first control sub-circuit provided for an exemplary embodiment. As Figure 3 shown, in an exemplary embodiment, the first control sub-circuit may include: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0145] In an exemplary embodiment, as Figure 3 shown, the control electrode of the first transistor T1 is electrically connected to the first control signal terminal MS1, the first pole of the first transistor T1 is electrically connected to the second pole of the second transistor T2, and the second pole of the first transistor T1 is electrically connected to the third control signal terminal MS3. The control electrode of the second transistor T2 is electrically connected to the third node N3, and the first pole of the second transistor T2 is electrically connected to the sixth node N6. The control electrode of the third transistor T3 is electrically connected to the first control signal terminal MS1, the first pole of the third transistor T3 is electrically connected to the second control signal terminal MS2, and the second pole of the third transistor T3 is electrically connected to the first pole of the fourth transistor T4. The control electrode of the fourth transistor is electrically connected to the first node N1, and the second pole of the fourth transistor is electrically connected to the sixth node N6.

[0146] Figure 3 An exemplary structure of the first control sub-circuit is shown. It is easy for those skilled in the art to understand that the implementation manner of the first control sub-circuit is not limited to this.

[0147] Figure 4 The equivalent circuit diagram of the second control sub-circuit provided for an exemplary embodiment. As Figure 4 shown, in an exemplary embodiment, the second control sub-circuit may include: a fifth transistor T5.

[0148] In an exemplary embodiment, as Figure 4 shown, the control electrode of the fifth transistor T5 is electrically connected to the sixth node N6, the first pole of the fifth transistor T5 is electrically connected to the first node N1, and the second pole of the fifth transistor T5 is electrically connected to the fourth node N4.

[0149] Figure 4 An exemplary structure of the second control sub-circuit is shown. It is easy for those skilled in the art to understand that the implementation manner of the second control sub-circuit is not limited to this.

[0150] Figure 5 The equivalent circuit diagram of the third control sub-circuit provided for an exemplary embodiment. As Figure 5 shown, in an exemplary embodiment, the third control sub-circuit includes: a sixth transistor T6.

[0151] In an exemplary embodiment, as Figure 5 shown, the control electrode of the sixth transistor T6 is electrically connected to the sixth node N6, the first electrode of the sixth transistor T6 is electrically connected to the second node N2, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5.

[0152] Figure 5 An exemplary structure of the third control sub-circuit is shown in. It is easy for those skilled in the art to understand that the implementation manner of the third control sub-circuit is not limited thereto.

[0153] Figure 6 The equivalent circuit diagram of the output control sub-circuit provided for an exemplary embodiment is shown in. As Figure 6 shown, in an exemplary embodiment, the output control sub-circuit may further include: a storage sub-circuit.

[0154] In an exemplary embodiment, as Figure 6 shown, the storage sub-circuit, which is electrically connected to the fourth node N4 and the sixth node N6 respectively, is configured to store the voltage difference between the signals of the sixth node and the fourth node.

[0155] Figure 6 An exemplary structure of the output control sub-circuit is shown in. It is easy for those skilled in the art to understand that the implementation manner of the output control sub-circuit is not limited thereto.

[0156] Figure 7 The equivalent circuit diagram of the storage sub-circuit provided for an exemplary embodiment is shown in. As Figure 7 shown, in an exemplary embodiment, the storage sub-circuit may include: a first capacitor C1, and the first capacitor includes a first electrode plate C11 and a second electrode plate C12.

[0157] In an exemplary embodiment, as Figure 7 shown, the first electrode plate C11 of the first capacitor C1 is electrically connected to the sixth node N6, and the second electrode plate C12 of the first capacitor C1 is electrically connected to the fourth node N4.

[0158] Figure 8 The equivalent circuit diagram of the scan output sub-circuit provided for an exemplary embodiment is shown in. As Figure 8 shown, in an exemplary embodiment, the scan output sub-circuit may include: a seventh transistor T7 and an eighth transistor T8.

[0159] In an exemplary embodiment, as Figure 8As shown, the control electrode of the seventh transistor T7 is electrically connected to the fourth node N4, the first electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1, and the second electrode of the seventh transistor T7 is electrically connected to the scan signal output terminal OUT. The control electrode of the eighth transistor T8 is electrically connected to the fifth node N5, the first electrode of the eighth transistor T8 is electrically connected to the scan signal output terminal OUT, and the second electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2.

[0160] Figure 8 An exemplary structure of the scan output sub-circuit is shown. It is easy for those skilled in the art to understand that the implementation manner of the scan output sub-circuit is not limited to this.

[0161] Figure 9 It is an equivalent circuit diagram of the scan output sub-circuit provided for an exemplary embodiment. As Figure 9 shown, in an exemplary embodiment, the scan output sub-circuit may further include: a second capacitor C2, and the second capacitor includes a first electrode plate C21 and a second electrode plate C22.

[0162] In an exemplary embodiment, as Figure 9 shown, the first electrode plate C21 of the second capacitor C2 is electrically connected to the fourth node N4, and the second electrode plate C22 of the second capacitor C2 is electrically connected to the first power supply terminal V1.

[0163] Figure 9 An exemplary structure of the scan output sub-circuit is shown. It is easy for those skilled in the art to understand that the implementation manner of the scan output sub-circuit is not limited to this.

[0164] Figure 10 It is an equivalent circuit diagram of the cascade output sub-circuit provided for an exemplary embodiment. As Figure 10 shown, in an exemplary embodiment, the cascade output sub-circuit may include: the ninth transistor T9 to the twenty-fifth transistor T25, and the third capacitor C3 to the sixth capacitor C6.

[0165] In an exemplary embodiment, as Figure 10As shown, the control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal V1, and the second electrode of the ninth transistor T9 is electrically connected to the cascade output terminal SOUT. The control electrode of the tenth transistor T10 is electrically connected to the third node N3, the first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal V2, and the second electrode of the tenth transistor T10 is electrically connected to the cascade output terminal SOUT. The control electrode of the eleventh transistor T11 is electrically connected to the second power supply terminal V2, the first electrode of the eleventh transistor T11 is electrically connected to the seventh node N7, and the second electrode of the eleventh transistor T11 is electrically connected to the ninth node N9. The control electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal V2, the first electrode of the twelfth transistor T12 is electrically connected to the second node N2, and the second electrode of the twelfth transistor T12 is electrically connected to the third node N3. The control electrode of the thirteenth transistor T13 is electrically connected to the third power supply terminal V3, the first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1, and the second electrode of the thirteenth transistor T13 is electrically connected to the second node N2. The control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK1, the first electrode of the fourteenth transistor T14 is electrically connected to the input terminal SIN, and the second electrode of the fourteenth transistor T14 is electrically connected to the eighth node N8. The control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal V2, the first electrode of the fifteenth transistor T15 is electrically connected to the eighth node N8, and the second electrode of the fifteenth transistor T15 is electrically connected to the twelfth node N12. The control electrode of the sixteenth transistor T16 is electrically connected to the twelfth node N12, the first electrode of the sixteenth transistor T16 is electrically connected to the third node N3, and the second electrode of the sixteenth transistor T16 is electrically connected to the twelfth node N12. The control electrode of the seventeenth transistor T17 is electrically connected to the first clock signal terminal CK1, the first electrode of the seventeenth transistor T17 is electrically connected to the input terminal SIN, and the second electrode of the seventeenth transistor T17 is electrically connected to the second node N2. The control electrode of the eighteenth transistor T18 is electrically connected to the second node N2, the first electrode of the eighteenth transistor T18 is electrically connected to the first clock signal terminal CK1, and the second electrode of the eighteenth transistor T18 is electrically connected to the seventh node N7. The control electrode of the nineteenth transistor T19 is electrically connected to the first clock signal terminal CK1, the first electrode of the nineteenth transistor T19 is electrically connected to the second power supply terminal V2, and the second electrode of the nineteenth transistor T19 is electrically connected to the seventh node N7. The control electrode of the twentieth transistor T20 is electrically connected to the second node N2, the first electrode of the twentieth transistor T20 is electrically connected to the second clock signal terminal CK2, and the second electrode of the twentieth transistor T20 is electrically connected to the eleventh node N11. The control electrode of the twenty-first transistor T21 is electrically connected to the seventh node N7, the first electrode of the twenty-first transistor T21 is electrically connected to the first power supply terminal V1, and the second electrode of the twenty-first transistor T21 is electrically connected to the eleventh node N11.The control electrode of the twenty-second transistor T22 is electrically connected to the ninth node N9, the first electrode of the twenty-second transistor T22 is electrically connected to the second clock signal terminal CK2, and the second electrode of the twenty-second transistor T22 is electrically connected to the tenth node N10. The control electrode of the twenty-third transistor T23 is electrically connected to the second clock signal terminal CK2, the first electrode of the twenty-third transistor T23 is electrically connected to the tenth node N10, and the second electrode of the twenty-third transistor T23 is electrically connected to the first node N1. The control electrode of the twenty-fourth transistor T24 is electrically connected to the second node N2, the first electrode of the twenty-fourth transistor T24 is electrically connected to the first power supply terminal V1, and the second electrode of the twenty-fourth transistor T24 is electrically connected to the first node N1. The control electrode of the twenty-fifth transistor T25 is electrically connected to the twelfth node N12, the first electrode of the twenty-fifth transistor T25 is electrically connected to the twelfth node N12, and the second electrode of the twenty-fifth transistor T25 is electrically connected to the fifth node N5. The first plate C31 of the third capacitor C3 is electrically connected to the third node N3, and the second plate C32 of the third capacitor C3 is electrically connected to the eleventh node N11. The fourth capacitor C4 includes a first plate C41 and a second plate C42. The first plate C41 of the fourth capacitor C4 is electrically connected to the second power supply terminal V2, and the second plate C42 of the fourth capacitor C4 is electrically connected to the cascade output terminal SOUT. The first plate C51 of the fifth capacitor C5 is electrically connected to the ninth node N9, and the second plate C52 of the fifth capacitor C5 is electrically connected to the tenth node N10. The first plate C61 of the sixth capacitor C6 is electrically connected to the first node N1, and the second plate C62 of the sixth capacitor C6 is electrically connected to the first power supply terminal V1.

[0166] Figure 10 An exemplary structure of the cascade output sub-circuit of the shift register model 16T3C is shown. It is easy for those skilled in the art to understand that the implementation manner of the cascade output sub-circuit is not limited to this.

[0167] In an exemplary embodiment, the shift register model can be 12T3C. When the shift register model is 12T3C, the cascade output sub-circuit may include Figure 10 or Figure 11 the ninth transistor T9 to the thirteenth transistor T13, the seventeenth transistor T17 to the twenty-third transistor T23 in

[0168] In an exemplary embodiment, the shift register model can be 10T3C. When the shift register model is 10T3C, the cascade output sub-circuit may include: the ninth transistor T9 to the twelfth transistor T12, the seventeenth transistor T17 to the twenty-second transistor T22.

[0169] In an exemplary embodiment, the first transistor T1 to the twenty-fifth transistor T25 can be type-six transistors or can be N-type transistors.

[0170] In an exemplary embodiment, a first power supply terminal V1 continuously provides a high-level signal, and a second power supply terminal V2 continuously provides a low-level signal. Since the second power supply terminal V2 continuously provides a low-level signal, the eleventh transistor T11, the twelfth transistor T12, and the fifteenth transistor T15 are continuously turned on.

[0171] In an exemplary embodiment, a third power supply terminal V3 is at a low-level signal during the power-on initialization stage to prevent the ninth transistor T9 and the tenth transistor T10 of the last-stage control shift register from being turned on simultaneously due to the delay of the output signal, or is at a low-level signal during the abnormal power-off stage to prevent the ninth transistor T9 and the tenth transistor T10 from being turned on simultaneously. The third power supply terminal V3 continuously provides a high-level signal during the normal display stage, that is, during the normal display stage, the thirteenth transistor T13 is continuously turned off.

[0172] Figure 11 An equivalent circuit diagram of a shift register provided for an exemplary embodiment. As Figure 11 shown, in an exemplary embodiment, the shift register may include: a cascaded output sub-circuit, an output control sub-circuit, and a scan output sub-circuit. The cascaded output sub-circuit may include: the ninth transistor T9 to the twenty-fifth transistor T25, the third capacitor C3 to the sixth capacitor C6, the output control sub-circuit may include: the first transistor T1 to the sixth transistor T6 and the first capacitor C1, and the scan output sub-circuit may include: the seventh transistor T7, the eighth transistor T8, and the second capacitor C2.

[0173] In an exemplary embodiment, as Figure 11As shown, the control electrode of the first transistor T1 is electrically connected to the first control signal terminal MS1, the first electrode of the first transistor T1 is electrically connected to the second electrode of the second transistor T2, and the second electrode of the first transistor T1 is electrically connected to the third control signal terminal MS3. The control electrode of the second transistor T2 is electrically connected to the third node N3, and the first electrode of the second transistor T2 is electrically connected to the sixth node N6. The control electrode of the third transistor T3 is electrically connected to the first control signal terminal MS1, the first electrode of the third transistor T3 is electrically connected to the second control signal terminal MS2, and the second electrode of the third transistor T3 is electrically connected to the first electrode of the fourth transistor T4. The control electrode of the fourth transistor is electrically connected to the first node N1, and the second electrode of the fourth transistor is electrically connected to the sixth node N6. The control electrode of the fifth transistor T5 is electrically connected to the sixth node N6, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4. The control electrode of the sixth transistor T6 is electrically connected to the sixth node N6, the first electrode of the sixth transistor T6 is electrically connected to the second node N2, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5. The control electrode of the seventh transistor T7 is electrically connected to the fourth node N4, the first electrode of the seventh transistor T7 is electrically connected to the first power supply terminal V1, and the second electrode of the seventh transistor T7 is electrically connected to the scan signal output terminal OUT. The control electrode of the eighth transistor T8 is electrically connected to the fifth node N5, the first electrode of the eighth transistor T8 is electrically connected to the scan signal output terminal OUT, and the second electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2. The control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal V1, and the second electrode of the ninth transistor T9 is electrically connected to the cascade output terminal SOUT. The control electrode of the tenth transistor T10 is electrically connected to the third node N3, the first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal V2, and the second electrode of the tenth transistor T10 is electrically connected to the cascade output terminal SOUT. The control electrode of the eleventh transistor T11 is electrically connected to the second power supply terminal V2, the first electrode of the eleventh transistor T11 is electrically connected to the seventh node N7, and the second electrode of the eleventh transistor T11 is electrically connected to the ninth node N9. The control electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal V2, the first electrode of the twelfth transistor T12 is electrically connected to the second node N2, and the second electrode of the twelfth transistor T12 is electrically connected to the third node N3. The control electrode of the thirteenth transistor T13 is electrically connected to the third power supply terminal V3, the first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1, and the second electrode of the thirteenth transistor T13 is electrically connected to the second node N2. The control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK1, the first electrode of the fourteenth transistor T14 is electrically connected to the input terminal SIN, and the second electrode of the fourteenth transistor T14 is electrically connected to the eighth node N8.The control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal V2, the first electrode of the fifteenth transistor T15 is electrically connected to the eighth node N8, and the second electrode of the fifteenth transistor T15 is electrically connected to the twelfth node N12. The control electrode of the sixteenth transistor T16 is electrically connected to the twelfth node N12, the first electrode of the sixteenth transistor T16 is electrically connected to the third node N3, and the second electrode of the sixteenth transistor T16 is electrically connected to the twelfth node N12. The control electrode of the seventeenth transistor T17 is electrically connected to the first clock signal terminal CK1, the first electrode of the seventeenth transistor T17 is electrically connected to the input terminal SIN, and the second electrode of the seventeenth transistor T17 is electrically connected to the second node N2. The control electrode of the eighteenth transistor T18 is electrically connected to the second node N2, the first electrode of the eighteenth transistor T18 is electrically connected to the first clock signal terminal CK1, and the second electrode of the eighteenth transistor T18 is electrically connected to the seventh node N7. The control electrode of the nineteenth transistor T19 is electrically connected to the first clock signal terminal CK1, the first electrode of the nineteenth transistor T19 is electrically connected to the second power supply terminal V2, and the second electrode of the nineteenth transistor T19 is electrically connected to the seventh node N7. The control electrode of the twentieth transistor T20 is electrically connected to the second node N2, the first electrode of the twentieth transistor T20 is electrically connected to the second clock signal terminal CK2, and the second electrode of the twentieth transistor T20 is electrically connected to the eleventh node N11. The control electrode of the twenty-first transistor T21 is electrically connected to the seventh node N7, the first electrode of the twenty-first transistor T21 is electrically connected to the first power supply terminal V1, and the second electrode of the twenty-first transistor T21 is electrically connected to the eleventh node N11. The control electrode of the twenty-second transistor T22 is electrically connected to the ninth node N9, the first electrode of the twenty-second transistor T22 is electrically connected to the second clock signal terminal CK2, and the second electrode of the twenty-second transistor T22 is electrically connected to the tenth node N10. The control electrode of the twenty-third transistor T23 is electrically connected to the second clock signal terminal CK2, the first electrode of the twenty-third transistor T23 is electrically connected to the tenth node N10, and the second electrode of the twenty-third transistor T23 is electrically connected to the first node N1. The control electrode of the twenty-fourth transistor T24 is electrically connected to the second node N2, the first electrode of the twenty-fourth transistor T24 is electrically connected to the first power supply terminal V1, and the second electrode of the twenty-fourth transistor T24 is electrically connected to the first node N1. The control electrode of the twenty-fifth transistor T25 is electrically connected to the twelfth node N12, the first electrode of the twenty-fifth transistor T25 is electrically connected to the twelfth node N12, and the second electrode of the twenty-fifth transistor T25 is electrically connected to the fifth node N5. The first plate C11 of the first capacitor C1 is electrically connected to the sixth node N6, and the second plate C12 of the first capacitor C1 is electrically connected to the fourth node N4. The first plate C21 of the second capacitor C2 is electrically connected to the fourth node N4, and the second plate C22 of the second capacitor C2 is electrically connected to the first power supply terminal V1.The first plate C31 of the third capacitor C3 is electrically connected to the third node N3, and the second plate C32 of the third capacitor C3 is electrically connected to the eleventh node N11. The fourth capacitor C4 includes a first plate C41 and a second plate C42. The first plate C41 of the fourth capacitor C4 is electrically connected to the second power supply terminal V2, and the second plate C42 of the fourth capacitor C4 is electrically connected to the cascaded output terminal SOUT. The first plate C51 of the fifth capacitor C5 is electrically connected to the ninth node N9, and the second plate C52 of the fifth capacitor C5 is electrically connected to the tenth node N10. The first plate C61 of the sixth capacitor C6 is electrically connected to the first node N1, and the second plate C62 of the sixth capacitor C6 is electrically connected to the first power supply terminal V1.

[0174] Figure 11 An exemplary structure of the shift register with the model number 16T3C is shown. It is easy for those skilled in the art to understand that the implementation manner of the shift register is not limited to this.

[0175] In an exemplary embodiment, the model number of the shift register can be 12T3C. When the model number of the shift register is 12T3C, the cascaded output sub - circuit may include Figure 10 or Figure 11 the ninth transistor T9 to the thirteenth transistor T13, and the seventeenth transistor T17 to the twenty - third transistor T23 in

[0176] In an exemplary embodiment, the model number of the shift register can be 10T3C. When the model number of the shift register is 10T3C, the cascaded output sub - circuit may include: the ninth transistor T9 to the twelfth transistor T12, and the seventeenth transistor T17 to the twenty - second transistor T22.

[0177] In an exemplary embodiment, the shift register is disposed on the display substrate. The display substrate may include: a plurality of scan signal lines. The working process of the display substrate may include: a display stage and a blank stage located between the display stages; the display substrate may include: a plurality of display regions. The refresh frequencies of different display regions include a first refresh frequency and a second refresh frequency, and the first refresh frequency is greater than the second refresh frequency.

[0178] When the working process of the display substrate is in the blank stage and the signal of the first control signal terminal MS1 is a low - level signal, the signals of the second control signal terminal MS2 and the third control signal MS3 are low - level signals.

[0179] When the working process of the display substrate is in the display stage and the shift register is connected to the scan signal line of the display region with the first refresh frequency, and the signal of the first control signal terminal MS1 is a low - level signal, the signals of the second control signal terminal MS2 and the third control signal terminal MS3 are low - level signals.

[0180] When the display substrate is in the display stage, the shift register is connected to the scan signal lines of the display area at the second refresh frequency, and the cascaded output terminal SOUT of the shift register outputs a low-level signal, when the signal of the first control signal terminal MS1 is a low-level signal, the signal of the second control signal terminal MS2 is a high-level signal, and the signal of the third control signal terminal MS3 is a low-level signal.

[0181] When the display substrate is in the display stage, the shift register is connected to the scan signal lines of the display area at the second refresh frequency, and the cascaded output terminal SOUT of the shift register outputs a high-level signal, when the signal of the first control signal terminal MS1 is a low-level signal, the signal of the second control signal terminal MS2 is a high-level signal, and the signal of the third control signal terminal is a low-level signal.

[0182] When the display substrate is in the display stage, the shift register is connected to the scan signal lines of the display area at the second refresh frequency, and the cascaded output terminal of the shift register outputs a low-level signal, when the signal of the first control signal terminal is a low-level signal, the signal of the second control signal terminal is a high-level signal, and the signal of the third control signal terminal is a low-level signal.

[0183] The duration for which the signal of the first control signal terminal MS1 is at a low level is less than the duration for which the signal of any one of the second control signal terminal MS2 and the third control signal terminal MS3 is at a low level.

[0184] Figure 12A For the working timing diagram of the shift register provided for an exemplary embodiment, the following is through Figure 11 The working process of the exemplary shift register is used to illustrate the exemplary embodiment of the present disclosure, taking Figure 11 the first transistor T1 to the eighth transistor T8, the first capacitor C1, the second capacitor C2, the first control signal terminal MS1 to the third control signal terminal MS3, the first node N1 to the fourth node N4, and the scan signal output terminal OUT provided in the shift register as an example.

[0185] In an exemplary embodiment, as Figure 12A shown, the working process of the shift register may include:

[0186] Stage S1 (Initialization Stage): The signal of the first node N1 is a high-level signal, and the signals of the third node N3, the first control signal MS1, the second control signal MS2, and the third control signal MS3 are low-level signals. Since the signal of the first control signal MS1 is a low-level signal, the first transistor T1 is turned on. As the signal of the third node N3 is a low-level signal, the second transistor T2 is turned on, and the low-level signal of the third control signal MS3 is written into the sixth node N6 through the turned-on first transistor T1 and second transistor T2. The signal of the sixth node N6 is a low-level signal and is held by the first capacitor C1, and the fifth transistor T5 and the sixth transistor T6 are turned on. The high-level signal of the first node N1 is written into the fourth node N4 through the turned-on fifth transistor T5. At this time, the seventh transistor T7 is turned off, and the low-level signal of the third node N3 is written into the fifth node N5 through the turned-on sixth transistor T6. At this time, the eighth transistor T8 is turned on, and the low-level signal of V2 is written into the scan signal output terminal OUT, and the output signal of the scan signal output terminal OUT is a low-level signal.

[0187] Stage S21 (The output of the low-frequency region cascade output terminal SOUT is low): The signals of the first node N1 and the second control signal MS2 are high-level signals, and the signals of the third node N3, the first control signal MS1, and the third control signal MS3 are low-level signals. Since the first control signal MS1 is a low-level signal, the first transistor T1 is turned on. As the third node N3 is at a low level, the second transistor T2 is turned on, and the low-level signal of the third control signal MS3 is written into the sixth node N6 through the turned-on first transistor T1 and second transistor T2. The signal of the sixth node N6 is a low-level signal and is held by the first capacitor C1, and the fifth transistor T5 and the sixth transistor T6 are turned on. The high-level signal of the first node N1 is written into the fourth node N4 through the turned-on fifth transistor T5. At this time, the seventh transistor T7 is turned off, and the low-level signal of the third node N3 is written into the fifth node N5 through the turned-on sixth transistor T6. At this time, the eighth transistor T8 is turned on, and the low-level signal of V2 is written into the scan signal output terminal OUT, and the output signal of the scan signal output terminal OUT is a low-level signal.

[0188] Stage S22 (the cascaded output terminal SOUT in the low-frequency region outputs a high level): The signals of the first node N1, the first control signal MS1, and the third control signal MS3 are low-level signals, and the signals of the third node N3 and the second control signal MS2 are high-level signals. Since the signal of the first control signal MS1 is a low-level signal, the third transistor T3 is turned on. Since the signal of the first node N1 is a low-level signal, the fourth transistor T4 is turned on. The high-level signal of the second control signal MS2 is written into the sixth node N6 through the turned-on third transistor T3 and fourth transistor T4. The signal of the sixth node N6 is a high-level signal and is held by the first capacitor C1. The fourth node N4 is maintained at the high-level signal of the previous stage by the second capacitor C2. At this time, the seventh transistor T7 is turned off. The fifth node N5 maintains a low-level signal. At this time, the eighth transistor T8 is turned on, and the low-level signal of V2 is written into the scan signal output terminal OUT, and the output signal of the scan signal output terminal OUT is a low-level signal.

[0189] Stage S31 (the cascaded output terminal SOUT in the high-frequency region outputs a high level): The signals of the first node N1, the first control signal MS1, the second control signal MS2, and the third control signal MS3 are low-level signals, and the signal of the third node N3 is a high-level signal. Since the first control signal MS1 is a low-level signal, the third transistor T3 is turned on. Since the first node N1 is at a low level, the fourth transistor T4 is turned on. The low-level signal of the second control signal MS2 is written into the sixth node N6 through the turned-on third transistor T3 and fourth transistor T4. The signal of the sixth node N6 is a low-level signal and is held by the first capacitor C1, and the fifth transistor T5 and the sixth transistor T6 are turned on. The high-level signal of the third node N3 is written into the fifth node N5 through the turned-on sixth transistor T6. At this time, the eighth transistor T8 is turned off. The low-level signal of the first node N1 is written into the fourth node N4 through the turned-on fifth transistor T5. At this time, the seventh transistor T7 is turned on, and the high-level signal of the first power supply terminal V1 is written into the scan signal output terminal OUT, and the output signal of the scan signal output terminal OUT is a high-level signal.

[0190] S32 stage (the output of the high-frequency region cascade output terminal SOUT is low level): The signal of the first node N1 is a high-level signal, and the signals of the third node N3, the first control signal MS1, the second control signal MS2, and the third control signal MS3 are low-level signals. Since the first control signal MS1 is a low-level signal, the first transistor T1 is turned on, the third node N3 is at a low level, the second transistor T2 is turned on, and the low-level signal of the third control signal MS3 is written into the sixth node N6 through the turned-on first transistor T1 and second transistor T2. The signal of the sixth node N6 is a low-level signal and is held by the first capacitor C1, and the fifth transistor T5 and the sixth transistor T6 are turned on. The high-level signal of the first node N1 is written into the fourth node N4 through the turned-on fifth transistor T5. At this time, the seventh transistor T7 is turned off, and the low-level signal of the third node N3 is written into the fifth node N5 through the turned-on sixth transistor T6. At this time, the eighth transistor T8 is turned on, and the low-level signal of V2 is written into the scan signal output terminal OUT, and the output signal of the scan signal output terminal OUT is a low-level signal.

[0191] Figure 12B The working timing diagram of the shift register provided for an exemplary embodiment is as follows. Next, Figure 11 the working process of the exemplary shift register is used to illustrate the exemplary embodiment of the present disclosure. Taking Figure 11 the first transistor T1 to the eighth transistor T8, the first capacitor C1, the second capacitor C2, the first control signal terminal MS1 to the third control signal terminal MS3, and the scan signal output terminal OUT in the provided shift register as examples, the scan signal output terminal OUT includes the scan signal output terminals Nout1... Noutn, Noutn+1, Nout... Nout m, Nout m+1, Nout m+2... Nout k of different frames.

[0192] In an exemplary embodiment, as Figure 12B shown, by changing the voltage of the control signal MS (the first control signal MS1, the second control signal MS2, and the third control signal MS3), it is possible to control whether to output a low-level signal at the scan signal output terminal OUT, and it is possible to achieve the high-level output of the scan signal output terminal within a frame, realize the update of the data voltage Vdata of some rows, control the local screen refresh of different frames, thereby reducing the power consumption of the display panel. While the scan signal output terminals of other rows are always at a low level and will not repeatedly charge and discharge the initial signal line and the data voltage Vdata, saving power.

[0193] In an exemplary embodiment, as Figure 12B shown, the working process of the shift register can be divided into three stages:

[0194] Initialization stage: When reaching the second last line of the initialization frame, the first pulse of the first control signal terminal MS1 turns on. At this time, the third node N3 is at a low-level signal, the first node N1 is at a high-level signal, the first transistor T1 and the second transistor T2 are turned on, and the fourth transistor T4 is turned off. The third node N3 writes the low-level signal of the third control signal terminal MS3 and is held by the first capacitor C1. The fifth transistor T5 and the sixth transistor T6 are turned on, the first node N1 is connected to the fourth node N4, and the second node N2 is connected to the fifth node N5. The scanning signal output terminals Nout1... Noutn, Noutn+1, Nout... Nout m, Nout m+1, Nout m+2... Nout k of different frames can output normally.

[0195] High-frequency to low-frequency stage: At the last line of the high-frequency region frame, the second pulse of the first control signal MS1 turns on. If the cascade output terminal Sout outputs a low-level signal at this time, that is, the first node N1 is at a high-level signal and the third node N3 is at a low-level signal, the first transistor T1 and the second transistor T2 are turned on, and the sixth node N6 writes the high-level signal of the third control signal MS3. The fifth transistor T5 and the sixth transistor T6 are turned off, the fourth node N4 maintains a high-level signal, and the fifth node N5 maintains a low-level signal, so that the scanning signal output terminals Nout1... Noutn, Noutn+1, Nout... Nout m, Nout m+1, Nout m+2... Nout k of the corresponding different frames can always be maintained at a low-level signal. If the cascade output terminal Sout outputs a high-level signal at this time, that is, the first node N1 is at a low-level signal and the third node N3 is at a high-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and the sixth node N6 writes the low-level signal of the second control signal MS2 and is held by the first capacitor C1. The fifth transistor T5 and the sixth transistor T6 are turned on, the fourth node N4 still maintains a low-level signal, and the fifth node N5 is still at a high-level signal. The scanning signal output terminals Nout1... Noutn, Noutn+1, Nout... Nout m, Nout m+1, Nout m+2... Nout k of different frames can still output a high-level signal. When the cascade output terminal Sout switches to a low level, the scanning signal output terminals Nout1... Noutn, Noutn+1, Nout... Nout m, Nout m+1, Nout m+2... Nout k of different frames can output a low-level signal. In other words, at this time, the scanning signal output terminals Nout1... Noutn, Noutn+1, Nout... Nout m, Nout m+1, Nout m+2... Nout k of the corresponding different frames can output a low-level signal after maintaining the complete high-level waveform output.

[0196] Low-frequency to high-frequency stage: At the last line of the frame in the low-frequency region, the third pulse of the first control signal MS1 turns on. If the output of the cascade output terminal Sout is a low-level signal at this time, the timing process is the same as that in the initialization stage, and the scan signal output terminals Nout1... Noutn, Noutn+1, Nout... Nout m, Nout m+1, Nout m+2... Nout k of different frames can be normally output. If the output of the cascade output terminal Sout is a high-level signal at this time, that is, the first node N1 is a low-level signal and the third node N3 is a high-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and the high-level signal of the second control signal MS2 is written to the sixth node N6 and is held by the first capacitor C1. The fourth node N4 is maintained at the high-level signal of the previous stage by the second capacitor C2, and the fifth node N5 remains at the low-level signal, and the output waveforms of the scan signal output terminals Nout1... Noutn, Noutn+1, Nout... Nout m, Nout m+1, Nout m+2... Nout k of the corresponding different frames can be maintained at the low level.

[0197] Figure 13 The output waveform diagram of the shift register provided for an exemplary embodiment is as Figure 13 shown, and the control of the scan signal output terminals OUT1 to OUT13 of thirteen rows of pixels can be realized by the voltage switching of the first control signal MS1, the first control signal MS2, and the third control signal MS3. Among them, Figure 13 the abscissa represents time, and the unit can be microseconds (us, which can be abbreviated as u).

[0198] Figure 14 The working timing diagram of the cascade output sub-circuit provided for an exemplary embodiment is as follows. Through Figure 10 or Figure 11 the working process of the example cascade output sub-circuit, the exemplary embodiments of the present disclosure will be described. Taking Figure 10 or Figure 11 the ninth transistor T9 to the twenty-fifth transistor T25, the third capacitor C3 to the sixth capacitor C6, the input terminal SIN, the first clock signal terminal CK1, the second clock signal terminal CK2, and the cascade output terminal SOUT in the provided cascade output sub-circuit as an example.

[0199] In an exemplary embodiment, as Figure 14 shown, the working process of the cascade output sub-circuit may include:

[0200] In the first stage E1, the signal of the second clock signal terminal CK2 is a high-level signal, and the signal of the first clock signal terminal CK1 is a low-level signal. Since the signal of the first clock signal terminal CK1 is a low-level signal, the seventeenth transistor T17, the nineteenth transistor T19, the twelfth transistor T12, and the fourteenth transistor T14 are turned on. The turned-on seventeenth transistor T17 transmits the high-level signal of the input terminal SIN to the second node N2, and the signal of the second node N2 becomes a high-level signal. The turned-on twelfth transistor T12 transmits the high-level signal of the second node N2 to the third node N3. The turned-on fourteenth transistor T14 transmits the high-level signal of the input terminal SIN to the eighth node N8, and the signal of the eighth node N8 becomes a high-level signal. The turned-on fifteenth transistor T15 transmits the high-level signal of the eighth node N8 to the twelfth node N12. The eighteenth transistor T18, the twentieth transistor T20, the twenty-fourth transistor T24, and the tenth transistor T10 are turned off. Additionally, the turned-on nineteenth transistor T19 transmits the low-level signal of the second power supply terminal V2 to the seventh node N7, and the signal of the seventh node N7 becomes a low-level signal. The turned-on eleventh transistor T11 transmits the low-level signal of the seventh node N7 to the ninth node N9, and the signal of the ninth node N9 becomes a low-level signal. The twenty-first transistor T21 and the twenty-second transistor T22 are turned on. The signal of the second clock signal terminal CK2 is a high-level signal, and the twenty-third transistor T23 is turned off. Additionally, due to the effect of the third capacitor C3, the ninth transistor T9 is turned off. In the first stage E1, since both the ninth transistor T9 and the tenth transistor T10 are turned off, the signal of the cascaded output terminal SOUT remains the previous low level.

[0201] In the second stage E2, the signal of the second clock signal terminal CK2 is a low-level signal, and the signal of the first clock signal terminal CK1 is a high-level signal. Since the signal of the second clock signal terminal CK2 is a low-level signal, the twenty-third transistor T23 is turned on. Since the signal of the first clock signal terminal CK1 is a high-level signal, the seventeenth transistor T17 and the nineteenth transistor T19 are turned off. Due to the effect of the third capacitor C3, the second node N2, the third node N3, the eighth node N8, and the twelfth node N12 can continue to maintain the high-level signals of the previous stage. Due to the effect of the fifth capacitor C5, the ninth node N9 can continue to maintain the low level of the previous stage. Therefore, the twenty-first transistor T21 and the twenty-second transistor T22 are turned on. The eighteenth transistor T18, the twentieth transistor T20, the twenty-fourth transistor T24, and the tenth transistor T10 are turned off. Additionally, the low-level signal of the second clock signal terminal CK2 is transmitted to the first node N1 through the turned-on twenty-second transistor T22 and the twenty-third transistor T23. The ninth transistor T9 is turned on. The turned-on ninth transistor T9 outputs the high-level signal of the first power supply terminal V1, and the signal of the cascaded output terminal SOUT is a high-level signal.

[0202] In the third stage E3, the signal of the first clock signal terminal CK1 is a low-level signal, and the signal of the second clock signal terminal CK2 is a high-level signal. Since the signal of the second clock signal terminal CK2 is a high-level signal, the twenty-third transistor T23 is cut off. The eighteenth transistor T18, the twentieth transistor T20, the twenty-fourth transistor T24, and the tenth transistor T10 are cut off. Since the signal of the first clock signal terminal CK1 is a low-level signal, the seventeenth transistor T17 and the nineteenth transistor T19 are turned on. Under the action of the third capacitor C3, the ninth transistor T9 remains in the on state, and the on ninth transistor T9 outputs the high-level signal of the first power supply terminal V1, and the signal of the cascade output terminal SOUT is still a high-level signal.

[0203] In the fourth stage E4, the signal of the second clock signal terminal CK2 is a low-level signal, and the signal of the first clock signal terminal CK1 is a high-level signal. Since the signal of the first clock signal terminal CK1 is a high-level signal, the seventeenth transistor T17 and the nineteenth transistor T19 are cut off. Since the signal of the second clock signal terminal CK2 is a low-level signal, the twenty-third transistor T23 is turned on. Due to the storage effect of the third capacitor C3, the signals of the second node N2, the third node N3, the eighth node N8, and the twelfth node N12 remain the high-level signals of the previous stage, and the eighteenth transistor T18, the twentieth transistor T20, the twenty-fourth transistor T24, and the tenth transistor T10 are cut off. Due to the storage effect of the fifth capacitor C5, the ninth node N9 continues to maintain the low level of the previous stage, and the twenty-first transistor T21 and the twenty-second transistor T22 are turned on. In addition, the low-level signal of the second clock signal terminal CK2 is transmitted to the first node N1 through the on twenty-second transistor T22 and the twenty-third transistor T23, the on ninth transistor T9 outputs the high-level signal of the first power supply terminal V1, and the signal of the cascade output terminal SOUT is still a high-level signal.

[0204] In the fifth stage E5, the signal of the second clock signal terminal CK2 is a high-level signal, and the signal of the first clock signal terminal CK1 is a low-level signal. Since the signal of the first clock signal terminal CK1 is a low-level signal, the seventeenth transistor T17, the nineteenth transistor T19, and the fourteenth transistor T14 are turned on. Since the signal of the second clock signal terminal CK2 is a high-level signal, the twenty-third transistor T23 is turned off. The turned-on seventeenth transistor T17 transmits the low-level signal of the input terminal SIN to the second node N2, and the signal of the second node N2 becomes a low-level signal. The turned-on twelfth transistor T12 transmits the low-level signal of the second node N2 to the third node N3, and the signal of the third node N3 becomes a low-level signal. The turned-on fourteenth transistor T14 transmits the low-level signal of the input terminal SIN to the eighth node N8, and the signal of the eighth node N8 becomes a low-level signal. The turned-on fifteenth transistor T15 transmits the low-level signal of the eighth node N8 to the twelfth node N12, and the signal of the twelfth node N12 becomes a low-level signal. The eighteenth transistor T18, the twentieth transistor T20, the twenty-fourth transistor T24, and the tenth transistor T10 are turned on. The turned-on eighteenth transistor T18 transmits the signal of the low-level first clock signal terminal CK1 to the seventh node N7, which can pull down the level of the seventh node N7. Therefore, the seventh node N7 and the ninth node N9 continue to maintain the low level of the previous stage, and the twenty-first transistor T21 and the twenty-second transistor T22 are turned on. Since the signal of the second clock signal terminal CK2 is a high-level signal, the twenty-third transistor T23 is turned off. Additionally, the turned-on twenty-fourth transistor T24 transmits the high-level signal of the first power supply terminal V1 to the first node N1, and the ninth transistor T9 is turned off. The turned-on tenth transistor T10 outputs the low-level signal of the second power supply terminal V2, and the signal of the cascaded output terminal SOUT becomes a low-level signal.

[0205] The embodiment of the present disclosure also provides a gate driving circuit, including: a plurality of cascaded shift registers; the signal output terminal of the i-th stage shift register is electrically connected to the signal input terminal of the (i + 1)-th stage shift register, where 1 ≤ i ≤ M - 1, and M is the total number of stages of the shift register.

[0206] The shift register can be the shift register provided in any of the foregoing embodiments. The implementation principle and implementation effect are similar and will not be elaborated here.

[0207] For different display products, the cascading relationship of the plurality of shift registers in the gate driving circuit may be different. Regardless of the cascading relationship of the plurality of shift registers, as long as each shift register drives several rows of sub-pixels, and as long as changes occur in large-area devices of this kind, and after such changes generate additional space, simple translations and stretches of small devices are within the protection scope of the present disclosure.

[0208] The gate driving circuit provided by an embodiment of the present disclosure is located in a display device. The display device is further provided with a pixel circuit and a gate line. The pixel circuit is electrically connected to at least one gate line, and the scan output signal terminal of the shift register in the gate driving circuit is electrically connected to the gate line.

[0209] The gate driving circuit provided by an embodiment of the present disclosure can drive the pixel circuit. Through the first control signal MS1 to the third control signal MS3, the local screen image is updated, and the remaining images do not require multiple charge and discharge operations, reducing the power consumption of OLED displays; or through local update of the display image, ultra-low power consumption of OLED products such as wearable devices, mobile phones, and notebook computers (NB) is achieved.

[0210] In an exemplary embodiment, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 15A It is a schematic diagram of an equivalent circuit of a pixel circuit. As Figure 15A shown, the pixel circuit may include seven control transistors (the first control transistor M1 to the seventh control transistor M7) and one capacitor C.

[0211] As Figure 15AAs shown, the gate electrode of the first control transistor M1 is electrically connected to the reset signal line Reset, the first pole of the first control transistor M1 is electrically connected to the first initial signal line INIT1, and the second pole of the first control transistor M1 is electrically connected to the first node E1; the gate electrode of the second control transistor M2 is electrically connected to the second scan signal line Gate2, the first pole of the second control transistor M2 is electrically connected to the first node E1, and the second pole of the second control transistor M2 is electrically connected to the third node E3; the gate electrode of the third control transistor M3 is electrically connected to the first node E1, the first pole of the third control transistor M3 is electrically connected to the second node E2, and the second pole of the third control transistor M3 is electrically connected to the third node E3; the gate electrode of the fourth control transistor M4 is electrically connected to the first scan signal line Gate1, the first pole of the fourth control transistor M4 is electrically connected to the data signal line Data, and the second pole of the fourth control transistor M4 is electrically connected to the second node E2; the gate electrode of the fifth control transistor M5 is electrically connected to the emission signal line EM, the first pole of the fifth control transistor M5 is electrically connected to the high-level power supply line VDD, and the second pole of the fifth control transistor M5 is electrically connected to the second node E2; the gate electrode of the sixth control transistor M6 is electrically connected to the emission signal line EM, the first pole of the sixth control transistor M6 is electrically connected to the third node E3, and the second pole of the sixth control transistor M6 is electrically connected to the fourth node E4; the gate electrode of the seventh control transistor M7 is electrically connected to the first scan signal line Gate1, the first pole of the seventh control transistor M7 is electrically connected to the second initial signal line INIT2, and the second pole of the seventh control transistor M7 is electrically connected to the fourth node E4; the first plate of the capacitor C is electrically connected to the first node E1, and the second plate of the capacitor C is electrically connected to the high-level power supply line VDD.

[0212] In an exemplary embodiment, the first control transistor M1 to the seventh control transistor M7 may be made of low-temperature polysilicon thin-film control transistors, or may be made of oxide thin-film control transistors, or may be made of a combination of low-temperature polysilicon thin-film control transistors and oxide thin-film control transistors. The active layer of the low-temperature polysilicon thin-film control transistor is made of low-temperature polysilicon (Low Temperature Poly-Silicon, abbreviated as LTPS), and the active layer of the oxide thin-film control transistor is made of oxide semiconductor (Oxide). The low-temperature polysilicon thin-film control transistor has advantages such as high mobility and fast charging, and the oxide thin-film control transistor has advantages such as low leakage current. Integrating the low-temperature polysilicon thin-film control transistor and the oxide thin-film control transistor on a display substrate to form an LTPO display substrate can utilize the advantages of both, enable low-frequency driving, reduce power consumption, and improve display quality.

[0213] In an exemplary embodiment, the control transistor types of the first control transistor M1 and the second control transistor M2 are opposite to those of the third control transistor M3 to the seventh control transistor M7. Exemplarily, the first control transistor M1 and the second control transistor M2 may be N-type control transistors, and the third control transistor M3 to the seventh control transistor M7 may be P-type control transistors.

[0214] In an exemplary embodiment, the first control transistor M1 and the second control transistor M2 may be oxide control transistors, and the third control transistor M3 to the seventh control transistor M7 may be low-temperature polysilicon control transistors.

[0215] In an exemplary embodiment, the voltage value of the signal on the first initial signal line INIT1 is constant and is a DC signal, and the voltage value of the signal on the first initial signal line INIT1 may be -3V.

[0216] In an exemplary embodiment, the voltage value of the signal on the second initial signal line INIT2 is constant and is a DC signal, and the voltage value of the signal on the second initial signal line INIT2 may be 0V.

[0217] In an exemplary embodiment, the light-emitting device L may be electrically connected to the fourth node E4 and the low-level power supply line VSS respectively.

[0218] In an exemplary embodiment, the high-level power supply line VDD continuously provides a high-level signal, and the low-level power supply line VSS continuously provides a low-level signal.

[0219] Figure 15B For Figure 15A the provided timing diagram of the pixel circuit. The following Figure 15A illustrates the exemplary embodiments of the present disclosure through the working process of the exemplary pixel circuit in the display stage. Figure 15B It is described by taking the first control transistor M1 and the second control transistor M2 as N-type control transistors and the third control transistor M3 to the seventh control transistor M7 as P-type control transistors as an example. Figure 15B The pixel circuit in

[0220] Combined with Figure 15A and Figure 15B , the working process of the pixel circuit may include:

[0221] The first stage P1, called the initialization stage, has the signal of the reset signal line Reset as a high-level signal. The first control transistor M1 is turned on, and the signal of the first initial signal line INIT1 is written into the first node E1 through the turned-on first control transistor M1 to initialize (reset) the first node E1, clear the pre-stored voltage inside it, and complete the initialization.

[0222] The second stage P2, called the data writing stage or the threshold compensation stage, has the first scan signal line Gate1 as a low-level signal, the second scan signal line Gate2 as a low-level signal, and the data signal line Data outputs a data voltage. In this stage, since the first node E1 is a low-level signal, the third control transistor M3 is turned on. The signal of the first scan signal line Gate1 is a low-level signal, the fourth control transistor M4 and the seventh control transistor M7 are turned on. The signal of the second scan signal line Gate2 is a high-level signal, the second control transistor M2 is turned on. The data voltage output by the data signal line Data is provided to the first node E1 through the turned-on fourth control transistor M4, the second node E2, the turned-on third control transistor M3, the third node E3, and the turned-on second control transistor M2. And the difference between the data voltage output by the data signal line Data and the threshold voltage of the third control transistor M3 is charged into the capacitor C until the voltage of the first node E1 is Vd - |Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third control transistor M3. The seventh control transistor M7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node E4 through the turned-on seventh control transistor M7 to initialize (reset) the first electrode of the light-emitting device L, clear the pre-stored voltage inside it, and complete the initialization.

[0223] The third stage P3, called the light-emitting stage, has the signal of the light-emitting signal line EM as a low-level signal. The fifth control transistor M5 and the sixth control transistor M6 are turned on. The power supply voltage output by the high-level power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth control transistor M5, the third control transistor M3, and the sixth control transistor M6 to drive the light-emitting device L to emit light.

[0224] During the driving process of the pixel circuit, the driving current flowing through the third control transistor M3 (driving control transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node E1 is Vd - |Vth|, the driving current of the third control transistor M3 is:

[0225] I = K * (Vgs - Vth) 2 = K * [(Vdd - Vd + |Vth|) - Vth] 2 = K * (Vdd - Vd) 2

[0226] Wherein, I is the driving current flowing through the third control transistor M3, which is also the driving current for driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first pole of the third control transistor M3, Vth is the threshold voltage of the third control transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0227] In an exemplary embodiment, the gate driving circuit provided by the embodiments of the present disclosure can be electrically connected to the second scanning signal line Gate2.

[0228] In an exemplary embodiment, Figure 16A is a schematic equivalent circuit diagram of another pixel circuit. As Figure 16A shown, the pixel circuit may include eight control transistors (the first control transistor M1 to the eighth control transistor M8), one capacitor C, and nine signal lines (data signal line Data, control signal line Scan, scanning signal line Gate, reset signal line Reset, light-emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, high-level power supply line VDD, and low-level power supply line VSS).

[0229] In an exemplary embodiment, as Figure 16AAs shown, the first electrode of the capacitor C is connected to the high-level power supply line VDD, and the second electrode of the capacitor C is connected to the first node E1. The control electrode of the first control transistor M1 is connected to the reset signal line Reset. The first electrode of the first control transistor M1 is connected to the first initial signal line INIT1, and the second electrode of the first control transistor is connected to the fourth node E4. The control electrode of the second control transistor M2 is connected to the scan signal line Gate. The first electrode of the second control transistor M2 is connected to the fourth node E4, and the second electrode of the second control transistor M2 is connected to the second node E2. The control electrode of the third control transistor M3 is connected to the first node E1. The first electrode of the third control transistor M3 is connected to the second node E2, and the second electrode of the third control transistor M3 is connected to the third node E3. The control electrode of the fourth control transistor M4 is connected to the scan signal line Gate. The first electrode of the fourth control transistor M4 is connected to the data signal line Data, and the second electrode of the fourth control transistor M4 is connected to the third node E3. The control electrode of the fifth control transistor M5 is connected to the emission signal line EM. The first electrode of the fifth control transistor M5 is connected to the high-level power supply line VDD, and the second electrode of the fifth control transistor M5 is connected to the third node E3. The control electrode of the sixth control transistor M6 is connected to the emission signal line EM. The first electrode of the sixth control transistor M6 is connected to the second node E2, and the second electrode of the sixth control transistor M6 is connected to the first electrode of the light-emitting device L. The control electrode of the seventh control transistor M7 is connected to the reset signal line Reset. The first electrode of the seventh control transistor M7 is connected to the second initial signal line INIT2, and the second electrode of the seventh control transistor M7 is connected to the first electrode of the light-emitting device L. The second electrode of the light-emitting device L is connected to the low-level power supply line VSS. The control electrode of the eighth control transistor M8 is connected to the control signal line Scan. The first electrode of the eighth control transistor M8 is connected to the first node E1, and the second electrode of the eighth control transistor M8 is connected to the fourth node E4.

[0230] In an exemplary embodiment, the control electrode of the seventh control transistor M7 can also be connected to the scan signal line Gate. The first electrode of the seventh control transistor M7 is connected to the second initial signal line INIT2, and the second electrode of the seventh control transistor M7 is connected to the first electrode of the light-emitting device L. The second electrode of the light-emitting device L is connected to the low-level power supply line VSS.

[0231] In an exemplary embodiment, the signal of the high-level power supply line VDD is a continuously provided high-level signal, and the signal of the low-level power supply line VSS is a low-level signal.

[0232] In an exemplary embodiment, the eighth control transistor M8 is a metal-oxide control transistor and is an N-type control transistor. The first control transistor M1 to the seventh control transistor M7 are low-temperature polysilicon control transistors and are P-type control transistors.

[0233] In an exemplary embodiment, the eighth control transistor M8 being an oxide control transistor can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.

[0234] In an exemplary embodiment, the gate driving circuit provided by the embodiments of the present disclosure can be electrically connected to the control signal line Scan.

[0235] Figure 16B For Figure 16A the provided timing diagram of the operation of the pixel circuit. The following Figure 16B illustrates the exemplary embodiments of the present disclosure through the operation process of the exemplary pixel circuit. The operation process of the pixel circuit may include:

[0236] The first stage A1, called the reset stage, the signals of the control signal line Scan, the light-emitting signal line EM, and the scanning signal line Gate are all high-level signals, and the signal of the reset signal line Reset is a low-level signal. Since the signal of the reset signal line Reset is a low-level signal, the first control transistor M1 is turned on, the signal of the first initial signal line INIT1 is provided to the fourth node E4, the seventh control transistor M7 is turned on, the initial voltage of the second initial signal line INIT2 is provided to the first pole of the light-emitting device L, and the first pole of the light-emitting device L is initialized (reset), for example: clearing the pre-stored voltage inside it, completing the initialization, and ensuring that the light-emitting device L does not emit light. Since the signal of the control signal line Scan is a high-level signal, the eighth control transistor M8 is turned on, the signal of the fourth node E4 is provided to the first node E1, and the capacitor C is initialized to clear the original data voltage in the capacitor C. Since the signals of the scanning signal line Gate and the light-emitting signal line EM are high-level signals, the second control transistor M2, the fourth control transistor M4, the fifth control transistor M5, the sixth control transistor M6, and the seventh control transistor M7 are turned off. In this stage, the light-emitting device L does not emit light.

[0237] The second stage A2, called the data writing stage or the threshold compensation stage, has the signal of the scanning signal line Gate as a low-level signal, the signals of the reset signal line Reset, the light-emitting signal line EM, and the control signal line Scan as high-level signals, and the data signal line Data outputs a data voltage. In this stage, since the first node E1 is a low-level signal, the third control transistor M3 is turned on. The signal of the scanning signal line Gate is a low-level signal, the second control transistor M2 and the fourth control transistor M4 are turned on, the signal of the control signal line Scan is a high-level signal, and the eighth control transistor M8 is turned on. The conduction of the second control transistor M2, the fourth control transistor M4, and the eighth control transistor M8 causes the data voltage output by the data signal line Data to be provided to the first node E1 through the third node E3, the turned-on third control transistor M3, the second node E2, the turned-on second control transistor M2, the fourth node E4, and the turned-on eighth control transistor M8, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third control transistor M3 is charged into the capacitor C until the voltage of the first node E1 is Vd - |Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third control transistor M3. The signal of the reset signal line Reset is a low-level signal, and the first control transistor M1 and the seventh control transistor M7 are turned off. The signal of the light-emitting signal line EM is a high-level signal, and the fifth control transistor M5 and the sixth control transistor M6 are turned off.

[0238] The third stage A3, called the light-emitting stage, has the signals of the control signal line Scan and the light-emitting signal line EM as low-level signals, and the signals of the scanning signal line Gate and the reset signal line Reset as high-level signals. The signal of the reset signal line Reset is a low-level signal, and the first control transistor M1 and the seventh control transistor M7 are cut off. The control signal line Scan is a low-level signal, and the signals of the scanning signal line Gate and the reset signal line Reset are high-level signals, so the second control transistor M2, the fourth control transistor M4, and the eighth control transistor M8 are cut off. The signal of the light-emitting signal line EM is a low-level signal, and the fifth control transistor M5 and the sixth control transistor M6 are turned on. The power supply voltage output by the high-level power supply line VDD provides a driving voltage to the first pole of the light-emitting device L through the turned-on fifth control transistor M5, the third control transistor M3, and the sixth control transistor M6 to drive the light-emitting device L to emit light.

[0239] During the driving process of the pixel circuit, the driving current flowing through the third control transistor M3 (driving control transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node E1 is Vd - |Vth|, the driving current of the third control transistor M3 is:

[0240] I = K * (Vgs - Vth)2 = K * [(Vdd - Vd + |Vth|) - Vth] 2 = K * (Vdd - Vd) 2

[0241] Wherein, I is the driving current flowing through the third control transistor M3, that is, the driving current for driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third control transistor M3, Vth is the threshold voltage of the third control transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0242] The gate driving circuit provided by the embodiments of the present disclosure can control the opening and closing of the gates of the transistors in the pixel circuit to achieve the refresh of the pixel brightness. When the gate driving circuit controls the gates of the transistors in the pixel circuit to be in the off state, it can achieve that some pixels are not refreshed, and in some special pictures, such as AOD, static pictures, or pictures with less updates, etc., the relevant pixel voltages are not updated, avoiding repeated writing to the relevant pixels, which may cause a relatively large power consumption of the display.

[0243] The embodiments of the present disclosure also provide a driving method for a shift register, configured to drive the shift register. The driving method of the shift register may include:

[0244] The cascaded output sub-circuit provides the signal of the first power supply terminal or the second power supply terminal to the cascaded output terminal under the control of the signals of the input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the second node, and the third node;

[0245] The output control sub-circuit provides the signal of the first node to the fourth node and the signal of the second node to the fifth node under the control of the signals of the first node, the third node, and the first control signal terminal to the third control signal terminal;

[0246] The scan output sub-circuit outputs the signal of the first power supply terminal or the second power supply terminal to the scan signal output terminal under the control of the signals of the fourth node and the fifth node.

[0247] The shift register is the shift register provided by any of the foregoing embodiments, and the implementation principle and implementation effect are similar, which will not be elaborated here.

[0248] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0249] For clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and dimensions of layers or microstructures are enlarged. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or intervening elements may be present.

[0250] Although the embodiments disclosed in the present disclosure are as described above, the above content is only an embodiment adopted for the convenience of understanding the present disclosure and is not intended to limit the present disclosure. Any person skilled in the art within the scope of the present disclosure may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present disclosure. However, the scope of patent protection of the present disclosure shall still be subject to the scope defined by the appended claims.

Claims

1. A shift register, characterized in that, Including: A cascaded output sub-circuit, an output control sub-circuit, and a scan output sub-circuit; The cascaded output sub-circuit is respectively electrically connected to an input end, a first clock signal end, a second clock signal end, a first power supply end, a second power supply end, a cascaded output end, a first node, a second node, and a third node, and is configured to provide the signal of the first power supply end or the second power supply end to the cascaded output end under the control of the signals of the input end, the first clock signal end, the second clock signal end, the first node, the second node, and the third node; The output control sub-circuit is respectively electrically connected to a first control signal end to a third control signal end, the first node, the second node, the third node, a fourth node, and a fifth node, and is configured to provide the signal of the first node to the fourth node and the signal of the second node to the fifth node under the control of the signals of the first node, the third node, and the first control signal end to the third control signal end; The scan output sub-circuit is respectively electrically connected to the fourth node, the fifth node, a scan signal output end, the first power supply end, and the second power supply end, and is configured to output the signal of the first power supply end or the second power supply end to the scan signal output end under the control of the signals of the fourth node and the fifth node.

2. The shift register according to claim 1, characterized in that The output control sub-circuit includes: a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit; The first control sub-circuit is respectively electrically connected to the first node, the third node, a sixth node, and the first control signal end to the third control signal end, and is configured to provide the signal of the second control signal end or the third control signal end to the sixth node under the control of the signals of the first node, the third node, and the first control signal end; The second control sub-circuit is respectively electrically connected to the first node, the fourth node, and the sixth node, and is configured to provide the signal of the first node to the fourth node under the control of the signal of the sixth node; The third control sub-circuit is respectively electrically connected to the second node, the fifth node, and the sixth node, and is configured to provide the signal of the second node to the fifth node under the control of the signal of the sixth node.

3. The shift register according to claim 2, wherein The first control sub-circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; The control electrode of the first transistor is electrically connected to the first control signal end, the first pole of the first transistor is electrically connected to the second pole of the second transistor, and the second pole of the first transistor is electrically connected to the third control signal end; The control electrode of the second transistor is electrically connected to the third node, and the first pole of the second transistor is electrically connected to the sixth node; The control electrode of the third transistor is electrically connected to the first control signal end, the first pole of the third transistor is electrically connected to the second control signal end, and the second pole of the third transistor is electrically connected to the first pole of the fourth transistor; The control electrode of the fourth transistor is electrically connected to the first node, and the second pole of the fourth transistor is electrically connected to the sixth node.

4. The shift register according to claim 2, characterized in that, The second control sub-circuit includes: a fifth transistor; The control electrode of the fifth transistor is electrically connected to the sixth node, the first pole of the fifth transistor is electrically connected to the first node, and the second pole of the fifth transistor is electrically connected to the fourth node.

5. The shift register according to claim 2, characterized in that, The third control sub-circuit includes: a sixth transistor; The control electrode of the sixth transistor is electrically connected to the sixth node, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the fifth node.

6. The shift register according to claim 2, wherein The output control sub-circuit further includes: a storage sub-circuit; The storage sub-circuit, which is electrically connected to the fourth node and the sixth node respectively, is configured to store the voltage difference between the signals of the sixth node and the fourth node.

7. The shift register according to claim 6, wherein The storage sub-circuit includes: a first capacitor, and the first capacitor includes a first electrode plate and a second electrode plate; The first electrode plate of the first capacitor is electrically connected to the sixth node, and the second electrode plate of the first capacitor is electrically connected to the fourth node.

8. The shift register according to claim 1, wherein The scan output sub-circuit includes: a seventh transistor and an eighth transistor; The control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode of the seventh transistor is electrically connected to the first power supply terminal, and the second electrode of the seventh transistor is electrically connected to the scan signal output terminal; The control electrode of the eighth transistor is electrically connected to the fifth node, the first electrode of the eighth transistor is electrically connected to the scan signal output terminal, and the second electrode of the eighth transistor is electrically connected to the second power supply terminal.

9. The shift register according to claim 8, wherein The scan output sub-circuit further includes: a second capacitor, and the second capacitor includes a first electrode plate and a second electrode plate; The first electrode plate of the second capacitor is electrically connected to the fourth node, and the second electrode plate of the second capacitor is electrically connected to the first power supply terminal.

10. The shift register according to claim 1, characterized in that, The cascaded output sub-circuit includes: a ninth transistor to a twenty-fifth transistor, and a third capacitor to a sixth capacitor; The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth transistor is electrically connected to the cascaded output terminal; The control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the cascaded output terminal; The control electrode of the eleventh transistor is electrically connected to the second power supply terminal, the first electrode of the eleventh transistor is electrically connected to the seventh node, and the second electrode of the eleventh transistor is electrically connected to the ninth node; The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the second node, and the second electrode of the twelfth transistor is electrically connected to the third node; The control electrode of the thirteenth transistor is electrically connected to the third power supply terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the second node; The control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the input terminal, and the second electrode of the fourteenth transistor is electrically connected to the eighth node; The control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, the first electrode of the fifteenth transistor is electrically connected to the eighth node, and the second electrode of the fifteenth transistor is electrically connected to the twelfth node; The control electrode of the sixteenth transistor is electrically connected to the twelfth node, the first electrode of the sixteenth transistor is electrically connected to the third node, and the second electrode of the sixteenth transistor is electrically connected to the twelfth node; The control electrode of the seventeenth transistor is electrically connected to the first clock signal terminal, the first electrode of the seventeenth transistor is electrically connected to the input terminal, and the second electrode of the seventeenth transistor is electrically connected to the second node; The control electrode of the eighteenth transistor is electrically connected to the second node, the first electrode of the eighteenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the eighteenth transistor is electrically connected to the seventh node; The control electrode of the nineteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the nineteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the nineteenth transistor is electrically connected to the seventh node; The control electrode of the twentieth transistor is electrically connected to the second node, the first electrode of the twentieth transistor is electrically connected to the second clock signal terminal, and the second electrode of the twentieth transistor is electrically connected to the eleventh node; The control electrode of the twenty-first transistor is electrically connected to the seventh node, the first electrode of the twenty-first transistor is electrically connected to the first power supply terminal, and the second electrode of the twenty-first transistor is electrically connected to the eleventh node; The control electrode of the twenty-second transistor is electrically connected to the ninth node, the first electrode of the twenty-second transistor is electrically connected to the second clock signal terminal, and the second electrode of the twenty-second transistor is electrically connected to the tenth node; The control electrode of the twenty-third transistor is electrically connected to the second clock signal terminal, the first electrode of the twenty-third transistor is electrically connected to the tenth node, and the second electrode of the twenty-third transistor is electrically connected to the first node; The control electrode of the twenty-fourth transistor is electrically connected to the second node, the first electrode of the twenty-fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the twenty-fourth transistor is electrically connected to the first node; The control electrode of the twenty-fifth transistor is electrically connected to the twelfth node, the first electrode of the twenty-fifth transistor is electrically connected to the twelfth node, and the second electrode of the twenty-fifth transistor is electrically connected to the fifth node; The third capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the third capacitor is electrically connected to the third node, and the second electrode plate of the third capacitor is electrically connected to the eleventh node; The fourth capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the fourth capacitor is electrically connected to the second power supply terminal, and the second electrode plate of the fourth capacitor is electrically connected to the cascaded output terminal; The fifth capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the fifth capacitor is electrically connected to the ninth node, and the second electrode plate of the fifth capacitor is electrically connected to the tenth node; The sixth capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the sixth capacitor is electrically connected to the first node, and the second electrode plate of the sixth capacitor is electrically connected to the first power supply terminal.

11. The shift register according to claim 1, characterized in that, The cascaded output sub-circuit includes: the ninth transistor to the twenty-fifth transistor, the third capacitor to the sixth capacitor. The output control sub-circuit includes: the first transistor to the sixth transistor and the first capacitor. The scan output sub-circuit includes: the seventh transistor, the eighth transistor and the second capacitor; The control electrode of the first transistor is electrically connected to the first control signal terminal, the first electrode of the first transistor is electrically connected to the second electrode of the second transistor, and the second electrode of the first transistor is electrically connected to the third control signal terminal; The control electrode of the second transistor is electrically connected to the third node, and the first electrode of the second transistor is electrically connected to the sixth node; The control electrode of the third transistor is electrically connected to the first control signal terminal, the first electrode of the third transistor is electrically connected to the second control signal terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the fourth transistor; The control electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the sixth node; The control electrode of the fifth transistor is electrically connected to the sixth node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the fourth node; The control electrode of the sixth transistor is electrically connected to the sixth node, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the fifth node; The control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode of the seventh transistor is electrically connected to the first power supply terminal, and the second electrode of the seventh transistor is electrically connected to the scan signal output terminal; The control electrode of the eighth transistor is electrically connected to the fifth node, the first electrode of the eighth transistor is electrically connected to the scan signal output terminal, and the second electrode of the eighth transistor is electrically connected to the second power supply terminal; The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth transistor is electrically connected to the cascade output terminal; The control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the cascade output terminal; The control electrode of the eleventh transistor is electrically connected to the second power supply terminal, the first electrode of the eleventh transistor is electrically connected to the seventh node, and the second electrode of the eleventh transistor is electrically connected to the ninth node; The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the second node, and the second electrode of the twelfth transistor is electrically connected to the third node; The control electrode of the thirteenth transistor is electrically connected to the third power supply terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the second node; The control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the input terminal, and the second electrode of the fourteenth transistor is electrically connected to the eighth node; The control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, the first electrode of the fifteenth transistor is electrically connected to the eighth node, and the second electrode of the fifteenth transistor is electrically connected to the twelfth node; The control electrode of the sixteenth transistor is electrically connected to the twelfth node, the first electrode of the sixteenth transistor is electrically connected to the third node, and the second electrode of the sixteenth transistor is electrically connected to the twelfth node; The control electrode of the seventeenth transistor is electrically connected to the first clock signal terminal, the first electrode of the seventeenth transistor is electrically connected to the input terminal, and the second electrode of the seventeenth transistor is electrically connected to the second node; The control electrode of the eighteenth transistor is electrically connected to the second node, the first electrode of the eighteenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the eighteenth transistor is electrically connected to the seventh node; The control electrode of the nineteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the nineteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the nineteenth transistor is electrically connected to the seventh node; The control electrode of the twentieth transistor is electrically connected to the second node, the first electrode of the twentieth transistor is electrically connected to the second clock signal terminal, and the second electrode of the twentieth transistor is electrically connected to the eleventh node; The control electrode of the twenty-first transistor is electrically connected to the seventh node, the first electrode of the twenty-first transistor is electrically connected to the first power supply terminal, and the second electrode of the twenty-first transistor is electrically connected to the eleventh node; The control electrode of the twenty-second transistor is electrically connected to the ninth node, the first electrode of the twenty-second transistor is electrically connected to the second clock signal terminal, and the second electrode of the twenty-second transistor is electrically connected to the tenth node; The control electrode of the twenty-third transistor is electrically connected to the second clock signal terminal, the first electrode of the twenty-third transistor is electrically connected to the tenth node, and the second electrode of the twenty-third transistor is electrically connected to the first node; The control electrode of the twenty-fourth transistor is electrically connected to the second node, the first electrode of the twenty-fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the twenty-fourth transistor is electrically connected to the first node; The control electrode of the twenty-fifth transistor is electrically connected to the twelfth node, the first electrode of the twenty-fifth transistor is electrically connected to the twelfth node, and the second electrode of the twenty-fifth transistor is electrically connected to the fifth node; The first capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the first capacitor is electrically connected to the sixth node, and the second electrode plate of the first capacitor is electrically connected to the fourth node; The second capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the second capacitor is electrically connected to the fourth node, and the second electrode plate of the second capacitor is electrically connected to the first power supply terminal; The third capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the third capacitor is electrically connected to the third node, and the second electrode plate of the third capacitor is electrically connected to the eleventh node; The fourth capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the fourth capacitor is electrically connected to the second power supply terminal, and the second electrode plate of the fourth capacitor is electrically connected to the cascaded output terminal; The fifth capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the fifth capacitor is electrically connected to the ninth node, and the second electrode plate of the fifth capacitor is electrically connected to the tenth node; The sixth capacitor includes a first electrode plate and a second electrode plate. The first electrode plate of the sixth capacitor is electrically connected to the first node, and the second electrode plate of the sixth capacitor is electrically connected to the first power supply terminal.

12. The shift register according to claim 1, wherein The shift register is disposed on a display substrate. The display substrate includes: a plurality of scan signal lines. The working process of the display substrate includes: a display stage and a blank stage located between the display stages; the display substrate includes: a plurality of display areas. The refresh frequencies of different display areas include a first refresh frequency and a second refresh frequency, and the first refresh frequency is greater than the second refresh frequency; When the signal of the first control signal terminal is a low-level signal in a state where the working process of the display substrate is a blank stage, the signals of the second control signal terminal and the third control signal terminal are low-level signals; When the signal of the first control signal terminal is a low-level signal in a state where the working process of the display substrate is a display stage and the shift register is connected to the scan signal line of the display area with the first refresh frequency, the signals of the second control signal terminal and the third control signal terminal are low-level signals; When the display substrate is in the display stage, the shift register is connected to the scan signal lines in the display area at the second refresh frequency, and the cascaded output terminal of the shift register outputs a low-level signal, when the signal at the first control signal terminal is a low-level signal, the signal at the second control signal terminal is a high-level signal, and the signal at the third control signal terminal is a low-level signal; When the display substrate is in the display stage, the shift register is connected to the scan signal lines in the display area at the second refresh frequency, and the cascaded output terminal of the shift register outputs a high-level signal, when the signal at the first control signal terminal is a low-level signal, the signal at the second control signal terminal is a high-level signal, and the signal at the third control signal terminal is a low-level signal; When the display substrate is in the display stage, the shift register is connected to the scan signal lines in the display area at the second refresh frequency, and the cascaded output terminal of the shift register outputs a low-level signal, when the signal at the first control signal terminal is a low-level signal, the signal at the second control signal terminal is a high-level signal, and the signal at the third control signal terminal is a low-level signal; The duration of the signal at the first control signal terminal being a low-level signal is less than the duration of the signal at any one of the second control signal terminal and the third control signal terminal being a low-level signal.

13. A gate driving circuit, characterized in that, Comprising: A plurality of cascaded shift registers as described in any one of claims 1 to 12; The cascaded output terminal of the i-th stage shift register is electrically connected to the input terminal of the (i + 1)-th stage shift register, where 1 ≤ i ≤ M - 1, and M is the total number of stages of the shift register.

14. A driving method for a shift register, characterized in that, Configured to drive the shift register as described in any one of claims 1 to 12, the method comprising: The cascaded output sub-circuit provides the signal of the first power supply terminal or the second power supply terminal to the cascaded output terminal under the control of the signals at the input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the second node, and the third node; The output control sub-circuit provides the signal of the first node to the fourth node and the signal of the second node to the fifth node under the control of the signals at the first node, the third node, and the first control signal terminal to the third control signal terminal; The scan output sub-circuit outputs the signal of the first power supply terminal or the second power supply terminal to the scan signal output terminal under the control of the signals at the fourth node and the fifth node.

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