Pixel luminance of a digital display

Abstract

A digital display includes a plurality of rows of pixels. For each row of pixels, the digital display includes an EM gate driver configured to provide a brightness control signal to the row of pixels during each of a plurality of image frames. A brightness controller is configured to instruct the EM gate driver to provide a pulse width modulated signal to the plurality of rows of pixels. On the same or different image frames, some rows of pixels are provided with a pulse width modulated signal that starts with a turn-on pulse, while some rows of pixels are provided with a pulse width modulated signal that starts with a turn-off pulse.

Description

Background Technology

[0001] A digital display consists of multiple pixels that can be controlled individually. The overall luminous intensity of the displayed image depends on the brightness of each individual pixel of the display.

[0002] Overview

[0003] This disclosure is provided to introduce, in a simplified form, a selection of concepts also described in the detailed description. This disclosure is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Furthermore, the claimed subject matter is not limited to the implementation of solutions to any or all the shortcomings mentioned in any part of this disclosure.

[0004] The digital display includes multiple rows of pixels. For each row of pixels, the digital display includes an EM gate driver configured to provide a brightness control signal to that row of pixels during each of multiple image frames. A brightness controller is configured to instruct the EM gate driver to provide pulse-width modulation (PWM) signals to the multiple rows of pixels. On the same or different image frames, some rows of pixels are provided with PWM signals that begin with a turn-on pulse, while others are provided with PWM signals that begin with a turn-off pulse.

[0005] Therefore, a digital display is provided according to each of the independent claims. Advantageous features are provided according to the dependent claims. Brief description of the attached diagram

[0007] Figure 1 An example digital display system is illustrated schematically.

[0008] Figure 2 schematically shown Figure 1 An example of a digital display system with multiple pixels.

[0009] Figure 3A and Figure 3B This illustrates the relationship between the pulse width modulation signal provided to the pixel row and different display refresh rates of the digital display.

[0010] Figure 4 The illustration schematically illustrates the provision of pulse width modulation signals to a first plurality of pixel rows and a second plurality of pixel rows.

[0011] Figure 5 The schematic depiction provides Figure 4 The pulse width modulation signal of the pixel row.

[0012] Figure 6 The illustration schematically demonstrates the provision of pulse width modulation signals to the pixel row during the first and second image frames.

[0013] Figure 7 The illustration schematically illustrates the provision of pulse width modulation signals to a first plurality of pixel rows and a second plurality of pixel rows during the first and second image frames.

[0014] Figure 8 An example computing system is illustrated schematically.

[0015] Detailed description

[0016] When controlling the brightness of a digital display, reducing the voltage supplied to the display pixels can reduce pixel brightness, and thus reduce the overall luminous intensity of the displayed image. The brightness of the display can be advantageously controlled by controlling the duty cycle of the pulse-width modulation (PWM) signal. For example, reducing brightness may be desirable when trying to save power or when ambient light levels are low; increasing brightness may be desirable when ambient light levels are high or when the device is plugged in and not relying on battery power. To some extent, brightness can be controlled by changing the pixel voltage amplitude. However, there is usually a lower limit beyond which reducing the pixel voltage will lead to inconsistent or unstable performance. To address this issue, instead of reducing the pixel voltage amplitude, the luminous intensity of the displayed image can be reduced by driving the pixels with a PWM signal. This causes the pixels to cycle rapidly between on and off, thereby reducing the total amount of light emitted or transmitted by the pixels during a given time interval (e.g., one image frame). The PWM signal can be driven at a sufficiently high frequency that the on / off cycling of the pixels is imperceptible to the human eye.

[0017] However, using pulse-width modulation (PWM) signals to control display brightness can cause problems in some scenarios. Specifically, the rate at which image frames are updated on a digital display is called the display refresh rate. The frequency of the PWM signal is typically set higher than the display refresh rate, resulting in multiple pixel on / off cycles occurring during each image frame. Problems can arise when the PWM signal is a non-integer multiple of the display refresh rate. For example, at some refresh rates, some image frames may end up with more PWM-modulated on pulses than off pulses. This can lead to a significant increase in the brightness of the displayed image compared to different refresh rates where the same number of on and off pulses occur per frame. For other refresh rates, the opposite problem may occur—that is, a significant decrease in brightness when an image frame contains more off pulses than on pulses.

[0018] This can be particularly true when digital displays use variable refresh rates. Depending on the type of content presented on the digital display, there are situations where the display's refresh rate may need to be changed. For example, a variable refresh rate can be used when a digital display is presenting visual content for a video game application, which outputs image frames at different rates depending on the current complexity of the scene. As another example, some display devices can be configured to dynamically change their refresh rate to save power—for instance, the refresh rate may decrease when the device's battery is depleted or when the device enters a "power-saving" mode. In any case, when the pixels of a display device are driven with pulse-width modulation signals and a variable refresh rate is used, the digital display can switch between different refresh rates, resulting in a noticeable increase or decrease in the brightness of the displayed image.

[0019] Therefore, this disclosure relates to techniques for using pulse-width modulation (PWM) signals to drive pixels of a digital display in a manner that mitigates or alleviates the aforementioned flicker problem. In one example, mitigation is achieved via spatial averaging, wherein a PWM signal having an opposite phase to the other half of the pixel rows (e.g., odd-numbered rows) is provided to one half of the pixel rows of the digital display. Thus, during image frames where the frequency of the PWM signal is a non-integer multiple of the refresh rate, one half of the pixel rows will have a relatively high luminous intensity, while the other half will have a relatively low luminous intensity. Through spatial averaging, the display can appear to have a relatively uniform brightness to a human viewer.

[0020] In another example, temporal averaging can be used in addition to, or as an alternative to, spatial averaging. In other words, for the first image frame, a pulse-width modulated (PWM) signal starting with a turn-on pulse can be provided to some or all of the pixel rows of the digital display. Then, during subsequent image frames, a PWM signal starting with a turn-off pulse can be provided to the same pixel rows. Thus, while some frames may have relatively higher luminous intensity than others, the frame refresh rate is fast enough that a human user perceives the displayed image as substantially uniform in brightness. Therefore, by using PWM signals with opposite phases, and through one or both spatial and temporal averaging, the display device can present image frames with reduced brightness while avoiding undesirable flickering effects.

[0021] Figure 1 An example digital display system 100, including a display 102, is schematically shown. Figure 1In this system, display system 100 displays visual content 104 based on input received from image source 106. Specifically, display controller 108 controls a plurality of pixels 110 of the digital display to form consecutive image frames depicting the visual content. For each image frame, the display controller controls each pixel to influence the color of the light emitted or transmitted by the pixel and form the image frame specified by image source 106. The visual content presented by the digital display can be updated at any suitable fixed or variable refresh rate. As an example, refresh rates of 30 frames per second (FPS), 60 FPS, or 120 FPS can be used. The brightness of the pixels of the display can also be controlled to increase or decrease the total luminous intensity of the displayed image. It is worth noting that the display brightness can be controlled independently of the color values ​​of individual pixels—in other words, even when displaying a static image, the display brightness can be controlled to increase or decrease the total amount of light emitted or transmitted by the pixels of the display.

[0022] Digital display systems, image sources, and display controllers can all take any suitable form. As non-limiting examples, digital displays can take the form of televisions, computer monitors, smartphones, tablets, laptops, smartwatch displays, or mixed reality displays. In some examples, digital displays can be touch-sensitive displays. Although in Figure 1 In this context, the digital display system includes only one display 102, but in some cases, it may include two or more displays—for example, with a fixed spatial relationship or arranged in a movable or foldable configuration. In such cases, the brightness control techniques described herein can be applied to any or all displays of the digital display system.

[0023] Digital display systems can use any suitable display technology—as an example, a digital display could be an organic light-emitting diode (OLED) display. As another example, a digital display could be a micro-LED display or a quantum dot light-emitting diode (QLED) display. In some examples, non-LED-based technologies can be used—for example, a digital display could be a liquid crystal display (LCD). In any case, a digital display can have any suitable pixel resolution, and the pixels of a digital display can be configured to support any suitable range of color values.

[0024] A digital display can present image frames based on input from any suitable image source. Image source 106 can be integrated internally or externally to the digital display system 100. Generally, image source 106 can take the form of computer logic configured to render image frames for display. As a non-limiting example, this can include rendering visual content from an operating system installed on the digital display system 100 or a separate computing system; rendering visual content from software applications such as video games, internet browsers, word processors, etc.; or decoding data representing a sequence of video frames from a still image file or video file.

[0025] Similarly, the display controller 108 can take the form of any suitable computer processor or other computer logic, configured to receive multiple image frames from the image source 106 and control the pixels 110 of the digital display to render the image frames for viewing. As discussed above, the display controller can be configured to update the display of visual content on the digital display at the display refresh rate. In some cases, the display controller can be further configured to dynamically change the display refresh rate—for example, based on the image content received from the image source, or based on the current power requirements of the digital display system.

[0026] Generally speaking, digital display systems, image controllers, and display controllers can all have any suitable capabilities, hardware configurations, and form factors.

[0027] Figure 2 Multiple pixels 200 are schematically shown. Pixels 200 can be, for example... Figure 1 A subset of pixels in a digital display system such as 100. Figure 2 In this configuration, pixels 200 are arranged in a grid comprising six rows and ten columns, with the pixel rows labeled as rows 202A-202F. However, it should be understood that this is not limiting, and the digital display may include any number of pixels arranged in any number of rows and columns.

[0028] exist Figure 2 In this digital display, the pixel rows are divided into two distinct groups. The first plurality of pixel rows, each comprising one or more pixels, include rows 202A, 202C, and 202E. The second plurality of pixel rows, 202B, 202D, and 202F, also each comprise one or more pixels and interweave with the first plurality of pixel rows. Figure 2 In the diagram, the second plurality of pixel rows are represented by a dot-filled pattern to visually distinguish them from the first plurality of pixel rows. However, it should be understood that the distinction between the first and second plurality of pixel rows is arbitrary, and in other examples, the rows of a digital display may be divided in different ways.

[0029] It is worth noting that this disclosure focuses primarily on controlling pixel rows. However, in other examples, pixels can be controlled by column rather than row, or the brightness of each pixel of a digital display can be controlled individually.

[0030] exist Figure 2 In this digital display, each row of pixels is controlled by a corresponding electromagnetic (EM) gate driver 204, including drivers 204A-204F. In other words, the digital display includes an EM gate driver configured to provide a brightness control signal to the pixel row during each of a plurality of image frames, for each of a first plurality of pixel rows and a second plurality of pixel rows. Therefore, during each image frame, the EM gate driver 204A controls the brightness of each pixel in the pixel row 202A.

[0031] It's important to note that pixel brightness refers to the amount of light emitted or transmitted by each pixel during any given image frame, and it can be set independently of the pixel's color value. In other words, by setting the brightness of individual pixels (or rows of pixels), the amount of light emitted by a digital display can be controlled—for example, increasing or decreasing the display's apparent brightness, regardless of the current image content. Pixel brightness can be set at any suitable granularity.

[0032] Both the EM gate driver and the brightness control signal can take any suitable form. In some examples, the EM gate driver can be in the form of a power amplifier that accepts a low-level input from the brightness controller 206 and amplifies the current used to drive each row of pixels. The "brightness control signal" refers to the electrical signal output by the EM gate driver and received by each row of pixels. In some cases, the brightness control signal can be a pulse-width modulated signal that causes each pixel to cycle on and off multiple times during each image frame, as will be discussed in more detail below.

[0033] The brightness controller 206 can take the form of any suitable computer logic configured to control the brightness of the pixels of the display device. As shown, the brightness controller is communicatively coupled to each of the plurality of EM gate drivers. Therefore, the brightness controller can instruct each EM gate driver to provide different brightness control signals to the respective pixel rows to globally affect the luminous intensity of the entire digital display. For example, the luminous intensity of the display can be reduced in response to low ambient light levels and / or for any other suitable reason to save device power.

[0034] As discussed above, the overall brightness of a display can be altered by changing the parameters of the pulse width modulation signal supplied to the pixel rows. For example, the duty cycle can be reduced to decrease the amount of light emitted or transmitted by each pixel within a specific time interval, thereby reducing the total amount of light emitted by the display during that time interval.

[0035] Figure 3A and Figure 3B An example pulse width modulation signal is illustrated schematically. Specifically, Figure 3A Includes graph 300A, depicting the pulse width modulation signal 302 during the F1-F4 sequence of image frames. In this example, the frequency of the pulse width modulation signal is an integer multiple of the display refresh rate. In other words, four pulse width modulation signal pulses (two on pulses and two off pulses) occur during each image frame, meaning the pulse width modulation signal is 4x the display refresh rate. As an example, the display refresh rate could be 60Hz, and the frequency of the pulse width modulation signal could be 240Hz. However, it should be understood that any suitable rate can be used.

[0036] In comparison, Figure 3B Different graphs 300B depicting the same pulse width modulation signal 302 are shown. Figure 3B In this case, the display refresh rate increases, resulting in shorter durations for each image frame. This is achieved without changing the frequency of the pulse width modulation (PWM) signal—in other words, at the beginning of each image frame, the PWM signal still begins with a turn-on pulse followed by a cut-off pulse, each lasting the same amount of time as the pulses shown in graph 300A. However, because the display refresh rate has changed, the frequency of the PWM signal is now a non-integer multiple of the display refresh rate. Therefore, in each image frame, there is not enough time for the entire subsequent turn-on pulse before the frame ends and after the cut-off pulse. Instead, each image frame ends with a partial turn-on pulse, and the PWM signal is reset at the beginning of the next image frame. Due to the relationship between the new display refresh rate and the unchanged frequency of the PWM signal, and the fact that the PWM signal is reset with a new turn-on pulse at the beginning of each frame, this has the effect of causing each pixel to spend more time in the turn-on state rather than in the cut-off state during each frame. However, in other examples, the PWM signal does not need to rest at the beginning of each image frame and can continue independently of the image frame timing.

[0037] exist Figure 3BIn the example, during each image frame, more overall light is emitted compared to curve 300A because each pixel is on for a longer period than it is off. This results in the undesirable flickering effect described above. In other words, as the display refresh rate increases from the rate shown in curve 300A to the rate shown in curve 300B, any viewer of a digital display can perceive an increase in apparent brightness. For other display refresh rates, the opposite effect may occur—that is, pixels may be off for a longer period than they are on during each frame, resulting in a decrease in apparent brightness. Therefore, when the display refresh rate changes repeatedly over time (e.g., to match the output of a video game application), viewers of a digital display may perceive repeated increases and decreases in apparent brightness, leading to an unsatisfactory viewing experience.

[0038] Therefore, in some cases, the brightness controller can enable the provision of pulse width modulation signals with opposite phases to different pixel rows on the same or different image frames. Figure 4 An example implementation is shown where spatial averaging is used. Specifically, Figure 4 Pixel 200 is shown again, this time including only the first pixel of each row 202A-202F. As shown, the brightness controller 206 instructs the EM gate drivers of the first plurality of pixel rows (including rows 202A, 202C, and 202E) to provide a pulse width modulation signal 400A to the pixel rows. As discussed above, the pulse width modulation signal can be modulated between high and low voltages, and in some cases, such modulation can occur more than once per image frame. To simplify the illustration, Figure 4 And other figures in this disclosure use the label “PWM+” to indicate that the pulse width modulation signal for a particular frame begins with a turn-on pulse (i.e., high voltage). For example... Figure 4 As shown, the brightness controller 206 instructs the EM gate drivers of the second plurality of rows (including rows 202B, 202D and 202F) to provide a pulse width modulation signal 400B, which begins with a cutoff pulse, to the pixel row. Figure 4 Other figures in this disclosure use the label “PWM-” to indicate that the pulse width modulation signal for a particular frame begins with a cutoff pulse (i.e., low voltage).

[0039] Although Figure 4Only six rows are depicted, but it should be understood that virtually all pixel rows of a digital display can be divided into interleaved first and second plurality of pixel rows, each provided with PWM+ and PWM- respectively. In other words, the first plurality of pixel rows can include all pixel rows satisfying (2×r)+1, where r is an integer starting from zero and incrementing every two rows. Conversely, the second plurality of pixel rows can include all pixel rows satisfying (2×r). Therefore, the first plurality of pixel rows can include the first row (r=0), the third row (r=1), the fifth row (r=2), and so on. Similarly, the second plurality of pixel rows can include the second row (r=1), the fourth row (r=2), the sixth row (r=3), and so on. In other words, the first plurality of rows can include all odd-numbered rows, while the second plurality of rows can include all even-numbered rows.

[0040] In other embodiments, pixel rows can be divided differently. For example, groups of two, three, or more adjacent rows can be interleaved. Furthermore, irregular interleaving patterns can be used in some cases. In other words, the second or more rows can be interleaved with the first or more rows using any pattern. For example, PWM+ can be provided to the first pixel row and PWM- to the second pixel row, PWM+ can be provided to the third and fourth pixel rows respectively, and PWM- to the fifth and sixth rows respectively, and so on. Generally, any suitable interleaving pattern can be used, as long as it enables the display of an image that appears to have substantially uniform brightness to a human viewer.

[0041] Figure 5 The schematic depiction provides Figure 4 An example representation of the pulse width modulation signal for a pixel row. Specifically, compared to the duration of a series of image frames F1-F6, Figure 5 This includes graph 500A depicting PWM+400A and graph 500B depicting PWM-400B. As shown, PWM+ starts with a turn-on pulse, while PWM- starts with a turn-off pulse, meaning the two signals are out of phase.

[0042] In this example, the frequency of the pulse width modulation signal is again a non-integer multiple of the display refresh rate. Therefore, as... Figure 3B Similar to the curve in 300B, PWM+ causes each pixel to spend more time on- than off during each image frame. However, because PWM+ and PWM- have opposite phases, PWM- causes each pixel to spend more time off than on during each image frame. It should be understood that... Figure 5 The specific display refresh rate and pulse width modulation signal frequency depicted are non-limiting examples, and any suitable rate and signal frequency can be used.

[0043] Using pulse width modulation signals with opposite phases (such as...) Figure 5The signals described above can help mitigate unwanted flicker associated with variable display refresh rates. Briefly returning to... Figure 4 The system provides PWM+ to the first plurality of pixel rows and PWM- to the second plurality of pixel rows. This way, when the frequency of the pulse width modulation signal is a non-integer multiple of the current display refresh rate, half of the pixel rows (e.g., corresponding to the first plurality of pixel rows) can emit more overall light per image frame. However, because the other half of the pixel rows (e.g., the second plurality of pixel rows) are provided with pulse width modulation signals with opposite phase, these pixel rows emit relatively less light per image frame. Since individual pixel rows are typically too small for the human eye to distinguish at normal viewing distances, any flicker caused by the changing refresh rate, if not completely imperceptible, is reduced when the PWM+ rows and PWM- rows are interleaved.

[0044] In some examples, time averaging can be used in addition to spatial averaging or as an alternative to spatial averaging. Figure 6 An example of this is illustrated in the diagram. Figure 6 The different pulse width modulation signals supplied to the first pixels of pixel rows 202A-202F are schematically depicted again. Although Figure 6 and 7 The brightness controller and EM gate driver are omitted, but it should be understood that each pixel row is communicatively coupled to a corresponding EM gate driver, which is instructed by the brightness controller to provide a pulse width modulation (PWM) signal to its pixel row. In this example, PWM+ is provided to all pixel rows on the first image frame F1. During the second image frame F2, PWM- is provided to all pixel rows. This pattern can be repeated for subsequent image frames—that is, PWM+ can be provided to pixel rows again during image frame F3, and PWM- can be provided to pixel rows again during frame F4. In other words, image frames can be divided into a first plurality of image frames and a second plurality of image frames interleaved with the first plurality of image frames. Depending on whether the current image frame is a first plurality of image frames or a second plurality of image frames, PWM signals starting with different polarities can be provided to any or all pixel rows of the digital display.

[0045] In one example, the brightness controller instructs the EM gate drivers of multiple pixel rows to provide a pulse width modulation (PWM) signal starting with a turn-on pulse for all image frames satisfying (2×t)+1, where t is an integer starting from zero and incrementing every two image frames. Conversely, the brightness controller can instruct the EM gate drivers of multiple pixel rows to provide a PWM signal starting with a cut-off pulse for all image frames satisfying (2×t). Thus, PWM+ can be provided to pixel rows on the first image frame (t=0), the third image frame (t=1), the fifth image frame (t=2), etc. Similarly, PWM- can be provided to pixel rows on the second image frame (t=1), the fourth image frame (t=2), the sixth image frame (t=3), etc. For example, PWM+ can be provided to pixel rows on odd-numbered frames and PWM- can be provided on even-numbered frames, or vice versa.

[0046] However, in other embodiments, frames can be divided differently. For example, groups of two, three, or more consecutive frames can be interleaved. Alternatively, irregular frame interleaving patterns can be used. In other words, a second plurality of image frames can be interleaved with the first plurality of image frames using any pattern. For example, PWM+ can be provided to all rows on the first frame, then PWM- to all rows on the second frame, PWB+ to all rows on the third and fourth frames, and PWM- to all rows on the fifth and sixth frames, and so on.

[0047] Similar to spatial averaging, any suitable interlacing mode can be used, as long as it can display an image that appears to have substantially uniform brightness to a human viewer.

[0048] As discussed above, when more pixel turn-on pulses occur than pixel cut-off pulses during each image frame, some display refresh rates can cause a significant increase in brightness, resulting in a net increase in light emitted per image frame. However, when using time averaging as described above, relatively less light will actually be emitted every other image frame because each pixel row is provided with PWM, resulting in more pixel cut-off pulses than turn-on pulses per image frame. When the refresh rate is high enough that a human viewer cannot distinguish between relatively bright and low-brightness image frames, the apparent brightness of the displayed image may not change. In other words, through time averaging, a viewer can perceive the displayed image as substantially uniform in brightness because the human visual system cannot individually distinguish image frames above a threshold refresh rate.

[0049] In some examples, spatial averaging and temporal averaging can be used together to further mitigate flicker caused by refresh rate variations. This is in Figure 7 The diagram illustrates that, Figure 7The different pulse width modulation signals provided to the first pixel of pixel rows 202A-202F during two different image frames F1 and F2 are schematically depicted again. Figure 4 Similarly, during the first image frame F1, PWM+ and PWM- are provided to the first and second plurality of pixel rows, respectively. During the second image frame F2, PWM- is provided to the first plurality of pixel rows, and PWM+ is provided to the second plurality of pixel rows. Thus, during each image frame, half of the pixel rows are provided with pulse width modulation signals having opposite phases to the other half of the pixel rows, thereby providing spatial averaging. Furthermore, for each new image frame, each pixel row is provided with a pulse width modulation signal having opposite phases to the previous image frame, thereby providing temporal averaging. In other words, both the pixel rows and the image frames can be divided into interleaved first and second groups.

[0050] In one example, the brightness controller may instruct the EM gate drivers of a first plurality of pixel rows (2×r)+1 to provide a pulse width modulation (PWM) signal starting with a turn-on pulse during image frame (2×t)+1, and instruct the EM gate drivers of a second plurality of pixel rows (2×r) to provide a PWM signal starting with a turn-off pulse. During image frame (2×t), the brightness controller instructs the EM gate drivers of the first plurality of pixel rows (2×r)+1 to provide a PWM signal starting with a turn-off pulse, and instructs the EM gate drivers of the second plurality of pixel rows (2×r) to provide a PWM signal starting with a turn-on pulse. However, as discussed above, any suitable interleaving mode can be used for either spatial averaging or temporal averaging. For example, the second plurality of rows can be interleaved with the first plurality of rows using any mode. Additionally or alternatively, the second plurality of image frames can be interleaved with the first plurality of image frames using any mode.

[0051] The methods and processes described herein can be attached to a computing system of one or more computing devices. Specifically, such methods and processes can be implemented as an executable computer application, a network-accessible computing service, an application programming interface (API), a library, or a combination of the above and / or other computing resources.

[0052] Figure 8 A simplified representation of a computing system 800 is schematically shown, which is configured to provide any and all of the computing functionalities described herein. Specifically, Figure 1The digital display system 100 can be implemented as a computing system 800. The computing system 800 can take the form of one or more personal computers, network-accessible server computers, digital display systems, tablet computers, home entertainment computers, gaming devices, mobile computing devices, mobile communication devices (e.g., smartphones), virtual / augmented / mixed reality computing devices, wearable computing devices, Internet of Things (IoT) devices, embedded computing devices, and / or other computing devices.

[0053] The computing system 800 includes a logic subsystem 802 and a storage subsystem 804. The computing system 800 may optionally include a display subsystem 806, an input subsystem 808, a communication subsystem 810, and / or... Figure 8 Other subsystems not shown in the diagram.

[0054] The logic subsystem 802 includes one or more physical devices configured to execute instructions. Any or all of the aforementioned display controller 108, image source 106, and brightness controller 206 can be implemented as logic subsystem 206. The logic subsystem can be configured to execute instructions as part of one or more applications, services, or other logical constructs. The logic subsystem may include one or more hardware processors configured to execute software instructions. Additionally or alternatively, the logic subsystem may include one or more hardware or firmware devices configured to execute hardware or firmware instructions. The processor of the logic subsystem may be single-core or multi-core, and the instructions executed thereon may be configured for serial, parallel, and / or distributed processing. Individual components of the logic subsystem may optionally be distributed among two or more separate devices, which may be located remotely and / or configured for collaborative processing. Aspects of the logic subsystem may be virtualized and executed by remotely accessible networked computing devices configured with cloud computing capabilities.

[0055] Storage subsystem 804 includes one or more physical devices configured to temporarily and / or permanently store computer information (such as data and instructions executable by the logical subsystem). When the storage subsystem includes two or more devices, these devices may coexist in one location and / or be located remotely. Storage subsystem 804 may include volatile, non-volatile, dynamic, static, read / write, read-only, random access, sequential access, location-addressable, file-addressable, and / or content-addressable devices. Storage subsystem 804 may include removable and / or built-in devices. The state of storage subsystem 804 may be transformed—for example, to hold different data—when the logical subsystem executes instructions.

[0056] Various aspects of the logic subsystem 802 and the storage subsystem 804 can be integrated together into one or more hardware logic components. Such hardware logic components may include, for example, application-specific integrated circuits (PASIC / ASIC), application-specific standard products (PSSP / ASSP), system-on-a-chip (SOC), and complex programmable logic devices (CPLD).

[0057] The logic subsystem and storage subsystem can collaborate to instantiate one or more logic machines. As used herein, the term machine is used uniformly to refer to a combination of hardware, firmware, software, instructions, and / or any other components that collaborate to provide computer functionality. In other words, "machine" is never an abstract concept but always has a tangible form. A machine can be instantiated by a single computing device, or a machine can include two or more sub-components instantiated by two or more different computing devices. In some implementations, a machine includes local components (e.g., software applications executed by a computer processor) that collaborate with remote components (e.g., cloud computing services provided by a network of server computers). The software and / or other instructions that give a particular machine its functionality may optionally be stored as one or more unexecuted modules on one or more suitable storage devices.

[0058] When included, display subsystem 806 can be used to present a visual representation of data held by storage subsystem 804. This visual representation may take the form of a graphical user interface (GUI). Display subsystem 806 may include one or more display devices utilizing substantially any type of technology. In some implementations, display subsystem may include one or more virtual reality, augmented reality, or mixed reality displays.

[0059] When including an input subsystem 808, the input subsystem 808 may include or be interfaced with one or more input devices. Input devices may include sensor devices or user input devices. Examples of user input devices include a keyboard, mouse, touchscreen, or game controller. In some embodiments, the input subsystem may include or be interfaced with selected Natural User Input (NUI) components. Such components may be integrated or peripheral, and the transduction and / or processing of input actions may be handled on-board or off-board. Example NUI components may include a microphone for speech and / or voice recognition; an infrared, color, stereo, and / or depth camera for machine vision and / or gesture recognition; and a head tracker, eye tracker, accelerometer, and / or gyroscope for motion detection and / or intent recognition.

[0060] When a communication subsystem 810 is included, the communication subsystem 810 can be configured to communicatively couple the computing system 800 to one or more other computing devices. The communication subsystem 810 may include wired and / or wireless communication devices compatible with one or more different communication protocols. The communication subsystem can be configured to communicate via personal networks, local area networks (LANs), and / or wide area networks (WANs).

[0061] This disclosure is presented by way of example and with reference to the associated accompanying drawings. Components, process steps, and other elements that may be substantially the same in one or more drawings are identified in a coordinated manner and described with minimal repetition. However, it should be noted that the elements identified in a coordinated manner may also differ to some extent. It should be further noted that some drawings may be schematic and not drawn to scale. Various drawing scales, aspect ratios, and numbers of components shown in the drawings may be intentionally distorted to make certain features or relationships easier to see.

[0062] In one example, a digital display includes: a first plurality of pixel rows, each comprising one or more pixels; a second plurality of pixel rows, each comprising one or more pixels, interleaved with the first plurality of pixel rows; for each of the first plurality of pixel rows and the second plurality of pixel rows, an electromagnetic EM gate driver is configured to provide a brightness control signal to the pixel row during each of a plurality of image frames; and a brightness controller configured to: instruct the EM gate drivers of the first plurality of pixel rows to provide a pulse width modulation signal starting with a turn-on pulse, and instruct the EM gate drivers of the second plurality of pixel rows to provide a pulse width modulation signal starting with a turn-off pulse. In this example or any other example, the digital display further includes: a display controller configured to update the display of visual content on the digital display at a display refresh rate. In this example or any other example, the frequency of the pulse width modulation signal is an integer multiple of the display refresh rate. In this example or any other example, the display controller is further configured to dynamically change the display refresh rate. In this example or any other example, for at least some of the plurality of image frames, the frequency of the pulse width modulation signal is a non-integer multiple of the display refresh rate. In this example or any other example, the digital display is an organic light-emitting diode (OLED) display or a quantum dot light-emitting diode (QLED) display. In this example or any other example, the digital display is a micro-LED display.

[0063] In one example, a digital display includes: a plurality of pixel rows, each comprising one or more pixels; for each of the plurality of pixel rows, an EM gate driver is configured to provide a brightness control signal to the pixel row during each of a first plurality of image frames and a second plurality of image frames interleaved with the first plurality of image frames; and a brightness controller configured to: for the first plurality of image frames, instruct the EM gate drivers of the plurality of pixel rows to provide a pulse width modulation signal starting with a turn-on pulse, and for the second plurality of image frames, instruct the EM gate drivers of the plurality of pixel rows to provide a pulse width modulation signal starting with a turn-off pulse. In this example or any other example, the digital display further includes a display controller configured to update the display of visual content on the digital display at a display refresh rate. In this example or any other example, the frequency of the pulse width modulation signal is an integer multiple of the display refresh rate. In this example or any other example, the display controller is further configured to dynamically change the display refresh rate. In this example or any other example, for at least some of the first plurality of image frames or the second plurality of image frames, the frequency of the pulse width modulation signal is a non-integer multiple of the display refresh rate. In this example or any other example, the digital display is an organic light-emitting diode (OLED) display or a quantum dot light-emitting diode (QLED) display. In this example or any other example, the digital display is a micro-LED display.

[0064] In one example, a digital display includes: a first plurality of pixel rows, each comprising one or more pixels; a second plurality of pixel rows, each comprising one or more pixels, interleaved with the first plurality of pixel rows; for each of the first plurality of pixel rows and the second plurality of pixel rows, an EM gate driver is configured to provide a brightness control signal to the pixel row during each of a first plurality of image frames and a second plurality of image frames interleaved with the first plurality of image frames; and a brightness controller configured to: during the first plurality of image frames, instruct the EM gate drivers of the first plurality of pixel rows to provide a pulse width modulation signal starting with a turn-on pulse, and instruct the EM gate drivers of the second plurality of pixel rows to provide a pulse width modulation signal starting with a turn-off pulse; and the brightness controller is configured to: during the second plurality of image frames, instruct the EM gate drivers of the first plurality of pixel rows to provide a pulse width modulation signal starting with a turn-off pulse, and instruct the EM gate drivers of the second plurality of pixel rows to provide a pulse width modulation signal starting with a turn-on pulse. In this example or any other example, the digital display further includes a display controller configured to update the display of visual content on the digital display at a display refresh rate. In this example or any other example, the frequency of the pulse width modulation signal is an integer multiple of the display refresh rate. In this example or any other example, the display controller is further configured to dynamically change the display refresh rate. In this example or any other example, for at least some of the first or second plurality of image frames, the frequency of the pulse width modulation signal is a non-integer multiple of the display refresh rate. In this example or any other example, the digital display is an organic light-emitting diode (OLED) display or a quantum dot light-emitting diode (QLED) display.

[0065] It should be understood that the configurations and / or methods described herein are exemplary in nature, and these specific embodiments or examples should not be considered limiting, as many variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, the various actions explained and / or described may be performed in the explained and / or described order, in a different order, in parallel, or omitted. Similarly, the order of the processes described above may be changed.

[0066] The subject matter of this disclosure includes all novel and non-obvious combinations and sub-combinations of the various processes, systems and configurations disclosed herein, as well as other features, functions, actions and / or attributes, and any and all equivalents thereof.

Claims

1. A digital display, comprising: Each consists of multiple pixel rows, including one or more pixels; A plurality of electromagnetic EM gate drivers, wherein each of the plurality of pixel rows is controlled by a respective EM gate driver of the plurality of EM gate drivers, and wherein for each of the plurality of pixel rows, the respective EM gate driver is configured to provide a brightness control signal to the pixel row during each of a first plurality of image frames and a second plurality of image frames interleaved with the first plurality of image frames; as well as A brightness controller communicatively coupled to each of the plurality of EM gate drivers, the brightness controller being configured to: for the first plurality of image frames, instruct the corresponding EM gate driver of each of the plurality of pixel rows to provide a brightness control signal in the form of a pulse width modulation signal starting with an on pulse, and for the second plurality of image frames, instruct the corresponding EM gate driver of each of the plurality of pixel rows to provide a brightness control signal in the form of a pulse width modulation signal starting with an off pulse; as well as A display controller is configured to update the display of visual content on the digital display at a display refresh rate, wherein the display controller is further configured to dynamically change the display refresh rate. For at least some of the first plurality of image frames or the second plurality of image frames, the frequency of the pulse width modulation signal is a non-integer multiple of the display refresh rate.

2. The digital display as described in claim 1, characterized in that, The digital display is an organic light-emitting diode (OLED) display or a quantum dot light-emitting diode (QLED) display.

3. The digital display as described in claim 1, characterized in that, The digital display is a micro-LED display.

4. A digital display, comprising: Each comprises a first row of multiple pixels containing one or more pixels; Each of the second plurality of pixel rows includes one or more pixels, and the second plurality of pixel rows are interleaved with the first plurality of pixel rows; A plurality of electromagnetic EM gate drivers, wherein each of the first plurality of pixel rows and the second plurality of pixel rows is controlled by a corresponding EM gate driver of the plurality of EM gate drivers, and wherein for each of the first plurality of pixel rows and the second plurality of pixel rows, the corresponding EM gate driver is configured to provide a brightness control signal to the pixel row during each of a first plurality of image frames and a second plurality of image frames interleaved with the first plurality of image frames; as well as A brightness controller communicatively coupled to each of the plurality of EM gate drivers, the brightness controller being configured to: during the first plurality of image frames, instruct the corresponding EM gate driver of the first plurality of pixel rows to provide a brightness control signal in the form of a pulse width modulation signal starting with an on pulse, and instruct the corresponding EM gate driver of the second plurality of pixel rows to provide a brightness control signal in the form of a pulse width modulation signal starting with an off pulse; The brightness controller is configured to: during the second plurality of image frames, instruct the EM gate driver of the first plurality of pixel rows to provide a pulse width modulation signal starting with a cutoff pulse, and instruct the EM gate driver of the second plurality of pixel rows to provide a pulse width modulation signal starting with a turn-on pulse; as well as A display controller is configured to update the display of visual content on the digital display at a display refresh rate, wherein the display controller is further configured to dynamically change the display refresh rate. For at least some of the first plurality of image frames or the second plurality of image frames, the frequency of the pulse width modulation signal is a non-integer multiple of the display refresh rate.

5. The digital display as described in claim 4, characterized in that, The digital display is an organic light-emitting diode (OLED) display or a quantum dot light-emitting diode (QLED) display.

6. A digital display, comprising: Each comprises a first row of multiple pixels containing one or more pixels; Each of the second plurality of pixel rows includes one or more pixels, and the second plurality of pixel rows are interleaved with the first plurality of pixel rows; A plurality of electromagnetic EM gate drivers, wherein each of the first plurality of pixel rows and the second plurality of pixel rows is controlled by a corresponding EM gate driver of the plurality of EM gate drivers, and wherein for each of the first plurality of pixel rows and the second plurality of pixel rows, the corresponding electromagnetic EM gate driver is configured to provide a brightness control signal to the pixel row during each of a plurality of image frames; A brightness controller communicatively coupled to each of the plurality of EM gate drivers, the brightness controller being configured to: instruct the respective EM gate driver of the first plurality of pixel rows to provide a brightness control signal in the form of a pulse width modulation signal starting with an on pulse, and instruct the respective EM gate driver of the second plurality of pixel rows to provide a brightness control signal in the form of a pulse width modulation signal starting with an off pulse; as well as A display controller is configured to update the display of visual content on the digital display at a display refresh rate, wherein the display controller is further configured to dynamically change the display refresh rate. For at least some of the plurality of image frames, the frequency of the pulse width modulation signal is a non-integer multiple of the display refresh rate.

7. The digital display as claimed in claim 6, characterized in that, The digital display is an organic light-emitting diode (OLED) display or a quantum dot light-emitting diode (QLED) display.

8. The digital display as claimed in claim 6, characterized in that, The digital display is a micro-LED display.

Images