An efficient area-power optimization method for operational amplifiers

By defining the search range in the operational amplifier design and utilizing neural networks and intelligent optimization algorithms to optimize design parameters, the problem of co-optimizing operational amplifier area and power consumption was solved, achieving efficient chip design.

CN116894415BActive Publication Date: 2026-07-24GALLIUM CORE TIMES (XIAN) ELECTRONIC TECHNOLOGY DEVELOPMENT CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
GALLIUM CORE TIMES (XIAN) ELECTRONIC TECHNOLOGY DEVELOPMENT CO LTD
Filing Date
2023-06-09
Publication Date
2026-07-24

AI Technical Summary

Technical Problem

Existing technologies struggle to efficiently and collaboratively optimize the area and power consumption of operational amplifiers. Traditional design schemes, when the design scope is not set reasonably, result in low data utilization and low optimization efficiency, making it difficult to balance multiple performance indicators.

Method used

By obtaining the basic design requirements of the operational amplifier, defining the area and parameter search range, using neural network models and intelligent optimization algorithms to filter design parameters during local iteration, and combining the global optimal solution to update the search range, the design parameters are optimized to narrow the search range and improve efficiency.

Benefits of technology

This significantly shortens the chip development cycle, reduces the chip design area and power consumption, and improves design efficiency and accuracy.

✦ Generated by Eureka AI based on patent content.

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Abstract

The application provides an efficient operational amplifier area power consumption optimization method, designs a global optimization iteration process and a local iteration optimization process, updates an area search range and a parameter search range through a current optimal solution in the global optimization iteration process, greatly reduces the search range, and saves the time for repeatedly determining the design parameters and the area when the operational amplifier is designed; in the local optimization iteration process, a local optimal solution is found by using an intelligent optimization algorithm, and whether the global optimal solution is updated is determined according to a target function value; in addition, the local iteration number is optimized by introducing the local iteration number, the local iteration number is set according to the area search range updated each time, and the optimization efficiency of the algorithm can be improved. Therefore, the application provides an efficient operational amplifier pre-design scheme for technicians, and the research and development cycle of the chip can be greatly reduced.
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Description

Technical Field

[0001] This invention belongs to the field of analog circuit design technology, specifically relating to a highly efficient method for optimizing the area and power consumption of operational amplifiers. Background Technology

[0002] Operational amplifiers are among the most common modules in analog integrated circuits, widely used in signal detection, signal power amplification, and power supply circuits. With the development of IoT technology, chip design is increasingly trending towards low power consumption and miniaturization, making the synergistic optimization of chip area and power consumption a major design challenge. As integrated circuit technology advances, the design of analog integrated circuits, such as operational amplifiers, becomes increasingly difficult. Due to the complexity of analog integrated circuit design, analog circuit design often requires trade-offs between multiple performance indicators. However, because manual design often relies on experience, it is difficult to simultaneously consider multiple indicators, resulting in significant limitations in the design process.

[0003] Traditional analog integrated circuit optimization techniques can be mainly divided into two types: data modeling-based optimization methods and hybrid optimization methods. Data modeling-based optimization methods treat the circuit design problem as a black-box function optimization problem, establishing a mapping relationship between design parameters and simulation data for optimization. However, data modeling-based optimization methods require a large amount of simulation data before optimization. When design rules are unclear, this method may waste significant simulation resources due to unreasonable parameter settings. To avoid this problem, the academic community has proposed hybrid optimization-based design methods. The main idea is to design the circuit through local modeling, local optimization, and then verification using a circuit simulator.

[0004] Traditional design schemes focus on design parameters when defining local scopes, resulting in low data utilization. Furthermore, since the optimization benefits differ across different local scopes, traditional algorithms use the same number of iterations across all scopes, leading to inefficient optimization. Additionally, traditional design schemes struggle with directly reducing the design scope when co-optimizing the area and power consumption of operational amplifiers. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a highly efficient method for optimizing the area and power consumption of operational amplifiers. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] This invention provides a highly efficient method for optimizing the area and power consumption of operational amplifiers, including:

[0007] S100: Obtain the basic design requirements of the operational amplifier, and define the area search range and parameter search range based on the basic design requirements;

[0008] S200 generates an optimized dataset within the area search range and parameter search range;

[0009] S300, in the current global iteration, use the optimized dataset to train the neural network model to obtain the current local model;

[0010] S400: In the current local iteration, the intelligent optimization algorithm searches the current local model by filtering local design parameters within the current parameter search range and the current area search range to obtain a local optimal solution; the local optimal solution is compared with the global optimal solution to determine whether to update the global optimal solution; if it is updated, the updated global optimal solution is obtained.

[0011] S500 updates the area search range and parameter search range in different ways depending on whether the number of times the global optimal solution has not been updated is greater than the maximum limit number of times.

[0012] S600: Use the updated area search range as the current area search range and the updated parameter search range as the current parameter search range, and repeat the process from S200 to S500 until the global maximum number of iterations is reached, and output the global optimal solution updated last time.

[0013] This invention provides a highly efficient method for optimizing the area and power consumption of operational amplifiers. It designs both a global optimization iteration process and a local optimization iteration process. During the global optimization iteration process, the area search range and parameter search range are updated using the area of ​​the current optimal solution, significantly narrowing the search range and saving time spent repeatedly determining design parameters and area during operational amplifier design. During the local optimization iteration process, an intelligent optimization algorithm is used to find local optima, and the global optimal solution is updated based on the objective function value. Furthermore, by introducing local iteration number optimization, which is set according to the area search range updated each time, the efficiency of the algorithm optimization can be improved. Therefore, this invention provides technicians with a highly efficient pre-design scheme for operational amplifiers, which can significantly reduce the chip development cycle. The invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of an efficient operational amplifier area and power consumption optimization method provided by the present invention;

[0015] Figure 2 Circuit diagram of the operational amplifier provided for this invention;

[0016] Figure 3A schematic diagram illustrating the convergence of the objective function provided by this invention;

[0017] Figure 4 This is a schematic diagram of area optimization convergence provided by the present invention;

[0018] Figure 5 This is a schematic diagram illustrating the power consumption optimization convergence provided by the present invention. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0020] like Figure 1 As shown, the present invention provides a highly efficient operational amplifier area and power consumption optimization method, comprising:

[0021] S100: Obtain the basic design requirements of the operational amplifier, and define the area search range and parameter search range based on the basic design requirements;

[0022] S200 generates an optimized dataset within the area search range and parameter search range;

[0023] S300, in the current global iteration, use the optimized dataset to train the neural network model to obtain the current local model;

[0024] S400: In the current local iteration, the intelligent optimization algorithm searches the current local model by filtering local design parameters within the current parameter search range and the current area search range to obtain a local optimal solution; the local optimal solution is compared with the global optimal solution to determine whether to update the global optimal solution; if it is updated, the updated global optimal solution is obtained.

[0025] S500 updates the area search range and parameter search range in different ways depending on whether the number of times the global optimal solution has not been updated is greater than the maximum limit number of times.

[0026] S600: Use the updated area search range as the current area search range and the updated parameter search range as the current parameter search range, and repeat the process from S200 to S500 until the global maximum number of iterations is reached, and output the global optimal solution updated last time.

[0027] In a specific embodiment of the present invention, S200 includes:

[0028] S210, Latin hypercube sampling is performed within the area search range to obtain the initial design parameter set;

[0029] S220, the initial design parameter set is filtered according to the area search range to obtain the filtered design parameter set;

[0030] S230 uses an analog circuit simulator to simulate the selected design parameter set to obtain the circuit performance parameter set;

[0031] S240, merge and filter the design parameter set and the circuit performance parameter set to obtain the optimized dataset.

[0032] In a specific embodiment of the present invention, S400 includes:

[0033] S410, in the current local iteration, the intelligent optimization algorithm is used to select the current local design parameters that are in line with the current area search range within the current parameter search range, and the current local design parameters are input into the latest local model to predict the current local design performance;

[0034] S420: If the current local iteration number is not the local maximum iteration number, repeat S410 until the local maximum iteration number is reached, and take the local design parameters, local design area, and local design performance of the local maximum iteration number as the local optimal solution.

[0035] S430: Compare the local optimal solution obtained in S420 with the global optimal solution to determine whether to update the global optimal solution. If it is updated, the updated global optimal solution is obtained.

[0036] In a specific embodiment of the present invention, S410 includes:

[0037] S411, in the first local iteration, generate initial design parameters within the parameter search range defined by S100; calculate the initial design area based on the initial design parameters, and determine whether the initial design area meets the area search range. If so, input the initial design parameters into the initial local model to estimate the initial design performance.

[0038] S412, in the current local iteration, filter the current design parameters within the current parameter search range; calculate the current design area based on the initial design parameters, and determine whether the current design area meets the current area search range. If so, input the current design parameters into the current local model to estimate the current local design performance; where the current parameter search range is the parameter search range updated in the last time.

[0039] The local maximum number of iterations is determined based on the global optimal solution, and is expressed as:

[0040]

[0041] Where, N A It is the area iteration factor, N min It is the local minimum number of iterations, A bestThe design area is the globally optimal solution.

[0042] In a specific embodiment of the present invention, S430 includes:

[0043] S431, Calculate the first objective function value of the local optimum and the second objective function value of the global optimum;

[0044] S432, if the value of the first objective function is less than the value of the second objective function, then it is determined that the global optimal solution needs to be updated, and the local optimal solution is used as the updated global optimal solution;

[0045] S433, if the value of the first objective function is greater than the value of the second objective function, then it is determined that there is no need to update the global optimal solution, so that the previously updated global optimal solution remains unchanged.

[0046] The expressions for calculating the first objective function and the second objective function are as follows:

[0047]

[0048] Where F is the objective function value, a is the area optimization factor, A is the area of ​​the operational amplifier, b is the power consumption optimization factor, P is the power consumption of the operational amplifier, M1 represents the number of design performance indicators, and P i This represents the penalty term for the i-th design performance of the operational amplifier.

[0049] In a specific embodiment of the present invention, S500 includes:

[0050] S510, determine whether the number of times the global optimal solution has not been updated has reached the maximum limit;

[0051] S520: If the number of times the global optimal solution has not been updated has not reached the maximum limit, then the area search range and parameter search range are updated using the global optimal solution.

[0052] In S520, the area search range updated using the global optimal solution is represented as follows:

[0053] A∈[max(k1·A best A min ),min(k2·A best A max )];

[0054] The parameter search range updated using the global optimal solution in S520 of this invention is expressed as follows:

[0055]

[0056] Among them, A best For the design area of ​​the globally optimal solution, A minIt is the minimum design area of ​​the operational amplifier, A max This represents the maximum area of ​​the operational amplifier design; k1 and k2 are pre-defined area range coefficients; W max W represents the maximum design width of the transistor. min The minimum design width of the transistor is represented by L, the length of the transistor is represented by L, and the number of transistors in the operational amplifier is represented by M2.

[0057] S530: If the number of times the global optimal solution has not been updated reaches the maximum limit, a new update strategy is adopted to update the area search range and parameter search range.

[0058] The area search range updated using the new update strategy in S530 of this invention is represented as follows:

[0059] A2∈[max(k3·A best A min ),min(A best A max )];

[0060] The parameter search range updated using the new update strategy is represented as follows:

[0061]

[0062] Where A2 represents the area search range updated using the new update strategy, k3 is the area range coefficient when the number of unupdated times exceeds the maximum limit, and A best A is the design area of ​​the globally optimal solution. min It is the minimum design area of ​​the operational amplifier, A max M1 represents the maximum area of ​​the operational amplifier design; M2 represents the number of transistors in the operational amplifier.

[0063] The optimization process of this invention is described below using an optimized Miller-compensated dual-stage operational amplifier based on TSMC's 65nm process as an example.

[0064] The objective function of the operational amplifier designed in this invention The values ​​of a and b are 1 / 2 and 1 / 300, respectively. Additionally, M1 represents the number of design performance indicators, which is 7, and P... i This represents the penalty term for the i-th design performance of the op-amp. Taking gain as an example, its specific expression is:

[0065] P A =P×(0.5-0.5*sign(Av-Av) min )+max(Av min -Av,0) / Av min )

[0066] Where P is the penalty coefficient, which must be greater than the maximum area of ​​the operational amplifier; here it is taken as 20. Av is the gain. min Gain constraints. The design performance constraints for the design area included in the basic design requirements are shown in Table 1:

[0067] Table 1 Design Performance Constraints

[0068]

[0069] There are seven design parameters: the lengths W1 of transistors MN1 and MN2, W2 of transistors MP1 and MP2, W3 of transistor MP3, W4 of transistors MN3 and MN4, W5 of transistor MN5, bias current I, and the ratio K of Miller capacitance Cc to load capacitance CL, where CL = 200fF. The value ranges of each parameter are shown in Table 2.

[0070] Table 2 Parameter Value Range Table

[0071]

[0072] Assume the area of ​​the global optimal solution is A. best Update the formula based on the area search range:

[0073] A∈[max(k1·A best A min ),min(k2·A best A max )],

[0074] In this design, A max 1μm 2 A min It is 0.0576μm 2 In this design, k1 and k2 are selected as 0.85 and 1.1, respectively. After obtaining the area boundary, the parameter search range of the operational amplifier can be obtained:

[0075]

[0076] In this design, A max 1μm 2 A min It is 0.0576μm 2 In this design, k1 and k2 are selected as 0.85 and 1.1, respectively. max The initial W represents the maximum design width of the transistor. max 12μm, W min The minimum design value for the transistor width is 0.12 μm, L represents the transistor length, which is 0.06 μm, and M2 represents the number of transistors in the circuit, which is 8.

[0077] The initial design parameter set is obtained by performing Latin hypercube sampling within the range defined by the operational amplifier design parameters. The initial design parameter set has 3000 parameters. The optimized dataset can be obtained by the optimization dataset establishment process according to the present invention.

[0078] A local optimum solution is obtained by using an intelligent optimization algorithm to optimize the local model. This design employs a particle swarm optimization algorithm with linearly decreasing inertia weights.

[0079] The particle swarm optimization algorithm with linearly decreasing inertia weights can be described as follows:

[0080] v i (t+1)=wv i (t)+c1r1(p i -x i (t))+c2r2(p g -x i (t))

[0081] x i (t+1)=x i (t)+v i (t+1)

[0082]

[0083] Where: x i and v i Let p represent the position vector and velocity vector of the i-th particle, respectively, w represent the inertia weight, and p represent the velocity vector. i p represents the local optimum. g This represents the global optimal position, where c1 and c2 are constants, r1 and r2 are random numbers between [0,1], iter represents the current iteration number, and N represents the global optimal position. local w represents the number of local iterations. max and w min These represent the maximum and minimum values ​​of the inertia weights, respectively. The initialization of the particle swarm parameters is shown in Table 3.

[0084] Table 3 Initialization table for particle swarm parameters

[0085]

[0086] A local reward estimation strategy is introduced. The area search region is determined based on the global optimum. According to the objective function F, regions with larger operational amplifier areas generally have lower rewards, while regions with larger area values ​​have higher rewards. Therefore, allocating more local iterations to smaller regions is more efficient. This design introduces a local reward estimation strategy, setting the number of local iterations N based on the area search region. local :

[0087]

[0088] Where, N A It is the area iteration factor, N min It represents the minimum number of iterations. In this design, N... A It is 7.5, N min Set to 10.

[0089] This design sets the global maximum number of iterations to 30. If the total number of searches does not reach the global maximum number of iterations, then it determines whether to update the global optimal solution based on the local optimal solution. If the global optimal solution is updated, the update strategy for the optimization range remains unchanged. If the global optimal solution is not updated, it checks whether the global optimal solution has reached the maximum number of iterations (Nupdate) without being updated. If the number of iterations without updating reaches Nupdate, the update strategy for the new range is as follows:

[0090] A∈[max(k3·A best A min ),min(A best A max )]

[0091] Where k3 is the area range coefficient when the number of unupdated times exceeds Nupdate. In this design, k3 is 0.85 and Nupdate is set to 10.

[0092] The optimization results for this example are shown in Tables 4 and 5, and the circuit design parameters are shown in Table 4:

[0093] Table 4 Design parameters of operational amplifiers

[0094]

[0095] The simulation results of the circuit performance after verification by the Ngspice simulator are shown in Table 5.

[0096] Table 5. Circuit Performance Simulation Results

[0097]

[0098] The iterative convergence of the objective function, optimal area, and power consumption is as follows: Figure 3-5 As shown in the figure. It can be seen that the optimized area is set at 1 μm. 2 The size was reduced to 0.22 μm. 2 The final search range is 0.055um. 2The parameter search range was reduced from a maximum width of 12μm to a maximum width of 3.19μm, a reduction of approximately 74.2%. Power consumption was reduced from the initially set 150uW to 30.67uW, a reduction of 79.55%.

[0099] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0100] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0101] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A highly efficient method for optimizing the area and power consumption of operational amplifiers, characterized in that, include: S100: Obtain the basic design requirements of the operational amplifier, and define the area search range and parameter search range based on the basic design requirements; S200 generates an optimized dataset within the area search range and parameter search range; S300, in the current global iteration, use the optimized dataset to train the neural network model to obtain the current local model; S400: In the current local iteration, the intelligent optimization algorithm searches the current local model by filtering local design parameters within the current parameter search range and the current area search range to obtain a local optimal solution; the local optimal solution is compared with the global optimal solution to determine whether to update the global optimal solution; if it is updated, the updated global optimal solution is obtained. S500 updates the area search range and parameter search range in different ways depending on whether the number of times the global optimal solution has not been updated is greater than the maximum limit number of times. S600: Use the updated area search range as the current area search range and the updated parameter search range as the current parameter search range, and repeat the process from S200 to S500 until the global maximum number of iterations is reached, and output the global optimal solution updated last time. S200 includes: S210, Latin hypercube sampling is performed within the area search range to obtain the initial design parameter set; S220, the initial design parameter set is filtered according to the area search range to obtain the filtered design parameter set; S230, The selected design parameter set is simulated using an analog circuit simulator to obtain a circuit performance parameter set; S240, merge the set of selected design parameters and the set of circuit performance parameters to obtain the optimized dataset; The S400 includes: S410, in the current local iteration, the intelligent optimization algorithm is used to select the current local design parameters that conform to the current area search range within the current parameter search range, and the current local design parameters are input into the latest local model to predict the current local design performance; S420: If the current local iteration number is not the local maximum iteration number, repeat S410 until the local maximum iteration number is reached, and take the local design parameters, local design area, and local design performance of the local maximum iteration number as the local optimal solution. S430: Compare the local optimal solution obtained in S420 with the global optimal solution to determine whether to update the global optimal solution. If it is updated, the updated global optimal solution is obtained. The local maximum number of iterations is determined based on the global optimal solution, and is expressed as: ; Where, N A It is the area iteration factor, N min It is the local minimum number of iterations. The design area is the globally optimal solution.

2. The efficient operational amplifier area and power consumption optimization method according to claim 1, characterized in that, S410 includes: S411, in the first local iteration, generate initial design parameters within the parameter search range defined by S100; calculate the initial design area based on the initial design parameters, and determine whether the initial design area meets the area search range. If so, input the initial design parameters into the initial local model to estimate the initial design performance. S412, in the current local iteration, filter the current design parameters within the current parameter search range; calculate the current design area based on the initial design parameters, and determine whether the current design area conforms to the current area search range. If so, input the current design parameters into the current local model to estimate the current local design performance; wherein, the current parameter search range is the parameter search range updated in the last time.

3. The efficient operational amplifier area and power consumption optimization method according to claim 1, characterized in that, The S430 includes: S431, Calculate the first objective function value of the local optimum and the second objective function value of the global optimum; S432, if the value of the first objective function is less than the value of the second objective function, then it is determined that the global optimal solution needs to be updated, and the local optimal solution is used as the updated global optimal solution; S433, if the value of the first objective function is greater than the value of the second objective function, then it is determined that there is no need to update the global optimal solution, so that the previously updated global optimal solution remains unchanged.

4. The efficient operational amplifier area and power consumption optimization method according to claim 3, characterized in that, The expressions for calculating the first objective function and the second objective function are as follows: ; Where F is the objective function value, As the area optimization factor, The area of ​​the operational amplifier. It is a power consumption optimization factor. This refers to the power consumption of the operational amplifier. The number of metrics representing design performance. Representing the operational amplifier's first i A penalty item for design performance.

5. The efficient operational amplifier area and power consumption optimization method according to claim 1, characterized in that, The S500 includes: S510, determine whether the number of times the global optimal solution has not been updated has reached the maximum limit; S520, if the number of times the global optimal solution has not been updated has not reached the maximum limit, then the area search range and the parameter search range are updated using the global optimal solution; S530: If the number of times the global optimal solution has not been updated reaches the maximum limit, a new update strategy is adopted to update the area search range and parameter search range.

6. The efficient operational amplifier area and power consumption optimization method according to claim 5, characterized in that, The area search range updated using the global optimal solution in S520 is represented as follows: ; The parameter search range updated using the global optimal solution in S520 is expressed as follows: ; in, The design area is the globally optimal solution. It is the minimum design area for the operational amplifier. It is the maximum area of ​​the operational amplifier design; k1 and k2 are pre-defined area range coefficients; This represents the maximum design width of the transistor. This represents the minimum design width of the transistor. Represents the length of the transistor. This represents the number of transistors in an operational amplifier.

7. The efficient operational amplifier area and power consumption optimization method according to claim 5, characterized in that, The area search range updated using the new update strategy in S530 is represented as follows: ; The parameter search range updated using the new update strategy is represented as follows: ; in, This indicates the area search range updated using the new update strategy. It is the area range coefficient when the number of times it has not been updated exceeds the maximum limit. It is the design area of ​​the globally optimal solution. It is the minimum design area for the operational amplifier. It is the maximum value of the operational amplifier design area; This represents the number of transistors in an operational amplifier.