Transconductance amplifier with high linearity and common mode rejection

Abstract

The present application relates to a transconductance amplifier with high linearity and common mode rejection. The transconductance amplifier includes a first MOS transistor configured to receive a first voltage at a first node and output a first current to a fifth node based on a third voltage at a third node, a second MOS transistor configured to receive a second voltage at a second node and output a second current to a sixth node based on a fourth voltage at a fourth node, a third MOS transistor configured to output a third current to the third node based on a fifth voltage at the fifth node, a fourth MOS transistor configured to output a fourth current to the fourth node based on a sixth voltage at the sixth node, and a source degeneration network disposed between the third node and the fourth node.

Description

Technical Field

[0001] This disclosure relates to transconductance amplifiers, and more particularly to transconductance amplifiers capable of achieving high linearity and common-mode rejection without large parasitic capacitance. Background Technology

[0002] A transconductance amplifier receives a voltage signal and outputs a current signal accordingly. Ideally, an increment in the voltage signal should cause a proportional increment in the current signal. When the increment in the current signal is not strictly proportional to the increment in the voltage signal, a non-ideal characteristic (also known as nonlinearity) occurs. It is worth noting that in embodiments employing differential signals, a voltage signal comprises a first voltage and a second voltage, while a current signal comprises a first current and a second current. For example... Figure 1 As shown, a prior art transconductance amplifier 100 employing differential signals includes: a first NMOS (N-channel metal-oxide-semiconductor) transistor 111 for receiving a first voltage V. P With the output of the first current I P ; and a second NMOS transistor 112, for receiving a second voltage V n With output a second current I n The aforementioned V P With V n They collectively define a voltage signal, and the aforementioned I P with I n They collectively define a current signal, I. P with I n It is received by a load 120. The load 120 includes a first resistor 121 and a second resistor 122, which are used to receive I respectively. P with I n In this disclosure, V DD This indicates the supply voltage of a power source.

[0003] One of the problems with the existing transconductance amplifier 100 is that its linearity is generally poor unless the two NMOS transistors 111 and 112 have a long channel length. However, if the two NMOS transistors 111 and 112 have a long channel length, this results in a large parasitic capacitance, which in turn limits the speed of the transconductance amplifier 100.

[0004] Furthermore, the existing transconductance amplifier 100 exhibits a high common-mode gain and the resulting poor common-mode rejection. The common-mode gain is determined by I... P with I nThe incremental change relative to V P With V n Defined by the incremental change, V at this time P With V n They are connected together and have the same voltage level.

[0005] In US Patent No. 10,892,717, the inventor surnamed Lin disclosed a transconductance amplifier that can achieve high linearity and does not have large parasitic capacitance, but did not really address the aforementioned problem of poor common-mode rejection.

[0006] In view of the above, this technical field needs a transconductance amplifier that can achieve high linearity and common-mode rejection without large parasitic capacitance. Summary of the Invention

[0007] In one embodiment of this disclosure, a transconductance amplifier includes: a first MOS (metal-oxide-semiconductor) transistor for receiving a first voltage at a first node based on a third voltage at a third node, and outputting a first current to a fifth node; a second MOS transistor for receiving a second voltage at a second node based on a fourth voltage at a fourth node, and outputting a second current to a sixth node; a third MOS transistor for outputting a third current to the third node based on a fifth voltage at the fifth node; a fourth MOS transistor for outputting a fourth current to the fourth node based on a sixth voltage at the sixth node; and a source degradation network disposed between the third node and the fourth node, including a source resistor connected in parallel, a fifth MOS transistor controlled by the first voltage, and a sixth MOS transistor controlled by the second voltage.

[0008] In one embodiment of this disclosure, a transconductance amplifier includes a first MOS (metal-oxide-semiconductor) transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a source degradation network, wherein: the gate, source, and drain of the first MOS transistor are respectively connected to a first node, a third node, and a fifth node; the gate, source, and drain of the second MOS transistor are respectively connected to a second node, a fourth node, and a sixth node; the gate, source, and drain of the third MOS transistor are respectively connected to the fifth node, a DC (direct current) node, and the third node; the gate, source, and drain of the fourth MOS transistor are respectively connected to the sixth node, the DC node, and the fourth node; and the source degradation network is disposed between the third node and the fourth node, and includes a source resistor connected in parallel, a fifth MOS transistor controlled by a first voltage of the node, and a sixth MOS transistor controlled by a second voltage of the second node. Attached Figure Description

[0009] Figure 1 This diagram shows a prior art transconductance amplifier;

[0010] Figure 2 A schematic diagram of a transconductance amplifier is shown according to an embodiment of the present disclosure;

[0011] Figure 3A An embodiment of the present disclosure shows a method for... Figure 2 A schematic diagram of the load of the transconductance amplifier;

[0012] Figure 3B According to another embodiment of this disclosure, it is shown that... Figure 2 A schematic diagram of the load of the transconductance amplifier; and

[0013] Figure 3C According to yet another embodiment of this disclosure, it is used for Figure 2 A schematic diagram of the load of the transconductance amplifier.

[0014] Symbol Explanation

[0015] 100: Transconductance Amplifier

[0016] 111: First NMOS transistor

[0017] 112: Second NMOS transistor

[0018] 120: Load

[0019] 121: First resistor

[0020] 122: Second resistor

[0021] I P First current

[0022] I n Second current

[0023] V DD Power supply voltage

[0024] 200: Transconductance Amplifier

[0025] 210: Source-Degenerate Networks

[0026] 220: Load

[0027] N1: First node

[0028] N2: Second node

[0029] N3: Third Node

[0030] N4: Fourth Node

[0031] N5: Fifth Node

[0032] N6: Sixth Node

[0033] M1: First NMOS transistor

[0034] M2: Second NMOS transistor

[0035] M3: Third NMOS transistor

[0036] M4: Fourth NMOS transistor

[0037] M5: Fifth NMOS transistor

[0038] M6: Sixth NMOS transistor

[0039] RB1: First bias resistor

[0040] RB2: Second bias resistor

[0041] R S Source degradation resistor

[0042] V1: First voltage

[0043] V2: Second voltage

[0044] V3: Third voltage

[0045] V4: Fourth voltage

[0046] V5: Fifth voltage

[0047] V6: Sixth voltage

[0048] V B Bias voltage

[0049] I1: First current

[0050] I2: Second current

[0051] I3: Third Current

[0052] I4: Fourth Current

[0053] I S Source current

[0054] DL1, DL2, DL3, DL4: Dashed lines

[0055] 310: Network

[0056] 311, 312: Resistors

[0057] 320: Network

[0058] 321, 322: Inductors

[0059] 323: Capacitor

[0060] 330: Network

[0061] 331, 332: Inductors

[0062] 333: Capacitor

[0063] 334: Mixer

[0064] N7: Seventh Node

[0065] N8: Eighth Node

[0066] S1: First Switch

[0067] S2: Second Switch

[0068] S3: Third Switch

[0069] S4: Fourth Switch

[0070] C1: First Clock

[0071] C2: Second Clock Detailed Implementation

[0072] This disclosure relates to transconductance amplifiers. Although several embodiments of this disclosure are presented as preferred examples for carrying out the invention, the invention can be implemented in various ways and is not limited to the specific examples described below, nor to the specific manner in which the technical features of said specific examples are implemented. In other instances, known details have not been shown or described to avoid obscuring the viewpoint of this disclosure.

[0073] Those skilled in the art will understand the microelectronics-related terms and basic concepts used in this disclosure, such as "voltage," "current," "signal," "transduction," "amplifier," "differential signal," "common mode," "load," "resistor," "capacitor," "inductor," "impedance," "parallel connection," "circuit node," "ground," "DC (direct current)," "AC (alternating current)," "switch," "open circuit," "short circuit," "mixer," "power supply," "MOS (metal-oxide-semiconductor) transistor," "CMOS (complementary metal-oxide-semiconductor) process technology," "NMOS (n-channel metal-oxide-semiconductor) transistor," and "PMOS (p-channel metal-oxide-semiconductor) transistor." Such terms and basic concepts are used in microelectronics literature and are readily apparent to those skilled in the art; therefore, their details are omitted here.

[0074] Those skilled in the art can understand circuit diagrams including electronic components such as inductors, capacitors, resistors, NMOS transistors, PMOS transistors, etc., without needing redundant explanations of how one component is connected to another. Those skilled in the art can also identify a ground symbol, a capacitor symbol, an inductor symbol, a resistor symbol, and the symbols for PMOS and NMOS transistors, and can identify the "source," "gate," and "drain" terminals of a MOS transistor. For the sake of brevity, in the following description, "source terminal" will be abbreviated as "source," "gate terminal" as "gate," and "drain terminal" as "drain."

[0075] A circuit is a collection of transistors, inductors, capacitors, resistors and / or other electronic devices interconnected in a particular manner to perform a particular function.

[0076] A network is a circuit or a collection of circuits.

[0077] In this disclosure, a DC node refers to a node having a substantially fixed voltage level. Both power supply nodes and ground nodes are DC nodes, but their voltage levels differ; the voltage level of a power supply node is higher than the voltage level of a ground node.

[0078] In this disclosure, when the meaning of a "circuit node" is clearly understood from the context, the "circuit node" is simply referred to as a "node".

[0079] A signal is a voltage or current with a variable level that carries specific information and can change over time. At any given moment, the level of the signal represents the state of the signal at that moment.

[0080] When a change in a signal originates from and is determined by a first device, and a second device only passively responds to the change in the signal, the signal is considered to be output from the first device to the second device.

[0081] A logic signal is a two-state voltage signal, meaning it has a low state and a high state. Regarding a logic signal Q, when we say "Q is high" or "Q is low," we mean "Q is in the high state" or "Q is in the low state."

[0082] A logic signal is often used as a control signal to enable or disable the function of a circuit. When a logic signal is in a logical state that enables the circuit's function, the logic signal is considered "asserted"; otherwise, it is considered "de-asserted." When a logic signal is "asserted" and high, it is considered "active high"; when a logic signal is "asserted" and low, it is considered "active low."

[0083] When a first logic signal and a second logic signal are always in opposite states, the first logic signal is considered a logical inversion of the second logic signal. That is, when the first logic signal is high, the second logic signal will be low; and when the first logic signal is low, the second logic signal will be high. When a first logic signal is a logical inversion of a second logic signal, the first logic signal is considered complementary to the second logic signal.

[0084] A switch is a device used to provide a connection between a first node and a second node based on a logic signal; when the logic signal is active, the switch is actually a short circuit; and when the logic signal is deactivated, the switch is actually an open circuit.

[0085] A clock is a logic signal that periodically toggles back and forth between a low state and a high state.

[0086] Figure 2A schematic diagram of a transconductance amplifier 200 is shown according to an embodiment of the present disclosure. The transconductance amplifier 200 is used to receive a first voltage V1 at a first node N1 and a second voltage V2 at a second node N2, and to output a first current I1 and a second current I2 to a load 220 via a fifth node N5 and a sixth node N6, respectively. The transconductance amplifier 200 includes: a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, and a source degradation network 210, wherein the gate, source, and drain of the NMOS transistor M1 are connected to the first node N1, the third node N3, and the fifth node N5, respectively; the gate, source, and drain of the NMOS transistor M2 are connected to the second node N2, the fourth node N4, and the sixth node N6, respectively; the gate, source, and drain of the NMOS transistor M3 are connected to the fifth node N5, ground, and the third node N3, respectively; the gate, source, and drain of the NMOS transistor M4 are connected to the sixth node N6, ground, and the fourth node N4, respectively; and the source degradation network 210 is disposed between the third node N3 and the fourth node N4.

[0087] The source degeneration network 210 includes a source degeneration resistor R connected in parallel. S A fifth MOS transistor M5 controlled by the first voltage V1 and a sixth MOS transistor controlled by the second voltage V2. The impedance Z of the source degradation network 210. sdn It can be expressed as follows:

[0088]

[0089] In the above formula, R on5 The resistor is the NMOS transistor M5, and is controlled by V1, while R... on6 The resistor is the NMOS transistor M6 and is controlled by V2.

[0090] Transduction amplifier 200 is a balanced circuit, meaning that the two NMOS transistors M1 and M2 are identical, the two NMOS transistors M3 and M4 are identical, the two NMOS transistors M5 and M6 are identical, and the impedance seen from node N5 to load 220 is the same as the impedance seen from node N6 to load 220. Let the transconductance of the two NMOS transistors M1 and M2 be g. m1 And the transconductance of the two NMOS transistors M3 and M4 is g m2 Let Z be the impedance seen from node N5 to load 220.L It is the same as the impedance seen from node N6 to load 220.

[0091] The NMOS transistor M1 embodies a first source follower determined by a third current I3, which is provided by the NMOS transistor M3 and controlled by V5 in a negative feedback manner to ensure that V3 follows V1. Similarly, the NMOS transistor M2 acts as a second source follower determined by a fourth current I4, which is provided by the NMOS transistor M4 and controlled by V6 in a negative feedback manner to ensure that V4 follows V2.

[0092] In the context of a differential-mode signal, the increment ΔV of V1 is always accompanied by the same decrease ΔV of V2. Mathematically, those skilled in the art can derive the increment of V3 as δV3, which can be expressed by the following formula:

[0093] δV3=ΔV·g m1 Z S / (1+g m1 Z S (1+g m2 Z L (2)

[0094] During this period, V4 will decrease by the same amount δV3. In the above equation, Z S The impedance is half that of the source-degraded network 210, equal to Z. sdn / 2. Those skilled in the art can also deduce that the increment of I1 is δI1, which can be expressed by the following formula:

[0095] δI1=ΔV·g m1 / (1+g m1 Z S (1+g m2 Z L (3)

[0096] During this period, I2 will decrease by the same amount δI1. In the above equation, (1+g m2 Z L Let be the gain of the negative feedback provided by the two NMOS transistors M3 and M4. In one embodiment, the negative feedback has a sufficiently large gain such that the following equation holds:

[0097] g m1 Z S (1+g m2 Z L )>>1 (4)

[0098] Based on the foregoing, equation (3) can be simplified as follows:

[0099] δI1=ΔV / (Z S (1+g m2 Z L (5)

[0100] As stated above, δI1 depends on g. m1 The characteristic of [the characteristic] is thus eliminated, and the nonlinearity of the two NMOS transistors M1 and M2 is effectively reduced, which allows the transconductance amplifier 200 to have high linearity without requiring the two NMOS transistors M1 and M2 to use a long channel length device. However, the denominator Z [is affected]. S (1+g m2 Z L It may still contribute to the nonlinearity. An increase in V1 leads to an increase in I3, and consequently to 1 / R. on5 The increase in V2 leads to an increase in the transconductance of the NMOS transistor M3; during this period, the decrease in V2 leads to a decrease in I4, and consequently to 1 / R on6 The reduction in the transconductance of NMOS transistor M3 and the reduction in the transconductance of NMOS transistor M4. Due to the quadratic law of MOS transistors, when ΔV becomes large, the increase in the transconductance of NMOS transistor M3 will be greater than the decrease in the transconductance of NMOS transistor M4, which makes g m2 The effective value of increases, which also makes the denominator (1+g) more effective. m2 Z L Effectively increased. However, 1 / R on5 The increment will also be greater than 1 / R on6 The reduction in quantity made Z S Decrease. Due to (1+g m2 Z L The increase of Z) S Reduced remedies, Z S (1+g m2 Z L The nonlinearity of ) is thus reduced.

[0101] In the case of a common-mode signal, V1 and V2 are always at the same level, therefore V3 and V4 are always at the same level, which causes the source current I flowing through the source degradation network 210 to be... SThe impedance remains zero, and the source degradation network 210 effectively becomes an open circuit with infinite impedance. When the increments of V1 and V2 are both ΔV, I1 and I2 remain constant in the first-order approximation, which neglects the output resistances of the NMOS transistors M1, M2, M3, and M4. Therefore, the transconductance amplifier 200 can achieve a very high common-mode rejection.

[0102] In one embodiment, V1 and V2 are AC-coupled and received from a pre-amplifier circuit. In one embodiment, the signal connections represented by dashed lines DL1 and DL2 are solid connections, while the signal connections represented by dashed lines DL3 and DL4 are broken. The transconductance amplifier 200 further includes a first bias resistor RB1 and a second bias resistor RB2, which are respectively used to convert a bias voltage V B Coupled to nodes N1 and N2, the NMOS transistors M1 and M2 are thus affected by the bias voltage V. B And biased. In another embodiment, the signal connection represented by dashed lines DL1 and DL2 is interrupted, while the signal connection represented by dashed lines DL3 and DL4 is physically connected. Node N1 is coupled to node N5 via the bias resistor RB1, node N2 is coupled to node N6 via the bias resistor RB2, and the two NMOS transistors M1 and M2 are referred to as "self-biased".

[0103] In another embodiment, V1 and V2 are DC coupled and receive signals from a preamplifier circuit. In this example, the two resistors RB1 and RB2 are unnecessary, and the signal connections represented by dashed lines DL1, DL2, DL3, and DL4 are all interrupted.

[0104] For the transconductance amplifier 200 to operate optimally, the NMOS transistors M1, M2, M3, and M4 must all be maintained in the saturation region. In an AC-coupled embodiment, the two NMOS transistors M1 and M2 can be maintained in the saturation region by an appropriate bias voltage (whether via VB or self-bias), or in a DC-coupled embodiment, the preamplifier circuit must ensure that V1 and V2 are supplied with an appropriate DC value. By making the over-drive voltage of the two NMOS transistors M1 and M2 greater than the over-drive voltage of the two NMOS transistors M3 and M4, the two NMOS transistors M1 and M2 can be kept in the saturation region (the over-drive voltage of an NMOS transistor is defined as the difference between a gate-to-source voltage and a threshold voltage of the NMOS transistor). This can be achieved by at least one (preferably a plurality of) the following means: first, implementing the two NMOS transistors M3 and M4 using high threshold voltage elements; second, implementing the two NMOS transistors M1 and M2 using low threshold voltage elements; and third, making the two NMOS transistors M1 and M2 have a much larger width-to-length ratio than the two NMOS transistors M3 and M4.

[0105] In one embodiment, the two NMOS transistors M3 and M4 are high-threshold voltage devices. In one embodiment, the two NMOS transistors M1 and M2 are low-threshold voltage devices. In one embodiment, the aspect ratio of the two NMOS transistors M1 and M2 is greater than the aspect ratio of the two NMOS transistors M3 and M4. In one embodiment, the aspect ratio of the two NMOS transistors M1 and M2 is increased by a factor of the aspect ratio of the two NMOS transistors M3 and M4, and this factor is between two and ten.

[0106] The source degradation network 210 determines a gain of the transconductance amplifier 200. A small R S The value results in a large gain, and the large aspect ratio of the two NMOS transistors M5 and M6 also results in a large gain.

[0107] At Figure 3A In one embodiment shown, the load 220 is implemented through a network 310, which includes two resistors 311 and 312, respectively, used to power a power supply node V. DD Coupled to node N5 and supplying power to node V DD It is coupled to node N6.

[0108] At Figure 3B In another embodiment shown, the load 220 is implemented via a network 320, which includes two inductors 321 and 322, respectively, for connecting a power supply node V. DD Coupled to node N5 and supplying power to node V DD A capacitor 323 is coupled to node N6; and a capacitor 323 is disposed between the two nodes N5 and N6. Network 320 is an LC resonant cavity, which is well known to those skilled in the art and therefore does not need to be described in detail.

[0109] At Figure 3C In another embodiment shown, the load 220 is implemented through a network 330, which includes two inductors 331 and 332, respectively used to power a power supply node V. DD Coupled to a seventh node N7 and the power supply node V DD A capacitor 333 is coupled to an eighth node N8; a capacitor 333 is disposed between the two nodes N7 and N8; and a mixer 334 is used to couple the two nodes N7 and N8 to the two nodes N5 and N6. The mixer 334 includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. The first switch S1 connects N7 and N5 according to a first clock C1; the second switch S2 connects N8 and N6 according to the first clock C1; the third switch S3 connects N8 and N5 according to a second clock C2; and the fourth switch S4 connects N7 and N6 according to the second clock C2. The first clock C1 and the second clock C2 are complementary. When C1 is asserted, C2 is de-asserted, and N7 and N8 are actually connected to N5 and N6, respectively; when C1 is de-asserted, C2 is asserted, and N7 and N8 are actually connected to N6 and N5, respectively. Mixer 334 is existing technology and therefore requires no further description. Furthermore, the transconductance amplifier 100, along with load 220 (implemented via network 330), is a well-known "double side-band mixer." Those skilled in the art can construct a "single side-band mixer" by using two instances of this circuit but sharing the same inductors 331 and 332 and capacitor 333 in the load.

[0110] Although the arrow symbol associated with I1 indicates that it points from the load network 220 to the drain of the NMOS transistor M1, it must be understood that I1 is actually a current signal output from the NMOS transistor M1 through node N5 to the load network 220. This is because the NMOS transistor M1 generates and dictates changes in I1, while the load network 220 only passively responds to changes in I1. The direction of the arrow symbol associated with I1 only indicates the direction of current flow, not the direction of signal flow, and it is incorrect to interpret I1 as a current signal output from the load network 220 to the NMOS transistor M1 simply because the arrow symbol shows a direction from the load 220 to the NMOS transistor M1. The same logic applies to I2, I3, and I4.

[0111] It is well known in the prior art that for a circuit comprising multiple NMOS transistors and / or multiple PMOS transistors, the function of the circuit can remain unchanged if each NMOS transistor is replaced with a PMOS transistor, each PMOS transistor is replaced with an NMOS transistor, each ground node is replaced with a power node connection, and each power node is replaced with a ground node connection. Therefore, in the present claims, NMOS transistors are simply referred to as "MOS transistors," and ground nodes are simply referred to as DC nodes.

[0112] Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the express or implied content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the claims of this specification.

Claims

1. A transconductance amplifier, comprising: A first metal-oxide-semiconductor transistor is used to receive a first voltage at a first node and output a first current to a fifth node based on a third voltage at a third node. A second metal-oxide-semiconductor transistor is used to receive a second voltage at a second node according to a fourth voltage at a fourth node, and to output a second current to a sixth node; A third metal-oxide-semiconductor transistor is used to output a third current to the third node based on a fifth voltage of the fifth node; A fourth metal-oxide-semiconductor transistor is used to output a fourth current to the fourth node based on a sixth voltage of the sixth node; and A source degradation network is disposed between the third node and the fourth node, comprising a source resistor connected in parallel, a fifth metal-oxide-semiconductor transistor controlled by the first voltage, and a sixth metal-oxide-semiconductor transistor controlled by the second voltage.

2. The transconductance amplifier of claim 1, wherein the first voltage and the second voltage are received from a preamplifier circuit that is DC coupled.

3. The transconductance amplifier of claim 1, wherein the first voltage and the second voltage are received from a preamplifier circuit that is AC coupled.

4. The transconductance amplifier of claim 3 further comprises: a first bias resistor and a second bias resistor, respectively used to couple a bias voltage to the first node and to the second node.

5. The transconductance amplifier of claim 3, further comprising: a first bias resistor and a second bias resistor, respectively used to couple the first node to the fifth node and the second node to the sixth node.

6. The transconductance amplifier of claim 1, further comprising: a load for connecting the fifth node and the sixth node.

7. The transconductance amplifier of claim 6, wherein the load comprises: two inductors for coupling a power supply node to the fifth node and coupling the power supply node to the sixth node, respectively; and a capacitor located between the fifth node and the sixth node.

8. The transconducting amplifier of claim 6, wherein the load comprises: two inductors for coupling a power supply node to a seventh node and coupling the power supply node to an eighth node, respectively; a capacitor located between the seventh node and the eighth node; and a mixer for coupling the seventh node and the eighth node to the fifth node and the sixth node according to a first clock and a second clock, wherein the first clock and the second clock are complementary.

9. The transconductance amplifier of claim 8, wherein the mixer comprises: a first switch for connecting the seventh node and the fifth node according to the first clock; a second switch for connecting the eighth node and the sixth node according to the first clock; a third switch for connecting the eighth node and the fifth node according to the second clock; and a fourth switch for connecting the seventh node and the sixth node according to the second clock.

10. A transconductance amplifier comprising a first metal-oxide-semiconductor transistor, a second metal-oxide-semiconductor transistor, a third metal-oxide-semiconductor transistor, a fourth metal-oxide-semiconductor transistor, and a source degradation network, wherein: The gate, source, and drain of the first metal-oxide-semiconductor transistor are respectively connected to a first node, a third node, and a fifth node. The gate, source, and drain of the second metal-oxide-semiconductor transistor are respectively connected to a second node, a fourth node, and a sixth node. The gate, source, and drain of the third metal-oxide-semiconductor transistor are respectively connected to the fifth node, the DC node, and the third node; The gate, source, and drain of the fourth metal-oxide-semiconductor transistor are respectively connected to the sixth node, the DC node, and the fourth node; as well as The source degradation network, located between the third node and the fourth node, includes a source resistor connected in parallel, a fifth metal-oxide-semiconductor transistor controlled by a first voltage of the node, and a sixth metal-oxide-semiconductor transistor controlled by a second voltage of the second node.

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