Communication method and apparatus

Abstract

The present application provides a communication method. A first apparatus can send a first RAM to a second apparatus, wherein the first RAM is used for triggering the second apparatus to stop receiving, by means of a first channel, data sent by the first apparatus, and the first channel is a channel via which the first apparatus sends the data to the second apparatus. Compared with conventional technology in which a second apparatus is triggered, on the basis of a received AM, to stop receiving, by means of a first channel, data sent by a first apparatus, since the locking cycle of an RAM is far less than that of the AM, using the present solution can enable the second apparatus to quickly complete an operation of switching the first channel from a working state to a non-working state, and accordingly, the first channel can be quickly switched from the working state to the non-working state, thereby effectively reducing the switching time of the first channel from the working state to the non-working state, and accordingly improving the energy-saving effect.

Description

A communication method and apparatus

[0001] This application claims priority to Chinese Patent Application No. 2024119995462, filed with the State Intellectual Property Office of China on December 31, 2024, entitled "A Communication Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, and in particular to a communication method and apparatus. Background Technology

[0003] In digital communication networks, especially campus networks, traffic exhibits typical tidal characteristics; for example, traffic during the night is generally much lower than the network's bandwidth. Currently, even when there is no traffic on the network, Ethernet interface devices need to remain operational. For instance, the physical layer (PHY) of Ethernet interface devices remains active, resulting in significant power consumption waste.

[0004] Currently, to reduce the power consumption of Ethernet interface devices, some channels of the Ethernet interface device can be shut down during low traffic periods, and then the shut-down channels can be activated when traffic increases, thereby achieving energy saving. However, even so, the energy saving effect is still limited.

[0005] Therefore, a solution is urgently needed to address the above problems. Summary of the Invention

[0006] This application provides a communication method that can improve the energy efficiency of Ethernet interface devices.

[0007] Firstly, this application provides a communication method applicable to a first device. The first device sends a first rapid alignment marker (RAM) to a second device. The first RAM triggers the first device to stop receiving data transmitted by itself through a first channel, where the first channel is the channel through which the first device transmits data to the second device. In one example, before sending the first RAM to the second device, the first channel is in an active state, meaning the first device can transmit data (e.g., service data) to the second device through the first channel. Using this solution, compared to the conventional method where the second device triggers the cessation of receiving data transmitted by the first device through the first channel based on a received alignment marker (AM), the locking period of the RAM is much shorter than that of the AM. Therefore, this solution allows the second device to quickly switch the first channel from an active state to a non-active state. Consequently, the first channel can quickly switch from an active state to a non-active state, effectively reducing the time required for the first channel to switch from an active state to a non-active state. Thus, given a fixed amount of time without transmission traffic on the first channel, this solution can increase the actual time the first channel is in a dormant state, thereby improving energy efficiency. The lock period of RAM can be understood as the distance between adjacent RAMs, and the lock period of AM can be understood as the distance between adjacent AMs.

[0008] In one possible implementation, to ensure the reliability of channel state switching, the first device can send N RAMs to the second device. The first RAM can be the last RAM sent by the first device among the N RAMs. The first RAM is also the last RAM among the N RAMs received by the second device. That is, the first device sends N RAMs to the second device, and the last RAM among these N RAMs serves as the switching boundary between the first and second devices for switching the first channel from an active state to a non-active state. Both devices switch based on the same switching boundary, allowing the first channel to quickly complete the switch from an active state to a non-active state after the second device receives the first RAM, thereby effectively reducing the sleep time of the first channel and improving energy efficiency.

[0009] In one possible implementation, each of the N RAMs carries a sequence number, which is used by the second device to determine the number of RAMs received. That is, the second device can determine the number of RAMs it has received based on the sequence numbers in the received RAMs. Thus, when the second device has received N RAMs, upon receiving the last RAM (i.e., the first RAM), it can stop receiving data through the first channel in response to receiving that first RAM.

[0010] In one possible implementation, the sequence number carried in the i-th RAM sent by the first device is N-i+1, where i is an integer greater than or equal to 1 and less than or equal to N. In this scenario, the second device can have consecutive sequence numbers in the N RAMs it receives, and upon receiving a RAM with sequence number 1 (i.e., the first RAM), it stops receiving data through the first channel in response to receiving the first RAM.

[0011] In one possible implementation, for any given RAM, the serial number carried by that RAM can be carried through any available field within that RAM. In one example, when the RAM includes CD3 and CD7 fields, the serial number can be carried by either the CD3 or CD7 field. Accordingly, the second device can parse the serial number based on either the CD3 or CD7 field in the RAM, thereby determining the number of RAMs it has received. Here, CD in CD3 and CD7 represents a countdown.

[0012] In one possible implementation, the data transmitted by the first device between any two adjacent RAMs of the N RAMs is spaced by a first preset length. The first preset length can be determined, for example, based on the correction capability of the second device. Specifically, the first preset length can be the length of multiple active channels that enable the second device to successfully align the data transmitted from the first device to the second device. The data spaced between any two RAMs can be service data or idle data.

[0013] In one possible implementation, the first preset length of data includes a first number of forward error correction (FEC) codewords, where the first number is a positive integer. In this case, the second device can perform RAM locking operations at intervals of the first number of FEC codewords.

[0014] In one possible implementation, the first quantity is greater than or equal to 1 and less than or equal to 32. For example, the first quantity is 2, 4, or 8. The smaller the first quantity, the shorter the sleep time of the first channel, and correspondingly, the better the energy-saving effect of this solution.

[0015] In one possible implementation, after sending the first RAM, the first device can, in response to sending the first RAM to the second device, stop sending data to the second device through the first channel. That is, after sending the first RAM, the first device no longer waits for AM, but quickly stops sending data to the second device through the first channel. The first RAM serves as the switching boundary for the first device to switch the state of the first channel from an active state to a non-active state. Using this method, the sleep time of the first channel can be effectively reduced, thereby effectively improving energy efficiency.

[0016] In one possible implementation, before sending the first RAM to the second device, or in other words, before sending the aforementioned N RAMs to the second device, the first device may send a first indication message to the second device. This first indication message instructs the second device to stop receiving data sent by the first device through the first channel after receiving the first RAM. In one example, to ensure the reliability of the first indication message, the first device may send multiple first indication messages to the second device; for example, the first device may send three first indication messages to the second device. Correspondingly, after receiving the first indication message, the second device may continue receiving the aforementioned N RAMs and lock them, so as to stop receiving data sent by the first device through the first channel after receiving the first RAM.

[0017] In one possible implementation, the N RAMs sent by the first device to the second device are located within the same AM cycle. For two adjacent AM cycles sent from the first device to the second device, the N RAMs are all located between these two AM cycles. For ease of description, these two adjacent AM cycles are referred to as the first AM and the second AM, with the first AM preceding the second AM. Therefore, the aforementioned N RAMs are all located between the first AM and the second AM.

[0018] In one possible implementation, the aforementioned first indication information is also located between the first AM and the second AM, that is, the aforementioned N RAMs and the first indication information are all located within the same AM cycle. In this case, using the solution of this application, the sleep time corresponding to the first channel can be reduced to within 1 AM cycle, thereby effectively reducing the sleep time of the first channel.

[0019] In one possible implementation, the aforementioned first indication information and the aforementioned N RAMs can also be located in different AM cycles. Assuming the third AM is the AM sent from the first device to the second device preceding the first AM, the first indication information can be located between the first AM and the third AM. In this case, although the first indication information and the aforementioned N RAMs are located in different AM cycles, the interval between the first indication information and the first RAM is much smaller than two AM cycles. Therefore, in this scenario, this solution can effectively reduce the sleep time of the first channel.

[0020] In one possible implementation, for ease of description, the first of the aforementioned N RAMs is referred to as the "second RAM". In one example, the first indication information may also indicate the data length between the first RAM and the second RAM. In this way, the second device can determine the timing to start receiving the aforementioned N RAMs and locking the second RAM based on the data length between the first RAM and the second RAM, so that the second device can receive and lock the N RAMs sent by the second device.

[0021] In one possible implementation, a second preset length of data is spaced between the first indication information and the second RAM. This second preset length can be a pre-set default value. For example, the second preset length of data can be a second number of FEC codewords; this embodiment does not specifically limit the second number, and the second number can be a positive integer. In a scenario where the first device sends multiple first indication messages to the second device, the second preset length of data spaced between the first indication information and the second RAM can be the second preset length of data spaced between the first first indication information and the second RAM. The data spaced between the first indication information and the second RAM can be service data or IDLE data.

[0022] In one possible implementation, the first device may send the first instruction information to the second device in response to detecting a rate-reduction command. The rate-reduction command instructs the first device to reduce the rate at which it transmits data to the second device. That is, upon detecting the rate-reduction command, the first device initiates the operation of switching the first channel from an active state to a non-active state.

[0023] Secondly, this application provides a communication method applicable to a second device. The second device receives a first RAM sent by a first device. This first RAM triggers the second device to stop receiving data sent by the first device through a first channel, where the first channel is the channel through which the first device sends data to the second device. Using this solution, compared to conventional techniques where the second device triggers to stop receiving data sent by the first device through the first channel based on a received AM (Advanced Modem), the locking period of the RAM is much shorter than the locking period of the AM. Therefore, this solution allows the second device to quickly switch the first channel from an active state to a non-active state. Consequently, the first channel can quickly switch from an active state to a non-active state, effectively reducing the time required for the first channel to switch from an active state to a non-active state. Thus, given a fixed amount of time without transmission traffic on the first channel, this solution can increase the actual time the first channel is in a dormant state, thereby improving energy efficiency.

[0024] In one possible implementation, the N RAMs are spaced apart by a first preset length of data between any two adjacent RAMs.

[0025] In one possible implementation, the data of the first preset length includes: a first number of forward error correction (FEC) codewords, where the first number is a positive integer.

[0026] In one possible implementation, the first quantity is greater than or equal to 1 and less than or equal to 32.

[0027] In one possible implementation, the method further includes: in response to receiving the first RAM, stopping the reception of data sent by the first device through the first channel, so that the first channel switches to a non-working state with the first RAM as the switching boundary, thereby reducing the sleep time of the first channel and improving energy saving.

[0028] In one possible implementation, before receiving the first RAM sent by the first device, the method further includes: receiving first indication information sent by the first device, the first indication information instructing the second device to stop receiving data sent by the first device through the first channel after receiving the first RAM.

[0029] In one possible implementation, the N RAMs sent by the first device to the second device are all located between the first alignment mark AM and the second alignment mark AM, where the first AM and the second AM are two adjacent AMs.

[0030] In one possible implementation, the first indication information is located between the first AM and the second AM.

[0031] In one possible implementation, the first AM is the AM preceding the second AM, and the first indication information also indicates the data length of the interval between the first AM and the second RAM, wherein the second RAM is the first RAM among N RAMs including the first RAM.

[0032] In one possible implementation, the first indication information and the second RAM are spaced apart by a second preset length of data.

[0033] In one possible implementation, each of the N RAMs carries a sequence number, which is used by the second device to determine the number of received RAMs.

[0034] In one possible implementation, the sequence number carried in the i-th RAM sent by the first device is N-i+1, where i is an integer greater than or equal to 1 and less than or equal to N.

[0035] In one possible implementation, the serial number is carried via a countdown CD3 field or a CD7 field in RAM.

[0036] Thirdly, this application provides a communication device applied to a first device, the device comprising: a transmitting unit for transmitting a first fast alignment mark RAM to a second device, the first RAM being used to trigger the second device to stop receiving data transmitted by the first device through a first channel, the first channel being a channel through which the first device transmits data to the second device.

[0037] In one possible implementation, the sending unit is specifically configured to: send N RAMs to the second device, wherein the first RAM is the last RAM received by the second device among the N RAMs.

[0038] In one possible implementation, the N RAMs are spaced apart by a first preset length of data between any two adjacent RAMs.

[0039] In one possible implementation, the data of the first preset length includes: a first number of forward error correction (FEC) codewords, where the first number is a positive integer.

[0040] In one possible implementation, the first quantity is greater than or equal to 1 and less than or equal to 32.

[0041] In one possible implementation, the transmitting unit is further configured to stop transmitting data to the second device via the first channel in response to transmitting the first RAM to the second device.

[0042] In one possible implementation, the sending unit is further configured to send a first indication message to the second device before sending the first RAM to the second device, the first indication message indicating that the second device stops receiving data sent by the first device through the first channel after receiving the first RAM.

[0043] In one possible implementation, the N RAMs sent by the first device to the second device are all located between the first alignment mark AM and the second alignment mark AM, where the first AM and the second AM are two adjacent AMs.

[0044] In one possible implementation, the first indication information is located between the first AM and the second AM.

[0045] In one possible implementation, the first AM is the AM preceding the second AM, and the first indication information also indicates the data length of the interval between the first AM and the second RAM, wherein the second RAM is the first RAM among N RAMs including the first RAM.

[0046] In one possible implementation, the first indication information and the second RAM are spaced apart by a second preset length of data.

[0047] In one possible implementation, the sending unit is specifically configured to: in response to detecting a rate-reduction command, send the first indication information to the second device, the rate-reduction command indicating a reduction in the rate at which the first device sends data to the second device.

[0048] In one possible implementation, each of the N RAMs carries a sequence number, which is used by the second device to determine the number of received RAMs.

[0049] In one possible implementation, the sequence number carried in the i-th RAM sent by the first device is N-i+1, where i is an integer greater than or equal to 1 and less than or equal to N.

[0050] In one possible implementation, the serial number is carried via a countdown CD3 field or a CD7 field in RAM.

[0051] Fourthly, this application provides a communication device applied to a second device, the device comprising: a receiving unit for receiving a first fast alignment mark RAM sent by a first device, the first RAM being used to trigger the second device to stop receiving data sent by the first device through a first channel, the first channel being a channel through which the first device sends data to the second device.

[0052] In one possible implementation, the receiving unit is specifically configured to: receive N RAMs sent by the first device, wherein the first RAM is the last RAM received by the second device among the N RAMs.

[0053] In one possible implementation, the N RAMs are spaced apart by a first preset length of data between any two adjacent RAMs.

[0054] In one possible implementation, the data of the first preset length includes: a first number of forward error correction (FEC) codewords, where the first number is a positive integer.

[0055] In one possible implementation, the first quantity is greater than or equal to 1 and less than or equal to 32.

[0056] In one possible implementation, the receiving unit is further configured to: stop receiving data sent by the first device through the first channel in response to receiving the first RAM.

[0057] In one possible implementation, the receiving unit is further configured to receive first indication information sent by the first device before receiving the first RAM sent by the first device, the first indication information instructing the second device to stop receiving data sent by the first device through the first channel after receiving the first RAM.

[0058] In one possible implementation, the N RAMs sent by the first device to the second device are all located between the first alignment mark AM and the second alignment mark AM, where the first AM and the second AM are two adjacent AMs.

[0059] In one possible implementation, the first indication information is located between the first AM and the second AM.

[0060] In one possible implementation, the first AM is the AM preceding the second AM, and the first indication information also indicates the data length of the interval between the first AM and the second RAM, wherein the second RAM is the first RAM among N RAMs including the first RAM.

[0061] In one possible implementation, the first indication information and the second RAM are spaced apart by a second preset length of data.

[0062] In one possible implementation, each of the N RAMs carries a sequence number, which is used by the second device to determine the number of received RAMs.

[0063] In one possible implementation, the sequence number carried in the i-th RAM sent by the first device is N-i+1, where i is an integer greater than or equal to 1 and less than or equal to N.

[0064] In one possible implementation, the serial number is carried via a countdown CD3 field or a CD7 field in RAM.

[0065] Fifthly, this application provides a device including a communication interface, the communication interface being used to perform data transmission and reception operations as described in the first aspect and any one of the first aspects above; or, the communication interface being used to perform data transmission and reception operations as described in the second aspect and any one of the second aspects above.

[0066] Optionally, the device further includes a processor, the processor being configured to perform the data processing operations in the method described in the first aspect and any one of the first aspects above; or, the processor being configured to perform the data processing operations in the method described in the second aspect and any one of the second aspects above.

[0067] In one possible implementation, the device further includes a memory for storing instructions or computer programs, and the processor for executing the instructions or computer programs in the memory to trigger the method described in the first aspect above and any one of the first aspects above; or, the processor is configured to execute the instructions or computer programs in the memory to perform the method described in the second aspect above and any one of the second aspects above.

[0068] In a sixth aspect, this application provides a communication device, the communication device including an interface circuit, the interface circuit being used to perform data transmission and reception operations in the methods described in the first aspect and any one of the first aspects above; or, the interface circuit being used to perform data transmission and reception operations in the methods described in the second aspect and any one of the second aspects above.

[0069] Optionally, the communication device further includes a processing circuit, which is configured to perform the data processing operation in the method described in the first aspect and any one of the first aspects above; or, the processing circuit is configured to perform the data processing operation in the method described in the second aspect and any one of the second aspects above.

[0070] In one example, the communication device is a network device, a chip, or an optical module, and the chip may be, for example, a PHY chip.

[0071] In a seventh aspect, this application provides a computer-readable storage medium, including instructions or a computer program that, when run on a computer, causes the computer to perform the methods described in the first aspect and any one of the first aspects above, or, when run on a computer, causes the computer to perform the methods described in the second aspect and any one of the second aspects above.

[0072] Eighthly, this application provides a computer program product comprising instructions or a computer program, which, when run on a computer, causes the computer to perform the methods described in the first aspect and any one of the first aspects above, or causes the computer to perform the methods described in the second aspect and any one of the second aspects above.

[0073] Ninthly, this application provides a communication system, including a first device for performing the method described in the first aspect and any one of the first aspects above, and a second device for performing the method described in the second aspect and any one of the second aspects above.

[0074] In a tenth aspect, embodiments of this application provide a chip system for performing the methods described in the first aspect and any one of the first aspects above, or for performing the methods described in the second aspect and any one of the second aspects above. Attached Figure Description

[0075] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0076] Figure 1a shows a schematic diagram of a transmitting end device and a receiving end device;

[0077] Figure 1b shows a schematic diagram of a scenario using EEE technology;

[0078] Figure 1c shows a schematic diagram of a channel-level energy-saving scheme;

[0079] Figure 1d shows a schematic diagram of a process for switching a channel from an active state to an inactive state;

[0080] Figure 2a is a schematic diagram of an exemplary application scenario of an embodiment of this application;

[0081] Figure 2b is a schematic diagram of another exemplary application scenario of the present application embodiment;

[0082] Figure 2c is a schematic diagram of another exemplary application scenario of this application embodiment;

[0083] Figure 3 is a schematic diagram of signaling interaction of a communication method provided in an embodiment of this application;

[0084] Figure 4a shows a schematic diagram of a RAM structure;

[0085] Figure 4b is a schematic diagram of data sent from a first device to a second device according to an embodiment of this application;

[0086] Figure 4c is a schematic diagram of data sent from a first device to a second device according to another embodiment of this application;

[0087] Figure 4d is a schematic diagram of a two-layer frame carrying first indication information provided in an embodiment of this application;

[0088] Figure 5a is a schematic diagram of a first device performing channel state switching according to an embodiment of this application;

[0089] Figure 5b is a schematic diagram of a channel state switching state performed by a second device according to an embodiment of this application;

[0090] Figure 5c is a schematic diagram of a first device performing channel state switching according to an embodiment of this application;

[0091] Figure 5d is a schematic diagram of a channel state switching state performed by a second device according to an embodiment of this application;

[0092] Figure 6 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0093] Figure 7 is a schematic diagram of another communication device provided in an embodiment of this application;

[0094] Figure 8 is a schematic diagram of another communication device provided in an embodiment of this application;

[0095] Figure 9 is a schematic diagram of the structure of a device provided in an embodiment of this application. Detailed Implementation

[0096] This application provides a communication method and apparatus that, based on a channel-level energy-saving control scheme, reduces the time required to switch a channel from an active state to a non-active state, thereby improving energy-saving performance.

[0097] The device mentioned in the embodiments of this application can be an Ethernet interface or a device including an Ethernet interface. A device including an Ethernet interface can be, for example, a network device including an Ethernet interface, or a component (e.g., a chip or board) on a network device including an Ethernet interface. This application does not specifically limit the scope of the device.

[0098] The Ethernet interface mentioned in this application embodiment includes an Ethernet media access control (MAC) layer device and a physical layer (PHY) device that support data transmission at a certain rate. Refer to Figure 1a for understanding; Figure 1a shows a schematic diagram of a transmitting end device and a receiving end device. Both the transmitting end device and the receiving end device include an Ethernet interface. The transmitting end device refers to the communication device acting as a data sender, and the receiving end device refers to the communication device acting as a data receiver. Considering that data traffic is bidirectional, the roles of the transmitting end device and the receiving end device shown in Figure 1a can be interchanged in some other scenarios.

[0099] As shown in Figure 1a, both the transmitting and receiving devices include a MAC layer (referred to as MAC in Figure 1a) and a physical layer (referred to as PHY in Figure 1a). The physical layer includes a physical coding sublayer (PCS), a physical medium attachment (PMA), and a physical medium dependent (PMD). PCS, PMA, and PMD are PHY devices. Additionally, a reconciliation sublayer (RS) may be included between the MAC layer and the physical layer. RS and PCS can communicate via a medium independent interface (MII) channel. The MII channel can be a virtual or logical channel. In some scenarios, PCS may also be referred to as FEC.

[0100] In one example, the aforementioned MAC layer device can be a MAC chip, and the physical layer device can be a PHY chip.

[0101] In another example, the aforementioned MAC layer device and physical layer device can be different functional circuits on the same chip.

[0102] When transmitting data, communication devices can process the data according to the seven-layer model of Open Systems Interconnection (OSI). The first layer of the OSI seven-layer model is the Physical Layer, the second layer is the Data Link Layer, and the Data Link Layer includes the MAC layer. The Physical Layer can include the aforementioned PCS, PMA, and PMD.

[0103] The MAC layer of the transmitting device can generate MAC frames. The MAC layer of the transmitting device sends the MAC frames to the physical layer of the transmitting device. In scenarios where an RS is included between the MAC layer and the physical layer, the RS can convert the serial MAC frames into a parallel data stream and pass the data stream to the PCS through the MII channel.

[0104] The PCS can process the data stream received through the MII channel. In a specific example, the PCS can first encode (e.g., 64B / 66B encoding) and rate match the data stream, and then transcode (e.g., 256B / 257B transcoding) the encoded and rate-matched data stream. Further, scrambling is performed on the transcoded data stream. After scrambling, alignment marker (AM) insertion is performed on the scrambled data stream to add AM. After adding AM, forward error correction (FEC) encoding is performed on the AM-encoded data stream, and interleaving and distribution are performed on the FEC-encoded data to distribute the interleaved data to m PCS lanes connected to the PMA, where "PCS lane" can be abbreviated as "PCSL". In one example, FEC encoding can be performed using Reed-Solomon (RS) codes. "FEC encoding using RS codes" can also be called RS-FEC encoding. Correspondingly, the FEC codewords obtained by encoding can be called RS-FEC codewords.

[0105] Currently, the bandwidth of a single PCSL is 25Gbps. For a 100GE Ethernet interface, the number of PCSLs is 4; for a 200GE Ethernet interface, the number of PCSLs is 8; for a 400GE Ethernet interface, the number of PCSLs is 16; and for an 800GE Ethernet interface, the number of PCSLs is 32.

[0106] PMA can perform m:n bit multiplexing on data from PCS (i.e., data from m PCSLs), mapping the data transmitted in the m PCSLs to n physical channels, so that the data carried by these n physical channels can be subsequently sent to the receiving device. The n physical channels can be physical channels connecting the transmitting and receiving devices. The n physical channels can also be internal physical channels of the transmitting device, such as attachment unit interfaces (AUIs). When the n physical channels are internal physical channels of the transmitting device, the transmitting device can further map the data on the internal physical channels of the transmitting device to the physical channels connecting the transmitting and receiving devices to send the data to the receiving device. Wherein:

[0107] The AUI (Automatic Interface) can be, for example, a serdes. The physical channel connecting the transmitting and receiving devices can be a serializer / deserializer (serdes), an optical channel, or an electrical channel. An optical channel can be, for example, an optical fiber, and an electrical channel can be, for example, a cable.

[0108] The physical layer of the receiving device also includes PMD, PMA, and PCS. The operations performed by the physical layer of the receiving device are the inverse operations performed by the physical layer of the data sending device, which will not be described in detail here.

[0109] In another example, although not shown in Figure 1a, both the transmitting and receiving devices may include two parts or two PMAs. Assuming the transmitting (or receiving) device includes PMA1 and PMA2, ​​PMA1 connects to the PCS and PMA2, ​​and PMA2 connects to PMA1 and PMD. The PMA and PMD can be interconnected via an AUI, which includes, but is not limited to, SerDes. The PMD and PMA2 connected to it may belong to the PHY module or other modules, such as optical modules or other electrical modules; this is not limited here.

[0110] In the Ethernet protocol defined by the IEEE standard, when traffic is low, Energy-Efficient Ethernet (EEE) technology is used to put the physical layer into a low-power idle (LPI) mode to save power. Specifically, EEE technology specifies that after a task is completed, some power-consuming components of the PHY layer of the Ethernet interface are turned off to save energy, and the turned-off power-consuming components are woken up before the next task arrives.

[0111] Please refer to Figure 1b, which shows a schematic diagram of a scenario for EEE technology.

[0112] As shown in Figure 1b, "active" indicates that the transmitting device is sending data to the receiving device, and "idle" indicates that the transmitting device is not sending data to the receiving device. In Figure 1b, Ts is the time it takes for the energy-consuming element to enter the sleep state from the working state (i.e., sleep time), Tw is the time it takes for the energy-consuming element to switch from the sleep state to the working state (i.e., wake-up time), and Tq is the energy-saving time that the energy-consuming element can achieve when it is actually in the sleep state.

[0113] It's easy to understand that, given a fixed IDLE time, a larger Ts+Tw results in a smaller actual energy-saving time Tq, and consequently, a worse energy-saving effect. Conversely, a smaller Ts+Tw results in a larger actual energy-saving time Tq, and consequently, a better energy-saving effect. When Ts+Tw = 0, the ideal 0 bits and 0 watts can be achieved, meaning energy consumption is directly proportional to link utilization.

[0114] However, due to limitations in device materials and manufacturing processes, it is difficult to achieve Ts+Tw=0. IEEE 802.3 has standardized a series of Ethernet interfaces. For example, the 802.3ae version released in 2002 standardized the EEE of the 10G BASE-T interface, requiring Ts=2.56 microseconds (us) and Tw=4.88us, that is: Ts+Tw=52.56us.

[0115] With Ts+Tw = 52.56µs, when network utilization is 10%, the energy consumption is equivalent to 88% of that when network utilization is 100%, resulting in poor energy saving. When network utilization is 20%, the energy consumption is equivalent to 81% of that when network utilization is 100%, also resulting in poor energy saving. When network utilization is 30%, the energy consumption is the same as that when network utilization is 100%, with almost no energy saving. The energy consumption mentioned here can include the energy consumption of the transmitting device and / or the energy consumption of the receiving device.

[0116] For a BASE-R optical link with a rate of 100 gigabits per second (Gbps), when Ts+Tw = 52.56us, the energy consumption level of a network utilization rate of 30% is equivalent to that of a network utilization rate of 100%, resulting in no energy saving effect; even if the network utilization rate is 2%, the energy consumption level is equivalent to 81% of the energy consumption of a network utilization rate of 100%.

[0117] Moreover, the higher the Ethernet interface speed, the smaller the Ts+Tw value needs to be to achieve energy saving. However, due to limitations in device materials and processes, it is difficult to guarantee a smaller Ts+Tw value.

[0118] In conclusion, current EEE technology does not perform well in terms of energy saving.

[0119] To improve the energy efficiency of communication devices, a channel-level energy-saving control method can be adopted in one example. Specifically, flexible lane (FlexLane) technology can be used, which allows some channels to be shut down to save energy when traffic is low. Refer to Figure 1c for understanding; Figure 1c shows a schematic diagram of a channel-level energy-saving scheme. As shown in Figure 1c, FlexLane technology divides the Ethernet interface into multiple channels. Figure 1c shows four channels, which are referred to here as virtual channels or logical channels. When traffic is high, more channels can be opened to transmit traffic; when traffic is low, some channels can be shut down to save energy. In some scenarios, the channels obtained by dividing the Ethernet interface can also be called sub-physical layers (subPHYs). That is, in this application, a subPHY is a logical channel obtained by dividing the Ethernet interface. For example, a 400GE Ethernet interface can be divided into four subPHYs, each with a rate of 100Gbps.

[0120] As described above in Figure 1b, both opening and closing the channel require a certain amount of time. The channel opening time corresponds to Tw, and the channel closing time corresponds to Ts. Due to factors such as the manufacturing process of the devices corresponding to the channel, Tw + Ts is rarely equal to 0, resulting in poor energy-saving performance of the flexible lane technology. However, reducing Tw + Ts can improve the energy-saving effect of the flexible lane technology.

[0121] Currently, when it is necessary to switch a channel from an active state to an inactive state, the transmitting and receiving devices can trigger the switch based on the AM boundary. Refer to Figure 1d for understanding; Figure 1d illustrates a flowchart of a channel switching process from an active to an inactive state. Figure 1d uses an example with four active channels between the transmitting and receiving devices, showing the data streams transmitted on the subPHY of the transmitting device and the subPHY of the receiving device.

[0122] As shown in Figure 1d:

[0123] After receiving the power-saving command, the transmitting device sends anchor messages to the receiving device via its Ethernet interface. The transmitting device's Ethernet interface can send multiple anchor messages (Figure 1d shows three). Based on these anchor messages, the channel state switch is completed after A AMs (default A=2). Specifically, the transmitting device can stop sending data streams through the channel (subPHY) that needs to be switched to a non-working state when sending the Ath AM after sending the anchor messages. Correspondingly, the receiving device stops receiving data through the channel that needs to be switched to a non-working state when receiving the Ath AM after receiving the anchor messages.

[0124] However, using the scheme shown in Figure 1d, the time (Ts) required from receiving the energy-saving command to the channel completing the switch from the working state to the non-working state is relatively long, approaching the time corresponding to two AM cycles. Assuming the channel (e.g., subPHY) rate is 50Gbps, a complete AM cycle corresponds to 2048 code words (CWs), each CW being 5440 bits, then Ts = 2048 * 5440 * 2 / 50 = 222.8 μs; assuming the channel rate is 100Gbps, a complete AM cycle corresponds to 2048 CWs, each CW being 5440 bits, then Ts = 2048 * 5440 * 2 / 100 = 111.4 μs. In other words, the Ts corresponding to the channel is on the order of hundreds of microseconds, which is quite long, resulting in poor energy-saving performance of FlexLane technology.

[0125] In view of this, embodiments of this application provide an energy-saving solution and device that can reduce the Ts of the channel, thereby improving the energy-saving effect.

[0126] Before introducing the solutions provided in the embodiments of this application, we will first introduce the possible application scenarios of this application.

[0127] Referring to Figures 2a to 2c, which illustrate three exemplary application scenarios of embodiments of this application.

[0128] As shown in Figure 2a, the transmitting and receiving devices are interconnected via SERDES. Both the transmitting and receiving devices include a MAC layer module, a PCS module, and a PMA module. The interconnection method shown in Figure 2a can be applied to scenarios such as chip interconnection, device interconnection, and board interconnection.

[0129] As shown in Figure 2b, the transmitting and receiving devices are interconnected via an optical lane. Both the transmitting and receiving devices include a MAC layer module, a PCS module, a PMA module, and an optical module. In both the transmitting and receiving devices, the PMA module and optical module are interconnected via SERDES. The optical module of the transmitting device includes a DSP, a driver, and a laser diode (LD). The optical module of the receiving device includes a photodiode (PD), a trans-impedance amplifier (TIA), and a DSP. The interconnection method shown in Figure 2b can be applied to short-distance or medium-distance optical interconnects. The DSP in the optical module can, for example, be an optical digital signal processor (oDSP). The optical module can be either a pluggable or non-pluggable type; this embodiment does not limit the type. Furthermore, this embodiment does not limit the speed of the optical module.

[0130] The difference between the scenario shown in Figure 2c and the scenario shown in Figure 2b is that neither the optical module of the transmitting device nor the optical module of the receiving device includes a DSP. The interconnection method shown in Figure 2c can be applied to short-distance optical interconnection.

[0131] In the scenarios shown in Figures 2a to 2c, both the transmitting and receiving devices can be network devices, such as switches or routers.

[0132] It should be noted that Figures 2a to 2c show three possible application scenarios, but the application scenarios of this solution are not limited to these three scenarios.

[0133] Next, referring to Figure 3, the communication method provided in the embodiments of this application will be described. Figure 3 is a schematic diagram of signaling interaction of a communication method provided in an embodiment of this application.

[0134] The method shown in Figure 3 can be applied to any of the application scenarios in Figures 2a to 2c. The first device in Figure 3 corresponds to the transmitting device in Figures 2a to 2c, and the second device in Figure 3 corresponds to the receiving device in Figures 2a to 2c. Wherein:

[0135] The first device corresponds to the transmitting device in Figures 2a to 2c, meaning that the first device can be either the transmitting device in Figures 2a to 2c or a part of the transmitting device in Figures 2a to 2c. For example, the first device can be the transmitting device in Figure 2a; or, for example,

[0136] The first device can be the transmitting device in Figure 2b, or the first device can be a chip in the transmitting device in Figure 2b that includes MAC, PCS and PMA; for example, the first device can be the transmitting device in Figure 2c, or the first device can be a chip in the transmitting device in Figure 2c that includes MAC, PCS and PMA.

[0137] The second device corresponds to the receiving device in Figures 2a to 2c. This means that the second device can be either the receiving device in Figures 2a to 2c or a part of the receiving device in Figures 2a to 2c. For example, the second device can be the receiving device in Figure 2a; or, the second device can be the receiving device in Figure 2b, or, the second device can be a chip in the receiving device in Figure 2b that includes a MAC, PCS, and PMA; or, the second device can be the receiving device in Figure 2c, or, the second device can be a chip in the receiving device in Figure 2c that includes a MAC, PCS, and PMA.

[0138] The first channel mentioned in Figure 3 refers to the end-to-end channel between the transmitting device and the receiving device. As shown in Figures 2a to 2c, the end-to-end channel between the transmitting device and the receiving device can include multiple sub-channels.

[0139] In the scenario shown in Figure 2a, the multi-segment sub-channels include: a sub-channel (i.e., subPHY) between the MAC and PMA of the transmitting device, a sub-channel between TX1 and RX1, and a sub-channel (i.e., subPHY) between the MAC and PMA of the receiving device.

[0140] In the scenarios shown in Figures 2b and 2c, each of the multiple sub-channels includes: a sub-channel (i.e., subPHY) between the MAC and PMA of the transmitting device, a sub-channel between TX1 and RX1, a sub-channel between RX1 and TX2, a sub-channel between TX2 and RX2, a sub-channel between RX2 and TX3, a sub-channel between TX3 and RX3, and a sub-channel (i.e., subPHY) between the MAC and PMA of the receiving device. The method shown in Figure 3 includes the following steps S101-S102.

[0141] S101: The first device sends a first RAM to the second device. The first RAM is used to trigger the second device to stop receiving data sent by the first device through the first channel. The first channel is the channel through which the first device sends data to the second device.

[0142] S102: The second device receives the first RAM sent by the first device.

[0143] In this application, the first device sends a first RAM to the second device, and correspondingly, the second device can receive the first RAM sent by the first device. The first RAM is used to trigger the second device to stop receiving data sent by the first device through the first channel. As an example, after receiving the first RAM, the second device can, in response to receiving the first RAM, stop receiving data sent by the first device through the first channel. That is, after receiving the first RAM, the second device no longer waits for AM, but quickly stops receiving data sent by the first device through the first channel. The first RAM serves as the switching boundary for the second device to switch the state of the first channel from an active state to a non-active state.

[0144] Furthermore, after sending the first RAM, the first device can, in response to sending the first RAM to the second device, stop sending data to the second device through the first channel. That is, after sending the first RAM, the first device no longer waits for AM, but quickly stops sending data to the second device through the first channel. The first RAM serves as the switching boundary for the first device to switch the state of the first channel from the working state to the non-working state.

[0145] In one example, the second device ceasing to receive data transmitted by itself through the first channel may include: the second device ceasing to receive data through its own subPHY included in the first channel. Similarly, the first device ceasing to transmit data to the second device through the first channel may include: the first device ceasing to transmit data to the second device through its own subPHY included in the first channel.

[0146] It should be noted that, for the first channel, the states of the multiple sub-channels included in the first channel should be consistent. This application does not limit the state switching control method for the other sub-channels included in the first channel besides the subPHY of the first device and the subPHY of the second device.

[0147] In one example, to ensure the reliability of channel state switching, the first device can send N RAMs to the second device. The first RAM can be the last RAM sent by the first device among the N RAMs. The first RAM is also the last RAM among the N RAMs received by the second device. That is, the first device sends N RAMs to the second device, and the last RAM among these N RAMs serves as the switching boundary between the first and second devices for switching the first channel from an active state to a non-active state. Both devices switch based on the same switching boundary, allowing the first channel to quickly complete the switch from an active state to a non-active state after the second device receives the first RAM.

[0148] The embodiments of this application do not specifically limit the specific value of N. N can be an integer greater than or equal to 2. For example, the value of N can be 36.

[0149] In this application, each of the N RAMs has the same structure. As an example, the RAM is a bit block of a specific length, for example, the length of the RAM is 120 bits. In one example, the structure of the RAM can be as shown in Figure 4a, which shows a schematic diagram of a RAM structure. The RAM structure shown in Figure 4a is modified based on the AM structure corresponding to 200G specified in IEEE 802.3. Specifically, the positions of CM3-CM5 and CM0-CM2 in the AM corresponding to 200G are interchanged, UP0 in the AM corresponding to 200G is modified to CD7, and UP1 in the AM corresponding to 200G is modified to CD3, thus obtaining the AM shown in Figure 4a.

[0150] In one example, each of the N RAMs carries a sequence number, which is used by the second device to determine the number of RAMs received. That is, the second device can determine the number of RAMs it has received based on the sequence numbers in the received RAMs. In this way, when the second device has received N RAMs, it can stop receiving data through the first channel in response to receiving the last RAM (i.e., the first RAM).

[0151] In a specific example, the sequence number carried in the i-th RAM sent by the first device is N-i+1, where i is an integer greater than or equal to 1 and less than or equal to N. Taking N as 36 as an example, the first RAM sent by the first device carries sequence number 36, the second RAM sent by the first device carries sequence number 35, and so on, with the 35th RAM sent by the first device carrying sequence number 2, and the 36th RAM sent by the first device carrying sequence number 1. In this scenario, the second device can have consecutive sequence numbers in the N RAMs it receives, and upon receiving the RAM with sequence number 1 (i.e., the first RAM), it stops receiving data through the first channel in response to receiving the first RAM.

[0152] In another example, the sequence number carried in the i-th RAM sent by the first device is i, where i is an integer greater than or equal to 1 and less than or equal to N. Taking N as 36 as an example, the first RAM sent by the first device carries sequence number 1, the second RAM sent by the first device carries sequence number 2, and so on, with the 35th RAM sent by the first device carrying sequence number 35, and the 36th RAM sent by the first device carrying sequence number 36. In this scenario, the second device can have consecutive sequence numbers in the N RAMs it receives, and upon receiving the RAM with sequence number 36 (i.e., the first RAM), it stops receiving data through the first channel in response to receiving the first RAM.

[0153] In this application, for any RAM, the serial number carried by the RAM can be carried through any available field in the RAM. In one example, when the RAM includes CD3 and CD7 fields, for example, when the RAM adopts the structure shown in Figure 4a, the serial number can be carried by either the CD3 field or the CD7 field. In one example, there can be a certain relationship between the value carried by the CD3 field and the value carried by the CD7 field. For example, the value carried by the CD3 field can be obtained by inverting each bit of the CD7 field. For example, if the value carried by the CD3 field is 00000100, then the value carried by the CD7 field is 1111011.

[0154] In this application, the first device can send the N RAMs to the second device through multiple channels between the first device and the second device, all of which are active channels. That is, the first device can send N RAMs to the second device through each of these multiple channels. Correspondingly, the second device can receive N RAMs through each of these multiple channels. For any RAM (referred to as a third RAM) sent by the first device through these multiple channels, after receiving the third RAM through each of these multiple channels, the second device can perform deskew on the received third RAMs to align them with the multiple channels. Similarly, after receiving multiple first RAMs through these multiple channels, the second device can perform deskew on the received first RAMs to align them with the multiple channels, and after aligning the multiple channels, the second device can stop receiving data through the first channels.

[0155] In one example, the data sent by the first device between any two adjacent RAMs of the N RAMs is spaced out by a first preset length. The data between any two RAMs can be service data or idle data (IDLE), and this embodiment of the application does not specifically limit this. As a concrete example, if the first device is sending service data to the second device within the time interval between any two RAMs, then the data between any two RAMs is service data; if the first device has no service data to send to the second device within the time interval between any two RAMs, then the data between any two RAMs is IDLE.

[0156] This application does not specifically limit the first preset length. The first preset length can be determined, for example, based on the correction capability of the second device. Specifically, the first preset length can be a length that ensures the second device can successfully perform correction on multiple of the aforementioned third RAMs. The first device can, for example, negotiate its capabilities with the second device to determine the first preset length.

[0157] In one example, the data of the first preset length may include a preset number of bits, or the data of the first preset length may include a first number of FEC codewords. The first number is a positive integer. This application does not specifically limit the first number; as long as the interval between two adjacent RAMs is the first number of FEC codewords, it can ensure that the second device can successfully perform bias correction on multiple of the aforementioned third RAMs. As a specific example, the first number can be an integer greater than or equal to 1 and less than or equal to 32, for example, the first number is 8, or 4, or 2.

[0158] In one example, before executing S101, the first device may also send a first indication message to the second device, the first indication message instructing the second device to stop receiving data sent by the first device through the first channel after receiving the first RAM. In one example, to ensure the reliability of the first indication message, the first device may send multiple first indication messages to the second device, for example, the first device may send three first indication messages to the second device.

[0159] After receiving the multiple first instruction messages, the second device can further receive the aforementioned N RAMs, and after receiving the aforementioned first RAMs, it quickly stops receiving data through the first channel.

[0160] In one example, the first device may send the first indication information to the second device in response to detecting a rate-down command. The rate-down command indicates a reduction in the rate at which the first device sends data to the second device. This application does not specifically limit the content of the rate-down command; in one example, the rate-down command may include a target rate, where the target rate is the rate at which the first device sends data to the second device after performing the rate-down operation. This application also does not specifically limit the object that generates the rate-down command; in one example, the rate-down command may be generated by a controller; in another example, the rate-down command may be generated by the processor of the network device to which the first device belongs, which will not be described in detail here.

[0161] In one example, the N RAMs sent by the first device to the second device are located within the same AM cycle. For two adjacent AMs sent by the first device to the second device, the N RAMs are all located between these two AMs. For ease of description, these two adjacent AMs are referred to as the first AM and the second AM, respectively. The first AM is the AM preceding the second AM; that is, the first device first sends the first AM to the second device, and after sending the first AM, it sends the second AM. Therefore, the aforementioned N RAMs are all located between the first AM and the second AM.

[0162] In one example, the aforementioned first indication information is also located between the first AM and the second AM, that is, the aforementioned N RAMs and the first indication information are all located within the same AM cycle. In this case, the solution of the present application embodiment can reduce the sleep time corresponding to the first channel to within 1 AM cycle, thereby effectively reducing the sleep time of the first channel.

[0163] In another example, the aforementioned first indication information and the aforementioned N RAMs can also be located in different AM cycles. Assuming the third AM is the AM sent from the first device to the second device, preceding the first AM, the first indication information can be located between the first AM and the third AM. In this case, although the first indication information and the aforementioned N RAMs are located in different AM cycles, the interval between the first indication information and the first RAM is much smaller than two AM cycles. Therefore, in this scenario, this solution can effectively reduce the sleep time of the first channel.

[0164] This application does not specifically limit the content of the first indication information. In one example, the first indication information includes at least information for indicating that the first channel is switched from a working state to a non-working state.

[0165] In another example, for ease of description, the first of the aforementioned N RAMs will be referred to as the "second RAM". In one example, the first indication information may also indicate the data length between the first RAM and the second RAM. In this way, the second device can determine the timing for starting to receive the aforementioned N RAMs and locking the second RAM based on the data length between the first RAM and the second RAM, so that the second device can receive and lock the N RAMs sent by the second device.

[0166] Regarding the second device locking RAM, its principle is the same as that of the second device locking AM. Both involve matching specific fields in RAM with a preset pattern. For example, matching the 48 bits of data CM3-CM5 and CM0-CM2 in RAM with the preset pattern. If the match is successful, it indicates that RAM locking is successful. In this application, although the principle of RAM locking is the same as that of AM locking, the structure of RAM in this application is different from that of AM. Therefore, the fields used for RAM locking and AM locking will also be different. Correspondingly, the preset pattern used for RAM locking is also different from that used for AM locking.

[0167] In one example, the data between the first indication information and the second RAM is spaced by a second preset length. This second preset length can be a pre-set default value. For example, the data of the second preset length can be a second number of FEC codewords. This embodiment does not specifically limit the second number; the second number can be a positive integer. As a specific example, the second number can be an integer greater than or equal to 30 and less than or equal to 50; for example, the second number can be 40. In a scenario where the first device sends multiple first indication messages to the second device, the data between the first indication information and the second RAM spaced by the second preset length can be the data between the first first indication information and the second RAM spaced by the second preset length.

[0168] In one example, the data length between the aforementioned first RAM and the second RAM can be calculated by the first device when sending the aforementioned first indication information. Refer to Figures 4b and 4c for further understanding. Figure 4b is a schematic diagram of data sent from a first device to a second device according to an embodiment of this application. Figure 4c is a schematic diagram of data sent from a first device to a second device according to another embodiment of this application.

[0169] As shown in Figure 4b, which illustrates the example where the first indication information and N RAMs are all located in the same AM cycle, the first device sends three first indication messages to the second device, followed by the sending of N RAMs. When sending the first indication message to the second device, the first device can determine the interval 401 between the first AM and the first indication message. Correspondingly, the interval 402 between the first indication message and the second RAM is fixed (e.g., 40 FEC codewords). Therefore, based on intervals 401 and 402, the first device can determine the data length 403 of the interval between the first AM and the second RAM. Specifically, the data length 403 of the interval between the first AM and the second RAM is equal to the sum of 402 and 401.

[0170] As shown in Figure 4c, which illustrates the example where the first indication information and N RAMs are located in different AM cycles, the first device sends three first indication messages to the second device, followed by the sending of N RAMs. When sending the first indication message to the second device, the first device can determine the interval 404 between the first AM and the first indication message. Correspondingly, the interval 405 between the first indication message and the second RAM is fixed (e.g., 40 FEC codewords). Therefore, based on intervals 404 and 405, the first device can determine the data length 406 of the interval between the first AM and the second RAM. Specifically, the data length 406 of the interval between the first AM and the second RAM is equal to 405 minus 404.

[0171] This application does not specifically limit the message format carrying the first indication information. In one example, the first indication information can be carried by a MAC frame. Refer to Figure 4d for understanding. Figure 4d is a schematic diagram of a Layer 2 frame structure carrying the first indication information provided by this application embodiment. As shown in Figure 4d, the Layer 2 frame includes: a PREAMBLE field, a start Frame delimiter (SFD) field, a reserved field, a message field (MSG_FIELD), a padding field, and a frame check sequence (FCS) field. Wherein:

[0172] The PREAMBLE field can have a value of 7B, which is defined by the standard Ethernet standard and will not be repeated here.

[0173] The SFD field is used to indicate that the Layer 2 frame is used for FlexLane negotiation, and the value of this field can be, for example, 0x3B.

[0174] Both reserved and padding are reserved.

[0175] The FCS field carries the Frame Check Sequence. The value of this field is determined in the same way as in standard Ethernet, and will not be repeated here. When either the first or second device does not support the FCS function, the value of this field is 0.

[0176] The MSG_FIELD field is used to carry first indication information, as shown in Figure 4b. The MSG_FIELD field includes:

[0177] The Message Type (MSG_TYPE) field indicates that the message indicates a speed reduction, that is, switching the channel from an active state to a non-active state.

[0178] The SubPHYStatInd (SPSI) field consists of multiple bits, each indicating the status of a subPHY. Bit 0 corresponds to the smallest subPHY number. A bit value of 1 indicates that the corresponding subPHY is in an active state, while a bit value of 0 indicates that the corresponding subPHY is switched to a non-active state.

[0179] The codeword count (CWCnt) field carries the number of FEC codewords between the aforementioned first AM and second RAM.

[0180] Reserved field, currently undefined. Based on the method provided in the above embodiments,

[0181] Next, with reference to Figures 5a and 5b, a possible embodiment of the present application will be described.

[0182] Figure 5a is a schematic diagram of a first device performing channel state switching according to an embodiment of this application. Figure 5b is a schematic diagram of a second device performing channel state switching according to an embodiment of this application.

[0183] As shown in Figures 5a and 5b, there are four end-to-end channels in operation between the first device and the second device. Figure 5a shows the four subPHYs corresponding to the first device in these four channels, and Figure 5b shows the four subPHYs corresponding to the second device in these four channels.

[0184] As shown in Figure 5a:

[0185] 1. The first device detects the speed reduction command and initiates the speed reduction operation to reduce the number of channels used for data transmission.

[0186] 2. The first device sends three first instruction messages to the second device, and plans to perform a boundary switch on the last RAM of the 36 RAMs following the first instruction messages.

[0187] 3. After sending three first instruction messages to the second device, the first device sends 36 RAMs to the second device. After the last RAM (corresponding to the first RAM in the above embodiment) is sent, the first device performs a switching operation and stops sending data streams on the subPHY to be shut down (corresponding to the first channel in the above embodiment).

[0188] As shown in Figure 5b:

[0189] 1. The second device receives the first instruction information and starts preparing to receive subsequent RAM.

[0190] 2. The second device receives RAM. The second device determines that it has received 36 RAMs. When the last RAM is received, the last received RAM (corresponding to the first RAM in the above embodiment) is used as the switching boundary to stop receiving data stream from the subPHY to be shut down (corresponding to the first channel in the above embodiment).

[0191] For the schemes shown in Figures 5a and 5b, the data length L between the first device sending the first indication information and sending the last RAM is: 3 * length of the first indication information + a1 * CWs + 40 * CWs + 36 * RAMs + 35 * a2 * CWs, where:

[0192] a1 is the number of FEC codewords between two adjacent first indication messages, and its value can be 2.

[0193] 40*CWs represents the data length between the first indication message and the first RAM.

[0194] 36*RAMs indicates a data length of 36 RAM bytes.

[0195] a2 represents the data length between two adjacent RAMs, and its value can be 2.

[0196] When the subPHY rate is 50Gbps, the duration corresponding to L is approximately 12.2 microseconds. When the subPHY rate is 100Gbps, the duration corresponding to L is approximately 6.1 microseconds.

[0197] As described above, the solution of this application embodiment, compared to the conventional technology where the second device stops receiving data sent by the first device through the first channel based on the received AM trigger, utilizes a solution where the RAM's locking period is much shorter than the AM's locking period. Therefore, this solution allows the second device to quickly switch the first channel from an active state to a non-active state. Consequently, the first channel can quickly switch from an active state to a non-active state, effectively reducing the time required for the first channel to switch from an active state to a non-active state, thus improving energy efficiency. As shown in Figures 5a and 5b, this solution can reduce the sleep time of the first channel from the traditional hundreds of microseconds to the tens of microseconds or even microseconds.

[0198] Figures 5c and 5d illustrate another possible embodiment of the present application. The flow executed by the first device in Figure 5c is the same as that executed by the first device in Figure 5a, and the flow executed by the second device in Figure 5d is the same as that executed by the second device in Figure 5b. The difference is that in the embodiments corresponding to Figures 5a and 5b, the 36 RAMs and 3 first indication information are located in the same AM cycle. However, in the embodiments shown in Figures 5c and 5d, the 36 RAMs and 3 first indication information are located in different AM cycles.

[0199] For the steps performed by the first device in Figure 5c, please refer to the description of Figure 5a above, and it will not be repeated here; for the steps performed by the second device in Figure 5d, please refer to the description of the corresponding Figure 5b above, and it will not be repeated here.

[0200] Based on the communication method provided in the above embodiments, this application also provides a corresponding communication device, which will be described below with reference to the accompanying drawings.

[0201] Referring to Figure 6, this figure is a schematic diagram of the structure of a communication device provided in an embodiment of this application. The communication device 600 shown in Figure 6 is applied to a first device and is used to perform the steps performed by the first device as provided in the above embodiments.

[0202] As shown in Figure 6, the communication device 600 includes a transmitting unit 601 and a processing unit 602, wherein the processing unit 602 is optional.

[0203] The sending unit 601 is used to send a first fast alignment mark RAM to the second device. The first RAM is used to trigger the second device to stop receiving data sent by the first device through the first channel. The first channel is the channel through which the first device sends data to the second device.

[0204] Optionally, the processing unit 602 is used to insert the first RAM.

[0205] In one possible implementation, the sending unit 601 is specifically configured to: send N RAMs to the second device, wherein the first RAM is the last RAM received by the second device among the N RAMs.

[0206] In one possible implementation, the N RAMs are spaced apart by a first preset length of data between any two adjacent RAMs.

[0207] In one possible implementation, the data of the first preset length includes: a first number of forward error correction (FEC) codewords, where the first number is a positive integer.

[0208] In one possible implementation, the first quantity is greater than or equal to 1 and less than or equal to 32.

[0209] In one possible implementation, the sending unit 601 is further configured to stop sending data to the second device through the first channel in response to sending the first RAM to the second device.

[0210] In one possible implementation, the sending unit 601 is further configured to send a first indication message to the second device before sending the first RAM to the second device, the first indication message indicating that the second device stops receiving data sent by the first device through the first channel after receiving the first RAM.

[0211] In one possible implementation, the N RAMs sent by the first device to the second device are all located between the first alignment mark AM and the second alignment mark AM, where the first AM and the second AM are two adjacent AMs.

[0212] In one possible implementation, the first indication information is located between the first AM and the second AM.

[0213] In one possible implementation, the first AM is the AM preceding the second AM, and the first indication information also indicates the data length of the interval between the first AM and the second RAM, wherein the second RAM is the first RAM among N RAMs including the first RAM.

[0214] In one possible implementation, the first indication information and the second RAM are spaced apart by a second preset length of data.

[0215] In one possible implementation, the sending unit 601 is specifically configured to: in response to detecting a rate-reduction command, send the first indication information to the second device, the rate-reduction command indicating a reduction in the rate at which the first device sends data to the second device.

[0216] In one possible implementation, each of the N RAMs carries a sequence number, which is used by the second device to determine the number of received RAMs.

[0217] In one possible implementation, the sequence number carried in the i-th RAM sent by the first device is N-i+1, where i is an integer greater than or equal to 1 and less than or equal to N.

[0218] In one possible implementation, the serial number is carried via a countdown CD3 field or a CD7 field in RAM.

[0219] Referring to Figure 7, this figure is a schematic diagram of another communication device provided in an embodiment of this application. The communication device 700 shown in Figure 7 is applied to a second device to perform the steps performed by the second device provided in the above embodiments.

[0220] As shown in Figure 7, the communication device 700 includes a receiving unit 701 and a processing unit 702, wherein the processing unit 702 is optional.

[0221] The receiving unit 701 is used to receive a first fast alignment mark RAM sent by the first device. The first RAM is used to trigger the second device to stop receiving data sent by the first device through a first channel. The first channel is the channel through which the first device sends data to the second device.

[0222] Optionally, the processing unit 702 is used to lock the first RAM.

[0223] In one possible implementation, the receiving unit 701 is specifically configured to: receive N RAMs sent by the first device, wherein the first RAM is the last RAM received by the second device among the N RAMs.

[0224] In one possible implementation, the N RAMs are spaced apart by a first preset length of data between any two adjacent RAMs.

[0225] In one possible implementation, the data of the first preset length includes: a first number of forward error correction (FEC) codewords, where the first number is a positive integer.

[0226] In one possible implementation, the first quantity is greater than or equal to 1 and less than or equal to 32.

[0227] In one possible implementation, the receiving unit 701 is further configured to: stop receiving data sent by the first device through the first channel in response to receiving the first RAM.

[0228] In one possible implementation, the receiving unit 701 is further configured to receive first indication information sent by the first device before receiving the first RAM sent by the first device, the first indication information instructing the second device to stop receiving data sent by the first device through the first channel after receiving the first RAM.

[0229] In one possible implementation, the N RAMs sent by the first device to the second device are all located between the first alignment mark AM and the second alignment mark AM, where the first AM and the second AM are two adjacent AMs.

[0230] In one possible implementation, the first indication information is located between the first AM and the second AM.

[0231] In one possible implementation, the first AM is the AM preceding the second AM, and the first indication information also indicates the data length of the interval between the first AM and the second RAM, wherein the second RAM is the first RAM among N RAMs including the first RAM.

[0232] In one possible implementation, the first indication information and the second RAM are spaced apart by a second preset length of data.

[0233] In one possible implementation, each of the N RAMs carries a sequence number, which is used by the second device to determine the number of received RAMs.

[0234] In one possible implementation, the sequence number carried in the i-th RAM sent by the first device is N-i+1, where i is an integer greater than or equal to 1 and less than or equal to N.

[0235] In one possible implementation, the serial number is carried via a countdown CD3 field or a CD7 field in RAM.

[0236] Referring to Figure 8, which is a schematic diagram of the structure of a communication device provided in an embodiment of this application, the communication device 800 shown in Figure 8 includes an interface circuit 801 and a processing circuit 802. The interface circuit 801 is used to receive and / or transmit data, and the processing circuit 802 is used to perform data processing. The processing circuit 802 is optional.

[0237] In a specific example, the communication device 800 is used to perform the steps performed by the first device as provided in the above embodiments. In this case:

[0238] The interface circuit 801 is used to send a first fast alignment mark RAM to the second device. The first RAM is used to trigger the second device to stop receiving data sent by the first device through the first channel. The first channel is the channel through which the first device sends data to the second device.

[0239] Optionally, the processing circuit 802 is used to insert the first RAM.

[0240] In yet another specific example, the communication device 800 is used to perform the steps provided in the above embodiments by the second device. In this case:

[0241] The interface circuit 801 is used to receive a first fast alignment mark RAM sent by the first device. The first RAM is used to trigger the second device to stop receiving data sent by the first device through the first channel. The first channel is the channel through which the first device sends data to the second device.

[0242] Optionally, the processing circuit 802 is used to lock the first RAM.

[0243] In one example, the device shown in Figure 8 may be a network device or a chip, wherein the chip may be, for example, a PHY chip.

[0244] In another example, the device shown in Figure 8 could be an optical module.

[0245] Referring to Figure 9, this figure is a schematic diagram of the structure of a device provided in an embodiment of this application.

[0246] In one example, the device 900 shown in Figure 9 can be used to perform the communication method provided in the above method embodiments.

[0247] Referring to Figure 9, the device 900 includes a processor 910 and a communication interface 920. The processor 910 is optional. The device 900 can have one or more processors 910; Figure 9 shows an example with one processor. The processor 910 is used to execute the communication method provided in the above method embodiments.

[0248] Processor 910 may be a central processing unit (CPU), an NP, or a combination of CPU and NP. Processor 910 may further include hardware chips. The aforementioned hardware chips may be ASICs, programmable logic devices (PLDs), or combinations thereof. The aforementioned PLD may be complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), generic array logic (GALs), or any combination thereof.

[0249] The communication interface 920 is used to receive and / or send data.

[0250] In a specific example, the device 900 is used to perform the steps performed by the first device as provided in the above embodiments. In this case:

[0251] The communication interface 920 is used to send a first fast alignment mark RAM to the second device. The first RAM is used to trigger the second device to stop receiving data sent by the first device through the first channel. The first channel is the channel through which the first device sends data to the second device.

[0252] Optionally, the processor 910 is used to insert the first RAM.

[0253] In yet another specific example, the device 900 is used to perform the steps provided in the above embodiments by the second device. In this case:

[0254] The communication interface 920 is used to receive a first fast alignment mark RAM sent by the first device. The first RAM is used to trigger the second device to stop receiving data sent by the first device through a first channel. The first channel is the channel through which the first device sends data to the second device.

[0255] Optionally, the processor 910 is used to lock the first RAM.

[0256] In one example, the device 900 further includes a memory 930. The memory 930 may include volatile memory, such as random-access memory (RAM); the memory 930 may also include non-volatile memory, such as flash memory, hard disk drive (HDD), or solid-state drive (SSD); the memory 930 may also include combinations of the above types of memory.

[0257] Optionally, the memory 930 stores an operating system and programs, executable modules, or data structures, or subsets thereof, or extended sets thereof. The programs may include various operation instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and handling hardware-based tasks. The processor 910 can read the programs from the memory 930 to implement the methods provided in the embodiments of this application.

[0258] In one example, the processor 910, communication interface 920, and memory 930 can be connected via a bus system or other means, with Figure 9 showing an example of connection via bus system 940.

[0259] The bus system 940 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus system 940 can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used in Figure 9, but this does not indicate that there is only one bus or one type of bus.

[0260] This application provides a computer-readable storage medium, including instructions or a computer program, which, when run on a computer, causes the computer to perform the methods described in the above method embodiments.

[0261] This application provides a computer program product containing instructions or computer programs, which, when run on a computer, causes the computer to perform the methods described in the above method embodiments.

[0262] This application also provides a communication system, which includes the first device and the second device mentioned in the above embodiments, for executing the method provided in the above embodiments by the first device and the second device.

[0263] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0264] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0265] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical business division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0266] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0267] Furthermore, the various business units in the embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software business unit.

[0268] If the integrated unit is implemented as a software business unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0269] Those skilled in the art will recognize that, in one or more of the examples above, the services described in this application can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these services can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of computer programs from one place to another. Storage media can be any available medium accessible to general-purpose or special-purpose computers.

[0270] The above specific embodiments further illustrate the purpose, technical solution and beneficial effects of this application. It should be understood that the above are only specific embodiments of this application.

[0271] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A communication method, characterized in that, Applied to a first device, the method includes: A first fast alignment mark RAM is sent to the second device. The first RAM is used to trigger the second device to stop receiving data sent by the first device through the first channel, which is the channel through which the first device sends data to the second device.

2. The method according to claim 1, characterized in that, Sending the first RAM to the second device includes: N RAMs are sent to the second device, where the first RAM is the last RAM received by the second device among the N RAMs.

3. The method according to claim 2, characterized in that, Data of a first preset length is spaced between any two adjacent RAMs in the N RAMs.

4. The method according to claim 3, characterized in that, The first preset length of data includes: The first number of forward error correction (FEC) codewords, where the first number is a positive integer.

5. The method according to claim 4, characterized in that, The first quantity is greater than or equal to 1 and less than or equal to 32.

6. The method according to any one of claims 1-5, characterized in that, The method further includes: In response to sending the first RAM to the second device, data transmission to the second device via the first channel is stopped.

7. The method according to any one of claims 1-6, characterized in that, Before sending the first RAM to the second device, the method further includes: Send a first instruction message to the second device, the first instruction message instructing the second device to stop receiving data sent by the first device through the first channel after receiving the first RAM.

8. The method according to claim 7, characterized in that, The N RAMs sent from the first device to the second device are all located between the first alignment mark AM and the second alignment mark AM, and the first AM and the second AM are two adjacent AMs.

9. The method according to claim 8, characterized in that, The first indication information is located between the first AM and the second AM.

10. The method according to claim 8 or 9, characterized in that, The first AM is the AM preceding the second AM, and the first indication information also indicates the data length of the interval between the first AM and the second RAM, wherein the second RAM is the first RAM among N RAMs including the first RAM.

11. The method according to claim 10, characterized in that, The first indication information and the second RAM are spaced apart by a second preset length of data.

12. The method according to any one of claims 7-11, characterized in that, Sending the first instruction information to the second device includes: In response to the detection of a speed reduction command, the first indication information is sent to the second device, the speed reduction command indicating a reduction in the rate at which the first device sends data to the second device.

13. The method according to any one of claims 2-5, characterized in that, Each of the N RAMs carries a serial number, which is used by the second device to determine the number of received RAMs.

14. The method according to claim 13, characterized in that, The sequence number carried in the i-th RAM sent by the first device is N-i+1, where i is an integer greater than or equal to 1 and less than or equal to N.

15. The method according to claim 13 or 14, characterized in that, The serial number is carried in the countdown CD3 field or CD7 field in RAM.

16. A communication method, characterized in that, Applied to a second device, the method includes: The device receives a first fast alignment mark RAM sent by the first device. The first RAM is used to trigger the second device to stop receiving data sent by the first device through a first channel, whereby the first channel is the channel through which the first device sends data to the second device.

17. The method according to claim 16, characterized in that, The first RAM received by the first device includes: The device receives N RAMs sent by the first device, wherein the first RAM is the last RAM received by the second device among the N RAMs.

18. The method according to claim 17, characterized in that, Data of a first preset length is spaced between any two adjacent RAMs in the N RAMs.

19. The method according to claim 18, characterized in that, The first preset length of data includes: The first number of forward error correction (FEC) codewords, where the first number is a positive integer.

20. The method according to claim 19, characterized in that, The first quantity is greater than or equal to 1 and less than or equal to 32.

21. The method according to any one of claims 16-20, characterized in that, The method further includes: In response to receiving the first RAM, the reception of data sent by the first device through the first channel is stopped.

22. The method according to any one of claims 16-21, characterized in that, Before receiving the first RAM sent by the first device, the method further includes: The device receives a first instruction message sent by the first device, which instructs the second device to stop receiving data sent by the first device through the first channel after receiving the first RAM.

23. The method according to claim 22, characterized in that, The N RAMs sent from the first device to the second device are all located between the first alignment mark AM and the second alignment mark AM, and the first AM and the second AM are two adjacent AMs.

24. The method according to claim 23, characterized in that, The first indication information is located between the first AM and the second AM.

25. The method according to claim 23 or 24, characterized in that, The first AM is the AM preceding the second AM, and the first indication information also indicates the data length of the interval between the first AM and the second RAM, wherein the second RAM is the first RAM among N RAMs including the first RAM.

26. The method according to claim 25, characterized in that, The first indication information and the second RAM are spaced apart by a second preset length of data.

27. The method according to any one of claims 17-20, characterized in that, Each of the N RAMs carries a serial number, which is used by the second device to determine the number of received RAMs.

28. The method according to claim 27, characterized in that, The sequence number carried in the i-th RAM sent by the first device is N-i+1, where i is an integer greater than or equal to 1 and less than or equal to N.

29. The method according to claim 27 or 28, characterized in that, The serial number is carried in the countdown CD3 field or CD7 field in RAM.

30. A communication device, characterized in that, It includes a processor and a communication interface, the communication interface being used to perform the receiving operation or the sending operation of any one of claims 1-29, and the processor being used to perform other operations of any one of claims 1-29 besides the receiving operation and the sending operation.

31. A communication system, characterized in that, The system includes: A first apparatus for performing the method according to any one of claims 1-15, and a second apparatus for performing the method according to any one of claims 16-29.

32. A chip, characterized in that, The chip includes an interface circuit and a processing circuit. The interface circuit is used to perform a receiving operation or a transmitting operation as described in any one of claims 1-29, and the processing circuit is used to perform other operations as described in any one of claims 1-29 besides the receiving operation and the transmitting operation.

33. A computer-readable storage medium, characterized in that, The system stores instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 1-29.

34. A computer program product, characterized in that, The computer program product includes instructions or a computer program that, when run on a computer, causes the computer to perform the method described in any one of claims 1-29.

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