A self-adjusting equal-precision frequency measurement system and method

By employing a design method that combines double-edge acquisition self-adjustment and acquisition window self-adjustment with CPLD and MCU, the problem of balancing accuracy and response time in existing speed and frequency measurement schemes is solved, achieving higher frequency measurement response speed and accuracy, and improving dynamic control performance.

CN116908536BActive Publication Date: 2026-06-26NANDA AUTOMATION TECH JIANGSU CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
NANDA AUTOMATION TECH JIANGSU CO LTD
Filing Date
2023-07-17
Publication Date
2026-06-26

AI Technical Summary

Technical Problem

Existing speed measurement frequency solutions struggle to achieve both high accuracy and fast response in both high and low frequency bands, making it difficult to balance measurement accuracy and response time, thus affecting dynamic control performance.

Method used

A design method of self-adjustment of pulse edge acquisition and acquisition window is adopted. Combined with CPLD and MCU, the acquisition of pulse edge signal and acquisition window length are automatically adjusted through PLL phase-locked loop module, parallel communication module, pulse filtering module and counting acquisition module, thereby improving frequency measurement response time and accuracy.

Benefits of technology

While ensuring frequency measurement accuracy, the frequency measurement response time has been improved, up to double, to meet the high control requirements of speed equipment in industrial settings and enhance dynamic control performance.

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Abstract

The present application relates to the technical field of frequency measurement system and method, and discloses a kind of based on self-adjusting equal-precision frequency measurement system and method, comprising: CPLD and MCU;CPLD includes PLL phase-locked loop module, PLL phase-locked loop module generates required clock, including reference clock, multi-level filter clock;Parallel communication module, parallel communication module simulates Flash read-write timing, simplifies the data read-write interaction of MCU side and CPLD, while ensuring the timeliness of data interaction;Pulse filter module, pulse filter module carries out filtering operation according to the filter level set, to avoid the pulse signal acquisition error caused by high-frequency interference.The present application adopts two kinds of design methods of double-edge collection self-adjustment and collection window self-adjustment, improves the response time of frequency measurement while ensuring the frequency measurement accuracy, compared with traditional frequency measurement mode, can improve the frequency response time by a factor of two at the fastest, meet the higher control demand of industrial field for speed device, improve dynamic control performance.
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