A hybrid multi-level converter dc bus capacitor minimization method

Abstract

The application provides a DC bus capacitor minimization method of a hybrid clamped converter (HCC), which comprises the following steps: obtaining system parameters when the hybrid clamped converter is working; determining a modulation wave; determining the duty cycle of each switch according to the modulation wave; determining the total neutral point current of the system; determining the fundamental wave component of the capacitor voltage of the upper and lower DC buses; determining the maximum voltage fluctuation of the upper and lower DC bus capacitors; and determining the minimum DC bus capacitor value meeting the system capacitor voltage fluctuation requirement by traversing the capacitor value. The application not only reduces the design complexity and cost of a high-power HCC system, but also improves the power density and reliability of the converter.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more specifically to a method for minimizing the DC bus capacitance of a hybrid multilevel converter. Background Technology

[0002] Multilevel converters are widely used in industrial applications due to their advantages such as lower dv / dt, better harmonic performance, and higher voltage and power ratings. However, the capacitors inside multilevel converters charge and discharge during system operation, leading to voltage fluctuations. The problem of severe capacitor voltage fluctuations in multilevel converters under low-frequency conditions is usually addressed by increasing the capacitor capacitance. However, for high-voltage capacitors, increasing the capacitance significantly increases their size and cost. Therefore, this inevitably increases system cost, reduces system power density, and renders multilevel converters unsuitable for practical applications.

[0003] For emerging medium- and high-voltage multilevel converters (HCCs), the presence of three DC bus capacitors and three flying capacitors presents a complex problem of minimizing capacitance values. Even after effectively controlling the DC bus capacitor voltage fluctuation, a complex relationship exists between the DC bus capacitor voltage fluctuation, capacitance size, and system parameters. In recent years, extensive research has been conducted to address several challenging issues in HCCs, including model building, voltage balance control, integrated control, and soft-start methods. However, few studies have specifically addressed the minimization of the DC bus capacitor in HCCs. This lack of a method for minimizing the DC bus capacitor makes the design and parameter selection of the DC bus capacitor in high-power HCC systems extremely difficult.

[0004] Therefore, proposing an effective design method for minimizing the DC bus capacitance of HCCs, and quickly and effectively determining the minimum DC bus capacitance of the system within the allowable capacitor voltage fluctuation range, is of great significance for the design of high-power HCC systems. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide an effective design method for minimizing the DC bus capacitance of hybrid multilevel converters (HCCs). This invention aims to solve the problem of difficult selection of HCC DC bus capacitors. According to the proposed HCC DC bus capacitance minimization design method, the DC bus capacitor parameters for high-power HCC system design can be quickly determined.

[0006] To achieve the above objectives, this invention provides a method for minimizing the DC bus capacitance of a hybrid multilevel converter, characterized by the following steps:

[0007] Step 1: Obtain the DC bus voltage V when the hybrid multilevel converter is operating. dc Reference wave frequency f ac Carrier frequency f c Modulation ratio m a Power factor Load impedance Z and system capacitor voltage fluctuation limit ΔV limit ;

[0008] Step 2: Determine the modulation wave V' ref_x :

[0009]

[0010] Among them, V ref_x Take V ref_a V ref_b or V ref_c V ref_a V ref_b and V ref_c These represent the modulation waves of phases a, b, and c, respectively; V com Indicates common-mode voltage;

[0011] Step 3: Based on the modulation wave V' ref_x Determine the duty cycle D of the HCC switch. Nx :

[0012]

[0013] Step 4: Based on the switch duty cycle D Nx and load current i ox Determine the total neutral point current i of the system. N :

[0014] i N =D Na ·i oa +D Nb ·i ob +D Nc ·i oc

[0015] Among them, D Nx Indicates the duty cycle of the switch for phase a, phase b, or phase c; D Na D represents the duty cycle of phase a; Nb D represents the duty cycle of phase b; Nc Indicates the duty cycle of the c-phase switch; i ox Indicates the load current of phase a, phase b, or phase c; i oa Indicates the load current of phase a; i ob Indicates the load current of phase b; i oc This represents the load current of phase c;

[0016] Step 5: Based on the total neutral point current i of the system N Determine the fundamental component V of the DC bus capacitor voltage on the upper and lower sides of the system. cap :

[0017]

[0018] Among them, C d1 This indicates the DC bus capacitance value to be determined. The DC bus capacitance is divided into three DC bus capacitances: upper, middle, and lower, and the capacitance values ​​of the three are equal.

[0019] Step 6: According to V cap Determine the maximum voltage fluctuation ΔV of the upper and lower DC bus capacitors. cd1 / cd3_max :

[0020]

[0021] In the formula, △V cd1 / cd3_f_max The fundamental component of the maximum voltage fluctuation of the upper and lower DC bus capacitors; ΔV cd1 / cd3_h_max The harmonic components of the maximum voltage fluctuation of the upper and lower DC bus capacitors; max(V cap ) represents the maximum value of the fundamental component of the upper and lower DC bus capacitor voltages, min(V cap ) represents the minimum fundamental component of the upper and lower DC bus capacitor voltages; ΔV cd2_max This represents the maximum voltage fluctuation of the intermediate DC bus capacitor.

[0022] Step 7: Adjust the capacitance value C d1 Starting from 0 to C max Iterate through the capacitors, with a step size of M1, repeating steps 1-6 to obtain the corresponding ΔV for different capacitance values. cd1 / cd3_max When △V cd1 / cd3_max The first time less than or equal to ΔV limit When the output capacitance value is reached, it is the minimum DC bus capacitance value that meets the system capacitor voltage fluctuation requirements.

[0023] Furthermore, in step 1, ΔV limit The range is 0-100% of the rated operating value of the capacitor voltage, which is one-third of the DC bus voltage.

[0024] Furthermore, in step 2,

[0025] Furthermore, in step 4, the load current i ox satisfy Where I represents the maximum load current amplitude,

[0026] Furthermore, in step 6, In the formula, T c For carrier frequency f c The reciprocal of.

[0027] Furthermore, minimizing the DC bus capacitance is based primarily on the maximum voltage fluctuation of the upper and lower DC bus capacitances.

[0028] Furthermore, in step 7, C max The value ranges from 0.001mF to 100mF, and the step size M1 ranges from 0.0001mF to 5mF.

[0029] Furthermore, this method is applicable to wide output voltage and current frequency conditions of 1-1000Hz and wide carrier frequency conditions of 500-10000Hz.

[0030] The beneficial effects of this invention are as follows:

[0031] 1) The HCC DC bus capacitor minimization design method provided by the present invention directly calculates the minimum DC bus capacitor that meets the voltage fluctuation requirements of HCC capacitor through the constructed mathematical model, avoiding the introduction of excessive DC bus capacitor, and significantly reducing the design complexity and volume of HCC system.

[0032] 2) The HCC DC bus capacitor minimization design method provided by this invention is applicable to wide frequency operating conditions, effectively solves the problem of selecting the minimum DC bus capacitor of HCC under common operating conditions, significantly reduces the design and construction cost of high-power HCC converters, and has promotion and application value in medium and high voltage power conversion and motor drive fields.

[0033] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0034] Figure 1 This is a flowchart of the design method for minimizing the DC bus capacitance of a hybrid multilevel converter according to the present invention;

[0035] Figure 2 This is a schematic diagram of the circuit connection of a three-phase four-level HCC converter;

[0036] Figure 3 The simulation waveforms of the DC bus capacitor voltages of the HCC system under the DC bus capacitor parameters obtained using the DC bus capacitor minimization design method of this invention are shown. Detailed Implementation

[0037] To make the technical solutions, advantages, and objectives of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the protection scope of this application.

[0038] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0039] Figure 2 This is a schematic diagram of a three-phase four-level HCC converter circuit. As shown in Figure 2, the circuit includes a DC power supply V. dc The three-phase HCC and three-phase load Z (each phase includes a resistor R and an inductor L connected in series). The three phases are phase a, phase b, and phase c (also written as phase A, phase B, and phase C).

[0040] The three-phase HCC includes three DC bus capacitors C connected in series. d1 C d2 and C d3 Three flying capacitors C fa (corresponding to phase a), C fb (corresponding to phase b) and C fc (Corresponding to phase C) and three bridge arms, each containing four sets of switches. Among them, the DC bus capacitor C... d1 It can also be called the upper DC bus capacitor, DC bus capacitor C d3 It can also be called the lower DC bus capacitor, DC bus capacitor C d2 It can also be called the intermediate DC bus capacitor.

[0041] For any phase x (phase a, phase b, or phase c), its corresponding flying capacitor C fx and bridge arm switch S 1x and S 1x ', S 2x and S 2x ', S 3x and S 3x ', S 4x and S 4x For example, such as Figure 2 As shown, for phase a, its corresponding flying capacitor C fa and bridge arm switch S 1a and S 1a ', S 2a and S 2a ', S 3a and S 3a ', S 4a and S 4a'. Among them, S 1a The first terminal is connected to the DC bus terminal capacitor C d1 The positive electrode is connected, S 1a The second end is connected to S 1a 'The first end and S 2a The first end, S 1a The first end of ' is also related to S 2a The first end is connected, S 1a The second end is connected to the DC bus capacitor C. d1 The negative electrode, S 2a The second end is connected to S 3a The first end, S 4a The first terminal is connected to the DC bus capacitor C. d3 The positive electrode, S 4a The second end is connected to S 2a 'The first end and S 4a The first end of 'S' 4a The second end is connected to the DC bus capacitor C. d3 The negative electrode, S 2a The second end of ' is connected to S 3a The first end of 'S' 3a The second end and S 3a The second end of each of the S's terminals is connected to a load. 2a The second end and S 3a The first end is connected to the flying capacitor C fa The positive electrode is connected, S 2a 'The second end and S 3a The first end of ' is connected to the flying capacitor C fa The negative terminal is connected.

[0042] It should be noted that, Figure 2 Only the specific connection method of phase a is shown; the specific connection methods of phases b and c are not shown. For those skilled in the art, according to... Figure 2 Based on the above description, it is easy to understand that the specific connection methods of phases b and c are similar to those of phase a, so they will not be repeated here.

[0043] Figure 1 This is a flowchart of the design method for minimizing the DC bus capacitance of a hybrid multilevel converter according to the present invention. Figure 1 As shown, the method includes:

[0044] Step 1: Obtain the DC bus voltage V when the hybrid multilevel converter is operating. dc Reference wave frequency f ac Carrier frequency f c Modulation ratio m a Power factor Load impedance Z and system capacitor voltage fluctuation limit ΔVlimit Among them, the capacitor voltage fluctuation is limited to ΔV. limit It is the maximum allowable DC bus capacitor voltage fluctuation of the system, ΔV limit The range is generally 0-100% of the rated operating value of the capacitor voltage, which is one-third of the DC bus voltage.

[0045] Step 2: Determine the modulation wave V' according to formula (1) ref_x :

[0046]

[0047] Among them, V ref_x Take V ref_a V ref_b or V ref_c V ref_a V ref_b and V ref_c These represent the modulation waves of phases a, b, and c, respectively; V com This indicates the common-mode voltage.

[0048] In some embodiments, V com satisfy In other words, this minimum design method is implemented based on the 25% amplitude tripled common-mode voltage injection control method. In other embodiments, the 25% amplitude can also be any other suitable value.

[0049] Step 3: Modulate the wave V' ref_x Substitute into formula (2) to determine the duty cycle D of the HCC switch. Nx :

[0050]

[0051] Wherein, the HCC switch duty cycle represents the switch Duty cycle, S 1x and S 2x These represent the internal switches S of the HCC. 1x and S 2x The on / off state, x is phase a, phase b or phase c, 1 is when the switch is on, 0 is when the switch is off; This represents the XOR operation.

[0052] Step 4: Based on the switch duty cycle D Nx and load current i ox Determine the total neutral point current i of the system. N The specific calculation method is as shown in formula (3):

[0053] i N =D Na ·i oa +DNb ·i ob +D Nc ·i oc (3)

[0054] Among them, D Nx Indicates the duty cycle of the switch for phase a, phase b, or phase c; D Na D represents the duty cycle of phase a; Nb D represents the duty cycle of phase b; Nc Indicates the duty cycle of the c-phase switch; i ox Indicates the load current of phase a, phase b, or phase c; i oa Indicates the load current of phase a; i ob Indicates the load current of phase b; i oc This represents the load current of phase c.

[0055] In some embodiments, the load current i ox Satisfy the following formula:

[0056]

[0057] Among them, the maximum load current amplitude I satisfies

[0058] Step 5: Based on the total neutral point current i of the system N Determine the fundamental component V of the DC bus capacitor voltage on the upper and lower sides of the system. cap The specific calculation method is shown in formula (4):

[0059]

[0060] Among them, C d1 This represents the DC bus capacitance value to be determined. The DC bus capacitance is divided into three DC bus capacitances: upper, middle, and lower, and all three have the same capacitance value.

[0061] Step 6: According to V cap Determine the maximum voltage fluctuation ΔV of the upper and lower DC bus capacitors. cd1 / cd3_max The specific calculation method is shown in formula (5):

[0062]

[0063] In the formula, △V cd1 / cd3_f_max The fundamental component of the maximum voltage fluctuation of the upper and lower DC bus capacitors; ΔV cd1 / cd3_h_max The harmonic components of the maximum voltage fluctuation of the upper and lower DC bus capacitors; max(V cap ) represents the maximum value of the fundamental component of the upper and lower DC bus capacitor voltages, min(V cap ) represents the minimum fundamental component of the upper and lower DC bus capacitor voltages; ΔVcd2_max This represents the maximum voltage fluctuation of the intermediate DC bus capacitor.

[0064] In some embodiments, △V cd2_max satisfy

[0065] Step 7: Adjust the capacitance value C d1 Starting from 0 to C max Iterate through the capacitors, with a step size of M1, repeating steps 1-6 to obtain the corresponding ΔV for different capacitance values. cd1 / cd3_max When △V cd1 / cd3_max The first time less than or equal to ΔV limit When the corresponding capacitance value is output, it represents the minimum DC bus capacitance value that meets the system's capacitor voltage fluctuation requirements, thus minimizing the DC bus capacitance. Where C... max M1 and C can take any suitable value. In some embodiments, C max The value ranges from 0.001mF to 100mF, and the step size M1 ranges from 0.0001mF to 5mF.

[0066] In some embodiments, the maximum voltage fluctuation of the intermediate DC bus capacitor is less than the maximum voltage fluctuation of the upper and lower DC bus capacitors, and the minimization of the DC bus capacitor is based primarily on the maximum voltage fluctuation of the upper and lower DC bus capacitors.

[0067] The method provided by this invention is applicable to wide output voltage and current frequency conditions of 1-1000Hz and wide carrier frequency conditions of 500-10000Hz.

[0068] This invention, based on the effective suppression of common-mode voltage injection and DC bus capacitor voltage fluctuations, constructs a precise correlation model between DC bus capacitor voltage fluctuations and DC bus capacitor values, and further proposes a design method for minimizing the HCC DC bus capacitor. By substituting given system parameters into the proposed design method, the minimum DC bus capacitor parameters of the HCC converter that meet the system voltage fluctuation requirements can be obtained quickly and accurately, reducing the cost, size, and weight of the bus capacitor. This invention not only reduces the design complexity and cost of high-power HCC systems but also improves the power density and reliability of the converter.

[0069] The following is an illustration through specific examples.

[0070] Example 1

[0071] The proposed method for minimizing DC bus capacitance is used to design the minimum DC bus capacitance of a specific three-phase HCC system. The specific parameters of the HCC system are as follows:

[0072] DC power supply V dcIt is used to provide DC power supply voltage of 3.3kV;

[0073] The HCC system has a modulation ratio of 1, a modulation wave frequency of 5Hz, and a carrier frequency of 4kHz.

[0074] The three-phase load consists of three resistors and inductors connected in series. The load resistor RL has a resistance of 8Ω and an inductance of 1mH. The system power factor is approximately 1.

[0075] HCC system capacitor voltage fluctuation limit ΔV limit This is ±10% of the capacitor's rated operating voltage of 1100V, which is 220V.

[0076] The HCC DC bus capacitance minimization design method in this embodiment is as follows: Figure 1 As shown, the specific steps are as follows:

[0077] (1) Obtain the following parameters when the hybrid multilevel converter is operating: DC bus voltage 3.3kV, reference wave frequency 5Hz, carrier frequency 4kHz, modulation ratio 1, power factor 1, and system capacitor voltage fluctuation limit 10%.

[0078] (2) The modulation wave V' is obtained according to formula (1). ref_x ,

[0079]

[0080] (3) Modulate wave V' ref_x Substituting into formula (2), the duty cycle D of the HCC switch is obtained. Nx ,

[0081]

[0082] (4) Set the duty cycle D Nx and load current i ox Substituting into formula (3), the total neutral point current of the system can be obtained.

[0083] i N =D Na ·i oa +D Nb ·i ob +D Nc ·i oc

[0084] Wherein, the load current satisfies Maximum load current

[0085] (5) The total neutral point current i of the system N Substituting into formula (4), the fundamental component V of the upper and lower DC bus capacitor voltages of the system is obtained. cap ,

[0086]

[0087] (6) V cap Substituting into formula (5), the maximum voltage fluctuation of the upper and lower DC bus capacitors can be obtained.

[0088]

[0089] In the formula, △V cd1 / cd3_f_max The fundamental component of the maximum voltage fluctuation of the upper and lower DC bus capacitors, ΔV cd1 / cd3_h_max The harmonic components of the maximum voltage fluctuation of the upper and lower DC bus capacitors, ΔV cd2_max The maximum voltage fluctuation of the intermediate DC bus capacitor satisfies

[0090] (7) Iterate through the capacitance values ​​from 0 to 10mF, with a step size of 0.01mF, and repeat the above 6 steps to obtain the corresponding ΔV for different capacitance values. cd1 / cd3_max ; Determine when △V cd1 / cd3_max When the voltage is less than or equal to 220V for the first time, the corresponding output capacitance value is 0.27mF, which means that the minimum DC bus capacitance value that meets the system capacitor voltage fluctuation requirements is 0.27mF.

[0091] The above method is used to obtain the limit ΔV of capacitor voltage fluctuation in the HCC system. limit The minimum DC bus capacitance is 0.27mF when the rated operating value of the capacitor voltage is ±10%.

[0092] Figure 3 The simulation waveforms of the DC bus capacitor voltages of the HCC system under a DC bus capacitor parameter of 0.27mF obtained using the DC bus capacitor minimization design method of this invention are shown.

[0093] from Figure 3 Analysis shows that, with the minimum DC bus capacitance of 0.27mF obtained using the DC bus capacitance minimization design method provided by this invention, the peak-to-peak value of the middle DC capacitor voltage is 20.98V, which is less than the voltage fluctuations of the upper and lower DC bus capacitors. The peak-to-peak value of the upper and lower DC bus capacitor voltages is 194.70V, with a fluctuation of ±8.9% of the rated operating value of the capacitor voltage. In actual capacitor value selection, a certain margin is often considered to prevent the capacitor voltage fluctuation from exceeding the system's allowable range in extreme cases. The actual HCC capacitor voltage fluctuation under the minimum capacitance value obtained by this invention differs from the maximum allowable fluctuation by less than 2%, achieving a relatively accurate calculation of the minimum DC bus capacitance value.

[0094] In summary, the hybrid multilevel converter DC bus capacitance minimization design method provided by this invention directly calculates the minimum DC bus capacitance parameters that meet the HCC capacitor voltage fluctuation requirements through the constructed mathematical model, significantly reducing the design complexity and size of the HCC system. This invention is applicable to a wide frequency range and effectively solves the problem of selecting the minimum DC bus capacitance for HCC under common operating conditions, making it valuable for widespread application in medium and high voltage power conversion and motor drive fields.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the protection scope of the present invention.

Claims

1. A method for minimizing the DC bus capacitance of a hybrid multilevel converter, characterized in that, Includes the following steps: Step 1: Obtain the DC bus voltage V when the hybrid multilevel converter is operating. dc Reference wave frequency f ac Carrier frequency f c Modulation ratio m a Power factor Load impedance Z and system capacitor voltage fluctuation limit ΔV limit ; Step 2: Determine the modulation wave V' ref_x : Among them, V ref_x Take V ref_a V ref_b or V ref_c V ref_a V ref_b and V ref_c These represent the modulation waves of phases a, b, and c, respectively; V com Indicates common-mode voltage; Step 3: Based on the modulation wave V' ref_x Determine the duty cycle D of the HCC switch. Nx : Step 4: Based on the switch duty cycle D Nx and load current i ox Determine the total neutral point current i of the system. N : i N =D Na ·i oa +D Nb ·i ob +D Nc ·i oc Among them, D Nx Indicates the duty cycle of the switch for phase a, phase b, or phase c; D Na D represents the duty cycle of phase a; Nb D represents the duty cycle of phase b; Nc Indicates the duty cycle of the c-phase switch; i ox Indicates the load current of phase a, phase b, or phase c; i oa Indicates the load current of phase a; i ob Indicates the load current of phase b; i oc This represents the load current of phase c; Step 5: Based on the total neutral point current i of the system N Determine the fundamental component V of the DC bus capacitor voltage on the upper and lower sides of the system. cap : Among them, C d1 This indicates the DC bus capacitance value to be determined. The DC bus capacitance is divided into three DC bus capacitances: upper, middle, and lower, and the capacitance values ​​of the three are equal. Step 6: According to V cap Determine the maximum voltage fluctuation ΔV of the upper and lower DC bus capacitors. cd1 / cd3_max : In the formula, △V cd1 / cd3_f_max The fundamental component of the maximum voltage fluctuation of the upper and lower DC bus capacitors; ΔV cd1 / cd3_h_max The harmonic components of the maximum voltage fluctuation of the upper and lower DC bus capacitors; max(V cap ) represents the maximum value of the fundamental component of the upper and lower DC bus capacitor voltages, min(V cap ) represents the minimum fundamental component of the upper and lower DC bus capacitor voltages; ΔV cd2_max This represents the maximum voltage fluctuation of the intermediate DC bus capacitor. Step 7: Adjust the capacitance value C d1 Starting from 0 to C max Iterate through the capacitors, with a step size of M1, repeating steps 1-6 to obtain the corresponding ΔV for different capacitance values. cd1 / cd3_max When △V cd1 / cd3_max The first time less than or equal to ΔV limit When the output capacitance value is reached, it is the minimum DC bus capacitance value that meets the system capacitor voltage fluctuation requirements.

2. The method for minimizing the DC bus capacitance of a hybrid multilevel converter according to claim 1, characterized in that, In step 1, ΔV limit The range is 0-100% of the rated operating value of the capacitor voltage, which is one-third of the DC bus voltage.

3. The method for minimizing the DC bus capacitance of a hybrid multilevel converter according to claim 1, characterized in that, In step 2, 4. The method for minimizing the DC bus capacitance of a hybrid multilevel converter according to claim 1, characterized in that, In step 4, the load current i ox satisfy Where I represents the maximum load current amplitude, 5. The method for minimizing the DC bus capacitance of a hybrid multilevel converter according to claim 1, characterized in that, In step 6, In the formula, T c For carrier frequency f c The reciprocal of.

6. The method for minimizing the DC bus capacitance of a hybrid multilevel converter according to claim 1, characterized in that, Minimize the DC bus capacitance, using the maximum voltage fluctuation of the upper and lower DC bus capacitances as the main reference.

7. The method for minimizing the DC bus capacitance of a hybrid multilevel converter according to claim 1, characterized in that, In step 7, C max The value ranges from 0.001mF to 100mF, and the step size M1 ranges from 0.0001mF to 5mF.

8. The method for minimizing the DC bus capacitance of a hybrid multilevel converter according to claim 1, characterized in that, This method is applicable to wide output voltage and current frequency conditions of 1-1000Hz and wide carrier frequency conditions of 500-10000Hz.

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