A ring gate transistor

Abstract

The application discloses a ring gate transistor, and relates to the technical field of semiconductors, which is used for enhancing the control ability of a gate stack structure to the edge part of each layer of nano structures along the length direction, and is beneficial to improving the driving performance of the ring gate transistor. The ring gate transistor comprises a semiconductor substrate, a source region, a drain region, at least one layer of nano structures, a gate stack structure and an inner side wall. The source region, the drain region and the at least one layer of nano structures are formed on the semiconductor substrate. The at least one layer of nano structures is located between the source region and the drain region. The gate stack structure surrounds the outer periphery of each layer of nano structures. The inner side wall is located between the gate stack structure and the source region and between the gate stack structure and the drain region. The inner side wall has an inner side wall close to the gate stack structure, and the surface of the middle area of the gate stack structure in the width direction is concave inward or convex outward relative to the surface of the edge area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a gate-around transistor. Background Technology

[0002] Gate-around transistors (GMT-A) offer advantages over planar transistors and fin field-effect transistors, such as higher gate control capability. Therefore, when all transistor types in an integrated circuit are GMT-A, it is beneficial to improve the operating performance of the integrated circuit. Furthermore, placing inner walls between the gate stack and the source region, and between the gate stack and the drain region in a GMT-A can limit the length of the gate stack and suppress the effects of short-channel effects.

[0003] However, the presence of inner walls in existing gate-around transistors results in poor control of the two edge portions of each nanostructure along the length direction by the gate stack structure, which is not conducive to improving the driving performance of gate-around transistors. Summary of the Invention

[0004] The purpose of this invention is to provide a gate ring transistor that enhances the control capability of the gate stack structure over the edge portions of each nanostructure along the length direction, thereby improving the driving performance of the gate ring transistor.

[0005] To achieve the above objectives, the present invention provides a gate-around transistor, comprising: a semiconductor substrate, a source region, a drain region, at least one nanostructure, a gate stack structure, and inner sidewalls. The source region, drain region, and at least one nanostructure are formed on the semiconductor substrate. The at least one nanostructure is located between the source region and the drain region. The gate stack structure surrounds the outer periphery of each nanostructure. The inner sidewalls are located between the gate stack structure and the source region, and between the gate stack structure and the drain region. The inner sidewalls have inner walls adjacent to the gate stack structure, and the surface of the middle region of the inner sidewall along the width direction of the gate stack structure is recessed inward or protrudes outward relative to the surface of the edge region.

[0006] With the above technical solution, the inner wall of the gate-ring transistor provided by the present invention, located between the gate stack structure and the source region, and between the gate stack structure and the drain region, has an inner wall close to the gate stack structure. Furthermore, the surface of the middle region of this inner wall along the width direction of the gate stack structure is either concave inward or convex outward relative to the surface of the edge region. When the surface of the middle region of the inner wall along the width direction of the gate stack structure is concave inward relative to the surface of the edge region, a portion of the gate stack structure can be formed within the corresponding notch in the middle region of the inner wall. This allows this portion of the gate stack structure to have a certain control capability over the edge portions of the nanostructure along the length direction when the gate-ring transistor is in operation, reducing the resistivity of the edge portions of the nanostructure along the length direction and improving the driving performance of the gate-ring transistor. Similarly, when the surface of the middle region of the inner wall protrudes outward relative to the surface of the edge region along the width direction of the gate stack structure, part of the gate stack structure can be formed in the notch corresponding to the edge region of the inner wall, which enhances the gate stack structure's ability to control the edge parts of the nanostructure along the length direction when the gate ring transistor is in operation, thus improving the driving performance of the gate ring transistor. Attached Figure Description

[0007] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0008] Figure 1 Parts (1) and (2) are longitudinal cross-sectional views of the structure of the gate ring transistor in the related technology at the middle and edge regions of the inner wall along the width direction of the gate stack structure.

[0009] Figure 2 This is a schematic cross-sectional view of the structure of a gate-ring transistor in a related technology at the inner sidewall.

[0010] Figure 3 Parts (1) and (2) are longitudinal cross-sectional views of the first structure of the ring gate transistor provided in the embodiments of the present invention at the middle and edge regions of the inner wall along the width direction of the gate stack structure.

[0011] Figure 4 A schematic cross-sectional view of the inner wall of the first structure of the ring gate transistor provided in an embodiment of the present invention;

[0012] Figure 5 Parts (1) and (2) are longitudinal cross-sectional views of the second structure of the ring gate transistor provided in the embodiments of the present invention at the middle and edge regions of the inner wall along the width direction of the gate stack structure.

[0013] Figure 6 This is a schematic cross-sectional view of the inner wall of a second structure of a gate ring transistor provided in an embodiment of the present invention.

[0014] Figure reference numerals: 11 is semiconductor substrate, 12 is source region, 13 is drain region, 14 is nanostructure, 15 is inner sidewall, 16 is gate stack structure, 17 is gate sidewall, and 18 is interlayer dielectric layer. Detailed Implementation

[0015] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0016] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0017] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0018] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0019] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0020] Gate-around transistors (GMT-Rs) offer advantages over planar transistors and fin field-effect transistors, such as higher gate control capability. Therefore, when all transistors in an integrated circuit are GMT-Rs, it improves the overall performance of the integrated circuit. Furthermore, such as... Figure 1 and Figure 2 As shown, an inner wall 15 is provided between the gate stack structure 16 and the source region 12, and between the gate stack structure 16 and the drain region 13 in the gate ring transistor. This can limit the length of the gate stack structure 16, suppress the influence of the short channel effect, and also reduce the parasitic capacitance between the gate and the source region 12, and between the gate and the drain region 13.

[0021] However, as Figure 1 and Figure 2 As shown, in existing gate ring transistors, the thickness of the inner sidewall 15 is equal along each part of the gate stack structure 16. The presence of the inner sidewall 15 means that when the gate ring transistor is in operation, the effective range of the gate stack structure 16 cannot cover the two sides of the length of each nanostructure 14. This results in poor control of the two sides of the length of each nanostructure 14 by the gate stack structure 16, which in turn causes the two sides of the length of each nanostructure 14 to be in a high-resistance state, which is not conducive to improving the driving performance of the gate ring transistor.

[0022] To address the aforementioned technical problems, embodiments of the present invention provide a gate-around-the-ring transistor. In this gate-around-the-ring transistor, the surface of the middle region of the inner sidewall along the width direction of the gate stack structure is recessed inward or protrudes outward relative to the surface of the edge region. A portion of the gate stack structure can be formed within a notch corresponding to the middle region of the inner sidewall or within a notch corresponding to the edge region of the inner sidewall. This allows the gate stack structure to exert a certain degree of control over the edge portions of the nanostructure along its length direction when the gate-around-the-ring transistor is in operation, thereby improving the driving performance of the gate-around-the-ring transistor.

[0023] Specifically, the gate ring transistor provided in this embodiment of the invention can be a junction-type gate ring transistor or a junctionless gate ring transistor. Here, "junction" refers to a PN junction. In a junction-type gate ring transistor, the conductivity types of the source and drain regions are opposite to those of the channel region. In a junctionless gate ring transistor, the conductivity types of the source and drain regions are the same as those of the channel region.

[0024] like Figures 3 to 6 As shown, the gate-ring transistor provided in this embodiment of the invention includes: a semiconductor substrate 11, a source region 12, a drain region 13, at least one nanostructure 14, a gate stack structure 16, and an inner sidewall 15. The source region 12, drain region 13, and at least one nanostructure 14 are formed on the semiconductor substrate 11. The at least one nanostructure 14 is located between the source region 12 and the drain region 13. The gate stack structure 16 surrounds the outer periphery of each nanostructure 14. The inner sidewall 15 is located between the gate stack structure 16 and the source region 12, and between the gate stack structure 16 and the drain region 13. Figure 4 and Figure 6 As shown, the inner wall 15 has an inner wall close to the grid stack structure 16, and the surface of the middle region of the inner wall along the width direction of the grid stack structure 16 is recessed inward or protruded outward relative to the surface of the edge region.

[0025] The semiconductor substrate can be a silicon substrate, a germanium-silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc., on which no structure is formed.

[0026] Alternatively, a semiconductor substrate with certain structures can be formed on the semiconductor substrate. Specifically, the structures formed on the semiconductor substrate can be determined according to the actual application scenario, and are not specifically limited here. For example, when the gate ring transistor provided in the embodiments of the present invention is applied to the second or higher layer of a gate ring transistor in an integrated circuit, the semiconductor substrate includes a semiconductor substrate, at least one layer of semiconductor device located below the gate ring transistor provided in the embodiments of the present invention, and an interlayer dielectric layer that isolates different layers of semiconductor devices.

[0027] For the aforementioned source and drain regions, the materials used are semiconductor materials such as silicon, germanium-silicon, or germanium. The materials of the source and drain regions can be the same or different. The specific materials of the source and drain regions can be determined based on the device type and conductivity type of the gate-ring transistor. For example, in the case where the gate-ring transistor provided in this embodiment is a junction-type gate-ring transistor and has a P-type conductivity, the materials of the source and drain regions can be germanium or germanium-silicon with a high germanium content, to provide compressive stress to each nanostructure layer, further improving the driving performance of the gate-ring transistor.

[0028] For the above-mentioned at least one nanostructure, the number of nanostructure layers located between the source and drain regions can be a single layer, or multiple layers spaced apart along the thickness direction of the semiconductor substrate. The specific number of nanostructure layers between the source and drain regions can be determined according to actual needs, as long as it can be applied to the gate-ring transistor provided in the embodiments of the present invention.

[0029] For the aforementioned gate stack structure, the gate stack structure may include a gate dielectric layer surrounding the periphery of each nanostructure layer, and a gate electrode located on the gate dielectric layer. The gate dielectric layer may be made of dielectric materials such as HfO2, ZrO2, TiO2, or Al2O3. The gate electrode may be made of conductive materials such as TiN, TaN, or TiSiN.

[0030] In one example, such as Figures 3 to 6 As shown, the aforementioned gate-ring transistor may further include a gate sidewall 17. The gate sidewall 17 is located at least on both sides of the gate stack structure 16 along its length to suppress leakage between the gate and other conductive structures. The gate sidewall 17 spans the two edge portions of at least one nanostructure 14 along its length. The material of the gate sidewall 17 can be an insulating material such as silicon oxide or silicon nitride, and the thickness of the gate sidewall 17 can be determined according to the actual application scenario; no specific limitation is made here.

[0031] It should be noted that when the gate-around transistor also includes a gate sidewall, the portion of the nanostructures surrounded by the gate stack structure constitutes the channel region of the gate-around transistor. The portion of the nanostructures located below the gate sidewall constitutes the semiconductor connection region between the channel region and the source region, and between the channel region and the drain region.

[0032] For the aforementioned inner wall, such as Figure 4 and Figure 6 As shown, the surface of the inner sidewall 15 in the central region along the width direction of the gate stack structure 16 is concave inward or convex outward relative to the surface of the edge region. Based on this, in actual manufacturing processes, two different material films (i.e., a first material film and a second material film) are typically placed between the bottom nanostructure and the semiconductor substrate, and between adjacent nanostructures, before releasing the nanostructure. The materials of both the first and second material films are different from the material of the nanostructure, and the second material film is located on both sides of the first material film along the width direction of the nanostructure. In this case, the edge portions on both sides of the first and second material films along the length direction can be etched by selecting etchants with different etching rates for the first and second material films. If the etching rate of the etchant on the first material film is greater than that on the second material film, then... Figure 4The surface of the central region of the inner wall 15 subsequently formed, as shown, protrudes outward relative to the surface of the edge region. If the etching rate of the etchant on the first material film layer is less than that on the second material film layer, then as... Figure 6 The surface of the middle region of the inner wall of the subsequently formed inner wall 15 is recessed inward relative to the surface of the edge region.

[0033] In the above-described case, from a material perspective, the material of the inner wall may include any insulating material different from the materials of the first and second material films. For example, the material of the inner wall may include at least one of silicon nitride, silicon oxynitride, and silicon carbide nitride.

[0034] In terms of morphology, the thickness of each region of the inner wall along the width direction of the grid stacking structure can be determined according to actual needs, as long as the surface of the middle region of the inner wall along the width direction of the grid stacking structure is concave inward or convex outward relative to the surface of the edge region. For example, Figure 4 and Figure 6 As shown, the thickness of each region in the middle part of the inner sidewall 15 along the width direction of the gate stack structure 16 can be equal. In this case, the surface of the middle region of the inner sidewall 15 is parallel to the width direction of the nanostructure 14, which is beneficial to make the size of the portion of the gate stack structure 16 filling the corresponding notch inside the inner sidewall 15 approximately the same, which is beneficial to make the control capability of the gate stack structure 16 over each part of the edge region of the nanostructure 14 approximately the same, and thus beneficial to make each part of the edge region of the nanostructure 14 have a low resistivity.

[0035] like Figure 4 and Figure 6 As shown, the thickness of each region of the edge portion of the inner wall 15 along the width direction of the grid stack structure 16 can be equal, which is beneficial to make the size of the portion of the grid stack structure 16 filled in the corresponding notch inside the inner wall 15 approximately the same.

[0036] Of course, in practical applications, the thickness of the middle or edge portions of the inner wall along the width of the grid stacking structure can also be unequal.

[0037] As for the outer wall of the inner wall (i.e., the inner wall sidewall closest to the source or drain region), such as Figure 3 and Figure 5 As shown, the outer wall of the inner wall 15 can be aligned with the sidewall of the nanostructure 14 along its length.

[0038] Secondly, along the length of the gate stack structure, the maximum thickness of the inner sidewall can be determined based on the length of the nanostructure in the actual application scenario and the length requirements of the gate stack structure; no specific limitation is made here. For example, in the case where the ring-gate transistor provided in this embodiment of the invention also includes a gate sidewall, the maximum thickness of the inner sidewall is less than or equal to the maximum thickness of the gate sidewall. Specifically, as shown... Figure 4 As shown, when the surface of the middle region of the inner sidewall 15 protrudes outward relative to the surface of the edge region, the maximum thickness of the middle portion of the inner sidewall 15 along the width direction of the nanostructure 14 is less than the maximum thickness of the gate sidewall 17. Figure 6 As shown, when the surface of the edge region of the inner sidewall 15 protrudes outward relative to the surface of the edge region, the maximum thickness of the edge portion of the inner sidewall 15 along the width direction of the nanostructure 14 is less than the maximum thickness of the gate sidewall 17.

[0039] Furthermore, the length by which the surface of the inner wall of the middle region along the width direction of the grid stack structure is recessed or protruded relative to the surface of the edge region can be determined according to the actual application scenario. For example, it can be determined based on the difference in etching rates of the first and second material films by the etchant, as mentioned above, and the maximum thickness of the formed inner wall; no specific limitation is made here.

[0040] For example, the length by which the surface of the central region of the inner sidewall is recessed inward or protruded outward relative to the surface of the edge region can be greater than 0 and less than or equal to 3 nm. For example: Figure 4 As shown, when the surface of the central region of the inner wall protrudes outward relative to the surface of the edge region, the length of this outward protrusion can be 1 nm, 1.5 nm, 2 nm, 2.5 nm, or 3 nm, etc. For example: Figure 6 As shown, when the surface of the middle region of the inner sidewall is recessed inward relative to the surface of the edge region, the length of the inward recess can be 1 nm, 1.5 nm, 2 nm, 2.5 nm, or 3 nm, etc. In the above case, the length of the inward recess or outward protrusion of the surface of the middle region of the inner sidewall relative to the surface of the edge region is within the above range. This can prevent the length from being too large, which would make it difficult to limit the length of the gate stack structure 16 through the inner sidewall 15 during the manufacturing process of the gate ring transistor, and can also prevent the degree of suppression of the short-channel effect and reduction of parasitic capacitance through the inner sidewall 15 from being too small. It can also prevent the length of the portion of the gate stack structure 16 filled into the notch from being too small, and ensure that the resistivity of the two edge portions of the nanostructure 14 along the length direction can be reduced through the portion of the gate stack structure 16 filled into the notch.

[0041] Along the width direction of the grid stack structure, the width of the central region and the width of the edge region of the inner wall of the inner sidewall can be determined according to actual needs, and are not specifically limited here. Among them, the width direction of the central region is parallel to the width direction of the grid stack structure.

[0042] For example, the width of the central region can be greater than or equal to 5 nm and less than or equal to 15 nm. For instance, the width of the central region can be 5 nm, 7 nm, 9 nm, 11 nm, 13 nm, or 15 nm, etc. In the above case, as described above, during the actual manufacturing process of the gate-around transistor provided in this embodiment of the invention, the surface of the central region is concave inward or convex outward relative to the surface of the edge region in the inner wall of the inner sidewall because the etching rate of the etchant on the first material film layer and the second material film layer is different. Therefore, the width of the central region is the same as the width of the first material film layer. When the width of the central region is greater than or equal to 5 nm and less than or equal to 15 nm, the width of the first material film layer is also greater than or equal to 5 nm and less than or equal to 15 nm. This prevents the first material film layer from being too thin, making it difficult to support the channel layer above it after the formation of the first material film layer and before the formation of the second material film layer, thus improving the yield of the gate-around transistor. At the same time, it can also prevent the width of the notch formed by the inward indentation of the edge region from being too small when the surface of the central region protrudes outward relative to the surface of the edge region due to the large width of the first material film layer. This ensures that the part of the gate stack structure filled in the notch has a certain width, thereby ensuring that the resistivity of the nanostructure on both sides of the edge portion along the length direction can be reduced through this part of the gate stack structure.

[0043] As for the edge area of ​​the inner wall within the inner wall, such as Figure 4 and Figure 6 As shown, in the aforementioned inner wall, the widths of the two edge regions located on both sides of the central region along the width direction of the gate stack structure 16 can be equal. In this case, it is advantageous that when the edge regions of the inner wall are recessed inward relative to the central region, the width of the interior of the gate stack structure 16 filled in the two recesses is the same, thereby enhancing the control capability of the gate stack structure 16 over each part of the edge regions on both sides of the nanostructure 14 along the length direction.

[0044] Secondly, such as Figure 4 As shown, when the surface of the central region protrudes outward relative to the surface of the edge region, the inner wall 15 has a protrusion on the side near the gate stack structure 16. The width of each part of the protrusion along the length direction of the gate stack structure 16 can be equal, so that the gate stack structure 16 fills the same width on both sides of the protrusion, thereby enhancing the control ability of the gate stack structure 16 over each part of the edge region on both sides of the nanostructure 14 along the length direction.

[0045] In addition, such as Figure 6 As shown, when the surface of the central region is recessed inward relative to the surface of the edge region, a notch is formed on the side of the inner wall 15 near the gate stack structure 16. The width of each part of the notch along the length direction of the gate stack structure 16 can be equal, so that the width of each part of the gate stack structure 16 filling the notch is the same, which helps to enhance the control ability of the gate stack structure 16 over each part of the edge region on both sides of the nanostructure 14 along the length direction.

[0046] Secondly, along the thickness direction of the semiconductor substrate, the cross-sectional areas of each part of the inner wall can be equal.

[0047] As for the specific shape of the inner wall, such as Figure 4 and Figure 6 As shown, the cross-sectional shape of the inner wall 15 can be any shape, such as a U-shape or a convex shape, in which the central region is concave inward or convex outward relative to the edge region, as long as it can be applied to the embodiments of the present invention.

[0048] In some cases, such as Figure 3 and Figure 5 As shown, the gate-around transistor provided in this embodiment of the invention may further include an interlayer dielectric layer 18 covering the semiconductor substrate 11 to prevent the source region 12 and drain region 13 from being affected during operations such as removing the sacrificial gate during the manufacturing process of the gate-around transistor, thereby improving the yield of the gate-around transistor. The top of the interlayer dielectric layer 18 is flush with the top of the gate stack structure 16, and the material of the interlayer dielectric layer 18 may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0049] In some cases, the gate ring transistor provided in the embodiments of the present invention may further include a shallow trench isolation structure formed on a semiconductor substrate to isolate different devices and suppress leakage current.

[0050] When the above technical solution is adopted, such as Figures 3 to 6 As shown, in the ring-gate transistor provided by the present invention, the inner sidewall 15 located between the gate stack structure 16 and the source region 12, and between the gate stack structure 16 and the drain region 13, has an inner sidewall close to the gate stack structure 16. Furthermore, the surface of the middle region of this inner sidewall along the width direction of the gate stack structure 16 is recessed inward or protrudes outward relative to the surface of the edge region. Wherein, as... Figure 6As shown, when the surface of the middle region of the inner sidewall 15 along the width direction of the gate stack structure 16 is recessed inward relative to the surface of the edge region, a portion of the gate stack structure 16 can be formed in the corresponding notch in the middle region of the inner sidewall. This allows the portion of the gate stack structure 16 to have a certain control capability over the edge portions of the nanostructure 14 along the length direction when the ring-gate transistor is in operation, reducing the resistivity of the edge portions of the nanostructure 14 along the length direction and thus improving the driving performance of the ring-gate transistor. Similarly, as... Figure 4 As shown, when the surface of the middle region of the inner sidewall 15 protrudes outward relative to the surface of the edge region along the width direction of the gate stack structure 16, part of the gate stack structure 16 can be formed in the notch corresponding to the edge region of the inner sidewall, which enhances the control capability of the gate stack structure 16 over the edge portions of the nanostructure 14 along the length direction when the gate ring transistor is in operation, and is beneficial to improving the driving performance of the gate ring transistor.

[0051] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0052] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A gate-ring transistor, characterized in that, include: Semiconductor substrate, A source region, a drain region, and at least one nanostructure are formed on the semiconductor substrate; the at least one nanostructure is located between the source region and the drain region; A gate stack structure surrounding the periphery of each layer of the nanostructure; And an inner wall located between the gate stack structure and the source region, and between the gate stack structure and the drain region; the inner wall has an inner wall close to the gate stack structure, and the surface of the middle region of the inner wall along the width direction of the gate stack structure is recessed inward or protruded outward relative to the surface of the edge region.

2. The gate-ring transistor according to claim 1, characterized in that, The width of the central region is greater than or equal to 5 nm and less than or equal to 15 nm; The width direction of the central region is parallel to the width direction of the gate stack structure.

3. The gate-ring transistor according to claim 1, characterized in that, The length by which the surface of the middle region of the inner wall is recessed inward or protruded outward relative to the surface of the edge region is greater than 0 and less than or equal to 3 nm.

4. The gate-ring transistor according to claim 1, characterized in that, In the inner wall, the widths of the two edge regions located on both sides of the central region along the width direction of the gate stack structure are equal; the width direction of the edge regions is parallel to the width direction of the gate stack structure.

5. The gate-to-ring transistor according to claim 1, characterized in that, Along the thickness direction of the semiconductor substrate, the cross-sectional areas of each portion of the inner sidewall are equal; and / or, The thickness of each region in the middle portion of the inner wall along the width direction of the grid stack structure is equal; and / or, The thickness of each region of the inner sidewall along the width direction of the grid stack structure is equal.

6. The gate-to-ring transistor according to claim 1, characterized in that, When the surface of the central region is recessed inward relative to the surface of the edge region, a notch is formed on the side of the inner sidewall near the grid stack structure, and the width of each portion of the notch is equal along the width direction of the grid stack structure; or, When the surface of the central region protrudes outward relative to the surface of the edge region, the inner wall has a protrusion on the side near the grid stack structure, and the width of each part of the protrusion is equal along the width direction of the grid stack structure.

7. The gate-ring transistor according to claim 1, characterized in that, The cross-sectional shape of the inner wall is either concave or convex.

8. The gate-ring transistor according to claim 1, characterized in that, The gate-ring transistor further includes gate sidewalls; the gate sidewalls are located at least on both sides of the gate stack structure along the length direction and span across both sides of the at least one nanostructure along the length direction; The maximum thickness of the inner sidewall is less than or equal to the maximum thickness of the gate sidewall.

9. The gate-to-ring transistor according to claim 1, characterized in that, The gate ring transistor is a junction gate ring transistor or a junctionless gate ring transistor.

10. The gate-ring transistor according to any one of claims 1 to 9, characterized in that, The material of the inner wall includes at least one of silicon nitride, silicon oxynitride, and silicon carbide.

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