A charge pump structure

Abstract

The embodiment of the present application provides a charge pump structure, and relates to the technical field of integrated circuits.The charge pump structure comprises a non-overlapping clock generation module and a charge pump circuit module connected with the non-overlapping clock generation module; the non-overlapping clock generation module is used for generating non-overlapping timing control signals for the charge pump circuit module; and the charge pump circuit module is used for performing voltage boosting processing on an input voltage under the timing control signals. The present application adopts non-overlapping clocks, avoids the situation that unexpected MOSFET switches are simultaneously turned on, performs ESD protection, prevents damage of static electricity to on-chip devices, has good reliability and safety, simultaneously adopts a parallel mode of multiple branches to reduce the conduction impedance between an input voltage port and an external capacitor path, thereby reducing power loss and improving the energy efficiency of the charge pump.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, specifically to a charge pump structure, and more particularly to a high-efficiency charge pump structure for achieving a 2x voltage boost. Background Technology

[0002] A charge pump is a commonly used circuit for DC-DC converters and an indispensable component in power management within integrated circuit design. The voltage conversion achieved by a charge pump involves two stages: the first is the charging stage, where a capacitor is used as an energy storage element to store the input voltage signal; the second is the conversion stage, where the charged capacitor outputs a higher output voltage signal. This type of circuit converts a lower input voltage signal into a higher output voltage signal, a voltage boosting method similar to a water pump, hence the name charge pump. Compared to inductive DC-DC converters that require a large number of off-chip inductors, charge pumps are widely used in non-volatile memory, smart power integrated circuits, and, in recent years, energy harvesting systems for energy-autonomous devices due to their simpler external circuitry, smaller chip area, and easier integration.

[0003] The charge pump model was first proposed by John F. Dickson in 1976 and is known as the Dickson charge pump, the most classic charge pump structure. Each stage of the Dickson charge pump is connected by a unidirectional diode. Due to the diode's on-resistance and the threshold voltage loss in each stage, its efficiency is relatively low. Based on the Dickson charge pump model, different charge pump topologies later emerged, including the Fibonacci charge pump (also called the Makowski charge pump), which has high boost conversion efficiency but complex timing control circuitry; the cross-coupled charge pump, whose conversion efficiency is still low due to the bias effect; and the four-phase charge pump, which significantly reduces the threshold voltage loss problem and improves voltage conversion efficiency, but its circuit design is complex and requires a significant sacrifice in design area.

[0004] With the continuous progress and development of integrated circuit power management and its entire manufacturing technology and processes, how to improve the energy efficiency of charge pumps while ensuring the simplicity of circuit structure and control timing has become an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a charge pump structure that can achieve a 2x voltage boost while keeping the circuit structure and control timing simple, and improve the energy efficiency of the charge pump.

[0006] To achieve the above objectives, the present invention provides a charge pump structure, including a non-overlapping clock generation module and a charge pump circuit module connected to the non-overlapping clock generation module;

[0007] The non-overlapping clock generation module is used to generate non-overlapping timing control signals for the charge pump circuit module;

[0008] The charge pump circuit module is used to boost the input voltage under the timing control signal.

[0009] In one embodiment, the non-overlapping clock generation module is implemented based on gate circuits;

[0010] When a clock input signal is given, the non-overlapping clock generation module uses the delay output of the gate circuit itself to generate two non-overlapping positive clock signals and an inverted clock signal.

[0011] In one embodiment, the charge pump circuit module includes two operating states: a charging state and a switching state, which alternate between the charging state and the switching state.

[0012] The charge pump circuit module includes an external capacitor;

[0013] When the charge pump circuit module is in a charging state, the input voltage is connected to the positive terminal of the external capacitor to charge the external capacitor.

[0014] When the charge pump circuit module is in the switching state, the input voltage is connected to the negative terminal of the external capacitor to boost the input voltage.

[0015] In one embodiment, the charge pump circuit module further includes a first circuit unit, a second circuit unit, a third circuit unit, a fourth circuit unit, and a fifth circuit unit;

[0016] The first circuit unit includes a first PMOS transistor P1 and a first resistor R1 connected in series.

[0017] The second circuit unit includes a first NMOS transistor N1 and a forty-third resistor R43 connected in series.

[0018] The third circuit unit includes a third PMOS transistor P3 and a third resistor R3 connected in series.

[0019] The fourth circuit unit includes a second PMOS transistor P2 and a second resistor R2 connected in series.

[0020] The fifth circuit unit includes a second NMOS transistor N2 and a third NMOS transistor N3 connected in series.

[0021] When the charge pump circuit module is in the charging state, the first PMOS transistor P1, the first NMOS transistor N1, the third NMOS transistor N3, and the second NMOS transistor N2 remain on, while the third PMOS transistor P3 and the second PMOS transistor P2 remain off.

[0022] When the charge pump circuit module is in the switching state, the first PMOS transistor P1, the first NMOS transistor N1, and the third NMOS transistor N3 remain off, while the third PMOS transistor P3, the second PMOS transistor P2, and the second NMOS transistor N2 remain on.

[0023] In one embodiment, the third circuit unit includes a fourth PMOS transistor P4 and a fourth resistor R4 connected in series, and the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected in parallel.

[0024] In one embodiment, the charge pump circuit module further includes a first buffer, a second buffer, a first inverter, and a second inverter;

[0025] The input terminal of the first buffer is connected to the input terminal of the positive clock signal, the input terminal of the second buffer is connected to the input terminal of the inverted clock signal, and the output terminal of the second buffer is connected to the input terminals of the first inverter and the second inverter.

[0026] In one embodiment, the source of the first PMOS is connected to the input voltage port and the source of the third PMOS, the gate of the first PMOS is connected to the drain of the second PMOS and the drain of the second NMOS, and the two ends of the first resistor are connected to the drain of the first PMOS and the positive terminal of the external capacitor.

[0027] The second resistor is connected to the positive terminal of the external capacitor and the source of the second PMOS, and the gate of the second PMOS is connected to the output terminal of the second inverter.

[0028] The two ends of the third resistor are connected to the negative terminal of the external capacitor and the drain of the third PMOS, respectively, and the gate of the third PMOS is connected to the output terminal of the first buffer.

[0029] The two ends of the forty-third resistor are respectively connected to the negative terminal of the external capacitor and the drain of the first NMOS, the gate of the first NMOS is connected to the output terminal of the first inverter, and the source of the first NMOS is connected to ground.

[0030] The gate of the second NMOS is connected to the input voltage port, the source of the second NMOS is connected to the drain of the third NMOS, the gate of the third NMOS is connected to the output of the first inverter, and the source of the third NMOS is connected to ground.

[0031] In one embodiment, both the positive and negative terminals of the external capacitor are connected in series with resistors for ESD protection.

[0032] In one embodiment, the path between the input voltage port and the negative terminal of the external capacitor is formed by a parallel connection of 40 PMOS devices and a resistor connected in series. Attached Figure Description

[0033] Figure 1 The diagram shown is a schematic of the charge pump structure of the present invention.

[0034] Figure 2 The diagram shown is a timing diagram of the non-overlapping clock of the present invention.

[0035] Figure 3 The diagram shown is an equivalent circuit diagram of the charge pump structure of the present invention during the charging phase.

[0036] Figure 4 The diagram shown is an equivalent circuit diagram of the charge pump structure of the present invention during the conversion stage.

[0037] Figure 5 The diagram shown is a schematic of the charge pump structure of the present invention used in a chip system architecture.

[0038] Figure 6 The diagram shows the trigger timing of the charge pump structure of the present invention for use in a chip system structure.

[0039] Figure 7 The diagram shown illustrates the simulation results of the charge pump structure of this invention used in a chip system architecture.

[0040] Figure 8 The results shown are the energy efficiency simulation results of the charge pump structure of the present invention used in a chip system structure. Detailed Implementation

[0041] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings to provide a clearer understanding of the purpose, features, and advantages of the present invention. It should be understood that the embodiments shown in the drawings are not intended to limit the scope of the present invention, but are merely illustrative of the essential spirit of the technical solution of the present invention.

[0042] In the following description, certain specific details are set forth for the purpose of illustrating various disclosed embodiments in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the art will recognize that embodiments may be practiced without one or more of these specific details. In other instances, well-known apparatuses, structures, and techniques associated with this application may not have been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0043] Unless the context requires otherwise, throughout the specification and claims, the word “comprising” and its variations, such as “including” and “having”, shall be understood to have an open, inclusive meaning, that is, to be interpreted as “including, but not limited to”.

[0044] Throughout this specification, references to "an embodiment" or "an embodiment" indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, the appearance of "in an embodiment" or "an embodiment" in various places throughout the specification does not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, or characteristic may be combined in any manner in one or more embodiments.

[0045] The singular forms “a” and “” used in this specification and the appended claims include plural references unless otherwise expressly stated herein. It should be noted that the term “or” is generally used to mean “or / and” unless otherwise expressly stated herein.

[0046] In the following description, in order to clearly demonstrate the structure and working method of the present invention, a number of directional terms will be used. However, terms such as "front", "back", "left", "right", "outside", "inside", "outward", "inward", "up", and "down" should be understood as convenient terms and not as limiting terms.

[0047] A charge pump is a commonly used circuit for DC-DC converters and an indispensable component in power management within integrated circuit design. Due to its simple peripheral circuitry, small chip area, and ease of integration, charge pumps are widely used in non-volatile memory, smart power integrated circuits, and, in recent years, energy harvesting systems for energy-autonomous devices.

[0048] Charge pumps have various topologies, including Dickson charge pumps, Fibonacci charge pumps, cross-coupled charge pumps, and four-phase charge pumps. These structures significantly reduce threshold voltage loss and improve voltage conversion efficiency, but they also involve complex circuit design and require a significant sacrifice in design area. With the continuous advancement of integrated circuit technology and processes, charge pumps with simpler circuit structures and control timings, and higher energy efficiency, will find widespread application in many scenarios.

[0049] like Figure 1 The diagram shows a schematic of the charge pump structure of the present invention. A high-efficiency charge pump structure for achieving a 2x voltage boost includes: a non-overlapping clock generation module and a charge pump circuit module. The non-overlapping clock module is connected to the charge pump circuit module and is used to generate non-overlapping timing control signals for the charge pump circuit.

[0050] The non-overlapping clock generation circuit module includes: a first inverter, a second inverter, a third inverter, a first NAND gate, a second NAND gate, a first delay unit, and a second delay unit; wherein,

[0051] The input of the first inverter is connected to the input clock signal port, the output of the first inverter is connected to one input of the first NAND gate, the other input of the first NAND gate is connected to the output of the second delay unit, the output of the first NAND gate is connected to the input of the first delay unit, the output of the first delay unit is connected to the input of the second inverter, and the output of the second inverter generates a non-overlapping positive clock CKP; one input of the second NAND gate is connected to the input clock signal port, the other input of the second NAND gate is connected to the output of the first delay unit, the output of the second NAND gate is connected to the input of the second delay unit, the output of the second delay unit is connected to the input of the third inverter, and the output of the third inverter generates a non-overlapping inverted clock CKN.

[0052] Furthermore, the aforementioned first delay unit and second delay unit utilize the inherent delay of the gate circuit itself, and achieve the delay by connecting an even number of inverters in series. The more inverters connected in series, the greater the delay generated by the delay unit, and thus the longer the non-overlapping time of the non-overlapping clock.

[0053] The charge pump circuit module includes: first to third NMOS transistors, first to forty-second PMOS transistors, first to forty-third resistors, a first buffer, a second buffer, a first inverter, a second inverter, and an external capacitor; wherein,

[0054] The first buffer input is connected to the non-inverting clock input, the second buffer input is connected to the inverting clock input, and the second buffer output is connected to the first inverter input and the second inverter input.

[0055] The source of the first PMOS is connected to the input voltage port and the sources of the third to forty-second PMOS transistors. The gate of the first PMOS is connected to the drain of the second PMOS and the drain of the second NMOS. The two ends of the first resistor are connected to the drain of the first PMOS and the positive terminal of the external capacitor. The second resistor is connected to the positive terminal of the external capacitor and the source of the second PMOS. The gate of the second PMOS is connected to the output terminal of the second inverter. The two ends of the third to forty-second resistors are respectively connected to the negative terminal of the external capacitor and the drain of the third to forty-second PMOS. The gates of the third to forty-second PMOS are connected to the output of the first buffer. The two ends of the forty-third resistor are respectively connected to the negative terminal of the external capacitor and the drain of the first NMOS. The gate of the first NMOS is connected to the output of the first inverter. The source of the first NMOS is connected to ground. The gate of the second NMOS is connected to the input voltage port. The source of the second NMOS is connected to the drain of the third NMOS. The gate of the third NMOS is connected to the output of the first inverter. The source of the third NMOS is connected to ground.

[0056] Furthermore, the non-overlapping clock generated by the aforementioned non-overlapping clock generation circuit is used to provide timing control signals to the gates of the MOSFETs in the aforementioned charge pump circuit, controlling the MOSFETs to turn on and off. The purpose of using non-overlapping is to avoid the situation where unexpected MOSFETs turn on simultaneously.

[0057] Furthermore, the capacitors in the aforementioned charge pump circuit are integrated off-chip, so resistors are connected in series between the positive and negative terminals of the capacitors and the internal components of the charge pump for ESD protection.

[0058] Furthermore, the path between the input voltage port and the negative terminal of the external capacitor is formed by a branch of 40 PMOS devices connected in series with a resistor in parallel. This is done to reduce the on-resistance between the input voltage port and the external capacitor during the boost stage, i.e. the conversion stage, thereby reducing the power loss caused by the on-resistance and achieving high energy efficiency output.

[0059] The timing diagram of the non-overlapping clock generation module is as follows: Figure 2 As shown, when a clock input signal CLK is given, the non-overlapping clock generation module uses the inherent delay output of the gate circuit to generate two non-overlapping positive and negative clock signals CKP and CKN. The delay unit in the non-overlapping clock generation module consists of an even number of inverters. The duration of non-overlapping between the two clock phases depends on the number of inverters in the delay unit; the more inverters in the delay unit, the longer the non-overlapping time.

[0060] The charge pump structure achieves a 2x voltage boost through two stages. The first stage is the charging stage, where the input voltage is connected to the positive terminal of an external capacitor to charge it. The second stage is the conversion stage, also called the boost stage, where the input voltage is connected to the negative terminal of the external capacitor. The 2x voltage boost output is achieved by utilizing the principle that the voltage difference across the capacitor cannot jump. The two-phase clock signals CKP and CKN from the non-overlapping clock output are used by a buffer and an inverter to generate timing control signals fi1, fi2, fi2d1, and fi2d2, which serve as control signals for the MOSFET switches in the charge pump. These signals control the MOSFET switches to turn on and off, thereby completing the charging and conversion stages of the charge pump.

[0061] like Figure 3 The diagram shows the equivalent circuit of the charge pump circuit of the present invention during the charging phase. Req1 represents the sum of the on-resistance of the first PMOS transistor P1 and the resistance of the first resistor R1, and Req2 represents the sum of the on-resistance of the first NMOS transistor N1 and the resistance of the forty-third resistor R43. During the charging phase, the non-overlapping two-phase clocks CKP and CKN are high and low, respectively. Therefore, the resulting control timing signal fi1 is high, meaning the gates of PMOS transistors P1 to P42 (from the third to the forty-second) are high, and all PMOS transistors are off. Control timing signal fi2 is low, so fi2d1 and fi2d2 are high. This means the gates of the first NMOS transistor N1 and the third NMOS transistor N3, controlled by fi2d1, are high, and the gate of the second PMOS transistor, controlled by fi2d2, is also high. Therefore, the first and third NMOS transistors are turned on, and the second PMOS transistor is turned off. It's important to note that the gate of the second NMOS transistor N2 is connected to the output voltage signal, so it remains high, meaning the second NMOS transistor is always on. Therefore, when the third NMOS transistor is on, the gate of the first PMOS transistor will be connected to ground, meaning the gate of the first PMOS transistor is low, and the first PMOS transistor is on. As mentioned earlier, during the charge pump charging phase, a... Figure 3 The equivalent circuit shown in this stage will charge the positive terminal of the capacitor with the power supply voltage Vin.

[0062] In this circuit, the second NMOS transistor is always on, so it has no impact on the circuit's function. Its presence ensures that the third NMOS transistor is in the saturation region when it is on. This is because the PMOS threshold voltage is larger than the NMOS threshold voltage. In this embodiment, both the input voltage and the high level of the clock signal are the power supply voltage VDD. Without the second NMOS transistor, when the first PMOS transistor is on, the drain-source voltage of the third PMOS transistor would be less than the overdrive voltage, with the difference equal to the difference between the PMOS and NMOS threshold voltages. Consequently, the third NMOS transistor would enter the linear region. However, by adding the second NMOS transistor, the third NMOS transistor is precisely in the saturation region when the first PMOS transistor is on.

[0063] like Figure 4 The diagram shows the equivalent circuit of the charge pump circuit of the present invention during the conversion stage. Req3 represents the equivalent resistance value of the on-resistance of the third PMOS transistor P3 to the forty-second PMOS transistor P42, connected in series and then in parallel with the third resistor R3 to the forty-second resistor R42. In fact, it is 1 / 40 of the sum of the on-resistances of the third PMOS transistor and the third resistor, because in this embodiment, the third to forty-second PMOS transistors are identical, and the third to forty-second resistors are also identical. During the conversion phase, the non-overlapping two-phase clocks CKP and CKN are low and high, respectively. Therefore, the resulting control timing signal fi1 is low, meaning the gates of PMOS transistors P1 to P42 (from the third to the forty-second) are low, and all PMOS transistors are turned on. Control timing signal fi2 is high, so fi2d1 and fi2d2 are low. This means the gates of the first NMOS transistor N1 and the third NMOS transistor N3, controlled by the fi2d1 signal, are low, and the gate of the second PMOS transistor, controlled by the fi2d2 signal, is also low. Therefore, the first and third NMOS transistors are turned off, and the second PMOS transistor is turned on. This results in the gate of the first PMOS transistor being high, and the first PMOS transistor being turned off. As mentioned earlier, during the charge pump conversion phase, a... Figure 4 The equivalent circuit shown in this stage is equivalent to a DC voltage, which is an input voltage Vin. Therefore, when an input voltage signal is applied to the negative terminal of the capacitor, since the voltage difference across the capacitor does not change, the positive terminal of the capacitor will generate an output voltage Vout with a voltage value equal to two input voltages.

[0064] like Figure 5The diagram shows a schematic of a chip system architecture design for the charge pump structure of the present invention in one embodiment. This embodiment is a chip transmitter for photoelectric sensing, comprising: an LED driver module, a control logic module, a non-overlapping clock generation module, and a charge pump module. The LED driver module provides driving current to off-chip integrated infrared and blue LEDs, driving them to emit light. In this embodiment, the power supply voltage VDD is 3V, which is sufficient to provide a driving voltage for the infrared LED. However, due to the relationship between the driving current and voltage of the blue LED, a forward driving voltage greater than VDD is required to ensure the blue LED operates normally. Therefore, a charge pump is needed to boost the power supply voltage to provide a driving voltage for the blue LED. The control logic module generates the control timing for each module, including the input clock timing for the non-overlapping clock module and the output current timing for the LED driver module.

[0065] like Figure 6 The diagram shows the trigger timing of the charge pump structure in one embodiment of the present invention. In this embodiment, the control logic module generates the timing of the infrared LED and the blue LED after a given input clock CLK_in, controlling the infrared LED and the blue LED to emit light. Before the timing of the blue LED arrives, the control logic module first generates an input signal CLK for a timing control non-overlapping clock. When the input signal CLK is low, the charge pump is in the charging phase. After CLK becomes high, the charge pump enters the conversion phase. The control logic module controls CLK to change from low to high, allowing the charge pump to complete the voltage boost. Then, when the timing of the blue LED arrives, the charge pump can provide sufficient bias voltage to the blue LED.

[0066] like Figure 7 The diagram shown illustrates the simulation results of the charge pump structure of the present invention in one embodiment. This simulation result only shows the light emission of the blue LED in the emitter of the aforementioned photoelectric sensor chip. Please refer to... Figure 7The signal CLK is the clock input of the aforementioned non-overlapping module; the signal CP is the positive voltage of the aforementioned external capacitor when the power supply voltage is 3V, i.e., the output voltage of the charge pump; the signal Iout2 is the driving current of the blue LED, which in this embodiment is 25mA. It can be seen that when the signal CLK is low, the output voltage of the charge pump is always the power supply voltage of 3V. When CLK jumps to high, the charge pump boosts the positive voltage of the capacitor to twice the power supply voltage, 6V. When the driving current signal Iout2 arrives, due to the equivalent resistance between the MOSFET switch's on-resistance and the path formed by the resistor value and the negative terminal CN of the capacitor, the output of the charge pump will experience a voltage drop. The loss is the voltage drop across this equivalent resistance caused by Iout2. Then, due to the presence of current, according to the relationship between capacitor current and voltage...

[0067]

[0068] A capacitor undergoes a discharge process, causing the voltage to change over time. The slope of this change is the ratio of the current value to the capacitance value, i.e., I / C.

[0069] like Figure 8 The figure shows the energy efficiency simulation results of the charge pump structure of the present invention in one embodiment. For a charge pump with a 2x boost voltage, its energy efficiency is...

[0070]

[0071] Based on the simulation results, it can be calculated that when the charge pump is used to drive the aforementioned blue LED, the energy efficiency of the charge pump is approximately 93.7%.

[0072] In this embodiment, the energy loss is mainly due to the voltage loss caused by the impedance between the capacitor and the input voltage port when the charge pump provides the driving voltage. Therefore, the smaller this impedance, the smaller the voltage loss. This embodiment uses forty identical branches connected in parallel to reduce this impedance value. In application, the number of parallel branches can be flexibly set according to the actual energy efficiency requirements; the higher the energy efficiency requirements, the more parallel branches are set. Secondly, the discharge of the capacitor when the charge pump provides the driving voltage is also a cause of energy loss. The larger the current, the more obvious the energy loss caused by this reason. As can be seen from the above relationship between capacitor voltage and current, the loss caused by capacitor discharge can be reduced by increasing the capacitor. In practical applications, the capacitor value should also be selected according to the design specifications.

[0073] Therefore, the high-efficiency charge pump structure for achieving a 2x voltage boost, as described in this invention, has a relatively simple circuit structure. Furthermore, the charge pump structure employs a non-overlapping clock to avoid unexpected simultaneous conduction of MOSFET switches. In addition, the charge pump structure also provides ESD protection for internal components, preventing damage from electrostatic discharge, thus exhibiting good reliability and safety. Regarding energy efficiency, the charge pump structure reduces the on-resistance between the capacitor and the input voltage when the charge pump provides the driving voltage to the circuit by connecting multiple identical branches in parallel. This reduces energy loss caused by on-resistance, achieving high-efficiency output from the charge pump. It has broad application prospects in circuit structures requiring a 2x voltage boost.

[0074] The preferred embodiments of the present invention have been described in detail above, but it should be understood that, if necessary, aspects of the embodiments can be modified to utilize aspects, features, and concepts from various patents, applications, and publications to provide other embodiments.

[0075] In light of the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the claims should not be considered limited to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments together with the full scope of equivalents enjoyed by these claims.

Claims

1. A charge pump structure, characterized in that, It includes a non-overlapping clock generation module and a charge pump circuit module connected to the non-overlapping clock generation module; The non-overlapping clock generation module is used to generate non-overlapping timing control signals for the charge pump circuit module; The charge pump circuit module is used to boost the input voltage under the timing control signal; The charge pump circuit module includes two operating states: a charging state and a switching state, which alternate between the charging state and the switching state. The charge pump circuit module includes an external capacitor; When the charge pump circuit module is in a charging state, the input voltage is connected to the positive terminal of the external capacitor to charge the external capacitor. When the charge pump circuit module is in the switching state, the input voltage is connected to the negative terminal of the external capacitor for boosting the input voltage. The charge pump circuit module further includes a first circuit unit, a second circuit unit, a third circuit unit, a fourth circuit unit, and a fifth circuit unit; The first circuit unit includes a first PMOS transistor P1 and a first resistor R1 connected in series. The second circuit unit includes a first NMOS transistor N1 and a forty-third resistor R43 connected in series. The third circuit unit includes a third PMOS transistor P3 and a third resistor R3 connected in series. The fourth circuit unit includes a second PMOS transistor P2 and a second resistor R2 connected in series. The fifth circuit unit includes a second NMOS transistor N2 and a third NMOS transistor N3 connected in series. When the charge pump circuit module is in the charging state, the first PMOS transistor P1, the first NMOS transistor N1, the third NMOS transistor N3, and the second NMOS transistor N2 remain on, while the third PMOS transistor P3 and the second PMOS transistor P2 remain off. When the charge pump circuit module is in the switching state, the first PMOS transistor P1, the first NMOS transistor N1, and the third NMOS transistor N3 remain off, while the third PMOS transistor P3, the second PMOS transistor P2, and the second NMOS transistor N2 remain on.

2. The charge pump structure according to claim 1, characterized in that, The non-overlapping clock generation module is implemented based on gate circuits; When a clock input signal is given, the non-overlapping clock generation module uses the delay output of the gate circuit itself to generate two non-overlapping positive clock signals and an inverted clock signal.

3. The charge pump structure according to claim 1, characterized in that, The third circuit unit includes a fourth PMOS transistor P4 and a fourth resistor R4 connected in series, and the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected in parallel.

4. The charge pump structure according to claim 2, characterized in that, The charge pump circuit module further includes a first buffer, a second buffer, a first inverter, and a second inverter; The input terminal of the first buffer is connected to the input terminal of the positive clock signal, the input terminal of the second buffer is connected to the input terminal of the inverted clock signal, and the output terminal of the second buffer is connected to the input terminals of the first inverter and the second inverter.

5. The charge pump structure according to claim 4, characterized in that, The source of the first PMOS is connected to the input voltage port and the source of the third PMOS transistor. The gate of the first PMOS is connected to the drain of the second PMOS and the drain of the second NMOS. The two ends of the first resistor are connected to the drain of the first PMOS and the positive terminal of the external capacitor. The second resistor is connected to the positive terminal of the external capacitor and the source of the second PMOS, and the gate of the second PMOS is connected to the output terminal of the second inverter. The two ends of the third resistor are connected to the negative terminal of the external capacitor and the drain of the third PMOS, respectively, and the gate of the third PMOS is connected to the output terminal of the first buffer. The two ends of the forty-third resistor are respectively connected to the negative terminal of the external capacitor and the drain of the first NMOS, the gate of the first NMOS is connected to the output terminal of the first inverter, and the source of the first NMOS is connected to ground. The gate of the second NMOS is connected to the input voltage port, the source of the second NMOS is connected to the drain of the third NMOS, the gate of the third NMOS is connected to the output of the first inverter, and the source of the third NMOS is connected to ground.

6. The charge pump structure according to claim 1, characterized in that, The positive and negative terminals of the external capacitor are connected in series with resistors for ESD protection.

7. The charge pump structure according to claim 1, characterized in that, The path between the input voltage port and the negative terminal of the external capacitor is formed by a parallel connection of several PMOS devices and resistors connected in series.

8. The charge pump structure according to claim 7, characterized in that, The path between the input voltage port and the negative terminal of the external capacitor is formed by a parallel connection of 40 PMOS devices and a resistor connected in series.

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