A buffer voltage equalization circuit and converter topology for turn-off converters

Abstract

The application belongs to the field of converters and provides a buffer voltage equalization circuit and a converter topology structure of a turn-off converter. The buffer voltage equalization circuit comprises a buffer circuit and a voltage equalization circuit, and the buffer circuit and the voltage equalization circuit are connected in parallel. The buffer circuit comprises a capacitor-resistor branch and a buffer branch connected in parallel with a turn-off device. The capacitor-resistor branch comprises a buffer capacitor and a buffer resistor connected in series. The buffer branch is connected in parallel with the buffer resistor. The buffer branch is turned on when the turn-off device is turned off, and the buffer resistor is short-circuited. By arranging the buffer branch connected in parallel with the buffer resistor Rs, when the turn-off device is turned off, the buffer resistor is short-circuited by controlling the turn-on of the buffer branch, so that the voltage on the buffer resistor is prevented from being too high and the turn-off device is prevented from being damaged.

Description

Technical Field

[0001] This invention belongs to the field of converters, and specifically relates to a buffer voltage equalization circuit and converter topology that can turn off a converter. Background Technology

[0002] In recent years, high-voltage direct current (HVDC) transmission technology has developed rapidly, and line-commutated converter (LCC-HVDC) technology plays an important role in HVDC transmission. However, LCC-HVDC technology can experience commutation failure when AC grid faults cause voltage drops.

[0003] To address the aforementioned issues, Chinese invention patent (patent application number: CN202010201942.1) discloses a voltage equalization circuit for a hybrid converter in high-voltage direct current transmission, proposing a novel hybrid converter topology. This converter differs from traditional converters in that its bridge arms are composed of turn-off valve strings. A portion of the thyristors in the traditional converter valve strings are replaced with fully controllable devices, forming a turn-off device-thyristor series structure. In this structure, the active turn-off capability of the fully controllable devices is utilized to solve the commutation failure problem. The adaptability of the buffer circuit needs to be considered for both normal steady-state operation and the turn-off process. In this patent, the buffer voltage equalization circuit is as follows: Figure 1 As shown, this type of buffer voltage equalization circuit requires a large resistor to buffer the voltage equalization effect in order to keep power consumption low during normal steady-state operation (including turn-on transient, on-state, and reverse recovery processes). During turn-off, because the current first transfers to the branch containing the larger resistor, a particularly large voltage is generated across this resistor. Due to the steep-wave effect of the surge arrester, this current cannot effectively protect the turn-off transistor, potentially causing it to break down. Therefore, a buffer voltage equalization circuit that can simultaneously meet both of these operating conditions is needed. Summary of the Invention

[0004] To address the aforementioned problems, this invention discloses a buffer voltage equalization circuit for a switchable converter, the buffer voltage equalization circuit comprising a buffer circuit and a voltage equalization circuit connected in parallel;

[0005] The buffer circuit includes a capacitor-resistor branch connected in parallel with the turn-off device and a buffer branch.

[0006] The capacitor-resistor branch includes a buffer capacitor and a buffer resistor connected in series.

[0007] The buffer branch is connected in parallel with the buffer resistor; the buffer branch is turned on when the turn-off device is turned off, short-circuiting the buffer resistor.

[0008] Furthermore, the buffer branch includes a unidirectional diode, which is connected in parallel with the buffer resistor;

[0009] The direction of the conduction current of the unidirectional diode is the same as the direction of the current generated when the turn-off device is turned off.

[0010] Furthermore, the buffer branch also includes a current-limiting resistor, which is connected in series with a unidirectional diode.

[0011] Furthermore, the buffer branch includes a thyristor, which is connected in parallel with the buffer resistor;

[0012] When the turn-off device receives the turn-off signal, the thyristor receives the turn-on trigger signal.

[0013] Furthermore, the buffer branch also includes a current-limiting resistor, which is connected in series with the thyristor.

[0014] Furthermore, the buffer branch includes a first surge arrester, which is connected in parallel with a buffer resistor;

[0015] The operating voltage of the first surge arrester is greater than the voltage across the terminals of the shut-off device under normal conditions.

[0016] Furthermore, the voltage equalization circuit includes a voltage equalization resistor connected in parallel with the turn-off device, the voltage equalization resistor being connected in parallel with the capacitor-resistor branch.

[0017] Furthermore, the voltage equalization circuit includes a second surge arrester connected in parallel with the turn-off device. The second surge arrester is connected in parallel with the capacitor-resistor branch to limit the damaging voltage generated across the turn-off device.

[0018] Furthermore, the turn-off device is an insulated gate bipolar transistor (IGBT), a gate turn-off thyristor (GTO), an integrated gate commutated thyristor (IGCT), an injection enhancement gate transistor (IEGT), or a combination thereof.

[0019] On the other hand, the present invention also discloses a converter topology, the topology including one or more single valves, the multiple single valves being electrically connected;

[0020] The single valve includes multiple sub-modules and a saturated reactor; the multiple sub-modules are interconnected and then connected in series with the saturated reactor.

[0021] The submodule includes multiple unit modules connected in series and a second surge arrester, and the total circuit composed of the multiple unit modules is connected in parallel with the second surge arrester;

[0022] The unit module includes the aforementioned buffer voltage equalization circuit and a turn-off device; the buffer voltage equalization circuit and the turn-off device are connected in parallel.

[0023] Furthermore, two single valves form a double valve, and the two single valves in the double valve are connected in series, with the AC branch connected between the two single valves.

[0024] Furthermore, multiple double valves are connected in parallel to form a first-level pulsating topology; each double valve is connected to an AC branch between the two single valves.

[0025] Furthermore, the double valve is connected in parallel with the protective surge arrester.

[0026] Furthermore, the two ends of the first-stage pulsating topology are respectively connected to the positive and negative terminals of the DC side.

[0027] Furthermore, multiple first-level pulsating topologies are connected in series to form a multi-level pulsating topology, with the two ends of the multi-level pulsating topology connected to the positive and negative terminals of the DC side, respectively.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] This invention provides a buffer voltage equalization circuit for a turn-off converter. A buffer branch is connected in parallel with a buffer resistor Rs. When the turn-off device is turned off, the conduction of the buffer branch is controlled to short-circuit the buffer resistor, preventing excessive voltage across it. Under normal steady-state operation, the buffer resistor Rs acts as a buffer voltage equalization device, achieving low power consumption during this process. During turn-off, the current first transfers to the buffer branch, short-circuiting the buffer resistor Rs and preventing excessive voltage across it. Even if the surge effect of the MOV (Medium-Voltage Transistor) occurs, it provides excellent protection for the turn-off device.

[0030] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures pointed out in the description and the drawings. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A schematic diagram of a buffer voltage equalization circuit for a turn-off converter in the prior art is shown;

[0033] Figure 2This diagram illustrates a buffer voltage equalization circuit for a turn-off converter according to an embodiment of the RCD scheme of the present invention.

[0034] Figure 3 A schematic diagram of a buffer voltage equalization circuit for another turn-off converter in the RCD scheme of this invention is shown.

[0035] Figure 4 A schematic diagram of a buffer voltage equalization circuit for a turn-off converter according to an embodiment of the RC-SCR scheme of the present invention is shown.

[0036] Figure 5 A schematic diagram of a buffer voltage equalization circuit for another turn-off converter in the RC-SCR scheme of this invention is shown.

[0037] Figure 6 A schematic diagram of a buffer voltage equalization circuit for a turn-off converter in an RC-MOV scheme according to an embodiment of the present invention is shown.

[0038] Figure 7 A schematic diagram of a buffer voltage equalization circuit for a turn-off converter according to an embodiment of the RC-DSCR scheme of the present invention is shown.

[0039] Figure 8 A schematic diagram of a buffer voltage equalization circuit for another turn-off converter in the RC-DSCR scheme of this invention is shown.

[0040] Figure 9 This invention illustrates a circuit diagram for protecting multiple unit modules in an embodiment of the present invention.

[0041] Figure 10 This invention illustrates another circuit diagram for protecting multiple unit modules in an embodiment of the present invention;

[0042] Figure 11 A schematic diagram of a single valve according to an embodiment of the present invention is shown;

[0043] Figure 12 A schematic diagram of a six-pulse converter topology according to an embodiment of the present invention is shown;

[0044] Figure 13 A schematic diagram of a twelve-pulse converter topology according to an embodiment of the present invention is shown. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] This invention proposes several buffer voltage equalization circuits for turn-off high-voltage direct current (HVDC) converters, primarily to resolve the contradiction between the need for a large buffer resistor Rs in the steady-state power dissipation of the turn-off device and the need for a smaller resistor due to the steep wave effect of the surge arrester MOV during turn-off current. The turn-off device can be an insulated-gate bipolar transistor (IGBT), a gate turn-off thyristor (GTO), an integrated gate commutated thyristor (IGCT), an injection enhancement-gate transistor (IEGT), or combinations thereof, or combinations thereof with thyristors.

[0047] In one embodiment of the present invention, the buffer voltage equalization circuit of the turn-off converter includes a buffer circuit and a voltage equalization circuit, wherein the buffer circuit and the voltage equalization circuit are connected in parallel.

[0048] The buffer circuit includes a buffer capacitor Cs resistor branch connected in parallel with the turn-off device and a buffer branch.

[0049] The buffer capacitor Cs resistor branch includes a buffer capacitor Cs and a buffer resistor Rs connected in series.

[0050] The buffer branch is connected in parallel with the buffer resistor Rs; the buffer branch is turned on when the turn-off device is turned off, short-circuiting the buffer resistor Rs.

[0051] The switchable device and its corresponding buffer voltage equalization circuit form a unit module.

[0052] One embodiment is as follows: the buffer branch includes a unidirectional diode D, which is connected in parallel with a buffer resistor Rs; the direction of the conduction current of the unidirectional diode D is the same as the direction of the current generated when the turn-off device is turned off. The buffer branch also includes a resistor R, which is connected in series with the unidirectional diode D.

[0053] Another approach is as follows: the buffer branch includes a thyristor connected in parallel with a buffer resistor Rs; when the turn-off device receives a turn-off signal, the thyristor receives a turn-on trigger signal. The buffer branch also includes a current-limiting resistor R connected in series with the thyristor.

[0054] A further embodiment is as follows: the buffer branch includes a first surge arrester, which is connected in parallel with a buffer resistor Rs; the operating voltage of the first surge arrester is greater than the voltage across the buffer resistor Rs when the turn-off device is in the on state.

[0055] The voltage equalization circuit in the above scheme includes a voltage equalization resistor Rp connected in parallel with the turn-off device, and the voltage equalization resistor Rp is connected in parallel with the resistor branch of the buffer capacitor Cs.

[0056] In addition, the voltage equalization circuit may also include a second surge arrester connected in parallel with the turn-off device, the second surge arrester being connected in parallel with the buffer capacitor Cs resistor branch.

[0057] In addition, multiple of the above-mentioned unit modules are connected in series; the total circuit composed of multiple unit modules is connected in parallel with the third surge arrester MOV to form a sub-module.

[0058] This submodule can be applied as a whole to the converter to form the converter's topology, which includes one or more single valves electrically connected to each other.

[0059] The single valve includes multiple sub-modules and a saturated reactor as described above; the multiple sub-modules are interconnected and then connected in series with the saturated reactor.

[0060] Two single valves form a double valve, and the two single valves in the double valve are connected in series, with the AC side branch connected between the two single valves.

[0061] Furthermore, multiple double valves connected in parallel can form a single-stage pulsating topology; each of the two single valves within a double valve is connected to an AC-side branch. Each of the double valves can be connected in parallel with a surge arrester (MOV). The two ends of the single-stage pulsating topology are connected to the positive and negative terminals of the DC side, respectively.

[0062] Furthermore, multiple first-level pulsating topologies connected in series can form a multi-level pulsating topology, with the two ends of the multi-level pulsating topology connected to the positive and negative terminals of the DC side, respectively.

[0063] To better explain the above technical solutions, the following examples will be used for detailed explanation.

[0064] like Figure 1 The diagram shows a buffer voltage equalization circuit for an existing turn-off converter. The buffer voltage equalization circuit includes a voltage equalization resistor Rp branch connected in parallel with the turn-off transistor Q, a surge arrester MOV branch, and an RC branch.

[0065] Figure 2The diagram shows a schematic of a buffer voltage equalization circuit for a turn-off converter according to an embodiment of the RCD scheme of the present invention. In this scheme, the turn-off device is a turn-off transistor Q, which is connected in parallel with the buffer circuit and the voltage equalization circuit. The buffer circuit includes a buffer capacitor Cs resistor branch and a buffer branch connected in parallel with the turn-off transistor Q.

[0066] The buffer capacitor Cs resistor branch includes a buffer capacitor Cs and a buffer resistor Rs connected in series.

[0067] The buffer branch is connected in parallel with the buffer resistor Rs; the buffer branch conducts when the turn-off device is turned off, short-circuiting the buffer resistor Rs; the buffer branch includes a unidirectional diode D, which is connected in parallel with the buffer resistor Rs; the direction of the conduction current of the unidirectional diode D is the same as the direction of the current generated when the turn-off device is turned off.

[0068] The switchable device and its corresponding buffer voltage equalization circuit form a unit module.

[0069] The voltage equalization circuit includes a voltage equalization resistor Rp connected in parallel with the turn-off device, and the voltage equalization resistor Rp is connected in parallel with the resistor branch of the buffer capacitor Cs.

[0070] The voltage equalization circuit also includes a second surge arrester connected in parallel with the turn-off device, and the second surge arrester is also connected in parallel with the buffer capacitor Cs resistor branch.

[0071] Figure 3 The diagram shows another schematic of a buffer voltage equalization circuit for a turn-off converter according to an embodiment of the RCD scheme of the present invention. In this scheme, the buffer branch further includes a current-limiting resistor R, which is connected in series with a unidirectional diode D.

[0072] The RCD scheme utilizes the single-phase current-carrying characteristic of diode D. When the turn-off transistor Q is on, diode D is off, and the charge on the buffer capacitor Cs is discharged through the buffer resistor Rs, effectively exhibiting a large resistance characteristic and preventing current from flowing during turn-off. During the conduction period, the characteristics are high resistance for half the time and low resistance for the other half, avoiding the problem of high power consumption when using only a small resistor. When the reverse recovery voltage of the buffer capacitor Cs is established, diode D is off, and the buffer capacitor Cs is reverse-charged through the buffer resistor Rs. When the turn-off transistor Q is off, since the current is forward, diode D conducts, preventing excessively high voltage from generating on the buffer resistor Rs and causing breakdown of the turn-off transistor Q and the buffer capacitor Cs. This resolves the contradiction between the need for a large buffer resistor Rs for the steady-state power consumption of the turn-off transistor Q and the need for a small resistor due to the steep wave effect of the surge arrester MOV during turn-off current. In this topology, the voltage equalization resistor Rp is a static voltage equalization resistor, also known as a DC voltage equalization resistor, which is typically in the tens of kiloohms range. It ensures the voltage equalization of multiple turn-off devices under DC bias. The surge arrester MOV protects the devices and prevents them from being damaged by high voltage during turn-off.

[0073] Figure 4 The diagram shows a schematic of a buffer voltage equalization circuit for a turn-off converter according to an embodiment of the RC-SCR scheme of the present invention. In this scheme, the turn-off transistor Q is a turn-off transistor Q, which is connected in parallel with the buffer circuit and the voltage equalization circuit. The buffer circuit includes a buffer capacitor Cs resistor branch and a buffer branch connected in parallel with the turn-off transistor Q. The buffer capacitor Cs resistor branch includes a buffer capacitor Cs and a buffer resistor Rs connected in series.

[0074] The buffer branch is connected in parallel with the buffer resistor Rs; the buffer branch is turned on when the turn-off transistor Q is turned off, short-circuiting the buffer resistor Rs; the buffer branch includes a thyristor SCR, which is connected in parallel with the buffer resistor Rs; when the turn-off transistor Q receives a turn-off signal, the thyristor receives a turn-on trigger signal.

[0075] The voltage equalization circuit includes a voltage equalization resistor Rp connected in parallel with the turn-off transistor Q, and the voltage equalization resistor Rp is connected in parallel with the resistor branch of the buffer capacitor Cs. The voltage equalization circuit also includes a second surge arrester connected in parallel with the turn-off transistor Q, and the second surge arrester is also connected in parallel with the resistor branch of the buffer capacitor Cs.

[0076] The turn-off transistor Q and its corresponding buffer voltage equalization circuit form a unit module.

[0077] Figure 5 The diagram shows a buffer voltage equalization circuit for another turn-off converter in the RC-SCR scheme of this invention. The buffer branch also includes a current-limiting resistor R, which is connected in series with the thyristor.

[0078] In the RC-SCR scheme, under normal operating conditions, the turn-off transistor Q operates without abnormalities, and the thyristor SCR does not conduct. When the turn-off transistor Q needs to perform its turn-off function, the turn-off signal and the thyristor SCR trigger signal are issued simultaneously. When the turn-off command is issued, the thyristor SCR conducts. At this time, the buffer resistor Rs is bypassed by the thyristor SCR, and no overvoltage will occur, thus protecting the device.

[0079] Figure 6 The diagram shows a schematic of a buffer voltage equalization circuit for a turn-off converter in an RC-MOV scheme according to an embodiment of the present invention. In this scheme, the turn-off transistor Q is a turn-off transistor Q, which is connected in parallel with the buffer circuit and the voltage equalization circuit. The buffer circuit includes a buffer capacitor Cs resistor branch and a buffer branch connected in parallel with the turn-off transistor Q. The buffer capacitor Cs resistor branch includes a buffer capacitor Cs and a buffer resistor Rs connected in series.

[0080] The buffer branch is connected in parallel with the buffer resistor Rs; the buffer branch is turned on when the turn-off transistor Q is turned off, short-circuiting the buffer resistor Rs; the buffer branch includes a first surge arrester, which is connected in parallel with the buffer resistor Rs; the operating voltage of the first surge arrester is greater than the voltage across the buffer resistor Rs when the turn-off device is on.

[0081] The voltage equalization circuit includes a voltage equalization resistor Rp connected in parallel with the turn-off transistor Q, and the voltage equalization resistor Rp is connected in parallel with the resistor branch of the buffer capacitor Cs. The voltage equalization circuit also includes a second surge arrester connected in parallel with the turn-off transistor Q, and the second surge arrester is also connected in parallel with the resistor branch of the buffer capacitor Cs.

[0082] The turn-off transistor Q and its corresponding buffer voltage equalization circuit form a unit module.

[0083] The working principle of the RC-MOV scheme is as follows: Under normal circumstances, the voltage across the buffer resistor Rs is relatively small, and it only becomes larger when the resistor is turned off. A first surge arrester is connected in parallel across the buffer resistor Rs, and the operating voltage of the first surge arrester is set to be slightly higher than the maximum value of the voltage of all turn-off transistors Q in the non-turn-off state. In this way, the first surge arrester will only work when the resistor is turned off, diverting the current and preventing a high voltage from appearing on the buffer resistor Rs, thus protecting the device.

[0084] Besides the aforementioned buffer voltage equalization circuits, the buffer branch can also be a module D / SCR including a diode D or a thyristor SCR, such as... Figure 7 Additionally, modules including diodes (D) or thyristors (SCRs) can be connected in series with current-limiting resistors (R) to form a buffer branch, such as... Figure 8 .

[0085] In the above-mentioned schemes, the second surge arrester in the voltage equalization circuit only protects one unit module. However, the second surge arrester can be modified to protect multiple units, such as... Figure 9 and Figure 10 As shown, with Figure 7 or Figure 8 The intermediate or complete buffer voltage equalization circuit and the turn-off transistor Q are connected as a unit module. Multiple unit modules are connected in series, and the total circuit composed of multiple unit modules is connected in parallel with the second surge arrester MOV to form a sub-module. The second surge arrester can protect multiple unit modules. Figure 9 The turn-off transistor Q is connected in parallel with the buffer circuit. Figure 10 The turn-off transistor Q is connected in parallel with the buffer circuit and the voltage equalization resistor Rp. It should also be noted that the buffer branch can be replaced with the buffer branch found in the RCD or RC-SCR schemes. A current-limiting resistor R can also be connected in series in the buffer branch.

[0086] by Figure 9 or Figure 10 This can be used as a submodule (SM) for further explanation. Figure 11 Medium single-weight valve, Figure 12 The topology of the six-pulse converter and Figure 13 Construction of the topology of the 12-pulse converter.

[0087] exist Figure 11 The single-phase valve described herein comprises multiple sub-modules (SM1, SM2, ..., SMn) and a saturated reactor; the multiple sub-modules are interconnected and then connected in series with the saturated reactor. The single-phase valve can be composed of a single sub-module SM or multiple sub-modules SM connected in a mixed configuration. Furthermore, the turn-off devices in the sub-module SM can be insulated-gate bipolar transistors (IGBTs), gate turn-off thyristors (GTOs), integrated gate commutated thyristors (IGCTs), injection-enhanced gate transistors (IEGTs), etc., and can be composed of a mixed configuration of these devices, or a mixed configuration of these active turn-off devices and the aforementioned thyristors.

[0088] Figure 12 A schematic diagram of a six-pulse converter topology according to an embodiment of the present invention is shown. The topology includes six single valves; two single valves form a double valve group, and the two single valves within each double valve group are connected in series. Three-phase branches A, B, and C on the AC side are each connected between two single valves in a double valve group. Multiple double valves connected in parallel constitute a single-stage pulsating topology, i.e., a six-pulsating converter topology. The two ends of the single-stage pulsating topology are connected to the positive terminal P and the negative terminal N of the DC side, respectively. Figure 12 The double valve selected in the middle box can also be connected in parallel with a protection MOV.

[0089] Figure 13A schematic diagram of a twelve-pulse converter topology according to an embodiment of the present invention is shown. This twelve-pulse converter topology (i.e., a two-stage pulsating topology) is composed of two six-pulse converter topologies connected in series. The two ends of the twelve-pulse converter topology are connected to the positive and negative terminals of the DC side, respectively. Figure 13 The four single valves selected in the middle frame form a quadruple valve, and the quadruple valve can also be connected in parallel with a protection MOV.

[0090] In actual engineering projects, there are also converter stations that consist of two or more twelve-pulse converters to achieve ultra-high voltage direct current transmission.

[0091] The six-pulse and twelve-pulse converters built from this submodule SM, and the multiple converters formed by them, can be connected in series and used in ultra-high voltage projects. This topology can be used on both the rectifier side and the inverter side.

[0092] This invention incorporates a buffer branch connected in parallel with the buffer resistor Rs. When the turn-off device is turned off, the conduction of the buffer branch is controlled to short-circuit the buffer resistor, preventing excessive voltage across it. Under normal steady-state operation, this buffer voltage equalization circuit allows the buffer resistor Rs to function as a buffer and equalizer, achieving the goal of low power consumption during normal steady-state operation. During turn-off, the current first transfers to the buffer branch, short-circuiting the buffer resistor Rs and preventing excessive voltage across it. Even if the steep wave effect of the surge arrester MOV occurs, it can still provide good protection for the turn-off device.

[0093] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A buffer voltage equalization circuit for a switchable converter, characterized in that, The buffer voltage equalization circuit includes a buffer circuit and a voltage equalization circuit, which are connected in parallel. The buffer circuit includes a capacitor-resistor branch connected in parallel with the turn-off device and a buffer branch. The capacitor-resistor branch includes a buffer capacitor and a buffer resistor connected in series. The buffer branch is connected in parallel with the buffer resistor; the buffer branch is turned on when the turn-off device is turned off, short-circuiting the buffer resistor. The voltage equalization circuit includes a voltage equalization resistor connected in parallel with the turn-off device, and the voltage equalization resistor is connected in parallel with the capacitor-resistance branch; The buffer branch includes a thyristor, which is connected in parallel with a buffer resistor; When the turn-off device receives the turn-off signal, the thyristor receives the turn-on trigger signal; The voltage equalization circuit includes a second surge arrester connected in parallel with the turn-off device. The second surge arrester is connected in parallel with the capacitor-resistor branch to limit the damaging voltage generated across the turn-off device.

2. The buffer voltage equalization circuit for a turn-off converter according to claim 1, characterized in that, The buffer branch also includes a current-limiting resistor, which is connected in series with the thyristor.

3. The buffer voltage equalization circuit for a turn-off converter according to claim 1, characterized in that, The buffer branch includes a first surge arrester, which is connected in parallel with a buffer resistor; The operating voltage of the first surge arrester is greater than the voltage across the terminals of the shut-off device under normal conditions.

4. The buffer voltage equalization circuit for a turn-off converter according to claim 1, characterized in that, The turn-off device is an insulated gate bipolar transistor (IGBT), a gate turn-off thyristor (GTO), an integrated gate commutated thyristor (IGCT), an injection enhancement gate transistor (IEGT), or a combination thereof.

5. A converter topology, characterized in that, The topology includes one or more single valves, and the multiple single valves are electrically connected. The single valve includes multiple sub-modules and a saturated reactor; the multiple sub-modules are interconnected and then connected in series with the saturated reactor. The submodule includes multiple unit modules connected in series and a second surge arrester, and the total circuit composed of the multiple unit modules is connected in parallel with the second surge arrester; The unit module includes a turn-off device and a buffer voltage equalization circuit as described in any one of claims 1-4; the buffer voltage equalization circuit is connected in parallel with the turn-off device.

6. The converter topology according to claim 5, characterized in that, Two single valves form a double valve, and the two single valves in the double valve are connected in series, with the AC side branch connected between the two single valves.

7. The converter topology according to claim 6, characterized in that, Multiple double valves are connected in parallel to form a single-stage pulsating topology; each double valve is connected to an AC branch between the two single valves.

8. The converter topology according to claim 6 or 7, characterized in that, The double valve is connected in parallel with the protective surge arrester.

9. The converter topology according to claim 7, characterized in that, The two ends of the first-stage pulsating topology are connected to the positive and negative terminals of the DC side, respectively.

10. The converter topology according to claim 7, characterized in that, Multiple first-level pulsating topologies are connected in series to form a multi-level pulsating topology, with the two ends of the multi-level pulsating topology connected to the positive and negative terminals of the DC side, respectively.

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