Display panel, display device including the same, and mobile terminal

Abstract

The present disclosure relates to a display panel, a display device and a mobile terminal including the same. The display panel includes a first pixel area, a second pixel area and a boundary pixel area arranged between the first pixel area and the second pixel area. The boundary pixel area includes a plurality of first emission areas and a plurality of second emission areas. The maximum brightness of the first emission area decreases as the distance from the second pixel area increases, and the maximum brightness of the second emission area increases as the distance from the second pixel area increases.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2022-0054899 filed in Korea on May 3, 2022, and Korean Patent Application No. 10-2022-0079664 filed in Korea on June 29, 2022, each of which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display panel having an optical element disposed thereunder, a display device including the same, and a mobile terminal. Background Art

[0004] According to the material of the light-emitting layer, electroluminescent display devices are generally classified into inorganic light-emitting display devices and organic light-emitting display devices. Active matrix organic light-emitting display devices include self-luminous organic light-emitting diodes (hereinafter referred to as "OLED"), and have the advantages of fast response speed and high luminous efficiency, brightness and viewing angle. In an organic light-emitting display device, an OLED is formed in a pixel. Since the organic light-emitting display device has a fast response speed, and is excellent in luminous efficiency, brightness and viewing angle, and can present a black gradient in a full black color, the organic light-emitting display device is excellent in contrast and color reproducibility.

[0005] Recently, various optical elements have been added to mobile terminals. The optical element may include a sensor or lighting device required to support multimedia functions or perform biometrics. The optical element may be assembled under the display panel. In order to expand the screen of the mobile terminal, the optical element may be set in a notch area designed to be concave on the top of the screen of the display panel, or in a perforation within the screen. However, since no image is displayed in the notch area or perforation, there are many limitations in the design of full-screen display. Summary of the invention

[0006] Recently, a technology has been proposed to provide an area with low pixel density in a display panel and to dispose an optical element below the area. This technology can realize full-screen display because the optical element is placed below the area where the image is displayed, but the boundary between the area with high pixel density and the area with low pixel density may be visually recognized, and a sense of unevenness in brightness and color between the areas may be felt.

[0007] An object of the present disclosure is to address the above-mentioned needs and / or problems.

[0008] The present disclosure provides a display panel capable of preventing boundary recognition and a sense of unevenness between regions having different pixel densities, and a display device and a mobile terminal including the same.

[0009] Problems of the present disclosure are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0010] A display panel according to an embodiment of the present disclosure includes a first pixel area, a second pixel area, and a boundary pixel area arranged between the first pixel area and the second pixel area. The boundary pixel area includes a plurality of first emission areas and a plurality of second emission areas. Each of the first emission area and the second emission area includes one or more pixels. At least one of the plurality of second emission areas is arranged between the first emission areas adjacent to each other. The maximum brightness of the first emission area decreases as the distance from the second pixel area increases, and the maximum brightness of the second emission area increases as the distance from the second pixel area increases.

[0011] A display device according to an embodiment of the present disclosure includes: a display panel, the display panel including a first pixel area, a second pixel area, and a boundary pixel area arranged between the first pixel area and the second pixel area; and a display panel driver, the display panel driver is configured to write pixel data of an input image into pixels arranged in the pixel area of ​​the display panel. The second pixel area includes a plurality of unit emission areas. The boundary pixel area includes a plurality of unit emission areas. Each of the unit emission areas of the second pixel area includes an emission area and a non-emission area. Each of the unit emission areas of the boundary pixel area has the same size as the unit emission area of ​​the second pixel area. Each of the unit emission areas of the boundary pixel area includes a first emission area and a second emission area. The distance between the first emission areas is equal to the distance between the emission areas of the second pixel area, wherein the second emission area is between the first emission areas. The maximum brightness of the first emission area decreases as the distance from the second pixel area increases, and the maximum brightness of the second emission area increases as the distance from the second pixel area increases.

[0012] A mobile terminal according to an embodiment of the present disclosure includes: a display panel, the display panel including a first pixel area, a second pixel area, and a boundary pixel area arranged between the first pixel area and the second pixel area; and a display panel driver, the display panel driver is configured to write pixel data of an input image into pixels arranged in the pixel area of ​​the display panel; and an optical element, the optical element is arranged below the second pixel area of ​​the display panel. The second pixel area includes a plurality of unit emission areas. The boundary pixel area includes a plurality of unit emission areas. Each of the unit emission areas of the second pixel area includes an emission area and a non-emission area. Each of the unit emission areas of the boundary pixel area has the same size as the unit emission area of ​​the second pixel area. Each of the unit emission areas of the boundary pixel area includes a first emission area and a second emission area. The first emission areas are spaced apart from each other by a distance equal to the distance between the emission areas of the second pixel area, wherein the second emission area is between the first emission areas. The maximum brightness of the first emission area decreases as the distance from the second pixel area increases, and the maximum brightness of the second emission area increases as the distance from the second pixel area increases.

[0013] According to the present disclosure, full screen display can be achieved because the optical module is disposed below the screen on which an image is displayed.

[0014] According to the present disclosure, by controlling the emission spatial periods of the boundary pixel region and the second pixel region to be substantially the same, the sense of non-uniformity of the boundary pixel region may be reduced.

[0015] According to the present disclosure, by controlling the brightness of the pixel so that the brightness of the first emission region of the boundary pixel region gradually changes between the first pixel region and the second pixel region, the sense of non-uniformity of the pixel region can be reduced.

[0016] According to the present disclosure, by controlling the brightness of the first emission area and the second emission area using the first gamma compensation curve and the second gamma compensation curve having different maximum brightness in the boundary pixel area, the color difference between the pixel areas can be improved.

[0017] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0019] Figure 1 is a cross-sectional view schematically showing a display panel according to an embodiment of the present disclosure;

[0020] Figure 2 is a diagram showing an optical element overlapping a second pixel region of a display panel according to an embodiment of the present disclosure;

[0021] Figure 3 is a diagram showing an example of an optical element disposed in a second pixel region and a notch region according to an embodiment of the present disclosure;

[0022] Figure 4 is a diagram showing a pixel arrangement of a first pixel region according to an embodiment of the present disclosure;

[0023] Figure 5A and Figure 5B is a diagram showing pixel arrangement of a boundary pixel region and a second pixel region according to an embodiment of the present disclosure;

[0024] Figures 6 to 8 is a circuit diagram showing various pixel circuits applicable to a display device according to an embodiment of the present disclosure;

[0025] Fig. 9 The present invention is a driving example of an embodiment of the present invention. Figure 8 A waveform diagram of the pixel circuit method shown;

[0026] Fig.10 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0027] Fig.11 is a diagram showing an example in which a display device is applied to a mobile device according to an embodiment of the present disclosure;

[0028] Fig. 12A and Fig. 12B is a plan view showing a unit emission area of ​​a second pixel region and a boundary pixel region according to an embodiment of the present disclosure;

[0029] Figures 13 to 16 2 is a diagram showing various embodiments of a second pixel region UDC and a boundary pixel region BDR according to an embodiment of the present disclosure;

[0030] Fig.17 is a diagram showing an example in which a spatial period of a unit emission area of ​​a boundary pixel region is the same as a spatial period of a unit emission area of ​​a second pixel region according to an embodiment of the present disclosure;

[0031] Fig.18 is a diagram showing an example in which the luminances of the first emission region and the second emission region of the boundary pixel region gradually change to be opposite to each other between the first pixel region and the second pixel region according to an embodiment of the present disclosure;

[0032] Fig.19A is a diagram showing an example of an area ratio between a first emission region and a second emission region in a boundary pixel area according to an embodiment of the present disclosure;

[0033] Fig.19B is a diagram showing a method for controlling a Fig.19A A diagram showing an example of a method for determining brightness per unit emission area in FIG.

[0034] Fig. 20A is a diagram showing another example of an area ratio between a first emission region and a second emission region in a boundary pixel area according to an embodiment of the present disclosure;

[0035] Fig. 20B is a diagram showing a method for controlling a Fig. 20A A diagram showing an example of a method for determining brightness per unit emission area in FIG.

[0036] Fig.21 and Fig. 22 is a diagram showing an effect of improving the sense of unevenness of a boundary pixel region according to an embodiment of the present disclosure;

[0037] Fig.23 is a diagram showing a comparative example in which high-brightness emission areas are adjacent to each other and low-brightness emission areas are adjacent to each other at the left boundary of the second pixel region according to an embodiment of the present disclosure;

[0038] Fig.24 is an enlarged view showing the left boundary of the second pixel region in the simulation of the comparative example;

[0039] Fig.25 is a diagram showing a comparative example in which high-brightness emission areas are adjacent to each other and low-brightness emission areas are adjacent to each other at an upper boundary of a second pixel region;

[0040] Fig.26 is an enlarged view showing an upper boundary of a second pixel region in a simulation of a comparative example;

[0041] Fig. 27 is a diagram showing an effect of improving color difference in a boundary pixel region according to an embodiment of the present disclosure; and

[0042] Fig.28 is a diagram illustrating an example of a single gamma reference voltage range and a gamma compensation curve according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] From the embodiments described below with reference to the accompanying drawings, the advantages and features of the present disclosure and the methods for realizing the same will be more clearly understood. However, the present disclosure is not limited to the following embodiments, but can be implemented in various forms. On the contrary, the present embodiments will make the disclosure of the present disclosure complete and enable those skilled in the art to fully understand the scope of the present disclosure.

[0044] The shapes, sizes, ratios, angles, numbers, etc. shown in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0045] Terms such as "include," "comprising," "having," and "including" used herein are generally intended to allow the addition of other components unless these terms are used with the term "only." Any reference to the singular may include the plural unless explicitly stated otherwise.

[0046] Even if not explicitly stated, the components are interpreted as including ordinary error ranges.

[0047] When terms such as "on", "above", "below", "beside", "connected", "coupled", "crossed", "intersecting", etc. are used to describe the positional relationship between two components, unless these terms are used with the terms "immediately" or "directly", one or more components may be located between the two parts.

[0048] The terms "first", "second", etc. may be used to distinguish components from each other, but the function or structure of a component is not limited by the sequence number or component name preceding the component. These terms may not limit any order.

[0049] Like reference numerals may refer to substantially like elements throughout this disclosure.

[0050] The following embodiments may be partially or entirely joined or combined with each other and may be linked and operated in various ways in technology. The embodiments may be performed independently or in association with each other.

[0051] In each display device of the present disclosure, the pixel circuit and the gate drive circuit may include a plurality of transistors. The transistor may be implemented as an oxide thin film transistor (oxide TFT) including an oxide semiconductor, a low temperature polysilicon (LTPS) TFT including low temperature polysilicon, etc. Each transistor may be implemented as a p-channel TFT or an n-channel TFT.

[0052] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that provides carriers to the transistor. In a transistor, carriers flow from the source. The drain is an electrode through which carriers leave the transistor. In a transistor, carriers can flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. An n-channel transistor has a current direction flowing from the drain to the source. In the case of a p-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0053] The gate signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate-on voltage, and is turned off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage VGH and VEH, and the gate-off voltage may be a gate low voltage VGL and VEL. In the case of a p-channel transistor, the gate-on voltage may be a gate low voltage VGL and VEL, and the gate-off voltage may be a gate high voltage VGH and VEH.

[0054] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0055] Reference Figures 1 to 3 , the display panel 100 includes a screen for reproducing an input image according to an embodiment of the present disclosure.

[0056] The pixel array constituting the screen of the display panel 100 may include a first pixel region NML and a second pixel region UDC. The first pixel region NML and the second pixel region UDC include pixels into which pixel data of an input image is written. Therefore, the input image may be displayed in the first pixel region NML and the second pixel region UDC.

[0057] The first pixel area NML is a display area where a plurality of pixels are arranged to reproduce an input image. The first pixel area NML is larger than the second pixel area UDC and is the main display area of ​​the screen on which most images are displayed. The second pixel area UDC is a display area where a plurality of pixels are arranged to reproduce an input image. The pixel density or resolution of the second pixel area UDC may be equal to or less than the pixel density or resolution of the first pixel area NML. The pixel density may be interpreted as pixels per inch (PPI).

[0058] The second pixel region UDC may include a plurality of light-transmitting portions without a light-blocking medium, but is not limited thereto. The light-transmitting portions may be disposed between sub-pixels. Light may pass through the light-transmitting portions with little loss. When the light-transmitting portions of the second pixel region UDC are enlarged to increase the amount of light received by the optical element incident thereon through the second pixel region UDC, the pixel density is reduced due to the area of ​​the light-transmitting portions, so that the pixel density or resolution of the second pixel region UDC may become less than the pixel density or resolution of the first pixel region NML.

[0059] Each pixel in the first pixel area NML and the second pixel area UDC includes sub-pixels with different colors to realize image color. The sub-pixels include red sub-pixels, green sub-pixels, and blue sub-pixels. Hereinafter, the red sub-pixel is abbreviated as "R sub-pixel", the green sub-pixel is abbreviated as "G sub-pixel", and the blue sub-pixel is abbreviated as "B sub-pixel". Each pixel may also include a white sub-pixel. Each sub-pixel may include a pixel circuit for driving a light-emitting element.

[0060] One or more optical elements 200 may be disposed under the rear surface of the display panel 100 to overlap the second pixel region UDC of the display panel 100. External light may travel to the optical element 200 disposed under the display panel 100 through the second pixel region UDC. The optical element 200 may include at least one of an image sensor (or camera), a proximity sensor, a white light illuminator, and an optical element for facial recognition.

[0061] The optical element for facial recognition may include an infrared light source, an infrared camera, an infrared illuminator, etc., which are disposed under the second pixel region UDC of the display panel 100. Figure 2 In the embodiment, reference numeral "201" denotes an infrared light source, and reference numeral "202" denotes an infrared camera, but they are not limited thereto. Figure 3 In the example of FIG. 2 , the ambient light sensor 204, the proximity sensor 205, the flood illuminator 206, the infrared camera 202, and the front camera 207 can be arranged in the notch area 210 of the mobile terminal, and the infrared light source 201 can be arranged in the second pixel area UDC. The notch area 210 is a non-display area without pixels at the top of the screen of the mobile terminal.

[0062] In the display device of the present disclosure, since the optical element 200 is disposed under the rear surface of the display panel 100 to overlap with the second pixel region UDC, the display area of ​​the screen is not limited by the optical element 200. Therefore, the display device of the present disclosure can realize full-screen display by expanding the display area of ​​the screen and increase the freedom of screen design.

[0063] The display panel 100 has a width along a first direction (X axis), a length along a second direction (Y axis), and a thickness along a third direction (Z axis). The first direction and the second direction are orthogonal to each other on the plane of the display panel 100. The display panel 100 may include a circuit layer 12 disposed on a substrate and a light emitting element layer 14 disposed on the circuit layer 12. A polarizing plate 18 may be disposed on the light emitting element layer 14, and a cover glass 20 may be disposed on the polarizing plate 18.

[0064] The circuit layer 12 may include pixel circuits connected to lines such as data lines, gate lines intersecting the data lines, and power lines, gate drivers connected to the gate lines, etc. The circuit layer 12 may include transistors implemented as thin film transistors (TFTs) and circuit elements such as capacitors. The wiring and circuit elements of the circuit layer 12 may be formed by a plurality of insulating layers, two or more metals separated by insulating layers, and an active layer including a semiconductor material.

[0065] The light emitting element layer 14 may include a light emitting element driven by a pixel circuit. The light emitting element may be implemented with an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), a light emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), but is not limited thereto. When a voltage is applied to the anode electrode and the cathode electrode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light emitting layer (EML) to form excitons, and visible light is emitted from the light emitting layer (EML). The light emitting element layer 14 may also include a color filter array disposed on the light emitting element to selectively transmit red wavelengths, green wavelengths, and blue wavelengths.

[0066] The light emitting element layer 14 may be covered by a passivation layer, and the passivation layer may be covered by an encapsulation layer. The passivation layer and the encapsulation layer may have a multi-insulating film structure in which an organic film and an inorganic film are alternately stacked. The inorganic film blocks the penetration of moisture or oxygen. The organic film flattens the surface of the inorganic film. When the organic film and the inorganic film are stacked into multiple layers, the movement path of moisture or oxygen becomes longer than that of a single layer, thereby effectively blocking the penetration of moisture / oxygen that affects the light emitting element layer 14.

[0067] A touch sensor layer omitted from the drawings may be formed on the encapsulation layer, and a polarizing plate 18 or a color filter layer may be provided on the touch sensor layer. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on a capacitance change before and after the touch input. The touch sensor layer may include an insulating film and a metal wiring pattern that form the capacitance of the touch sensor. The insulating film may insulate the cross-section in the metal wiring pattern and may flatten the surface of the touch sensor layer. The polarizing plate 18 may improve visibility and contrast by converting the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer. The polarizing plate 18 may be implemented as a circular polarizing plate or a polarizing plate in which a linear polarizing plate and a phase delay film are bonded. The cover glass 20 may be bonded to the polarizing plate 18. The color filter layer provided on the touch sensor layer may include a red filter, a green filter, and a blue filter. The color filter layer may also include a black matrix pattern. The color filter layer may absorb a portion of the wavelength of light reflected from the circuit layer and the touch sensor layer to replace the role of the polarizing plate 18 and increase the color purity of the image reproduced in the pixel array. In this case, the polarizing plate 18 is not required.

[0068] Figure 4 is a diagram showing an example of pixel arrangement of the first pixel region NML according to an embodiment of the present disclosure. Figure 5A and Figure 5B is a diagram showing an example of pixels and light-transmitting portions of a second pixel region UDC according to an embodiment of the present disclosure. Figures 4 to 5B The lines connecting to the pixels are omitted.

[0069] Reference Figure 4 , the first pixel region NML includes a plurality of pixels. Each pixel may be implemented as a real-type pixel in which an R sub-pixel, a G sub-pixel, and a B sub-pixel of three primary colors are configured as one pixel. Each pixel may also include a W sub-pixel omitted in the drawings. The pixel density of the first pixel region NML may be higher than the pixel density of the second pixel region UDC.

[0070] Using a sub-pixel rendering algorithm, each pixel may be composed of two sub-pixels. For example, a first pixel may be composed of an R sub-pixel and a first G sub-pixel, and a second pixel may be composed of a B sub-pixel and a second G sub-pixel. The insufficient color representation in each of the first pixel and the second pixel may be compensated by the average value of the corresponding color data between adjacent pixels.

[0071] In a sub-pixel, the luminous efficiency of the light-emitting element may be different for each color. Taking this into account, the size of the sub-pixel may be different for each color. For example, among the R sub-pixel, the G sub-pixel, and the B sub-pixel, the B sub-pixel may be the largest, and the G sub-pixel may be the smallest.

[0072] Reference Figure 5A and Figure 5B , the second pixel region UDC includes pixel groups PG spaced apart by a predetermined distance and a light-transmitting portion AG disposed between adjacent pixel groups PG. The pixel group disposed in the region indicated by the dotted line includes a plurality of sub-pixels.

[0073] The light-transmitting portion AG is a region without pixels. The light-transmitting portion AG may be made of a transparent insulating material without including metal lines or pixels. Due to the light-transmitting portion AG, the pixel density of the second pixel region UDC may be reduced, but the average light transmittance of the second pixel region UDC may become greater than the average light transmittance of the first pixel region NML, thereby increasing the amount of light received by the optical element 200.

[0074] In the second pixel region UDC, one or two pixels may be included in the pixel group PG to emit light having a brightness corresponding to the grayscale of the pixel data. Each pixel in the pixel group PG may include two to four sub-pixels. Figure 5A and Figure 5B In the example of , the first pixel is composed of an R sub-pixel and a G sub-pixel, and the second pixel is composed of a B sub-pixel and a G sub-pixel, but the present disclosure is not limited thereto. The emission area in the pixel group PG is determined as the sum of the emission areas of the sub-pixels connected to the pixel group PG.

[0075] The shape and size of the emission area of ​​each color in each pixel in the first pixel area and the second pixel area are determined by a fine metal mask (FMM). The emission area of ​​each color in the pixel group PG of the second pixel area UDC can be designed to be substantially the same as the emission area of ​​each color of the first pixel area NML, or can be designed to have a shape and / or size different from the shape and / or size of the emission area of ​​the first pixel area NML by using an FMM having a shape different from that of the first pixel area NML.

[0076] The shape of the light-transmitting portion AG is Figure 5A and Figure 5B For example, the light-transmitting portion AG may be designed in various shapes, such as a circle, an ellipse, and a polygon.

[0077] Due to process deviation and element characteristic deviation caused in the manufacturing process of the display panel, there may be differences in the electrical characteristics of the driving element between pixels, and such differences may increase as the driving time of the pixels elapses. In order to compensate for the deviation of the electrical characteristics of the driving element between pixels, an internal compensation technology or an external compensation technology may be applied to the organic light emitting display device.

[0078] like Figure 5A and Figure 5BAs shown, the pixel array of the display panel 100 further includes a boundary pixel region BDR having a predetermined size disposed between the first pixel region NML and the second pixel region UDC.

[0079] The boundary pixel region BDR is a pixel region of a predetermined size between the first pixel region NML and the second pixel region UDC. The boundary pixel region BDR includes a plurality of pixels. Figure 5A As shown, the pixel density of the boundary pixel region BDR can be designed to be substantially the same as the pixel density of the first pixel region NML and higher than the pixel density of the second pixel region UDC. The pixel density of the boundary pixel region BDR can be less than the pixel density of the first pixel region NML. In another embodiment, as Figure 5B As shown, the pixel density of a portion of the boundary pixel region BDR adjacent to the second pixel region UDC may be lower than the pixel density of the first pixel region NML, and may be equal to or higher than the pixel density of the second pixel region UDC.

[0080] At least one of the pixel density, pixel size, and pixel maximum brightness may be different between the first pixel region NML and the second pixel region UDC. Therefore, the boundary pixel region BDR may be viewed differently from the first pixel region NML and the second pixel region UDC. In order to reduce the phenomenon of visually identifying the boundary pixel region BDR, in the present disclosure, Fig. 12A and Fig. 12B As shown, a unit emission area UA' having the same size as the unit emission area UA of the second pixel area UDC is defined in the boundary pixel area BDR. The first emission area BA in each unit emission area UA' of the boundary pixel area BDR has a spatial period (or distance) similar to or equal to the spatial period (or distance) of the emission area A of the second pixel area UDC.

[0081] The pixel density of the boundary pixel region BDR may be designed to be the same as the pixel density of the first pixel region NML. The boundary pixel region BDR may be interpreted as a partial pixel region included in the first pixel region NML close to the second pixel region UDC.

[0082] The internal compensation technology uses an internal compensation circuit implemented in each pixel circuit to sense the threshold voltage of the driving element of each sub-pixel, and compensates the gate-source voltage Vgs of the driving element by the threshold voltage. The external compensation technology uses an external compensation circuit to sense the current or voltage of the driving element in real time according to the change of the electrical characteristics of the driving element. The external compensation technology compensates for the deviation (or change) of the electrical characteristics of the driving element in each pixel in real time by modulating the pixel data (digital data) of the input image according to the deviation (or change) of the electrical characteristics of the driving element sensed for each pixel.

[0083] Figures 6 to 8 is a circuit diagram showing various pixel circuits applicable to any display device according to an embodiment of the present disclosure.

[0084] In the first example, refer to Figure 6 The pixel circuit includes a light emitting element EL, a driving element DT configured to supply current to the light emitting element EL, a switching element M01 configured to connect the data line DL to the second node n2 in response to a scan pulse SCAN, and a capacitor Cst connected between the second node n2 and a third node n3. The driving element DT and the switching element M01 may be implemented as n-channel transistors.

[0085] The driving element DT includes a gate electrode connected to the second node n2, a first electrode connected to the first node n1, and a second electrode connected to the third node n3. A VDD (power) line PL to which a pixel driving voltage ELVDD is applied is connected to the first node n1. The light emitting element EL includes an anode connected to the third node n3 and a cathode connected to a VSS line to which a low potential power voltage ELVSS is applied.

[0086] The driving element DT drives the light emitting element EL by supplying current to the light emitting element EL according to the gate-source voltage Vgs. When the forward voltage between the anode and the cathode is equal to or greater than the threshold voltage, the light emitting element EL is turned on and emits light. The capacitor Cst is connected between the gate electrode and the source electrode of the driving element DT to maintain the gate-source voltage Vgs of the driving element DT.

[0087] Figure 7 A second example of a pixel circuit according to an embodiment is shown.

[0088] Reference Figure 7 ,Apart from Figure 6 In addition to the configuration of the pixel circuit shown, the pixel circuit further includes a second switch element M02 connected between the reference voltage line REFL and the second electrode of the driving element DT. In the pixel circuit, the driving element DT and the switch elements M01 and M02 can be implemented as n-channel transistors.

[0089] The second switching element M02 applies a reference voltage VREF to the third node n3 in response to a scan pulse SCAN or a separate sensing pulse SENSE. The reference voltage VREF is applied to the pixel circuit through a REF line REFL.

[0090] In the sensing mode, the current flowing through the channel of the driving element DT or the voltage between the driving element DT and the light-emitting element EL can be sensed through the reference line REFL. The current flowing through the reference line REFL is converted into a voltage by an integrator and converted into digital data by an analog-to-digital converter (hereinafter referred to as "ADC"). The digital data is sensing data including the threshold voltage or mobility information of the driving element DT. The sensing data is sent to the data operation unit. The data operation unit receives the sensing data from the ADC and compensates for the driving deviation and degradation of the pixel by adding the compensation value selected based on the sensing data to the pixel data or by multiplying the compensation value selected based on the sensing data by the pixel data.

[0091] Figure 8 is a circuit diagram showing a third example of the pixel circuit according to an embodiment of the present disclosure. Fig. 9 The present invention is a driving example of an embodiment of the present invention. Figure 8 The waveform diagram of the pixel circuit method is shown.

[0092] Reference Figure 8 and Fig. 9 The pixel circuit includes a light emitting element EL, a driving element DT configured to supply current to the light emitting element EL, and a switch circuit configured to switch voltages applied to the light emitting element EL and the driving element DT.

[0093] The switch circuit is connected to the power lines PL1, PL2 and PL3, the data line DL and the gate lines GL1, GL2 and GL3 to which the pixel driving voltage ELVDD, the low potential power voltage ELVSS and the initialization voltage Vini are applied, and switches the voltage applied to the light emitting element EL and the driving element DT in response to the gate signal. The gate signal may include scan pulses SCAN (N-1) and SCAN (N) and an emission control pulse (hereinafter referred to as "EM pulse") EM (N). Here, N is a number, such as a positive integer.

[0094] The switching circuit includes an internal compensation circuit that samples a threshold voltage Vth of the driving element DT using a plurality of switching elements M1 to M6, stores the voltage in a capacitor Cst, and compensates a gate voltage of the driving element DT by the threshold voltage Vth of the driving element DT. Each of the driving element DT and the switching elements M1 to M6 may be implemented as a p-channel TFT.

[0095] The driving period of the pixel circuit can be divided into an initialization period Tini, a sampling period Tsam and a light emitting period Tem. Fig. 9 shown.

[0096] In the sampling period Tsam, the Nth scan pulse SCAN(N) is generated at the gate-on voltage VGL and applied to the first gate line GL1. In the initialization period Tini before the sampling period, the (N-1)th scan pulse SCAN(N-1) is generated at the gate-on voltage VGL and applied to the second gate line GL2. In the initialization period Tini and the sampling period Tsam, an emission control pulse (hereinafter referred to as an "EM pulse") EM(N) is generated at the gate-off voltage VEH and applied to the third gate line GL3.

[0097] During the initialization period Tini, the (N-1)th scan pulse SCAN(N-1) is generated at the gate-on voltage VGL, and the voltage of each of the Nth scan pulse SCAN(N) and the EM pulse EM(N) is the gate-off voltage VGH / VEH. During the sampling period Tsam, the Nth scan pulse SCAN(N) is generated at the gate-on voltage VGL, and the voltage of each of the (N-1)th scan pulse SCAN(N-1) and the EM pulse EM(N) is the gate-off voltage VGH / VEH. During at least a portion of the light emission period Tem, the EM pulse EM(N) is generated at the gate-on voltage VEL, and the voltage of each of the (N-1)th scan pulse SCAN(N-1) and the Nth scan pulse SCAN(N) is the gate-off voltage VGH.

[0098] During the initialization period Tini, the fifth switching element M5 is turned on in response to the gate-on voltage VGL of the (N-1)th scan pulse SCAN(N-1) to initialize the pixel circuit. During the sampling period Tsam, the first switching element M1 and the third switching element M3 are turned on in response to the gate-on voltage VGL of the Nth scan pulse SCAN(N), so that the data voltage Vdata compensated by the threshold voltage of the driving element DT is stored in the capacitor Cst. In addition, during the sampling period Tsam, the sixth switching element M6 is turned on to reduce the voltage of the fourth node n4 to the reference voltage VREF, thereby suppressing the light emission of the light emitting element EL.

[0099] When the light-emission period Tem starts, the EM line GL3 is inverted to the gate-on voltage VEL. During the light-emission period Tem, the scan lines GL1 and GL2 maintain the gate-off voltage VGH. During the light-emission period Tem, since the second switch element M2 and the fourth switch element M4 are turned on, the light-emitting element EL can emit light. During the light-emission period Tem, in order to accurately express the brightness of the low gray scale, the voltage level of the EM pulse EM(N) can be inverted between the gate-on voltage VEL and the gate-off voltage VEH at a predetermined duty ratio. In this case, the second switch element M2 and the fourth switch element M4 can be repeatedly turned on / off according to the duty ratio of the EM pulse EM(N) during the light-emission period Tem.

[0100] The anode of the light emitting element EL is connected to the fourth node n4 between the fourth switching element M4 and the sixth switching element M6. The fourth node n4 is connected to the anode of the light emitting element EL, the second electrode of the fourth switching element M4, and the second electrode of the sixth switching element M6. The cathode of the light emitting element EL is connected to the VSS line PL3 to which the low potential power supply voltage ELVSS is applied. The light emitting element EL emits light using the current Ids flowing according to the gate-source voltage Vgs of the driving element DT. The current path of the light emitting element EL is switched by the second switching element M2 and the fourth switching element M4.

[0101] The storage capacitor Cst is connected between the VDD line PL1 and the second node n2. The data voltage Vdata compensated by the threshold voltage Vth of the driving element DT is charged into the capacitor Cst. Since the data voltage Vdata in each sub-pixel is compensated by the threshold voltage Vth of the driving element DT, the characteristic deviation of the driving element DT in the sub-pixel is compensated.

[0102] The third switching element M3 is turned on in response to the gate-on voltage VGL of the Nth scan pulse SCAN(N) to connect the second node n2 to the third node n3. The second node n2 is connected to the gate electrode of the driving element DT, the first electrode of the capacitor Cst, and the first electrode of the third switching element M3. The third node n3 is connected to the second electrode of the driving element DT, the second electrode of the third switching element M3, and the first electrode of the fourth switching element M4. The gate electrode of the third switching element M3 is connected to the Nth scan line GL1 to receive the Nth scan pulse SCAN(N). The first electrode of the third switching element M3 is connected to the second node n2, and the second electrode of the third switching element M3 is connected to the third node n3.

[0103] Since the first switching element M1 is turned on during a very short one horizontal period (1H) in which the Nth scan signal SCAN(N) is generated as the gate-on voltage VGL in one frame period, leakage current may occur in the off state. In order to suppress the leakage current of the first switching element M1, the first switching element M1 may be implemented with a transistor having a dual-gate structure in which two transistors are connected in series.

[0104] The first switching element M1 is turned on in response to the gate-on voltage VGL of the Nth scan pulse SCAN(N) to supply the data voltage Vdata to the first node n1. The gate electrode of the first switching element M1 is connected to the Nth gate line GL1 to receive the Nth scan pulse SCAN(N). The first electrode of the first switching element M1 is connected to the first node n1. The second electrode of the first switching element M1 is connected to the data line DL of the first area DA to which the data voltage Vdata is applied. The first node n1 is connected to the first electrode of the first switching element M1, the second electrode of the second switching element M2, and the first electrode of the driving element DT.

[0105] The second switch element M2 is turned on in response to the gate-on voltage VEL of the EM pulse EM(N) to connect the VDD line PL1 to the first node n1. The gate electrode of the second switch element M2 is connected to the EM line GL3 to receive the EM pulse EM(N). The first electrode of the second switch element M2 is connected to the VDD line PL1. The second electrode of the second switch element M2 is connected to the first node n1.

[0106] The fourth switch element M4 is turned on in response to the gate-on voltage VEL of the EM pulse EM(N) to connect the third node n3 to the anode of the light emitting element EL. The gate electrode of the fourth switch element M4 is connected to the EM line GL3 to receive the EM pulse EM(N). The first electrode of the fourth switch element M4 is connected to the third node n3, and the second electrode is connected to the fourth node n4.

[0107] The fifth switch element M5 is turned on in response to the gate-on voltage VGL of the N-1th scan pulse SCAN (N-1) to connect the second node n2 to the Vini line PL2. The gate electrode of the fifth switch element M5 is connected to the N-1th scan line GL2 to receive the N-1th scan pulse SCAN (N-1). The first electrode of the fifth switch element M5 is connected to the second node n2, and the second electrode is connected to the Vini line PL2. In order to suppress the leakage current of the fifth switch element M5, the fifth switch element M5 is implemented with a transistor having a dual-gate structure in which two transistors are connected in series.

[0108] The sixth switching element M6 is turned on in response to the gate-on voltage VGL of the Nth scan pulse SCAN(N) to connect the Vini line PL2 to the fourth node n4. The gate electrode of the sixth switching element M6 is connected to the Nth scan line GL1 to receive the Nth scan pulse SCAN(N). The first electrode of the sixth switching element M6 is connected to the Vini line PL2, and the second electrode of the sixth switching element M6 is connected to the fourth node n4.

[0109] In another embodiment, the gate electrodes of the fifth switching element M5 and the sixth switching element M6 may be commonly connected to the N-1th scan line GL2 to which the N-1th scan pulse SCAN(N-1) is applied. In this case, the fifth switching element M5 and the sixth switching element M6 may be simultaneously turned on in response to the N-1th scan pulse SCAN(N-1).

[0110] The driving element DT drives the light emitting element EL by controlling the current flowing through the light emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate connected to the second node n2, a first electrode connected to the first node n1, and a second electrode connected to the third node n3. Fig. 9 In FIG. 1 , “DTG” is the gate voltage of the driving element DT, that is, the voltage of the second node n2.

[0111] It should be noted that the configuration of the pixel circuit present in the display device of the present disclosure is not limited to Figures 6 to 8 For example, the data voltage Vdata may be applied to the gate electrode of the driving element DT or to the first electrode or the second electrode of the driving element DT. The gamma characteristic curve of the data voltage Vdata may be set to a positive gamma curve or an inverse gamma curve according to the channel characteristics of the driving element DT or the electrode to which the data voltage Vdata is applied. The data voltage Vdata may be applied to the first electrode or the second electrode of the n-channel driving element DT, or the data voltage Vdata may be applied to the gate electrode of the p-channel driving element DT. The data voltage Vdata applied to the gate electrode of the n-channel driving element DT is a voltage determined by a positive gamma curve. The data voltage Vdata applied to the first electrode or the second electrode of the n-channel driving element DT is a voltage determined by an inverse gamma curve. The data voltage Vdata applied to the gate electrode of the p-channel driving element DT is a voltage determined by an inverse gamma curve. The data voltage Vdata applied to the first electrode or the second electrode of the p-channel driving element DT is a voltage determined by a positive gamma curve.

[0112] Fig.10 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0113] Reference Fig.10A display device according to an embodiment of the present disclosure includes: a display panel 100, display panel drivers 110 and 120 for writing pixel data of an input image into pixels P of the display panel 100, a timing controller 130 for controlling the display panel driver, and a power supply unit 150 for generating power required to drive the display panel 100.

[0114] The display panel 100 includes a pixel array for displaying an input image on a screen. As described above, the pixel array may be divided into a first pixel region NML and a second pixel region UDC. Each sub-pixel of the pixel array may be used Figures 6 to 8 The pixel circuit shown is used to drive the light emitting element EL. As a variation, the pixel array may include one or more first pixel areas DA and one or more second pixel areas CA.

[0115] A touch sensor may be provided on the screen of the display panel 100. The touch sensor may be implemented as an on-cell type or add-on type touch sensor provided on the screen of the display panel, or may be implemented as an in-cell type touch sensor embedded in a pixel array.

[0116] The display panel 100 may be implemented as a flexible display panel in which pixels P are provided on a flexible substrate such as a plastic substrate or a metal substrate. In a flexible display, the size and shape of the screen may be changed by rolling, folding or bending the flexible display panel. The flexible display may include a slidable display, a rollable display, a bendable display, a foldable display, etc.

[0117] The display panel driver reproduces an input image on the screen of the display panel 100 by writing pixel data of the input image into sub-pixels. The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may further include a demultiplexer 112 disposed between the data driver 110 and the data lines DL.

[0118] Each display panel driver can operate in a low-speed drive mode under the control of the timing controller 130. In the low-speed drive mode, by analyzing the input image, when the input image does not change within a preset time, the power consumption of the display device can be reduced. In the low-speed drive mode, when a still image is input for a predetermined time or longer, the power consumption can be reduced by reducing the refresh rate of the pixel P and controlling the data write period of the pixel P to be longer. The low-speed drive mode is not limited to the case of inputting a still image. For example, when the display device is operating in a standby mode, or when a user command or an input image is not input to the display panel drive circuit for a predetermined time or longer, the display panel drive circuit can operate in a low-speed drive mode.

[0119] The data driver 110 receives pixel data of an input image as digital data, and generates a data voltage Vdata using a digital-to-analog converter (hereinafter referred to as a "DAC"). The DAC receives the pixel data as digital data, and receives a gamma reference voltage from a gamma voltage generator of the power supply unit 150. The data driver 110 divides the gamma reference voltage into gamma compensation voltages corresponding to the grayscales of the pixel data, respectively, by using a voltage divider circuit. The DAC of the data driver 110 is disposed in each channel of the data driver 110. The DAC converts the pixel data into a gamma compensation voltage by using a switching element array that selects a voltage in response to a bit of the pixel data, and outputs the data voltage Vdata. The data voltage Vdata output from each channel of the data driver 110 can be supplied to the data line DL of the display panel 100 through the demultiplexer 112.

[0120] The demultiplexer 112 time-divides and distributes the data voltage Vdata output through the channels of the data driver 110 to a plurality of data lines DL. Due to the demultiplexer 112, the number of channels of the data driver 110 can be reduced. The demultiplexer 112 can be omitted. In this case, the channels of the data driver 110 are directly connected to the data lines DL.

[0121] The gate driver 120 may be implemented as a gate-in-panel (GIP) circuit that is directly formed on the bezel region BZ of the display panel 100 together with the TFT array of the pixel array. The gate driver 120 outputs a gate signal to the gate line GL under the control of the timing controller 130. The gate driver 120 may sequentially supply the gate signal to the gate line GL by shifting the gate signal using a shift register. The voltage of the gate signal swings between a gate-off voltage VGH and a gate-on voltage VGL. The gate signal may include Figures 6 to 8 The scan pulses, EM pulses, sensing pulses, etc. are shown.

[0122] The gate driver 120 may be provided on each of the left and right frames (or two opposite sides) of the display panel 100, so as to supply the gate signal to the gate line GL in a dual-feed method. In the dual-feed method, the gate drivers 120 on both sides are synchronized so that the gate signal can be applied simultaneously from both ends of one gate line. In another exemplary embodiment, the gate driver 120 may be provided on either of the left and right frames (or two opposite sides) of the display panel 100, and the gate signal may be supplied to the gate line GL in a single-feed method.

[0123] The gate driver 120 may include a first gate driver 121 and a second gate driver 122. The first gate driver 121 outputs a scan pulse and a sensing pulse, and shifts the scan pulse and the sensing pulse according to a shift clock. The second gate driver 122 outputs an EM pulse and shifts the EM pulse according to a shift clock. In the case of a borderless model, at least some of the switching elements constituting the first gate driver 121 and the second gate driver 122 may be distributedly arranged in a pixel array.

[0124] The timing controller 130 receives pixel data of an input image and a timing signal synchronized with the pixel data from a host system. The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, a data enable signal DE, and the like. One cycle of the vertical synchronization signal Vsync is a frame period. One cycle of each of the horizontal synchronization signal Hsync and the data enable signal DE is a horizontal period 1H. The pulse of the data enable signal DE is synchronized with a row of data of a pixel P to be written into a pixel row. Since the frame period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted.

[0125] The timing controller 130 sends the pixel data of the input image to the data driver 110, and synchronizes the data driver 110, the demultiplexer 112, and the gate driver 120. The timing controller 130 may include a data operator that receives the sensing data obtained from the pixel P in the display panel driver to which the external compensation technology is applied and modulates the pixel data. In this case, the timing controller 130 may send the pixel data modulated by the data operator to the data driver 110.

[0126] The timing controller 130 can control the operation timing of the display panel drivers 110, 112, and 120 by multiplying the input frame frequency by i times (i is a positive integer greater than 0) to input a frame frequency of frame frequency×i Hz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) scheme and 50 Hz in the Phase Alternating Line (PAL) scheme. In the low-speed driving mode, the timing controller 130 can reduce the frame frequency to a frequency between 1 Hz and 30 Hz to reduce the refresh rate of the pixel P.

[0127] The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110 , a switch control signal for controlling the operation timing of the demultiplexer 112 , and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system.

[0128] The voltage level of the gate timing control signal output from the timing controller 130 may be converted into a gate high voltage VGH / VEH and a gate low voltage VGL / VEL by a level shifter omitted in the figure, and may be supplied to the gate driver 120. The level shifter receives the clock of the gate timing control signal from the timing controller 130, and outputs a timing signal such as a start pulse and a shift clock required to drive the gate driver 120. The low level voltage of the gate timing control signal input to the level shifter may be converted into a gate low voltage VGL by the level shifter, and the high level voltage of the gate timing control signal may be converted into a gate high voltage VGH / VEH.

[0129] The power supply unit 150 may include a charge pump, a regulator, a buck converter, a boost converter, a gamma voltage generating circuit, etc. The power supply unit 150 adjusts the DC input voltage from the host system to generate the power required to drive the display panel 100 and the display panel driver. The power supply unit 150 may output DC voltages such as a gamma reference voltage, a gate turn-off voltage VGH / VEH, a gate turn-on voltage VGL / VEL, a pixel driving voltage ELVDD, a low potential power voltage ELVSS, an initialization voltage Vini, and a reference voltage VREF.

[0130] The gamma voltage generating circuit can be implemented with a programmable gamma IC (P-GMAIC). The programmable gamma IC can change the gamma reference voltage according to the register setting value. The gamma reference voltage is supplied to the data driver 110. The gate turn-off voltage VGH / VEH and the gate turn-on voltage VGL / VEL are supplied to the level shifter and the gate driver 120. The pixel drive voltage ELVDD, the low potential power voltage ELVSS, the initialization voltage Vini and the reference voltage VREF are jointly supplied to the pixel circuit through the power line. The pixel drive voltage ELVDD is set to be higher than the low potential power voltage ELVSS, the initialization voltage Vini and the reference voltage VREF.

[0131] The host system can be a main circuit board of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a home theater system, a mobile device, or a wearable device. Fig.11 As shown, the timing controller 130, the data driver 110 and the power supply unit 150 may be integrated into one driver integrated circuit (D-IC). Fig.11, reference numeral "200" denotes a host system. The host system 200 includes an authentication module. The authentication module may execute a facial recognition algorithm that processes user authentication by comparing facial pattern data received from the infrared camera 202 with preset feature points of the user's facial pattern. The authentication module may be software stored in hardware (e.g., a processor circuit) to process user authentication.

[0132] In the present disclosure, in order to reduce the difference in brightness and color of the boundary pixel region BDR, as shown in FIG. Fig. 12A and 12B As shown, unit emission areas UA and UA' of the same size are defined in the second pixel region UDC and the boundary pixel region BDR, and the unit emission area UA' of the boundary pixel region BDR is divided into first and second emission areas BA and BB whose brightness is differently controlled.

[0133] Fig. 12A is a plan view showing a unit emission area UA of the second pixel region UDC according to an embodiment of the present disclosure. Fig. 12B is a plan view showing a first emission region and a second emission region of a boundary pixel region BDR according to an embodiment of the present disclosure. Fig. 12A and Fig. 12B , “R” represents an R sub-pixel, “G” represents a G sub-pixel, and “B” represents a B sub-pixel.

[0134] like Figure 5A and Figure 5B As shown, the second pixel region UDC includes pixel groups PG spaced apart at a predetermined distance. The second pixel region UDC has repeatability, in which the unit emission areas UA including one pixel group PG are regularly arranged along the X-axis and the Y-axis.

[0135] Each unit emission area UA in the second pixel area UDC includes an emission area A and a non-emission area NA arranged around the emission area A. The emission area A may include at least one pixel or two or more sub-pixels having different colors, and may include two or more color emission areas. Each sub-pixel may drive a light-emitting element of a color emission area. In the second pixel area UDC, a plurality of emission areas A are spaced apart from each other by a distance corresponding to the length of the unit emission area UA, and the non-emission area NA is located between the emission areas A. The non-emission area NA may include a light-transmitting portion AG having no pixel.

[0136] The boundary pixel region BDR includes a unit emission area UA' having the same size as the unit emission area UA. The unit emission area UA' includes a first emission area BA set to have the same size as the emission area A of the unit emission area UA, and a second emission area BB set to have the same size as the non-emission area NA of the unit emission area UA. Each of the first emission area BA and the second emission area BB may include at least one pixel or at least two or more sub-pixels having different colors, and may include two or more color emission areas. Each sub-pixel may drive a light-emitting element of a color emission area.

[0137] Each of the first emission area BA and the second emission area BB may have one or more pixels disposed therein to include an emission area. At least one of the second emission areas BB may be disposed between adjacent first emission areas BA. The brightness of the first emission area BA and the brightness of the second emission area BB may be controlled differently, for example, opposite to each other.

[0138] In the boundary pixel region BDR, the number of sub-pixels of the same color in the first emission area BA and the second emission area BB satisfies an integer multiple relationship. Fig. 12B In the embodiment, the number of sub-pixels of each color in the second emission area BB is three times the number of sub-pixels of the same color in the first emission area BA. Fig. 12B , the first emission area BA of the unit emission area UA' includes two R sub-pixels, four G sub-pixels and two B sub-pixels. The second emission area BB of the unit emission area UA' includes six R sub-pixels, twelve G sub-pixels and six B sub-pixels.

[0139] At the same time, if Figure 5B As shown, in a portion of the boundary pixel region BDR adjacent to the second pixel region UDC, the second emission region BB may not include pixels and color emission regions.

[0140] like Fig. 12A As shown, in one unit emission area UA, the emission area A occupies about 25%, but is not limited thereto. For example, the emission area A may be set to occupy about 25% to 75% in one unit emission area UA.

[0141] Figures 13 to 16 2 is a diagram illustrating various embodiments of the second pixel region UDC and the boundary pixel region BDR according to an embodiment of the present disclosure.

[0142] Reference Figures 13 to 16, the unit emission area UA' of the boundary pixel region BDR may include more sub-pixels than the unit emission area UA of the second pixel region UDC. The sub-pixels set in the unit emission area UA' of the boundary pixel region BDR may include an emission area having a shape different from that of the emission area of ​​the sub-pixels set in the unit emission area UA of the second pixel region UDC. The number and shape of the sub-pixels set in the unit emission area UA' of the boundary pixel region BDR may be the same as the number and shape of the sub-pixels set in the first pixel region NML with the same size. Each sub-pixel set in the unit emission area UA of the second pixel region UDC has a larger and different shape than the sub-pixel of the same color set in the unit emission area UA' of the boundary pixel region BDR.

[0143] exist Fig.13 In the example, the unit emission area UA of the second pixel area UDC may include two emission areas A. The area occupied by the two emission areas A in the unit emission area UA may be approximately 1 / 2. Each emission area A may include one R sub-pixel, two G sub-pixels and one B sub-pixel. Each sub-pixel arranged in the emission area A may include a square or rectangular color emission area. The R sub-pixel of the second pixel area UDC may be larger than the R sub-pixel of the boundary pixel area BDR, and the G sub-pixel of the second pixel area UDC may be larger than the G sub-pixel of the boundary pixel area BDR. In addition, the B sub-pixel of the second pixel area UDC may be larger than the B sub-pixel of the boundary pixel area BDR.

[0144] exist Fig.13 In the example of FIG. 1 , the unit emission area UA′ and the first emission area BA in the boundary pixel region BDR respectively have the same shape and the same size as the unit emission area UA and the emission area A in the second pixel region UDC. In the unit emission area UA′ of the boundary pixel region BDR, the first emission area BA and the second emission area BB may each occupy approximately 1 / 2 of the unit emission area.

[0145] In the boundary pixel region BDR, 1 / 3 of the first emission area BA and the second emission area BB having the same size may include two R sub-pixels, four G sub-pixels and two B sub-pixels. Each sub-pixel disposed in the first emission area BA and the second emission area BB may include a rhombus or parallelogram color emission area.

[0146] exist Fig.14In the example, the unit emission area UA of the second pixel area UDC may include one emission area A. The area occupied by one emission area A in the unit emission area UA may be approximately 1 / 4. Each emission area A may include two R sub-pixels, four G sub-pixels, and two B sub-pixels. The G sub-pixels arranged in the emission area A may each include a square or rectangular color emission area, and the R sub-pixels and the B sub-pixels may each include a wedge-shaped color emission area with an inclined corner. The R sub-pixel of the second pixel area UDC may be larger than the R sub-pixel of the boundary pixel area BDR, and the B sub-pixel of the second pixel area UDC may be larger than the B sub-pixel of the boundary pixel area BDR. The G sub-pixel of the second pixel area UDC may be equal to or larger than the G sub-pixel of the boundary pixel area BDR.

[0147] exist Fig.14 In the example of , the unit emission area UA' and the first emission area BA of the boundary pixel region BDR have the same shape and the same size as the unit emission area UA and the emission area A of the second pixel region UDC, respectively. In the unit emission area UA' of the boundary pixel region BDR, the area occupied by the first emission area BA may be approximately 1 / 4, and the area occupied by the second emission area BB may be approximately 3 / 4.

[0148] In the boundary pixel region BDR, 1 / 3 of the first emission area BA and the second emission area BB having the same size may include two R sub-pixels, four G sub-pixels and two B sub-pixels. Each sub-pixel disposed in the first emission area BA and the second emission area BB may include a square or rectangular color emission area.

[0149] exist Fig.15 In the example, the unit emission area UA of the second pixel area UDC may include an emission area A. The area occupied by one emission area A in the unit emission area UA may be approximately 1 / 2. The emission area A may include an R sub-pixel, a G sub-pixel and a B sub-pixel. Each sub-pixel arranged in the emission area A may include a square, octagonal, circular or elliptical color emission area. The R sub-pixel of the second pixel area UDC may be larger than the R sub-pixel of the boundary pixel area BDR, and the G sub-pixel of the second pixel area UDC may be larger than the G sub-pixel of the boundary pixel area BDR. In addition, the B sub-pixel of the second pixel area UDC may be larger than the B sub-pixel of the boundary pixel area BDR.

[0150] exist Fig.15 In the example of FIG. 1 , the unit emission area UA′ and the first emission area BA of the boundary pixel region BDR respectively have the same size as the unit emission area UA and the emission area A of the second pixel region UDC. In the unit emission area UA′ of the boundary pixel region BDR, the first emission area BA and the second emission area BB may each occupy approximately 1 / 2 of the unit emission area.

[0151] In the unit emission area UA' of the boundary pixel region BDR, the first emission area BA and the second emission area BB may each include one R subpixel, two G subpixels and one B subpixel. Each subpixel disposed in the first emission area BA and the second emission area BB may include a diamond or rectangular emission area for each color.

[0152] like Figures 13 to 15 It can be seen that at least one of the number, size and shape of the sub-pixels arranged in the unit emission area UA of the second pixel region UDC can be designed to be different from at least one of the number, size and shape of the sub-pixels in the boundary pixel region BDR. Fig.16 As shown, the number, size, and shape of sub-pixels disposed in the unit emission area UA of the second pixel region UDC may be designed to be the same as or similar to the number, size, and shape of sub-pixels of the boundary pixel region BDR.

[0153] The host system 200 or the timing controller 130 may control the brightness of the first emission area BA and the second emission area BB of the boundary pixel region BDR to be different from each other.

[0154] Fig.17 is a diagram showing an example in which a spatial period of a unit emission area of ​​a boundary pixel region is the same as a spatial period of a unit emission area of ​​a second pixel region according to an embodiment of the present disclosure.

[0155] Reference Fig.17 , the unit emission area UA' of the boundary pixel area BDR is defined as having substantially the same size as the unit emission area UA of the second pixel area UDC. In the boundary pixel area BDR, the distance or gap Lx, Ly between the adjacent first emission areas BA in each of the first direction (X axis) and the second direction (Y axis) is set to be equal to or similar to the distance Lx, Ly between the emission areas A of the second pixel area UDC. In other words, at the boundary between the boundary pixel area BDR and the second pixel area UDC, the separation distance between the first emission area BA of the boundary pixel area BDR and the emission area A of the second pixel area UDC may be constant. The distance Lx, Ly between the first emission area BA of the boundary pixel area BDR and the emission area A of the second pixel area UDC existing at the boundary between the boundary pixel area BDR and the second pixel area UDC is equal to or similar to the distance Lx, Ly between the emission areas A of the second pixel area UDC. Therefore, the light emission spatial period of the bright pixel in the boundary pixel area BDR close to the second pixel area can become substantially the same as the light emission spatial period of the second pixel area UDC, thereby reducing the sense of unevenness of the boundary pixel area BDR.

[0156] like Fig.17 As shown, the low-brightness second emission region BB is disposed between the emission region A of the second pixel region UDC and the first emission region BA of the boundary pixel region BDR to ensure the separation distances Lx and Ly.

[0157] like Fig.17 As shown, the second pixel region UDC and the boundary pixel region BDR include a first line LINE1 and a second line LINE2, on which bright emission areas A and BA and relatively dark areas NA and BB are arranged along a first direction X, and on which relatively dark areas NA and BB are arranged along the first direction X. The first emission areas BA and the second emission areas BB are alternately arranged on the first line LINE1 of the boundary pixel region BDR. The second emission areas BB are continuously arranged on the second line LINE2 of the boundary pixel region BDR without the first emission areas BA.

[0158] Fig.18 1 is a diagram showing an example in which the luminances of the first emission area BA and the second emission area BB of the boundary pixel area BDR between the first pixel area NML and the second pixel area UDC gradually change to be opposite to each other.

[0159] Reference Fig.18 As the distance from the second pixel region UDC increases, that is, as the distance to the first pixel region NML decreases, the maximum brightness of the first emission area BA in the boundary pixel region BDR decreases to a level equal to or similar to the maximum brightness of the first pixel region NML. In the boundary pixel region BDR, as the distance from the second pixel region UDC increases, that is, as the distance to the first pixel region NML decreases, the maximum brightness of the sub-pixels of the second emission area BB arranged around the first emission area BA increases to a level equal to or similar to the maximum brightness of the first pixel region NML. Therefore, since the average brightness of the unit emission areas UA and UA' between the first pixel region NML and the second pixel region UDC can be the same or almost the same, the boundary pixel region BDR can be prevented from appearing in the form of a bright line or a dark line.

[0160] The maximum brightness of the second pixel region UDC may be set to be higher than the maximum brightness of the first pixel region NML. Fig.19B and Fig. 20B It can be seen that the maximum brightness of the first emission area BA in the boundary pixel area BDR can be less than the maximum brightness of the second pixel area UDC and higher than the maximum brightness of the first pixel area NML. The maximum brightness of the second emission area BB in the boundary pixel area BDR can be less than the maximum brightness of the second pixel area UDC and less than the maximum brightness of the first pixel area NML.

[0161] Fig.19Ais a diagram showing an example of an area ratio between the first emission region BA and the second emission region BB in the boundary pixel region BDR. Fig.19A In , "BA+BB" indicates a pixel group including a first emission area BA emitting high brightness light and a second emission area BB emitting low brightness light in the unit pixel area UA' of the boundary pixel area BDR. Fig.19A In the example of , the sub-pixel arrangement of the first emission area BA is the same as the sub-pixel arrangement of the unit emission area UA of the second pixel area UDC. Fig.19A In the example of FIG. 1 , the area ratio of the first emission area BA to the second emission area BB is approximately 1:3.

[0162] Fig.19B is a diagram showing a method for controlling a Fig.19A An example of a method for measuring the brightness of the unit emission areas UA and UA' in FIG. Fig.19B In the figure, the numbers outside the brackets represent the maximum brightness, and the numbers inside the brackets represent the brightness contribution rate (%) of the unit emission areas UA and UA' of the application area ratio.

[0163] like Fig.19B As shown, the second pixel region UDC and the boundary pixel region BDR include a first line LINE1 and a second line LINE2, on which bright emission areas A and BA and relatively dark areas NA and BB are arranged along a diagonal direction θ between the first direction X and the second direction Y, and on which relatively dark areas NA and BB are arranged along a diagonal direction θ. The first emission areas BA and the second emission areas BB are alternately arranged on the first line LINE1 of the boundary pixel region BDR. The second emission areas BB are continuously arranged on the second line LINE2 of the boundary pixel region BDR without the first emission areas BA.

[0164] Fig. 20A is a diagram showing another example of an area ratio between the first emission area BA and the second emission area BB of the boundary pixel region BDR according to an embodiment of the present disclosure. Fig. 20A In , "BA+BB" represents a pixel group including a first emission area BA and a second emission area BB that emit high brightness light in a unit pixel area UA' of a boundary pixel area BDR. Fig. 20A In the example of , the sub-pixel arrangement of the first emission area BA is different from the sub-pixel arrangement of the unit emission area UA of the second pixel area UDC. Fig. 20A In the example of FIG. 5 , the area ratio of the first emission area BA to the second emission area BB is approximately 1:1.

[0165] Fig. 20B is a diagram showing a method for controlling a Fig. 20AAn example of a method for measuring the brightness of the unit emission areas UA and UA' in FIG. Fig. 20B In the figure, the numbers outside the brackets represent the maximum brightness, and the numbers inside the brackets represent the brightness contribution rate (%) of the unit emission areas UA and UA' of the application area ratio.

[0166] Reference FIG. 19A to FIG. 20B , the maximum brightness of the first emission area BA in the boundary pixel area BDR may gradually decrease as the distance to the first pixel area NML decreases. On the other hand, the maximum brightness of the second emission area BB in the boundary pixel area BDR gradually increases as the distance to the second pixel area UDC increases, that is, gradually increases as the distance to the first pixel area NML decreases. The maximum brightness difference between the first emission area BA and the second emission area BB decreases as the distance from the second pixel area UDC increases. As described above, the maximum brightness of the first emission area BA in the boundary pixel area BDR may be less than the maximum brightness of the second pixel area UDC and greater than the maximum brightness of the first pixel area NML. The maximum brightness of the second emission area BB in the boundary pixel area BDR may be less than the maximum brightness of the second pixel area UDC and less than the maximum brightness of the first pixel area NML. This method for controlling the brightness of the first emission area BA and the second emission area BB can improve such as Fig.21 and Fig. 22 The perception of non-uniformity of the boundary pixel area BDR is shown. Fig.21 The left image is as Fig.13 emitting light having a middle gray scale, and the right figure thereof shows pixels of the second pixel region UDC and the boundary pixel region BDR adjacent thereto. Fig. 22 The left image is as Fig.16 emitting light having a middle gray scale, and the right figure thereof shows pixels of the second pixel region UDC and the boundary pixel region BDR adjacent thereto.

[0167] In the second pixel region UDC, only the sub-pixel of the emission region A emits light. Therefore, the brightness contribution rate of the emission region A in the second pixel region UDC is 100%. The brightness contribution rates of the first emission region BA and the second emission region BB in the boundary pixel region BDR can be calculated using their maximum brightness and area ratio.

[0168] like Fig.19AIn the example, when the area ratio of the first emission area BA to the second emission area BB is 1:3, the brightness contribution rate of the first emission area BA is the value obtained by multiplying the maximum brightness by 1 / 4. The brightness contribution rate of the second emission area BB is the value obtained by multiplying the maximum brightness by 3 / 4. Here, 1 / 4 is the ratio of the area occupied by the first emission area BA in the unit emission area UA', and 3 / 4 is the ratio of the area occupied by the second emission area BB in the unit emission area UA'. The brightness of the unit emission area UA' is the value obtained by adding the brightness of the first emission area BA and the brightness of the second emission area BB. Therefore, in the unit emission area UA', the sum of the brightness contribution rate (%) of the first emission area BA and the brightness contribution rate (%) of the second emission area BB is 100%. For example, in the unit emission area UA' adjacent to the first pixel area NML, the brightness contribution rate of the first emission area BA is 160*(1 / 4)=40%, and the brightness contribution rate of the second emission area BB is 80*(3 / 4)=60%. In the unit emission area UA' adjacent to the second pixel area UDC, the brightness contribution rate of the first emission area BA is 340*(1 / 4)=85%, and the brightness contribution rate of the second emission area BB is 20*(3 / 4)=15%.

[0169] like Fig. 20A In the example of , when the area ratio of the first emission area BA to the second emission area BB is 1:1, the brightness contribution rate of the first emission area BA is the value obtained by multiplying the maximum brightness by 1 / 2. Similarly, the brightness contribution rate of the second emission area BB is the value obtained by multiplying the maximum brightness by 1 / 2. Fig. 20A and Fig. 20B In the example, in the unit emission area UA' adjacent to the first pixel area NML, the brightness contribution rate of the first emission area BA is 120*(1 / 2)=60%, and the brightness contribution rate of the second emission area BB is 80*(1 / 2)=40%. In the unit emission area UA' adjacent to the second pixel area UDC, the brightness contribution rate of the first emission area BA is 180*(1 / 2)=90%, and the brightness contribution rate of the second emission area BB is 20*(1 / 2)=10%. Fig. 20B The middle diagram in FIG. 1 shows high brightness 20a and low brightness 20b of the gray scale in the unit emission areas UA and UA′.

[0170] At the same time, Figure 23 to Figure 26In the comparative example shown, in the second pixel area UDC and the boundary pixel area BDR, the emission areas A and BA of high brightness can be arranged adjacent to each other with almost no gap, or the emission area BB or the non-emission area NA of low brightness can be arranged adjacent to each other with almost no gap. In the comparative example, in the boundary pixel area BDR between the first pixel area NML and the second pixel area UDC, the bright spot BPNT appears significantly due to the bright pixels being adjacent to each other, and the dark spot DPNT appears significantly due to the dark pixels being adjacent to each other. In this comparative example, bright spots and dark spots are periodically seen in the boundary pixel area BDR, so that the user feels a sense of unevenness. In contrast, in an embodiment of the present disclosure, at the boundary between the boundary pixel area BDR and the second pixel area UDC along each of the first direction X and the second direction Y, the separation distance Lx, Ly between the first emission area BA of the boundary pixel area BDR and the emission area A of the second pixel area UDC is constant, so that the boundary pixel area BDR is not visually recognized, and the user does not feel a sense of unevenness about the boundary pixel area BDR.

[0171] In the boundary pixel region BDR, the pixels of the first emission area BA and the pixels of the second emission area BB can emit light through gamma compensation curves having different maximum brightness. The second emission area BB can emit light having a brightness defined by a first gamma compensation curve whose maximum brightness is equal to or less than the maximum brightness of the first pixel area NML. The first emission area BA can emit light having a brightness defined by a second gamma compensation curve whose maximum brightness is equal to or less than the maximum brightness of the second pixel area UDC. The maximum brightness defined by the second gamma compensation curve may be higher than the maximum brightness of the first gamma compensation curve. As described above, the pixels of the first emission area BA and the second emission area BB emit light through the first gamma compensation curve and the second gamma compensation curve having different maximum brightness within the boundary pixel region BDR. Therefore, even if the color difference between the first pixel area NML and the second pixel area UDC is recognized due to the difference in color coordinates between them, as Fig. 27 As shown, the color difference can also be improved by gradually changing the color coordinate values ​​and the brightness effect (grayscale effect).

[0172] Digital gamma technology and analog gamma technology can be used to control the maximum brightness of a pixel. In the present disclosure, by using a multi-phase gamma compensation voltage, a multi-phase gamma compensation curve with different maximum brightness can be used. For example, Fig.28As shown, the programmable gamma IC can generate a gamma reference voltage in a single gamma reference voltage range (PGMA range), which can obtain a brightness equal to or greater than the maximum brightness of the second pixel area UDC. The timing controller 130 can modulate the gamma characteristics of the pixel data by using a digital gamma compensation technique using first and second lookup tables (LUTs). The first lookup table includes data (or gamma compensation values) defining a first gamma compensation curve of voltage-brightness within a range less than or equal to the maximum brightness of the first pixel area NML. The second lookup table includes data (or gamma compensation values) defining a second gamma compensation curve of voltage-brightness within a range less than or equal to the maximum brightness of the second pixel area UDC. Fig.28 In the figure, “NMLGMA” is the brightness range defined by the first gamma compensation curve. “UDC GMA” is the brightness range defined by the second gamma compensation curve.

[0173] The timing controller 130 may input pixel data of pixels to be written in the first pixel region NML into the first lookup table to modulate the pixel data of pixels to be written in the first pixel region NML. The timing controller 130 may input pixel data of pixels set in the second emission region BB of the boundary pixel region BDR into the first lookup table to modulate the pixel data of pixels to be written in the second emission region BB of the boundary pixel region BDR.

[0174] The timing controller 130 may input pixel data of pixels set in the emission area A of the second pixel area UDC to be written into the second lookup table to modulate the pixel data of pixels in the emission area A of the second pixel area UDC to be written. The timing controller 130 may input pixel data of pixels set in the first emission area BA of the boundary pixel area BDR to be written into the second lookup table to modulate the pixel data of pixels in the first emission area BA of the boundary pixel area BDR to be written. When the pixel data is input into the lookup table, the gamma compensation value data stored in the address indicated by the pixel data is output. Therefore, the timing controller 130 may modulate the gamma characteristics of the pixel data by using the first lookup table and the second lookup table.

[0175] The above-mentioned objects to be achieved by the present disclosure, means for achieving the objects, and advantages and effects of the present disclosure do not specify essential features of the claims, and therefore, the scope of the claims is not limited to the disclosure of the present disclosure.

[0176] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present disclosure.

Claims

1. A display panel, comprising a first pixel region, a second pixel region, and a boundary pixel region arranged between the first pixel region and the second pixel region, in, The boundary pixel area includes: a plurality of first emission regions; and a plurality of second emission regions, wherein each of the first emission area and the second emission area includes one or more pixels, The second pixel region includes a plurality of emission regions, At least one of the second emission areas is disposed between the first emission areas adjacent to each other, The maximum brightness of the first emission area decreases as the distance from the second pixel area increases, and the maximum brightness of the second emission area increases as the distance from the second pixel area increases, and A separation distance between the first emission region of the boundary pixel region and the emission region of the second pixel region is constant at a boundary between the boundary pixel region and the second pixel region, and The distance between the emission areas of the second pixel regions adjacent to each other and the first emission area of ​​the boundary pixel region is equal to the distance between the emission areas adjacent to each other in the second pixel region.

2. The display panel according to claim 1, wherein: The maximum brightness of the first emission area is lower than the maximum brightness of the second pixel area and higher than the maximum brightness of the first pixel area, and The maximum brightness of the second emission area is lower than the maximum brightness of the second pixel area and lower than the maximum brightness of the first pixel area.

3. The display panel according to claim 1, wherein: Light travels through the second pixel region to an optical element disposed below the display panel.

4. The display panel according to claim 1, wherein: A difference between a maximum brightness of the first emission area and a maximum brightness of the second emission area decreases as a distance from the second pixel region increases.

5. The display panel according to claim 1, wherein: A distance between the first emission regions adjacent to each other is equal to a distance between the emission regions adjacent to each other in the second pixel region.

6. The display panel according to claim 1, wherein: Each of the first emission area and the second emission area includes a plurality of sub-pixels having different colors, and Among sub-pixels of the same color, the number of sub-pixels arranged in the second emission area is an integer multiple of the number of sub-pixels arranged in the first emission area.

7. The display panel according to claim 6, wherein: The integer multiple is two or three times.

8. The display panel according to claim 1, wherein: The pixel density of the boundary pixel area is the same as the pixel density of the first pixel area and is higher than the pixel density of the second pixel area.

9. The display panel according to claim 1, wherein: A pixel density of a portion of the boundary pixel region adjacent to the second pixel region is lower than a pixel density of the first pixel region and is equal to or higher than a pixel density of the second pixel region.

10. The display panel according to claim 1, wherein: The pixels of the first pixel area and the pixels disposed in the second emission area of ​​the boundary pixel area emit light having a brightness defined by a first gamma compensation curve, The pixels of the second pixel area and the pixels disposed in the first emission area of ​​the boundary pixel area emit light having a brightness defined by a second gamma compensation curve, and The maximum brightness of the second gamma compensation curve is higher than the maximum brightness of the first gamma compensation curve.

11. A display device, comprising: A display panel, the display panel comprising a first pixel region, a second pixel region, and a boundary pixel region disposed between the first pixel region and the second pixel region; as well as A display panel driver configured to write pixel data of an input image into pixels arranged in a pixel region of the display panel, wherein: The second pixel region includes a plurality of unit emission regions, and The boundary pixel region includes a plurality of unit emission regions, wherein: Each of the unit emission regions of the second pixel area includes an emission region and a non-emission region, Each of the unit emission areas of the boundary pixel region has the same size as a unit emission area of ​​the second pixel region, and Each of the unit emission regions of the boundary pixel area includes a first emission region and a second emission region, wherein: The first emission areas are spaced apart from each other by a distance equal to a distance between emission areas of the second pixel region, wherein the second emission area is between the first emission areas, The maximum brightness of the first emission area decreases as the distance from the second pixel area increases, and the maximum brightness of the second emission area increases as the distance from the second pixel area increases, and A separation distance between the first emission region of the boundary pixel region and the emission region of the second pixel region is constant at a boundary between the boundary pixel region and the second pixel region, and The distance between the emission areas of the second pixel regions adjacent to each other and the first emission area of ​​the boundary pixel region is equal to the distance between the emission areas adjacent to each other in the second pixel region.

12. The display device according to claim 11, wherein: The maximum brightness of the first emission area is lower than the maximum brightness of the second pixel area and higher than the maximum brightness of the first pixel area, and The maximum brightness of the second emission area is lower than the maximum brightness of the second pixel area and lower than the maximum brightness of the first pixel area.

13. The display device according to claim 11, wherein: Light travels through the second pixel region to an optical element disposed below the display panel.

14. The display device according to claim 11, wherein: A difference between a maximum brightness of the first emission area and a maximum brightness of the second emission area decreases as a distance from the second pixel region increases.

15. The display device according to claim 11, wherein: Each of the first emission area and the second emission area includes a plurality of sub-pixels having different colors, and For each color, the number of sub-pixels arranged in the first emission area and the number of sub-pixels arranged in the second emission area differ by an integer multiple.

16. The display device according to claim 11, wherein: The pixels of the first pixel area and the pixels disposed in the second emission area of ​​the boundary pixel area emit light having a brightness defined by a first gamma compensation curve, The pixels of the second pixel area and the pixels disposed in the first emission area of ​​the boundary pixel area emit light having a brightness defined by a second gamma compensation curve, and The maximum brightness of the second gamma compensation curve is higher than the maximum brightness of the first gamma compensation curve.

17. A mobile terminal, comprising: A display panel, the display panel comprising a first pixel region, a second pixel region, and a boundary pixel region disposed between the first pixel region and the second pixel region; a display panel driver configured to write pixel data of an input image into pixels provided in a pixel region of the display panel; as well as An optical element is disposed below the second pixel region of the display panel, wherein: The second pixel region includes a plurality of unit emission regions, and The boundary pixel region includes a plurality of unit emission regions, wherein: Each of the unit emission regions of the second pixel area includes an emission region and a non-emission region, Each of the unit emission areas of the boundary pixel region has the same size as a unit emission area of ​​the second pixel region, and Each of the unit emission regions of the boundary pixel area includes a first emission region and a second emission region, wherein: The first emission areas are spaced apart from each other by a distance equal to a distance between emission areas of the second pixel region, wherein the second emission area is between the first emission areas, The maximum brightness of the first emission area decreases as the distance from the second pixel area increases, and the maximum brightness of the second emission area increases as the distance from the second pixel area increases, and A separation distance between the first emission region of the boundary pixel region and the emission region of the second pixel region is constant at a boundary between the boundary pixel region and the second pixel region, and The distance between the emission areas of the second pixel regions adjacent to each other and the first emission area of ​​the boundary pixel region is equal to the distance between the emission areas adjacent to each other in the second pixel region.

18. The mobile terminal according to claim 17, wherein: The maximum brightness of the first emission area is lower than the maximum brightness of the second pixel area and higher than the maximum brightness of the first pixel area, The maximum brightness of the second emission area is lower than the maximum brightness of the second pixel area and lower than the maximum brightness of the first pixel area, and A difference between a maximum brightness of the first emission area and a maximum brightness of the second emission area decreases as a distance from the second pixel region increases.

19. The mobile terminal according to claim 17, wherein: The pixels of the first pixel area and the pixels disposed in the second emission area of ​​the boundary pixel area emit light having a brightness defined by a first gamma compensation curve, The pixels of the second pixel area and the pixels disposed in the first emission area of ​​the boundary pixel area emit light having a brightness defined by a second gamma compensation curve, and The maximum brightness of the second gamma compensation curve is higher than the maximum brightness of the first gamma compensation curve.

Images