A method for evaluating the grade of the appearance of a circuit layout wiring schematic diagram

Abstract

The present application relates to the technical field of circuit automation design, and provides a circuit layout wiring schematic diagram aesthetic grade evaluation method.The method comprises the following steps: based on a sliding window strategy, a circuit layout wiring schematic diagram obtained is segmented to obtain a local subgraph; a Laplace convolution kernel is used to extract a graph type subgraph feature of the local subgraph and reduce a feature vector space to obtain a numerical type subgraph feature vector; the local subgraph is clustered based on a genetic clustering algorithm according to the subgraph feature vector; a local subgraph with the smallest Euclidean distance to a clustering center point in each cluster in a clustering result is selected as a representative subgraph, a residual neural network is used to predict the representative subgraph, and a subgraph aesthetic evaluation score is obtained; a schematic diagram aesthetic evaluation score is calculated, and a score grade mapping relationship is used to calculate an aesthetic evaluation grade of a to-be-evaluated schematic diagram.The method improves a basic evaluation index of a circuit layout wiring generation algorithm, and facilitates early and rapid understanding of a circuit and error checking.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit automation design, and in particular to a circuit layout and wiring schematic diagram aesthetic grade evaluation method. BACKGROUND

[0002] In the field of electronic design automation (EDA), the research on the layout and wiring method from the netlist file to the schematic diagram is a very important sub-problem. The layout and wiring method from the netlist file to the schematic diagram converts the complex netlist file recording the connection relationship of the elements stored by the machine into a logical and aesthetic circuit layout and wiring schematic diagram that can be easily understood by relevant personnel, thereby facilitating relevant designers to quickly understand the circuit and perform early error troubleshooting in the early stage of circuit design.

[0003] However, there are few related public technical data on the research on the circuit layout and wiring method from the complex netlist file to the schematic diagram, which greatly limits the research and development in this field. Among the searchable public data, the existing research results on the layout and wiring method from the netlist to the schematic diagram can be divided into two categories: traditional methods based on formalization and knowledge-based methods.

[0004] However, both the traditional method based on formalization and the knowledge-based method use the number of elements, the utilization rate per unit area, the wiring length, the number of wiring intersections and other indicators to evaluate the pros and cons of the generated schematic diagram, and do not comprehensively and effectively evaluate the "logical clarity" and "aesthetics" of the schematic diagram from the perspective of the schematic diagram user. SUMMARY

[0005] The present application aims to at least solve one of the technical problems in the related art. To this end, the present application provides a circuit layout and wiring schematic diagram aesthetic grade evaluation method.

[0006] The present application provides a circuit layout and wiring schematic diagram aesthetic grade evaluation method, comprising:

[0007] S100: obtaining a circuit layout and wiring schematic diagram, segmenting the circuit layout and wiring schematic diagram based on a sliding window strategy to obtain a local subgraph of the circuit layout and wiring schematic diagram;

[0008] S200: extracting a graph type subgraph feature of the local subgraph by a Laplacian convolution kernel, dimensionally reducing a feature vector space of the graph type subgraph feature to obtain a numerical type subgraph feature vector;

[0009] S300: clustering the local subgraph based on a genetic clustering algorithm according to the subgraph feature vector to obtain a clustering result;

[0010] S400: select a local subgraph with the minimum Euclidean distance to the cluster center point in each cluster in the clustering result as a representative subgraph, predict the representative subgraph through a residual neural network, and obtain a subgraph aesthetics evaluation score of the representative subgraph;

[0011] S500: calculate a schematic diagram aesthetics evaluation score of the circuit layout and wiring schematic diagram according to the subgraph aesthetics evaluation score, and calculate an aesthetics evaluation grade of the circuit layout and wiring schematic diagram to be evaluated based on the schematic diagram aesthetics evaluation score and a grade mapping relationship.

[0012] According to the circuit layout and wiring schematic diagram aesthetics grade evaluation method provided by the application, the Laplacian convolution kernel in step S200 is represented as:

[0013]

[0014] Wherein, δ is the Laplacian convolution kernel.

[0015] According to the circuit layout and wiring schematic diagram aesthetics grade evaluation method provided by the application, step S300 includes:

[0016] S310: generating a plurality of random center points in the local subgraph, grouping the plurality of random center points into a set and encoding them into a string;

[0017] S320: determining the basic operation parameters of the genetic clustering algorithm, initializing the string as a genetic population, and the basic operation parameters including the upper limit number of iteration operations;

[0018] S330: selecting a sample center point according to the Euclidean distance to add to the genetic population, and calculating the fitness value of all individuals in the genetic population according to the fitness function through the DB index;

[0019] S340: sorting all individuals in the genetic population according to the fitness value, and performing crossover, selection and mutation on the sorted genetic population according to the basic operation parameters to obtain a new generation of genetic population;

[0020] S350: sorting all individuals in the new generation of genetic population, and performing crossover, selection and mutation on the sorted new generation of genetic population according to the basic operation parameters, until the optimal genetic population meeting the upper limit number of iteration operations is obtained as the clustering result.

[0021] According to the circuit layout and wiring schematic diagram aesthetics grade evaluation method provided by the application, the basic operation parameters in step S320 further include genetic selection probability, total number of individuals included in the genetic population, genetic crossover probability and genetic mutation probability.

[0022] According to the circuit layout wiring schematic diagram aesthetic grade evaluation method provided by the application, the calculation formula of the fitness function in step S330 is:

[0023]

[0024] Wherein, DNA x is the xth genetic individual in the genetic population, x is a first index value, f(DNA x ) is the fitness function corresponding to the xth genetic individual, K is a preset maximum clustering parameter, s a is the diameter of the ath cluster, s b is the diameter of the bth cluster, d ab is the Euclidean distance between the center points of the ath cluster and the bth cluster.

[0025] According to the circuit layout wiring schematic diagram aesthetic grade evaluation method provided by the application, the residual neural network in step S400 is pre-trained before predicting the representative subgraph, and the pre-training step includes:

[0026] S410: Obtain a circuit layout wiring training graph in a real netlist file, and randomly crop the circuit layout wiring training graph to obtain a training subgraph;

[0027] S420: After labeling the training subgraph, vertical flipping and horizontal flipping are performed to obtain a training subgraph dataset with an aesthetic score;

[0028] S430: Pre-train a residual neural network according to the training subgraph dataset.

[0029] According to the circuit layout wiring schematic diagram aesthetic grade evaluation method provided by the application, the schematic diagram aesthetic evaluation score of the circuit layout wiring schematic diagram in step S500 is obtained by introducing a maximum value aggregation strategy, an average value aggregation strategy, a mode average value aggregation strategy and a weighted average value aggregation strategy into the subgraph aesthetic evaluation score.

[0030] The one or more technical solutions in the embodiments of the application have at least one of the following technical effects:

[0031] The circuit layout wiring schematic diagram aesthetic grade evaluation method provided by the application solves the difficulty problem that the evaluation index of the circuit layout wiring schematic diagram in the field of circuit automatic design lacks comprehensive evaluation from the perspective of related practitioners from the perspective of clear and aesthetic evaluation of the circuit diagram logic, and effectively evaluates the logic clarity and aesthetics of the schematic diagram, thereby facilitating relevant designers to quickly understand the circuit and check errors in the early design stage.

[0032] Additional aspects and advantages of the present application will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the present application or the prior art, the drawings required to be used in the following embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort based on these drawings.

[0034] Figure 1 A circuit layout wiring schematic diagram aesthetics level evaluation method flowchart provided by an embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described clearly and completely in the following with reference to the drawings in the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort belong to the protection scope of the present application. The following embodiments are used to illustrate the present application, but cannot be used to limit the scope of the present application.

[0036] In the description of the embodiments of the present application, it should be noted that the orientations or positional relationships indicated by the terms “center”, “longitudinal”, “transverse”, “upper”, “lower”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer” and the like are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the embodiments of the present application. In addition, the terms “first”, “second”, “third” are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0037] In the description of the embodiments of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms “connected” and “connected” should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0038] In the embodiments of the present application, unless otherwise explicitly specified and limited, the first feature is "on" or "under" the second feature, which can be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature can be "above", "over" and "on" the second feature, which can be that the first feature is directly above or obliquely above the second feature, or only means that the first feature is higher in horizontal height than the second feature. The first feature can be "under", "below" and "underneath" the second feature, which can be that the first feature is directly below or obliquely below the second feature, or only means that the first feature is lower in horizontal height than the second feature.

[0039] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples without contradiction.

[0040] The embodiments provided by the present application are described below in conjunction with Figure 1 The embodiments provided by the present application are described below in conjunction with

[0041] The present application provides a circuit layout and wiring schematic diagram aesthetic grade evaluation method, comprising:

[0042] S100: Obtain a circuit layout and wiring schematic diagram, segment the circuit layout and wiring schematic diagram based on a sliding window strategy, and obtain a local subgraph of the circuit layout and wiring schematic diagram;

[0043] S200: Extract a graph type subgraph feature of the local subgraph through a Laplacian convolution kernel, reduce a dimension feature vector space of the graph type subgraph feature, and obtain a numerical type subgraph feature vector;

[0044] In step S200, the Laplacian convolution kernel is represented as:

[0045]

[0046] Wherein, δ is the Laplacian convolution kernel.

[0047] S300: Clustering the local subgraph based on a genetic clustering algorithm according to the subgraph feature vector, and obtaining a clustering result;

[0048] In step S300, the Laplacian convolution kernel is represented as:

[0049] S310: generating a plurality of random center points in the local subgraph, grouping the plurality of random center points into a set and encoding the set into a string;

[0050] S320: determining basic running parameters of the genetic clustering algorithm, initializing the string as a genetic population, the basic running parameters including an upper limit number of iteration runs;

[0051] In step S320, the basic running parameters further include a genetic selection probability, a total number of individuals included in the genetic population, a genetic crossover probability, and a genetic mutation probability.

[0052] S330: selecting sample center points according to the Euclidean distance to add to the genetic population, and calculating fitness values of all individuals in the genetic population according to an adaptive function through a DB index;

[0053] In some embodiments, samples with small Euclidean distances are added to the current cluster for each genetic individual, and fitness values of all individuals in the current population are calculated according to an adaptive function using a DB index (Davies-Bouldin).

[0054] In step S330, the adaptive function is calculated according to the following formula:

[0055]

[0056] In the formula, DNA x is the xth genetic individual in the genetic population, x is a first index value, f(DNA x ) is the adaptive function corresponding to the xth genetic individual, K is a preset maximum clustering parameter, s a is the diameter of the ath cluster, s b is the diameter of the bth cluster, and d ab is the Euclidean distance between the center points of the ath cluster and the bth cluster.

[0057] S340: sorting all individuals in the genetic population according to the fitness values, and performing crossover, selection, and mutation on the sorted genetic population according to the basic running parameters to obtain a new generation of genetic population;

[0058] S350: sorting all individuals in the new generation of genetic population, and performing crossover, selection, and mutation on the sorted new generation of genetic population according to the basic running parameters, until an optimal genetic population that satisfies the upper limit number of iteration runs is obtained as the clustering result.

[0059] Further, the clustering operation in step S300 is automatic clustering. The purpose of selecting the sample center point is to reduce the cumulative effect of errors generated by the subsequent residual neural network in performing aesthetic degree prediction on the subgraph, and to reduce the multiple calculations of the subgraph obtained by the sliding window strategy segmentation, and to be more consistent with the reading specification of the circuit layout and wiring schematic diagram user, and the relevant practitioners pay more attention to local information.

[0060] S400: selecting a local subgraph with the smallest Euclidean distance to the cluster center point in each cluster in the clustering result as a representative subgraph, predicting the representative subgraph by a residual neural network to obtain a subgraph aesthetic degree evaluation score of the representative subgraph;

[0061] In some embodiments, the schematic diagram representative subgraph calculated by the genetic clustering algorithm in step S400 is used to obtain a subgraph aesthetic degree evaluation score value of the representative subgraph by a residual neural network, which mainly includes two stages of pre-training and prediction, and the residual neural network used is a pre-trained residual neural network.

[0062] In step S400, the residual neural network predicts the representative subgraph after pre-training. The pre-training step includes:

[0063] S410: obtaining a circuit layout and wiring training graph in a real netlist file, and obtaining a training subgraph by randomly cropping the circuit layout and wiring training graph;

[0064] S420: obtaining a training subgraph dataset with an aesthetic degree score by labeling, vertically flipping and horizontally flipping the training subgraph;

[0065] S430: pre-training a residual neural network according to the training subgraph dataset.

[0066] S500: calculating a schematic diagram aesthetic degree evaluation score of the circuit layout and wiring schematic diagram according to the subgraph aesthetic degree evaluation score, and calculating an aesthetic degree evaluation grade of the circuit layout and wiring schematic diagram to be evaluated based on the schematic diagram aesthetic degree evaluation score and the grade mapping relationship.

[0067] Further, the schematic diagram aesthetic degree evaluation score and the grade mapping relationship are shown in Table 1.

[0068] Table 1: Aesthetic evaluation score grade mapping relationship

[0069]

[0070] In some embodiments, the Calibre software is used to run the real netlist file to obtain the original layout and routing schematic diagram, the subgraph labeling is performed through random cropping and combined with expert experience, 5331 subgraph datasets with aesthetic score values are obtained through vertical and horizontal flipping strategies of the subgraph to train and verify, the verification set accounts for 15%, the transfer learning strategy is used for the training set, the pool layer is fine-tuned based on the neural network parameters of the ImageNet-1K dataset, and finally the pre-training model of the deep residual neural network is obtained.

[0071] In step S500, the schematic diagram aesthetic evaluation score of the circuit layout and routing schematic diagram is obtained by introducing the subgraph aesthetic evaluation score into the maximum value aggregation strategy, the average value aggregation strategy, the mode average value aggregation strategy and the weighted average value aggregation strategy.

[0072] In some embodiments, the average value aggregation strategy is represented as:

[0073]

[0074] wherein p is the circuit layout and routing schematic diagram, avg(p) is the average value aggregation strategy calculation model corresponding to the circuit layout and routing schematic diagram, j is the second index value, i is the total number of representative subgraphs, h j is the subgraph aesthetic evaluation score corresponding to the representative subgraph in the jth cluster.

[0075] In some embodiments, the mode average value aggregation strategy is represented as:

[0076]

[0077] wherein mavg(p) is the mode average value aggregation strategy calculation model corresponding to the circuit layout and routing schematic diagram, mode is the total mode set, mode j is the mode set corresponding to the jth cluster.

[0078] In some embodiments, the weighted average value aggregation strategy is represented as:

[0079]

[0080] wherein wavg(p) is the weighted average value aggregation strategy calculation model corresponding to the circuit layout and routing schematic diagram, |clu j | is the number of subgraphs of the jth cluster in the automatic clustering center subgraph stage, m is the row dimension of the circuit layout and routing schematic diagram, n is the column dimension of the circuit layout and routing schematic diagram, and s is the sliding window size adopted when the circuit layout and routing schematic diagram is segmented.

[0081] In some embodiments, first, the Calibre software is used to generate the original layout and routing schematic diagram of the real netlist file obtained in the cooperative enterprise engineering application, then the subgraph labeling is performed through random cropping combined with expert experience, and finally, 5331 subgraph datasets are obtained through vertical and horizontal flipping of the subgraphs for model training and verification, wherein the verification set of the deep learning algorithm model accounts for about 15%, and the evaluation and verification of the deep learning algorithm model framework acc(t) index are performed on the subgraph dataset for 6 kinds of widely used deep learning algorithm models ResNet34, AlexNet, Vgg11, SqueezeNet, InceptionV3 and SwinTransformer, wherein acc(t) represents the proportion of correctly predicted samples in total samples under the tolerance t error condition, and the larger the acc(t) index, the better the algorithm prediction effect, and the results show that the residual neural network ResNet34 shows the best overall prediction effect, and when t is 0, 1, 2 and 3, the prediction accuracy is 0.412, 0.790 and 0.933 respectively, which shows that the residual neural network algorithm model is the most effective in extracting and learning the layout and routing schematic diagram of the circuit.

[0082] In some embodiments, in order to evaluate the overall performance of the novel circuit layout and routing schematic diagram aesthetic degree evaluation method, a test dataset containing 192 real original pictures is used for overall performance verification, and in order to determine the gain influence of the genetic clustering algorithm on the present application, the above-mentioned four aggregation modes are run using 192 netlist files without using the genetic clustering algorithm (Without GKA) and using the genetic clustering algorithm (With GKA), including the acc(t) values obtained by the maximum value aggregation strategy, the average value aggregation strategy, the mode average value aggregation strategy and the weighted average value aggregation strategy, and the results show that among the four aggregation rules, the average value aggregation strategy and the weighted average value aggregation strategy show the best evaluation effect, and in the acc(t=2) case, a high accuracy score of 0.953 is obtained, which shows that the average value aggregation strategy and the weighted average value aggregation strategy are more in line with the evaluation reading habit of designers from the whole to the local and then to the whole during the schematic diagram reading process.

[0083] The circuit layout and routing schematic diagram aesthetic degree evaluation method provided by the present application objectively quantifies the subjective experience in the field of circuit automation design with the powerful learning and fitting capability of deep learning technology, perfects the basic evaluation index of the circuit layout and routing generation algorithm, comprehensively and effectively evaluates the logic clarity and aesthetic degree of the schematic diagram, and further facilitates relevant designers to quickly understand the circuit and check errors in the early design stage.

[0084] It should be pointed out finally that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit the same; and although the present application has been described in detail with reference to the foregoing embodiments, it should be appreciated by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for evaluating the aesthetic level of circuit layout and wiring schematics, characterized in that, include: S100: Obtain the circuit layout and routing schematic diagram, and segment the circuit layout and routing schematic diagram based on the sliding window strategy to obtain a local sub-graph of the circuit layout and routing schematic diagram. S200: Extract graph-type subgraph features of the local subgraph using a Laplacian convolution kernel, and reduce the dimensionality of the graph-type subgraph features to a feature vector space to obtain a numerical subgraph feature vector; S300: Perform clustering on the local subgraph based on the feature vector of the subgraph using a genetic clustering algorithm to obtain the clustering result; S310: Generate multiple random center points in the local subgraph, and encode the multiple random center points into a set as a string; S320: Determine the basic operating parameters of the genetic clustering algorithm, initialize the string as a genetic population, the basic operating parameters include the upper limit of the number of iterations; the basic operating parameters also include the genetic selection probability, the total number of individuals in the genetic population, the genetic crossover probability, and the genetic mutation probability; S330: Select the sample center point according to Euclidean distance and add it to the genetic population. Calculate the fitness value of all individuals in the genetic population using the DB index and the fitness function. The fitness function is calculated as follows: in, The first in the genetic population Individual genetic traits The first index value, For the first The fitness function corresponding to each genetic individual The preset maximum clustering parameter, For the first Cluster diameter, For the first Cluster diameter, For the first Cluster and the first Euclidean distance between the centers of each cluster; S340: Sort all individuals in the genetic population according to the fitness value, and perform crossover, selection and mutation on the sorted genetic population according to the basic operating parameters to obtain a new generation of genetic population; S350: Sort all individuals in the new generation of genetic population, and perform crossover, selection and mutation on the sorted new generation of genetic population according to the basic operating parameters until the optimal genetic population that meets the upper limit of the iteration operation is obtained as the clustering result; S400: Select the local subgraph with the smallest Euclidean distance from the cluster center point within each cluster in the clustering results as the representative subgraph, predict the representative subgraph through the residual neural network, and obtain the subgraph aesthetic evaluation score of the representative subgraph. S5 00: Calculate the schematic aesthetics score of the circuit layout and wiring schematic based on the aesthetics score of the sub-graph, and calculate the aesthetics evaluation level of the circuit layout and wiring schematic to be evaluated based on the mapping relationship between the schematic aesthetics score and the score level.

2. The method for evaluating the aesthetic level of circuit layout and wiring schematics according to claim 1, characterized in that, The Laplacian convolution kernel mentioned in step S200 is represented as follows: in, is the Laplace convolution kernel.

3. The method for evaluating the aesthetic level of circuit layout and wiring schematics according to claim 1, characterized in that, The residual neural network described in step S400 is pre-trained before predicting the representative subgraph. The pre-training steps include: S410: Obtain the circuit layout and routing training diagram from the real netlist file, and randomly crop the circuit layout and routing training diagram to obtain a training sub-diagram. S420: After labeling the training subgraphs, vertically and horizontally flip them to obtain a training subgraph dataset with aesthetic scores; S430: Pre-train the residual neural network based on the training subgraph dataset.

4. The method for evaluating the aesthetic level of circuit layout and wiring schematics according to claim 1, characterized in that, In step S500, the schematic aesthetics evaluation score of the circuit layout and wiring schematic is obtained by introducing the maximum value aggregation strategy, the average value aggregation strategy, the mode average value aggregation strategy, and the weighted average value aggregation strategy into the sub-graph aesthetics evaluation score.

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