Test circuit inspection method, test platform, storage medium and test system
By sending control signals to the test circuit of the semiconductor memory and analyzing the test mode signals, the problem of address latch configuration errors was solved, and efficient error checking and verification were achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-05-06
- Publication Date
- 2026-07-24
AI Technical Summary
In the prior art, the test circuits in semiconductor memories are prone to configuration errors due to the large number of address latches, which affects the normal use of the test functions.
By sending control signals to the test circuit, the address latch output test mode signals are selected in sequence, and the signals are analyzed to determine whether there are configuration errors in the latch, and a simulation result report is output.
It quickly and efficiently checks for configuration errors in address latches, improving work efficiency and verification accuracy.
Smart Images
Figure CN117059155B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor memory technology, and in particular to a test circuit inspection method, test platform, storage medium and test system. Background Technology
[0002] Electronic devices contain numerous test circuits that provide functions such as circuit boundary scanning, internal parameter output, internal function switching, and local circuit timing adjustment under different test modes. Specifically, these test circuits are controlled by a large number of address latches. Different address latches are needed to activate the corresponding circuit sections for testing in different test modes. Furthermore, the output pins of the same address latch also correspond to different test modes. In other words, a specific test mode requires activation via a specific pin of a specific address latch. However, due to the large number of address latches, address latch configuration errors frequently occur, affecting the normal operation of the test functions. Summary of the Invention
[0003] This disclosure provides a circuit inspection method, test platform, storage medium, and test system that can check for configuration errors in address latches, thereby improving work efficiency and verification accuracy.
[0004] The technical solution disclosed herein is implemented as follows:
[0005] In a first aspect, embodiments of this disclosure provide a test circuit inspection method applied to a test platform, wherein the test circuit includes a plurality of address latches, and the test platform and the test circuit are connected, the method comprising:
[0006] A control signal is sent to the test circuit to determine the test mode signal output by the test circuit; wherein, the test circuit sequentially selects a plurality of the address latches according to the control signal to output the test mode signal;
[0007] The test mode signal is analyzed to determine whether there are errors in several address latches in the test circuit;
[0008] Output simulation results report.
[0009] In some embodiments, the control signal includes multiple sets of address signals, each set of address signals including a main address signal and a preset number of sub-address signals. Sending the control signal to the test circuit to determine the test mode signal output by the test circuit includes:
[0010] Send the main address signal to the test circuit to select the target address latch from the plurality of address latches;
[0011] A preset number of sub-address signals are sequentially sent to the test circuit to control the target address latch to traverse and output all test mode signals.
[0012] In some embodiments, after sequentially sending a preset number of the sub-address signals to the test circuit, the method further includes:
[0013] The target address latch is reset.
[0014] In some embodiments, analyzing the test mode signal to determine whether there are errors in several address latches in the test circuit includes:
[0015] After sending the main address signal to the test circuit, the target address latch and the target quantity are determined;
[0016] Based on the first design parameters, the target address latch and the target number are analyzed to determine whether there is a Type I error in several address latches in the test circuit;
[0017] The first type of error refers to an incorrect configuration of the main address of the address latch, an incorrect placement of the address latch, or an omission of an address latch in the preset area.
[0018] In some embodiments, the target quantity includes a first target quantity and a second target quantity, wherein the first target quantity refers to the number of target address latches and the second target quantity refers to the number of target address latches belonging to the preset region;
[0019] The analysis of the target address latch and the target quantity based on the first design parameters, to determine whether several address latches in the test circuit have a Type I error, includes:
[0020] Based on a preset association relationship, the target location information corresponding to the test mode signal is determined; wherein, the preset association relationship is used to indicate the circuit location information of each test mode signal in the test circuit;
[0021] The target location information is subjected to keyword matching processing to determine the target address latch; and the first target quantity and the second target quantity are determined based on the target location information.
[0022] In some embodiments, analyzing the test mode signal to determine whether there are errors in a plurality of address latches in the test circuit further includes:
[0023] After sequentially sending a preset number of sub-address signals to the test circuit, the signal value array of the target address latch is determined according to the test mode signal output by the test circuit.
[0024] Based on the second design parameters, the signal value array is analyzed to determine whether there is a type II error in several address latches in the test circuit;
[0025] The second type of error refers to an incorrect initial value configuration of the address latch.
[0026] In some embodiments, determining the signal value array of the target address latch based on the test mode signal output by the test circuit includes:
[0027] After sending a sub-address signal to the test circuit, the level state of the corresponding output pin in the target address latch is determined according to the test mode signal output by the test circuit.
[0028] The level state of the corresponding output pin in the target address latch is converted into binary to obtain a signal value in the signal value array;
[0029] After sequentially sending a preset number of the sub-address signals to the test circuit, the signal value array is obtained.
[0030] In some embodiments, when there are multiple target address latches, the method further includes:
[0031] After sending a sub-address signal to the test circuit, multiple target signal names are determined based on the test mode signal output by the test circuit.
[0032] A consistency comparison is performed on multiple target signal names to determine whether a certain number of address latches in the test circuit have a Type III error;
[0033] The third type of error refers to a sub-address configuration error of the address latch.
[0034] In some embodiments, determining multiple signal names based on the test mode signal output by the test circuit includes:
[0035] Based on a preset association relationship, determine multiple target location information corresponding to the test mode signal;
[0036] The target location information is truncated to obtain multiple signal names.
[0037] In some embodiments, the consistency comparison of the plurality of signal names includes:
[0038] Determine the identifier value corresponding to each of the multiple signal names; wherein the identifier value is obtained by accumulating the ASCII code value of each element in the signal name;
[0039] The identifier values corresponding to each of the multiple signal names are compared to determine whether the multiple signal names are consistent.
[0040] In some embodiments, the method further includes:
[0041] After sending all the main address signals to the test circuit, the first total number and the second total number are counted; wherein, the first total number refers to the total number of times that a plurality of address latches in the test circuit are selected, and the second total number refers to the total number of times that a plurality of address latches in the preset area are selected.
[0042] Based on the third design parameters, the first total quantity and the second total quantity are analyzed to determine whether the test circuit has a fourth type of error;
[0043] The third design parameter refers to the expected total number of times the address latch in the test circuit is selected, and the fourth type of error refers to the address latch being placed outside the preset area.
[0044] In some embodiments, the calculation of the first total quantity and the second total quantity includes:
[0045] Before sending the first master address signal, both the first total quantity and the second total quantity are initialized to 0;
[0046] After sending a master address signal to the test circuit and determining the first target quantity and the second target quantity, the first total quantity is updated using the sum of the first target quantity and the first total quantity, and the second total quantity is updated using the sum of the second target quantity and the second total quantity.
[0047] Secondly, embodiments of this disclosure provide a test platform connected to a test circuit including a plurality of address latches. The test platform includes a test unit, a parsing unit, and an output unit; wherein...
[0048] The test unit is configured to send a control signal to the test circuit to determine the test mode signal output by the test circuit; wherein, the test circuit sequentially selects a plurality of the address latches according to the control signal to output the test mode signal;
[0049] The analysis unit is configured to analyze the test mode signal to determine whether there are errors in several address latches in the test circuit;
[0050] The output unit is configured to output a simulation result report.
[0051] Thirdly, embodiments of this disclosure provide a test platform including a memory and a processor; wherein the memory is used to store a computer program capable of running on the processor; and the processor is used to execute the steps of the method described in the first aspect when running the computer program.
[0052] Fourthly, embodiments of this disclosure provide a computer storage medium storing a computer program that, when executed by at least one processor, implements the steps of the method as described in the first aspect.
[0053] Fifthly, embodiments of this disclosure provide a testing system, which includes at least the testing platform as described in the second or third aspect and a testing circuit including a plurality of address latches.
[0054] This disclosure provides a test circuit inspection method, test platform, storage medium, and test system, which can quickly and efficiently check whether there are configuration errors in the address latches in the test circuit, promptly detect circuit problems, and improve work efficiency and verification accuracy. Attached Figure Description
[0055] Figure 1 A schematic flowchart of a test circuit inspection method provided in an embodiment of this disclosure;
[0056] Figure 2 This is a schematic diagram of the structure of an address latch provided in an embodiment of the present disclosure;
[0057] Figure 3 A flowchart illustrating another test circuit inspection method provided in this disclosure embodiment;
[0058] Figure 4 A schematic diagram of the composition structure of a test platform provided in an embodiment of this disclosure;
[0059] Figure 5 This is a schematic diagram of the specific hardware structure of a test platform provided in an embodiment of the present disclosure;
[0060] Figure 6 This is a schematic diagram of the structure of a testing system provided in an embodiment of this disclosure. Detailed Implementation
[0061] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the relevant applications and not intended to limit the scope of the applications. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.
[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.
[0063] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0064] The following describes the technical terms and abbreviations used in the embodiments of this disclosure.
[0065] Dynamic Random Access Memory (DRAM)
[0066] Low Power Double Data Rate SDRAM (LPDDR)
[0067] Memory compliant with the 5th generation LPDDR standard (LPDDR5)
[0068] Semiconductor memories (such as DRAM chips) contain numerous Design for Test (DFT) circuits. These circuits provide functions such as circuit boundary scanning, internal parameter output, internal function switching, and local circuit timing adjustment without affecting the original design functionality. Taking LPDDR5 as an example, there are over 500 test modes, each accessible by a specific test mode address. These are represented by multiple address latches in the circuit. Address latches at the same address are not necessarily unique and are distributed across various locations within the circuit based on functional requirements for better control of the test circuitry. Designers compile statistics on all test modes and determine the access addresses, number, and location of each test mode using a table. However, due to the large number of test mode address latches distributed across more than ten designated locations on the chip, configuration errors are prone to occur.
[0069] This disclosure provides a test circuit inspection method that can quickly and efficiently check whether there are configuration errors in the address latches in the test circuit, thereby improving work efficiency and verification accuracy.
[0070] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0071] In one embodiment of this disclosure, see Figure 1 This illustrates a flowchart of a test circuit inspection method provided in an embodiment of this disclosure. Figure 1 As shown, the method may include:
[0072] S101: Send a control signal to the test circuit to determine the test mode signal output by the test circuit; wherein, the test circuit selects several address latches in sequence according to the control signal to output the test mode signal.
[0073] S102: Analyze the test mode signals to determine whether there are errors in several address latches in the test circuit.
[0074] S103: Output simulation results report.
[0075] It should be noted that the test circuit inspection method provided in this embodiment is applied to a test platform, which is connected to the test circuit, and the test circuit includes several address latches, so that the designer can check the configuration of several address latches in the test circuit through the test platform.
[0076] Here, the test platform can be various computing devices, and the test platform implements the test circuit inspection method through pre-installed software programs. For example, the software program can be written in Verilog or Perl. Additionally, the test circuit can refer to the circuitry within DRAM.
[0077] It should be noted that, in some embodiments, after the test platform and test circuit are connected, the method further includes:
[0078] The test platform is bound to the output signals of several address latches, establishing a preset association within the test platform to enable real-time monitoring of signal transitions in the test circuit. This preset association is used to monitor the transitions of each output signal, i.e., the test mode signal, in the test circuit.
[0079] In this way, after the test platform sends a control signal to the test circuit, if the output signal of a certain address latch in the test circuit jumps, the test platform can identify the jump output signal according to the preset correlation, and then determine the corresponding address latch to check whether the address latch has a configuration error, thus improving work efficiency and verification accuracy.
[0080] See Figure 2This illustration shows a schematic diagram of an address latch provided in an embodiment of this disclosure. Figure 2 As shown, the input terminals of the address latch are used to receive the main address signal Main Addr and the sub-address signal Sub Addr, respectively. Based on the main address signal Main Addr and the sub-address signal Sub Addr, the latch outputs test mode signals (e.g., Test Mode0, Test Mode1, Test Mode2, Test Mode3, and Test Mode4) through corresponding output pins to control the operating state of subsequent circuits. Specifically, the main address signal Main Addr is used to select a specific address latch, and the sub-address signal Sub Addr is used to control the selected address latch to output the corresponding test mode signal.
[0081] Therefore, in some embodiments, the control signal includes multiple sets of address signals, each set of address signals including a main address signal Main Addr and a preset number of sub-address signals Sub Addr. Sending the control signal to the test circuit to determine the test mode signal output by the test circuit includes:
[0082] Send the main address signal Main Addr to the test circuit to select the target address latch from several address latches; send a preset number of sub-address signals Sub Addr to the test circuit in sequence to control the target address latch to traverse and output all test mode signals.
[0083] It should be noted that the preset number needs to be determined based on the number of output pins of the address latch. This disclosure does not limit this. For example, regarding... Figure 2 The address latches in the memory have a default quantity of 5.
[0084] It should be understood that the master address signal can be sent first, followed by a predetermined number of sub-address signals in sequence, or the master address signal can be sent simultaneously with the first sub-address signal. Furthermore, the corresponding master address signal remains valid throughout the process of traversing the sub-address signals. In other words, after sending the master address signal, it remains valid until the next master address signal is sent.
[0085] like Figure 2 As shown, the address latch is also used to receive a reset signal Reset, and performs a reset process upon receiving the reset signal Reset to reset the output signal of the address latch to its initial value. Therefore, in some embodiments, after sequentially sending a preset number of sub-address signals to the test circuit, the method further includes: resetting the target address latch.
[0086] It should be noted that for the test circuit, the address latch may have the following error types: Error (1), main address configuration error; Error (2), sub-address configuration error; Error (3), initial value configuration error; Error (4), address latch is not placed in the preset area; Error (5), address latch is placed outside the preset area.
[0087] Assuming the DRAM chip has six memory regions, A, B, ..., F, and these regions are where the address latches for the test mode are concentrated, then the error types can be represented as follows:
[0088] Error (1), main address configuration error: The address latch corresponding to the main address 100 is planned to be placed in area D, but the designer accidentally configured its main address as 101 during configuration;
[0089] Error (2), Sub-address configuration error: The address latches corresponding to the main address 100 are placed in areas A to F respectively. The sub-address 2 of the address latches in area A controls the test mode TM100. The designer accidentally connected the test mode controlled by the sub-address 2 of the address latches in area F to TM200.
[0090] Error (3), initial value configuration error: the initial value of the five output control pins of the address latch can be set to 0 or 1 upon power-on. The designer may have configured the initial value incorrectly.
[0091] Error (4): The address latch was missing or misplaced in the preset area: The address latch corresponding to the main address 100 was planned to be placed in four areas from A to D. The designer accidentally missed the corresponding address latch in area D or misplaced the corresponding address latch in area E.
[0092] Error (5), address latch placed outside the preset area: an address latch was mistakenly placed outside the area from A to F.
[0093] For the aforementioned error types, specific inspection methods are provided below.
[0094] In some embodiments, analyzing the test mode signal to determine whether there are errors in several address latches in the test circuit includes:
[0095] After sending the main address signal to the test circuit, the target address latch and the target number are determined according to the test mode signal output by the test circuit. Based on the first design parameters, the target address latch and the target number are analyzed to determine whether there are Type I errors in several address latches in the test circuit.
[0096] Here, the first type of error refers to an incorrect main address configuration of the address latch, an incorrect placement of the address latch, or an omission of the address latch in the preset area, as detailed in the aforementioned error (1) or error (4). In addition, the preset area refers to the area in the test circuit used to place the latch.
[0097] It should be noted that the design parameters of the test circuit record the correct information of each address latch, which can have various forms of representation, such as tables, index trees, etc., and this disclosure embodiment does not limit them.
[0098] Since the main address signal is used to select a specific address latch, if the actual target address latch detected does not conform to the design parameters of the test circuit, it indicates that the main address signal may have been configured to the wrong address latch. Additionally, since the target address latch is determined based on the circuit location corresponding to the output signal that triggers the jump, the main address signal may also have been configured to the correct address latch, but the latch's placement is incorrect.
[0099] In some embodiments, the target quantity includes a first target quantity and a second target quantity, wherein the first target quantity refers to the number of target address latches and the second target quantity refers to the number of target address latches belonging to a preset region.
[0100] The step of determining the target address latch and the target quantity based on the test mode signal output by the test circuit includes:
[0101] Based on a preset association relationship, the target location information corresponding to the test mode signal is determined; wherein, the preset association relationship is used to indicate the circuit location information corresponding to each test mode signal in the test circuit; keyword matching processing is performed on the target location information to determine the target address latch; and, based on the target location information, the first target quantity and the second target quantity are determined.
[0102] It should be noted that, as mentioned above, the preset association is used to indicate the circuit location information corresponding to each test mode signal in the test circuit. That is, the target location information is used to determine the circuit location level of the output signal that causes the jump, and then determine the first target quantity, the second target quantity, and the target address latch.
[0103] For example, the output signal jump of the address latch triggers the $sformat function in the test platform to capture the target location information, which can be a combination of letters and numbers. Then, the address latch in operation is identified by matching keywords to the target location information. For example, if the target location information of two address latches are TOP.Chip.***.I_TMLeft.I_LatchX5_1955 and TOP.Chip.***.I_TMRight.I_Latch_278, the two latches can be distinguished by the keywords "TMLeft" and "TMRight".
[0104] It should be noted that, in a hypothetical scenario, after sending a master address signal 100, two test mode signals that caused a jump were captured. These signals belong to the "TMLeft" region and the "TMRight" region, respectively, both of which are preset regions. In the first scenario, the main address signal 100 in the first design parameter corresponds to two latches, placed in the "TMLeft" and "TMRight" regions respectively, indicating that the latch corresponding to the main address signal 100 does not have a Type I error. In the second scenario, the main address signal 100 in the first design parameter corresponds to three latches, placed in the "TMLeft," "TMRight," and "DMLeft" regions respectively, indicating that the latch corresponding to the main address signal 100 is missing from the "DMLeft" region, or the main address signal of the latch corresponding to "DMLeft" is incorrectly configured as 101. In the third scenario, the main address signal 100 in the first design parameter corresponds to both the "DMRight" and "DMLeft" regions, indicating that the latch corresponding to the main address signal 100 is incorrectly placed in either the "DMRight" or "DMLeft" region. Here, both misplacement and omission will result in the corresponding address latch not being detected. These two scenarios are difficult to distinguish clearly and the distinction is not very meaningful, so both can be classified as Type I errors, requiring manual verification by the designer.
[0105] Additionally, if the number of the first target and the number of the second target are different, it can also indicate that the address latch is mistakenly placed outside the preset area. See the following explanation for details.
[0106] In this way, based on the correspondence between the main address signal and the target address latch, it is possible to check whether there is a main address configuration error, an address latch missing from the preset area, or an address latch placed incorrectly in the test circuit.
[0107] It should be understood that there are multiple possible timings for checking and determining Type I errors. For example, if there is an output signal jump when the address latch switches from an unselected state to a selected state, then a Type I error check can be performed on the address latch after sending the first main address signal; or, if there is no output signal jump when the address latch switches from an unselected state to a selected state, then a Type I error check can only be performed after sending at least one first sub-address signal. Of course, in practical applications, it is also possible to choose to perform a unified analysis based on the overall results of the monitored test mode signals after all control signals have been sent.
[0108] In some embodiments, analyzing the test mode signal to determine whether there are errors in several address latches in the test circuit further includes:
[0109] After sequentially sending a preset number of sub-address signals to the test circuit, the signal value array of the target address latch is determined based on the test mode signal output by the test circuit; the signal value array is analyzed based on the second design parameters to determine whether several address latches in the test circuit have Type II errors.
[0110] Here, the second type of error refers to the incorrect initial value configuration of the address latch, as detailed in the aforementioned error (3).
[0111] In some embodiments, determining the signal value array of the target address latch based on the test mode signal output by the test circuit includes:
[0112] After sending a sub-address signal to the test circuit, the level state of the corresponding output pin in the target address latch is determined according to the test mode signal output by the test circuit; the level state of the corresponding output pin in the target address latch is converted into binary to obtain a signal value in the signal value array; after sending a preset number of sub-address signals to the test circuit in sequence, the signal value array is obtained.
[0113] It should be noted that we assume the target address latch has 5 output pins. After sending a sub-address signal, the level state of each output pin in the target address latch is obtained. For example, if the output pin is high, it is recorded as signal value "1"; if the output pin is low, it is recorded as signal value "0", to achieve binary conversion processing. After sending a preset number of sub-address signals, the signal values of output pin 1 for the first sub-address signal... and output pin 5 for the fifth sub-address signal are combined to obtain a signal value array of "01001" (for example only). Correspondingly, according to the design parameters of the test circuit, each address latch will also correspond to an expected signal value array. If the signal value arrays are consistent, it means that the address register does not have a Type II error; if the signal value arrays are inconsistent, it means that the address register has a Type II error, that is, an initial value configuration error.
[0114] For example, if the initial value of output pin 1 in an address register should be 0 but is misconfigured as 1, the address register can be detected as having an initial value configuration error after traversing the sub-address signals.
[0115] It should be understood that the same primary address can select the same latch in different regions simultaneously. Specifically, in the embodiments of this disclosure, for ease of explanation, latches corresponding to the same primary address in different regions are referred to as different address latches, and the subsequent description is based on this. In the industry, it is also customary to collectively refer to latches corresponding to the same primary address in different regions as a single address latch, and the subsequent description can be understood accordingly.
[0116] In other words, a certain test mode may involve multiple address registers in different regions. In this case, the main address signal used to indicate the test mode will select multiple address registers simultaneously. That is, for a single main address signal, the number of target address registers can be one or more.
[0117] Therefore, when there are multiple target address latches, the method further includes:
[0118] After sending a sub-address signal to the test circuit, multiple signal names are determined based on the test mode signal output by the test circuit.
[0119] A consistency comparison is performed on multiple signal names to determine whether several address latches in the test circuit have Type III errors.
[0120] Here, the third type of error refers to the sub-address configuration error of the address latch, as detailed in the aforementioned error (2).
[0121] It should be noted that, theoretically, the output signals of address latches corresponding to the same address (both the main address signal and the sub-address signal are identical) should correspond to the same test mode, therefore their output signal names should be the same. Thus, by checking whether the signal names are consistent, it can be determined whether the address latch exhibits a Type III error.
[0122] In some embodiments, determining multiple signal names based on the test mode signal output by the test circuit includes:
[0123] Based on the preset correlation, determine the location information of multiple targets corresponding to the test mode signal;
[0124] Multiple target location information is truncated to obtain multiple signal names.
[0125] In some embodiments, the consistency comparison of multiple signal names includes:
[0126] Determine the identifier value corresponding to each of the multiple signal names; the identifier value is obtained by accumulating the ASCII code value of each element in the signal name; compare the identifier values corresponding to the multiple signal names to determine whether the multiple signal names are consistent.
[0127] For example, suppose that after sending the main address signal and the sub-address signal, the test platform captures two test mode signals that have jumped, with target location information of TOP.Chip.***.I_TMLeft.EnEcc and TOP.Chip.***.I_TMRight.EnEcc respectively. The accumulated ASCII values of the signal names "EnEcc" and "EnEcc" are the same, indicating that the controlled objects of the selected address latches are the same. Conversely, if the target location information of the two output signals that have jumped are TOP.Chip.***.I_TMLeft.EnEcc and TOP.Chip.***.I_TMRight.EnOut respectively, and the accumulated ASCII values of the signal names "EnEcc" and "EnOut" are different, it indicates that the controlled objects of the selected address latches are different.
[0128] In some embodiments, when signal binding is performed between the test platform and the test circuit, a preset area is generally used as the binding object. If the address latch is mistakenly placed outside the preset area, the test platform cannot capture its output signal, which may result in missed detection. Therefore, in some embodiments, the method further includes:
[0129] After sending all the main address signals to the test circuit, the first total number and the second total number are counted. The first total number refers to the total number of times that several address latches in the test circuit are selected, and the second total number refers to the total number of times that several address latches in the preset area are selected. The first total number and the second total number are analyzed based on the third design parameters to determine whether there is a Type IV error in the test circuit. The Type IV error refers to the address latch being placed outside the preset area.
[0130] Here, the third design parameter refers to the expected total number of times the address latch in the test circuit is selected, and the fourth type of error refers to the address latch being placed outside the preset area, see the aforementioned error (5) for details.
[0131] For example, if the third design parameter, the first total number, and the third total number are the same, it means that the address latch is not placed outside the preset area; if the first total number is greater than the second total number, it means that an address latch is placed outside the preset area; if the third design parameter is greater than the first total number, it means that an address latch may be missing from the test circuit, or the main address of the address latch may be incorrectly configured.
[0132] In particular, the above types of errors are not absolute and are only provided for designers' reference. In other words, after an error is detected in the address latch in the test circuit, the designer needs to manually check it. Therefore, the relevant errors are for reference only.
[0133] It should be noted that, in some embodiments, the counting of the first total quantity and the second total quantity includes:
[0134] Before sending the first master address signal, both the first total quantity and the second total quantity are initialized to 0. After sending a master address signal to the test circuit and determining the first target quantity and the second target quantity, the first total quantity is updated using the sum of the first target quantity and the first total quantity, and the second total quantity is updated using the sum of the second target quantity and the second total quantity.
[0135] It should be understood that some information involved in the above error checking process can be used in combination, and the checking results can also be combined with each other. Therefore, the checking of various errors has a relatively flexible combination method, which is not limited in the embodiments disclosed herein. For example, assuming that after sending the main address signal and the sub-address signal, the test platform captures two test mode signals that have jumped, and their target location information is TOP.Chip.***.I_TMLeft.EnEcc and TOP.Chip.***.I_TMRight.EnEcc, respectively. This target location information can be used to determine whether the target latch corresponding to the main address signal meets the expectation, and can also be used to horizontally compare whether the names of the test mode signals corresponding to the same address signal are consistent.
[0136] In this way, the above-described test circuit inspection method can detect various configuration errors in the address register. If the common errors mentioned above are found, error messages will be printed in the simulation report, and the simulation will be reported as failed. If no errors are found, and the total number of times the address latch is selected in the full-chip test mode meets expectations, the simulation will be reported as passed. This allows for a quick and efficient check for configuration errors in the address latches in the test circuit, improving work efficiency and verification accuracy.
[0137] In summary, the number of address latches corresponding to the test modes is large, distributed across more than ten designated locations on the chip, and many of these address latches are not unique. During development, various sporadic human errors are inevitable. Some are relatively easy to detect as the verification process progresses, such as mismatched address decoding, mismatched initial latch values, and misplaced address latches. However, others are difficult to detect, such as address latches corresponding to the same address controlling inconsistent test modes in different locations, or address latches being mistakenly placed outside their designated locations. Therefore, this disclosure provides a test circuit inspection method that can quickly and efficiently check for configuration errors in address latches within the test circuit, improving work efficiency and verification accuracy.
[0138] In another embodiment of this disclosure, see Figure 3 This illustrates a schematic diagram of a test circuit inspection method provided in an embodiment of this disclosure. Figure 3 As shown, the method may include:
[0139] S201: Select all address latches sequentially by sending the main address signal; wherein, for each selected address latch, traverse all combinations of output signals through the sub-address signal and reset the address latch.
[0140] It should be noted that the embodiments disclosed herein relate to semiconductor integrated circuits, and particularly to memory. Specifically, the test circuit inspection method is applied to a test platform, and the test platform stores a test circuit inspection program written in Verilog or Perl, which can check whether the address latches corresponding to all test modes in the DRAM chip meet the design expectations.
[0141] Furthermore, the embodiments disclosed herein are intended to illustrate the overall logic of the test circuit inspection method, rather than specific implementation details. Therefore, steps S201 and subsequent steps S202, S203, and S204 are not divided in the order of execution, and there may even be overlap.
[0142] S202: Bind all address latches in the test platform and monitor them in real time. During the monitoring, determine whether the address latch position meets expectations by identifying the circuit location level of any address latch with active output signals and the number of output signals.
[0143] Here, the number of output signals includes the total number of output signals of the entire circuit as well as the number of output signals located only in the preset area.
[0144] S2021: Determine if there is a main address configuration error or if an address latch is missing or incorrectly placed within the preset area.
[0145] It should be noted that the test platform is bound to the output signals of the address latches corresponding to all test modes in the circuit netlist. This way, after the test platform sends the main address signal and / or sub-address signal, any jump in the output signal of any address latch will trigger the test platform's monitoring function to identify the address latch that has taken action.
[0146] For example, when a jump in the output signal of an address latch is detected, the `$sformat` function is triggered to capture the circuit location level of the module. The circuit location level is a combination of letters and numbers. By matching keywords, the address latch that is currently active can be identified. For instance, if the circuit levels of two latches corresponding to the same address are TOP.Chip.***.I_TMLeft.I_LatchX5_1955 and TOP.Chip.***.I_TMRight.I_Latch_278, these two address latches can be distinguished by matching TMLeft and TMRight.
[0147] In other words, the address latch whose output signal is active is equivalent to the aforementioned "target address latch", and its circuit location level is equivalent to the aforementioned "target location information". In this way, the target address latch that has taken action can be determined by the jump signal. Based on the correspondence between the main address signal and the target address latch, it can be determined whether the location of the target address latch meets the expectation. For details, please refer to the aforementioned error (1) or error (4).
[0148] S203: During the process of traversing and sending sub-address signals, the test mode signal output each time will be monitored in real time to check whether the test mode signal meets the expectations and to compare the names of the test mode signals that trigger the jump at the same address horizontally to see if they are consistent.
[0149] Here, assuming the primary address is configured correctly, if the names of the test mode signals that trigger a jump from the same address are the same, it means the sub-address is configured correctly; if the names of the test mode signals that trigger a jump from the same address are different, it means the sub-address is configured incorrectly.
[0150] S2031: Determine if there is an initial value configuration error and determine if there is a sub-address mismatch.
[0151] It should be noted that when traversing the sub-address signals, the output test mode signals can be checked to see if they meet expectations. Specifically, after sending the sub-address signal, the level state of the output pin of the target address latch is captured and converted into a binary array like 01001. The test platform has expectations for the correct state of each output pin, and the same binary array is formed for comparison to determine whether there is an initial value configuration error. See the error (3) mentioned above for details.
[0152] In addition, when traversing sub-address signals, it is also possible to horizontally compare whether the test mode signals opened by the address latches (placed in different positions) corresponding to the same address are consistent. After sending the main address signal and the corresponding sub-address signal, the circuit location level of the opened test mode signal is captured, the string of the lowest level, i.e. the signal name, is extracted, and the cumulative ASCII code value of each string is calculated to perform a consistency comparison. For example, the circuit levels of the two test mode signals of the same address are TOP.Chip.***.I_TMLeft.EnEcc and TOP.Chip.***.I_TMRight.EnEcc, respectively. The cumulative ASCII code value of the signal name EnEcc is 69+110+69+99+99=446. The cumulative ASCII code values of the two places are compared to determine whether the address latches of the same address signal are used to control the same test mode, i.e., whether the sub-address is configured incorrectly. See the error (2) mentioned above for details.
[0153] S204: Each time an address latch is selected for traversal, the number of open address latches in the entire chip and the number of open address latches in the preset area are monitored simultaneously. These two numbers are continuously accumulated during the simulation process, and the first total number and the second total number are obtained after the scan ends.
[0154] Here, the number of address latches opened across the entire chip can be the first target number mentioned above, and the number of address latches opened in the preset area can be the second target number mentioned above.
[0155] S2041: Based on the expected total number of selections, the first total number, and the second total number, determine whether there is an address latch that is mistakenly placed outside the preset area.
[0156] By comparing the expected total number of selections (i.e. the aforementioned third design parameter), the first total number, and the second total number, it is possible to determine whether there is a latch that is mistakenly placed outside the preset area, i.e., an error (5).
[0157] This embodiment provides a test circuit inspection method. The specific implementation of the aforementioned embodiments is described in detail in this embodiment. It can be seen that the test platform can quickly and efficiently check whether there are configuration errors in the address latch in the test circuit, promptly detect circuit problems, and improve work efficiency and verification accuracy.
[0158] In another embodiment of this disclosure, based on the same concept as the foregoing embodiments, see [link to previous embodiment]. Figure 4 This diagram illustrates the structural composition of a test platform 30 provided in an embodiment of this disclosure. The test platform 30 is connected to a test circuit including a plurality of address latches. Figure 4 As shown, the test platform 30 includes a test unit 301, a parsing unit 302, and an output unit 303; wherein,
[0159] Test unit 301 is configured to send a control signal to the test circuit to determine the test mode signal output by the test circuit; wherein, the test circuit selects a number of address latches in sequence according to the control signal to output the test mode signal.
[0160] The analysis unit 302 is configured to analyze the test mode signal to determine whether there are errors in several address latches in the test circuit;
[0161] Output unit 302 is configured to output a simulation result report.
[0162] In some embodiments, the control signal includes multiple sets of address signals, and each set of address signals includes a main address signal and a preset number of sub-address signals. Accordingly, the test unit 301 is specifically configured to send a main address signal to the test circuit to select a target address latch among several address latches; and to send a preset number of sub-address signals to the test circuit in sequence to control the target address latch to traverse and output all test mode signals.
[0163] In some embodiments, the test unit 301 is further configured to reset the target address latch after sequentially sending a preset number of sub-address signals to the test circuit.
[0164] In some embodiments, the parsing unit 302 is further configured to, after sending the main address signal to the test circuit, determine the target address latch and the target quantity; analyze the target address latch and the target quantity based on the first design parameters to determine whether there is a first type of error in a plurality of address latches in the test circuit; wherein, the first type of error refers to an incorrect main address configuration of the address latch, or an incorrect placement of the address latch, or an address latch being omitted from a preset area.
[0165] In some embodiments, the target quantity includes a first target quantity and a second target quantity. The first target quantity refers to the number of target address latches, and the second target quantity refers to the number of target address latches belonging to a preset region. The parsing unit 302 is further configured to determine target location information corresponding to a test mode signal based on a preset association relationship; wherein the preset association relationship is used to indicate the circuit location information of each test mode signal in the test circuit; perform keyword matching processing on the target location information to determine the target address latches; and determine the first target quantity and the second target quantity based on the target location information.
[0166] In some embodiments, the parsing unit 302 is further configured to, after sequentially sending a preset number of sub-address signals to the test circuit, determine the signal value array of the target address latch based on the test mode signal output by the test circuit; analyze the signal value array based on the second design parameters to determine whether there is a second type of error in several address latches in the test circuit; wherein, the second type of error refers to an incorrect initial value configuration of the address latch.
[0167] In some embodiments, the parsing unit 302 is further configured to, after sending a sub-address signal to the test circuit, determine the level state of the corresponding output pin in the target address latch according to the test mode signal output by the test circuit; perform binary conversion processing on the level state of the corresponding output pin in the target address latch to obtain a signal value in the signal value array; and obtain the signal value array after sequentially sending a preset number of sub-address signals to the test circuit.
[0168] In some embodiments, the parsing unit 302 is further configured to, after sending a sub-address signal to the test circuit, determine multiple signal names based on the test mode signal output by the test circuit; perform a consistency comparison on the multiple signal names to determine whether a certain number of address latches in the test circuit have a third type of error; wherein, the third type of error refers to a sub-address configuration error of the address latch.
[0169] In some embodiments, the parsing unit 302 is further configured to determine multiple target location information corresponding to the test mode signal according to a preset location association relationship; and to extract characters from the multiple target location information to obtain multiple signal names.
[0170] In some embodiments, the parsing unit 302 is further configured to determine the identifier value corresponding to each of the plurality of signal names; wherein the identifier value is obtained by accumulating the ASCII code value of each element in the signal name; and to compare the identifier values corresponding to the plurality of signal names to determine whether the plurality of signal names are consistent.
[0171] In some embodiments, the parsing unit 302 is further configured to, after sending all main address signals to the test circuit, count a first total number and a second total number; wherein, the first total number refers to the total number of times a plurality of address latches in the test circuit are selected, and the second total number refers to the total number of times a plurality of address latches in a preset area are selected; and analyze the first total number and the second total number based on a third design parameter to determine whether the test circuit has a fourth type of error; wherein, the third design parameter refers to the expected total number of times the address latches in the test circuit are selected, and the fourth type of error refers to the address latches being placed outside the preset area.
[0172] In some embodiments, the parsing unit 302 is further configured to initialize both the first total quantity and the second total quantity to 0 before sending the first master address signal; after sending a master address signal to the test circuit and determining the first target quantity and the second target quantity, update the first total quantity using the sum of the first target quantity and the first total quantity, and update the second total quantity using the sum of the second target quantity and the second total quantity.
[0173] Understandably, in this embodiment, a "unit" can be a portion of a circuit, a portion of a processor, a portion of a program or software, etc., and can also be a module or a non-modular component. Furthermore, the components in this embodiment can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional module.
[0174] If the integrated unit is implemented as a software functional module and not sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the method described in this embodiment. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0175] Therefore, this embodiment provides a computer storage medium storing a computer program that, when executed by at least one processor, implements the steps of any of the methods described in the foregoing embodiments.
[0176] Based on the composition of the aforementioned test platform 30 and the computer storage medium, see [link to relevant documentation]. Figure 5 This illustrates a schematic diagram of the specific hardware structure of a test platform 30 provided in an embodiment of this disclosure. For example... Figure 5 As shown, the test platform 30 may include a communication interface 401, a memory 402, and a processor 403; the various components are coupled together via a bus system 404. It is understood that the bus system 404 is used to implement communication between these components. In addition to a data bus, the bus system 404 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 5 The general designates all buses as Bus System 404. Among them,
[0177] Communication interface 401 is used for receiving and sending signals during the process of sending and receiving information with other external network elements;
[0178] Memory 402 is used to store computer programs that can run on processor 403;
[0179] Processor 403, when running the computer program, performs the following:
[0180] A control signal is sent to the test circuit to determine the test mode signal output by the test circuit; wherein, the test circuit selects a number of address latches in sequence according to the control signal to output the test mode signal;
[0181] Analyze the test mode signals to determine if there are errors in several address latches in the test circuit;
[0182] Output simulation results report.
[0183] It is understood that the memory 402 in this embodiment can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The memory 402 of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.
[0184] The processor 403 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 403 or by software instructions. The processor 403 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this disclosure can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory 402, and the processor 403 reads the information in memory 402 and, in conjunction with its hardware, completes the steps of the above method.
[0185] It is understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described herein, or combinations thereof.
[0186] For software implementation, the techniques described herein can be achieved through modules (e.g., procedures, functions, etc.) that perform the functions described herein. The software code can be stored in memory and executed by a processor. The memory can be implemented within the processor or externally.
[0187] Alternatively, as another embodiment, the processor 403 is further configured to perform the steps of the method described in any of the foregoing embodiments when running the computer program.
[0188] This disclosure provides a testing platform that allows for quick and efficient checking of address latches in test circuits for configuration errors, timely detection of circuit problems, and improved work efficiency and verification accuracy.
[0189] In another embodiment of this disclosure, based on the same concept as the foregoing embodiments, see [link to previous embodiment]. Figure 6 This illustrates a schematic diagram of the composition of a test system 50 provided in an embodiment of this disclosure. For example... Figure 6 As shown, the test system 50 includes at least the aforementioned test platform 30 and a test circuit 501 including several address latches.
[0190] In this way, the test platform 30 can quickly and efficiently check whether there are configuration errors in the address latch in the test circuit 501, thus improving work efficiency and verification accuracy.
[0191] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.
[0192] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0193] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0194] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.
[0195] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.
[0196] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.
[0197] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A method for testing circuits, characterized in that, The method, applied to a test platform, includes a test circuit comprising several address latches, and the test platform and the test circuit are connected. A control signal is sent to the test circuit to determine the test mode signal output by the test circuit; wherein, the test circuit sequentially selects a plurality of the address latches according to the control signal to output the test mode signal; The test mode signal is analyzed to determine whether there are errors in several address latches in the test circuit; Output simulation results report.
2. The test circuit inspection method according to claim 1, characterized in that, The control signal includes multiple sets of address signals, each set of address signals including a main address signal and a preset number of sub-address signals. Sending the control signal to the test circuit to determine the test mode signal output by the test circuit includes: Send the main address signal to the test circuit to select the target address latch from the plurality of address latches; A preset number of sub-address signals are sequentially sent to the test circuit to control the target address latch to traverse and output all test mode signals.
3. The test circuit inspection method according to claim 2, characterized in that, After sequentially sending a preset number of sub-address signals to the test circuit, the method further includes: The target address latch is reset.
4. The test circuit inspection method according to claim 2, characterized in that, The analysis of the test mode signal to determine whether there are errors in several address latches in the test circuit includes: After sending the main address signal to the test circuit, the target address latch and the target quantity are determined; Based on the first design parameters, the target address latch and the target number are analyzed to determine whether there is a Type I error in several address latches in the test circuit; The first type of error refers to an incorrect configuration of the main address of the address latch, an incorrect placement of the address latch, or an omission of an address latch in the preset area.
5. The test circuit inspection method according to claim 4, characterized in that, The target quantity includes a first target quantity and a second target quantity. The first target quantity refers to the number of target address latches, and the second target quantity refers to the number of target address latches belonging to the preset region. The analysis of the target address latch and the target quantity based on the first design parameters, to determine whether several address latches in the test circuit have a Type I error, includes: Based on a preset association relationship, the target location information corresponding to the test mode signal is determined; wherein, the preset association relationship is used to indicate the circuit location information of each test mode signal in the test circuit; The target location information is subjected to keyword matching processing to determine the target address latch; and the first target quantity and the second target quantity are determined based on the target location information.
6. The test circuit inspection method according to claim 2, characterized in that, The step of analyzing the test mode signal to determine whether there are errors in several address latches in the test circuit also includes: After sequentially sending a preset number of sub-address signals to the test circuit, the signal value array of the target address latch is determined according to the test mode signal output by the test circuit. Based on the second design parameters, the signal value array is analyzed to determine whether there is a type II error in several address latches in the test circuit; The second type of error refers to an incorrect initial value configuration of the address latch.
7. The test circuit inspection method according to claim 6, characterized in that, The step of determining the signal value array of the target address latch based on the test mode signal output by the test circuit includes: After sending a sub-address signal to the test circuit, the level state of the corresponding output pin in the target address latch is determined according to the test mode signal output by the test circuit. The level state of the corresponding output pin in the target address latch is converted into binary to obtain a signal value in the signal value array; After sequentially sending a preset number of the sub-address signals to the test circuit, the signal value array is obtained.
8. The test circuit inspection method according to claim 2, characterized in that, When there are multiple target address latches, the method further includes: After sending a sub-address signal to the test circuit, multiple target signal names are determined based on the test mode signal output by the test circuit. A consistency comparison is performed on multiple target signal names to determine whether a certain number of address latches in the test circuit have a Type III error; The third type of error refers to a sub-address configuration error of the address latch.
9. The test circuit inspection method according to claim 8, characterized in that, The step of determining multiple signal names based on the test mode signal output by the test circuit includes: Based on a preset association relationship, determine multiple target location information corresponding to the test mode signal; The target location information is truncated to obtain multiple signal names.
10. The test circuit inspection method according to claim 9, characterized in that, The consistency comparison of the multiple signal names includes: Determine the identifier value corresponding to each of the multiple signal names; wherein the identifier value is obtained by accumulating the ASCII code value of each element in the signal name; The identifier values corresponding to each of the multiple signal names are compared to determine whether the multiple signal names are consistent.
11. The test circuit inspection method according to claim 5, characterized in that, The method further includes: After sending all the main address signals to the test circuit, the first total number and the second total number are counted; wherein, the first total number refers to the total number of times that a plurality of address latches in the test circuit are selected, and the second total number refers to the total number of times that a plurality of address latches in the preset area are selected. Based on the third design parameters, the first total quantity and the second total quantity are analyzed to determine whether the test circuit has a fourth type of error; The third design parameter refers to the expected total number of times the address latch in the test circuit is selected, and the fourth type of error refers to the address latch being placed outside the preset area.
12. The test circuit inspection method according to claim 11, characterized in that, The statistics of the first total quantity and the second total quantity include: Before sending the first master address signal, both the first total quantity and the second total quantity are initialized to 0; After sending a master address signal to the test circuit and determining the first target quantity and the second target quantity, the first total quantity is updated using the sum of the first target quantity and the first total quantity, and the second total quantity is updated using the sum of the second target quantity and the second total quantity.
13. A testing platform, characterized in that, The test platform is connected to a test circuit comprising several address latches. The test platform includes a test unit, a parsing unit, and an output unit. The test unit is configured to send a control signal to the test circuit to determine the test mode signal output by the test circuit; wherein, the test circuit sequentially selects a plurality of the address latches according to the control signal to output the test mode signal; The analysis unit is configured to analyze the test mode signal to determine whether there are errors in several address latches in the test circuit; The output unit is configured to output a simulation result report.
14. A testing platform, characterized in that, The test platform includes a memory and a processor; wherein... The memory is used to store computer programs that can run on the processor; The processor is configured to perform the steps of the method as described in any one of claims 1 to 12 when running the computer program.
15. A computer storage medium, characterized in that, The computer storage medium stores a computer program that, when executed by at least one processor, implements the steps of the method as described in any one of claims 1 to 12.
16. A testing system, characterized in that, The test system includes at least the test platform as described in claim 13 or 14 and a test circuit including a plurality of address latches.