FPGA-based satellite 5g large dynamic high-speed transmission real-time receiving and time synchronization method and system

Abstract

The application is a satellite 5G large dynamic high-speed transmission real-time receiving and time synchronization method and system based on FPGA, and belongs to the technical field of wireless communication.The system is provided with a real-time receiving module, a time synchronization module and the like at the receiving end of a satellite-ground transmission link.The method comprises the following steps: the receiving end stores data into a DDR3 in real time by using an asynchronous FIFO, and performs time synchronization once every transmission half-frame signal;the starting point of a symbol is calculated in a multi-symbol combination mode, the content of each symbol is obtained according to the starting point of the symbol, a correlation value is calculated according to a known PSS sequence, the starting point of the half-frame signal is obtained, and subsequent CP removal and demodulation operations are continuously performed;the application solves the problem of timing synchronization difficulty caused by large time delay and large frequency offset, realizes low complexity and timing synchronization error not affected by carrier frequency offset under the premise of ensuring accuracy, and can be used for the time synchronization process of a satellite mobile communication system with large dynamic frequency offset.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology and relates to next-generation mobile data communication services. Specifically, it relates to a method and system for real-time reception and time synchronization of satellite 5G high dynamic range transmission based on FPGA (Field Programmable Gate Array), which is applied in satellite-to-ground transmission links. Background Technology

[0002] Satellite communication, integrating terrestrial and satellite technologies, has become a crucial mode of information transmission and communication, while traditional terrestrial cellular networks have experienced explosive growth in users and access devices. Terrestrial communication networks suffer from microsecond-level transmission latency but require large-scale deployment of base station equipment, while satellite communication networks can achieve wide-area coverage but have significant transmission latency. Based on the limitations and advantages of both terrestrial and satellite communication networks, the complementary integration of satellite communication with terrestrial 5G and its evolution technologies represents the future development direction of mobile communication systems. In wireless communication systems, spread spectrum orthogonal frequency division multiplexing (DFT-S-OFDM) technology, based on discrete Fourier transform, is widely used as an important multi-carrier modulation technique. It divides the complete channel into several mutually orthogonal sub-channels, modulating multiple data streams onto each sub-channel for parallel transmission. The mutual orthogonality between subcarriers results in higher spectral efficiency compared to traditional frequency division multiplexing (FDM). Furthermore, the relatively flat sub-channels created by OFDM effectively mitigate the effects of frequency-selective fading. However, when multiple or all subcarriers overlap in the same direction at a certain moment, the system peak power reaches its maximum, resulting in a large peak-to-average power ratio (PAPR) and reducing the power efficiency of the RF amplifier. In LTE systems, DFT-S-OFDM can effectively solve the problem of OFDM PAPR, so it is often used in communication links that are sensitive to transmit power.

[0003] The typical orbital altitude of a Low Earth Orbit (LEO) satellite is approximately 400km-2000km, with round-trip transmission latency reaching tens of milliseconds. The orbital altitude of a Geostationary Orbit (GEO) satellite is approximately 36,000km, with round-trip transmission latency reaching hundreds of milliseconds, far exceeding the millisecond-level latency requirements of terrestrial 5G systems. Furthermore, satellites form several identical spot beams within a certain range through beamforming. Within the coverage area of ​​each beam, there is a significant difference in round-trip latency between terminals closer to the satellite and those farther away. The random access sequence of terrestrial 5G systems cannot meet the uplink access and synchronization requirements of satellites. Large transmission latency and latency differences increase the difficulty of protocol-level integration between satellites and 5G systems, and also affect the performance of satellite-to-ground link synchronization. Terrestrial mobile communication systems can support a maximum user movement speed of 500km / h, corresponding to typical scenarios like high-speed rail. In satellite mobile communication systems, the orbital speed of LEO satellites can reach approximately 7.5km / s, constituting one of the main characteristics distinguishing satellite communication systems from terrestrial mobile communication systems: high dynamic range. Large dynamic range manifests as large Doppler frequency offset and large frequency offset change rate. Therefore, in satellite-to-ground transmission links, there are problems of large time delay and large frequency offset, which will lead to greater SFO (symbol timing deviation) and CTO (carrier frequency deviation), making timing synchronization difficult and seriously affecting the transmission quality and communication quality of satellite-to-ground links. Summary of the Invention

[0004] To address the issues of large latency and large frequency offset in the aforementioned satellite-to-ground transmission links, this invention, based on DFT-S-OFDM technology, provides a method and system for real-time reception and time synchronization of satellite 5G high-dynamic-range transmission with large frequency offset, using FPGA. Through real-time reception of buffered data and a time synchronization architecture design based on cyclic prefix (CP), it is suitable for DFT-S-OFDM systems and can effectively suppress the impact of large latency and large frequency offset on communication quality.

[0005] The present invention proposes a real-time reception and time synchronization method for high-speed, large-dynamic-range satellite 5G transmission based on FPGA. Time synchronization is required after each half-frame of signal transmission. This method includes:

[0006] Step 1: After receiving the data signal and enable signal, the receiving end of the satellite-to-ground transmission link first passes the data through an asynchronous FIFO (first-in, first-out) and then stores it in the DDR3 storage module.

[0007] Step 2: The receiving end sets up a time synchronization module. The time synchronization module retrieves data from DDR3 and stores it in RAM (Random Access Memory) via an asynchronous FIFO. The CP (Cyclic Prefix) module in the time synchronization module retrieves data from RAM, calculates the symbol start point using a multi-symbol merging method, and sends the calculation result to the PSS (Master Synchronization Signal) module of the time synchronization module. The PSS module obtains useful information for each symbol based on the symbol start point, calculates the correlation value between the useful information of each symbol and the known PSS sequence, and the symbol start point corresponding to the maximum correlation value is the start point of the half-frame signal.

[0008] Step 3: The CP module retrieves data from the DDR3 memory module sequentially based on the enable signal and calculation results, removes the cyclic prefix from the data signal, and outputs the results to the subsequent module for demodulation.

[0009] In step 1, two data buffers of half-frame signal length are allocated in the DDR3 storage module at the receiving end, and a ping-pong mechanism is used to buffer the received data in real time. Additionally, a sub-frame length data buffer is added after the data buffers to ensure the integrity of the half-frame data signal.

[0010] Accordingly, the FPGA-based satellite 5G high dynamic range high-speed transmission real-time reception and time synchronization system provided by the present invention includes a real-time reception module, a time synchronization module, and a CP removal module.

[0011] When the receiving end of the satellite-to-ground transmission link receives the data signal and the enable signal, it inputs them into the real-time receiving module. The real-time receiving module then stores the data in the DDR3 storage module after passing it through an asynchronous FIFO.

[0012] The time synchronization module includes a CP module, a PSS module, and a master control module. The time synchronization module retrieves data from DDR3 and stores it in RAM via an asynchronous FIFO. The CP module retrieves data from RAM, calculates the symbol start position using a multi-symbol merging method, and sends the calculation result to the PSS module of the time synchronization module. The PSS module obtains useful information for each symbol based on the symbol start position, calculates the correlation value between the useful information of each symbol and the known PSS sequence, and the symbol start position corresponding to the maximum correlation value is the start point of the half-frame signal.

[0013] The CP module retrieves data from the DDR3 memory module sequentially based on the enable signal and calculation results, removes the cyclic prefix from the data signal, and outputs the results to the subsequent module for demodulation.

[0014] The advantages and positive effects of this invention are as follows: symbol synchronization and frame synchronization can be achieved at the receiver end using known training symbols, unaffected by multipath channels, but the computational complexity is relatively high. The real-time reception and time synchronization system and method for high-speed, large-dynamic-range satellite 5G transmission based on FPGA provided by this invention utilizes the characteristic of adding a cyclic prefix during DFS-S-OFDM transmission to combat inter-symbol interference (ISI) and inter-subcarrier interference (ICI). It employs a symbol timing synchronization algorithm based on the cyclic prefix for time synchronization calculation. First, the information received at the receiver is cached in real-time in a DDR3 storage module. Then, multi-symbol synchronization is performed using the cyclic prefix to obtain the starting position of the symbol. Near the starting position, the similarity between the known training sequence and the useful information of different symbols is maximized to obtain the half-frame synchronization starting point. This reduces computational complexity and saves hardware resources while ensuring accuracy, solving the problem of timing synchronization difficulties caused by large time delays and large frequency offsets. The system and method of this invention have low implementation complexity and the timing synchronization error is unaffected by carrier frequency offset, making it suitable for the time synchronization process of satellite mobile communication systems with large dynamic frequency offsets. Attached Figure Description

[0015] Figure 1 This is a flowchart illustrating the real-time reception and real-time synchronization method of the receiving end of the present invention.

[0016] Figure 2 This is a data processing flowchart of the time synchronization CP module of the present invention;

[0017] Figure 3 This is a data processing flowchart of the time synchronization PSS module of the present invention. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0019] like Figure 1 As shown, the present invention implements a satellite 5G high dynamic range high speed transmission real-time reception and time synchronization method based on FPGA, which includes the following steps 1 to 3.

[0020] Step 1: After receiving the data signal and enable signal, the DDR3 control module controls the data to first pass through a first-level asynchronous FIFO (first-in, first-out) and then be stored in the DDR3 storage module.

[0021] Due to the requirements of actual communication, the receiving end needs to buffer the data in real time and perform operations such as time synchronization and demodulation. Since time synchronization is required every half-frame (5ms), and calculating time synchronization takes up transmission time, the receiving end must buffer the data. Therefore, to ensure continuous data transmission, two half-frame data buffers are allocated in the DDR3 storage module, using a ping-pong mechanism for real-time data buffering. Considering potential time offsets, an additional subframe data buffer is added after the buffers to ensure the integrity of the half-frame data signal. A half-frame contains multiple subframes. Because the data sampling clock and the output clock of the DDR3 storage module (i.e., the operating clock of the subsequent module) are inconsistent, the data is processed through a first-level asynchronous FIFO before entering the DDR3 storage module. The asynchronous FIFO is written to by a control signal from one clock domain and read out by a control signal from another clock domain. In other words, this invention first uses the FIFO as a data buffer, employing different frequency read / write clocks to allow data to be transmitted across different clock domains, avoiding timing issues and enabling interconnection of data interfaces with different data widths.

[0022] Step 2: The time synchronization module retrieves data from the DDR3 storage module, calculates the starting point of the half-frame signal, and sends the calculation result to the DDR3 control module.

[0023] The time synchronization module includes a FIFO module, a CP module, a PSS (Master Synchronization Signal) module, and a master control module. The time synchronization FIFO module retrieves time-domain data from the DDR3 memory module and stores the time-domain data in the RAM of the time synchronization module.

[0024] Since the cyclic prefix itself lacks ideal autocorrelation characteristics, gain can be further obtained by using multiple symbol merging methods to meet the time synchronization requirements under low signal-to-noise ratio conditions in satellite mobile communication systems. Because the time synchronization calculation uses multi-symbol merging, it requires calling a large number of multipliers, resulting in a long calculation time. To ensure that the total time for the time synchronization module to read data and calculate the synchronization result is within 5ms, the operating clock frequency of the time synchronization module needs to be further increased based on the DDR3 output clock. To avoid timing issues, the data is first processed through a single-level asynchronous FIFO before time synchronization.

[0025] In the method of the present invention, the starting point of the half-frame signal is calculated as described in steps 2.1 to 2.2.

[0026] Step 2.1: The time synchronization CP module calculates the symbol start point based on the data in RAM using a time synchronization algorithm based on cyclic prefixes and a multi-symbol merging method, and sends the result to the time synchronization PSS module.

[0027] like Figure 2 As shown, the CP module assumes the symbol start position, i.e., the starting point of the fixed sliding window, reads the sliding window data corresponding to two symbols from the data buffer RAM, and performs conjugate multiplication and summation operations on the data of the two sliding windows to obtain the correlation value. This invention uses a multi-symbol merging method for symbol synchronization calculation. Therefore, it needs to traverse multiple symbols, continue fixing the sliding window at the current assumed symbol start position, obtain the data within the fixed window of the subsequent few symbols, calculate the correlation value of the data of the two windows, and then calculate the average of multiple correlation values. The calculated average value is stored in the correlation value cache block. Then, assuming the symbol start point moves forward by one sampling point, i.e., the sliding window begins to slide, the above operation of traversing multiple symbols and calculating the average correlation value is repeated to obtain the correlation result of the second assumed symbol start point. This process continues until the correlation results of all assumed symbol start points within the sliding window's sliding range are calculated, and the results are all stored in the correlation value cache block. After the sliding ends, the correlation results in the correlation value cache block are compared, i.e., the correlation between the two sliding windows is maximized to obtain the corresponding symbol start point, and this result is sent to the time synchronization PSS module.

[0028] Step 2.2: The time synchronization PSS module calculates the correlation between the signal and the known PSS sequence to obtain the starting point of the half-frame signal. The time synchronization master control module sends the calculated starting point of the half-frame signal to the DDR3 control module.

[0029] like Figure 3 As shown, the PSS module receives the symbol start value output by the CP module, calculates the start value of the useful information for each symbol, and reads the useful information for each symbol from the time-domain data buffer RAM. The time synchronization PSS module then calls the Fast Fourier Transform (FFT) IP core to transform the useful information of the symbol from the time domain to the frequency domain, and stores the frequency domain information in the frequency domain data buffer module. A known PSS sequence is loaded from the reference PSS storage module. The length of the PSS sequence is the same as that of the useful information of the symbol. The PSS sequence and the frequency domain data are multiplied by conjugate and summed to calculate the correlation value. The first calculated correlation value is stored in a register. The correlation value between the PSS sequence and the frequency domain data of the useful information of each symbol is calculated iteratively, and the correlation value in the register is continuously updated. The register always stores the maximum correlation value. After the iterative process is completed, the starting point of the symbol corresponding to the maximum correlation value is the starting point of the half-frame signal finally obtained by time synchronization.

[0030] The time synchronization master control module primarily buffers multiple symbol start positions from the time synchronization CP module and adjusts the sliding window's range. The sliding window length is fixed to the CP length. When calculating the first symbol start point, the corresponding sliding range is the sum of the first symbol's length and the CP length. For the remaining symbol start points, the sliding range is centered on the sum of the previous symbol start point, the length of the previous symbol, and the CP length, with 40 sampling points to the left and right. The time synchronization master control module receives the symbol start points from the time synchronization CP module and provides the sliding window range corresponding to the next symbol start position for the CP module's calculation. After obtaining all symbol start positions within a subframe, they are sent to the time synchronization PSS module for synchronization to obtain the half-frame signal start position, which is then sent to the time synchronization master control module.

[0031] Step 3: The CP module retrieves data from the DDR3 memory module sequentially based on the enable signal and calculation results, removes the cyclic prefix from the data signal, and outputs the results to the subsequent module for demodulation.

[0032] Starting from time 0, the DDR3 control module writes data to the DDR3 storage module and simultaneously reads data from the DDR3 storage module for a little over 1ms, sending it to the time synchronization module. The time synchronization module takes 3ms to calculate the start point, obtaining the calculation result for the half-frame signal start point, which is then sent to the DDR3 control module. When the first time synchronization module finishes its calculation, around 4ms, the DDR3 control module transmits data to the demodulation module, which then begins demodulation. At 5ms, the second time synchronization begins, sequentially fetching and calculating data. Around 9ms, the calculation result is sent to the DDR3 control module, and the second demodulation module begins, continuing the process sequentially.

[0033] It should be noted that the symbolic useful information mentioned above refers to the symbolic content remaining in a symbol excluding CP.

[0034] Accordingly, this invention provides a real-time reception and time synchronization system for high-speed, high-dynamic-range satellite 5G transmission based on FPGA, including a real-time reception module, a time synchronization module, and a CP removal module. When the receiving end of the satellite-to-ground transmission link receives the data signal and the enable signal, it inputs them to the real-time reception module. The real-time reception module then stores the data in a DDR3 storage module after passing it through an asynchronous FIFO.

[0035] The time synchronization module comprises a CP module, a PSS module, and a master control module. The time synchronization module retrieves data from DDR3 and stores it in RAM via an asynchronous FIFO. The CP module retrieves data from RAM, calculates the symbol start position using a multi-symbol merging method, and sends the calculation result to the PSS module of the time synchronization module. The method by which the CP module calculates the symbol start position using multi-symbol merging is as follows: Figure 2 As shown, the specific implementation will not be elaborated further. The PSS module obtains useful information for each symbol based on its symbol start position, calculates the correlation value between the useful information of each symbol and the known PSS sequence, and the symbol start position corresponding to the maximum correlation value is the start point of the half-frame signal. The specific process of the PSS module calculating the start point of the half-frame signal is as follows: Figure 3 As shown, it will not be repeated here. The main control module is used to set the length of the sliding window, cache the starting position of the symbol in the CP module, and adjust the sliding range of the sliding window. The specific implementation function has been explained in step 2 above, and will not be repeated here.

[0036] The CP module retrieves data from the DDR3 memory module sequentially based on the enable signal and calculation results, removes the cyclic prefix from the data signal, and outputs the results to the subsequent module for demodulation.

[0037] Except for the technical features described in the specification, all other technologies are known to those skilled in the art. Descriptions of well-known components and technologies are omitted in this invention to avoid redundancy and unnecessary limitation. The embodiments described above do not represent all embodiments consistent with this application. Various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of this invention are still within the protection scope of this invention.

Claims

1. A method for real-time reception and time synchronization of high-speed, large dynamic range satellite 5G transmission based on FPGA, characterized in that, Includes the following steps: Step 1: After receiving the data signal and enable signal, the receiving end of the satellite-to-ground transmission link first passes the data through an asynchronous FIFO and then stores it in the DDR3 storage module. Step 2: The receiving end sets up a time synchronization module. The time synchronization module retrieves data from DDR3 and stores it in RAM via an asynchronous FIFO. The CP module in the time synchronization module retrieves data from RAM, calculates the symbol start position using a multi-symbol merging method, and sends the calculation result to the PSS module of the time synchronization module. The PSS module obtains useful information for each symbol based on the symbol start position, calculates the correlation value between the useful information of each symbol and the known PSS sequence, and the symbol start position corresponding to the maximum correlation value is the start point of the half-frame signal. After receiving the symbol start position output by the CP module, the PSS module calculates the start value of the useful information of each symbol and reads the useful information of each symbol from the RAM. The PSS module calls the FFT IP core to transform the useful symbol information from the time domain to the frequency domain; The PSS module loads the known PSS sequence from the reference PSS storage module. The length of the PSS sequence is the same as that of the useful information of the symbol. The PSS sequence is multiplied by the frequency domain data of the useful information of each symbol and summed to calculate the correlation value. Step 3: The CP module retrieves data from the DDR3 memory module sequentially based on the enable signal and calculation results, removes the cyclic prefix from the data signal, and outputs the results to the subsequent module for demodulation. In this context, FIFO stands for First In First Out, FPGA stands for Field Programmable Gate Array, RAM stands for Random Access Memory, CP stands for Cyclic Prefix, PSS stands for Master Synchronization Signal, and FFT stands for Fast Fourier Transform.

2. The method according to claim 1, characterized in that, In step 1, two data buffers of half-frame signal length are opened in the DDR3 storage module at the receiving end, and the received data is cached in real time using a ping-pong mechanism; a data buffer of subframe length is added after the data buffers.

3. The method according to claim 1, characterized in that, In step 2, the CP module performs the following: (11) Assuming the current symbol start position, determine the current sliding window start point; (12) Read the sliding window data corresponding to the two symbols from RAM, perform conjugate multiplication and summation on the two sliding window data to obtain the correlation value; (13) Traverse the subsequent symbols, calculate the correlation value of multiple adjacent symbols in the manner of (12), and take the average value of all correlation values ​​calculated under the current symbol start position as the correlation result of the current symbol start position; (14) Move the symbol start position back by one sampling point, slide the sliding window, and perform the above (12) and (13) to obtain the correlation result of the current symbol start position; (15) Calculate the correlation result of all assumed symbol start positions within the sliding window range; (16) Select the symbol start position corresponding to the maximum correlation result and output it to the PSS module.

4. The method according to claim 1 or 3, characterized in that, In step 2, the time synchronization module also includes a central control module. The central control module sets the length of the sliding window to be fixed at the CP length, caches the symbol start position of the CP module, and adjusts the sliding range of the sliding window. The central control module sets the sliding range of the sliding window as follows: the sliding range of the sliding window corresponding to the first symbol start position is the sum of the length of the first symbol and the CP length; the sliding range of the sliding window corresponding to the start positions of other symbols is the range of 40 sampling points to the left and right of the sum of the previous symbol start position plus the length of the first symbol and the CP length. After receiving the symbol start position from the CP module, the central control module provides the sliding range of the sliding window corresponding to the next symbol start position.

5. A satellite 5G high-dynamic-range high-speed transmission, real-time reception, and time synchronization system based on FPGA, characterized in that, The system is deployed at the receiving end of the satellite-to-ground transmission link and includes a real-time receiving module, a time synchronization module, and a CP removal module. When the receiving end of the satellite-to-ground transmission link receives the data signal and the enable signal, it inputs them into the real-time receiving module. The real-time receiving module then stores the data in the DDR3 storage module after passing it through an asynchronous FIFO. The time synchronization module includes a CP module, a PSS module, and a master control module; the time synchronization module retrieves data from DDR3 and first stores it into RAM via an asynchronous FIFO; The CP module retrieves data from RAM, calculates the symbol start position using a multi-symbol merging method, and sends the calculation result to the PSS module of the time synchronization module. The PSS module obtains useful information for each symbol based on the symbol start position, calculates the correlation value between the useful information of each symbol and the known PSS sequence, and the symbol start position corresponding to the maximum correlation value is the start point of the half-frame signal. The PSS module, after receiving the symbol start position output by the CP module, calculates the start value of the useful information of each symbol and reads the useful information of each symbol from RAM; The PSS module calls the FFT IP core to transform the useful symbol information from the time domain to the frequency domain; The PSS module loads the known PSS sequence from the reference PSS storage module. The length of the PSS sequence is the same as that of the useful information of the symbol. The PSS sequence is multiplied by the frequency domain data of the useful information of each symbol and summed to calculate the correlation value. The starting position of the symbol corresponding to the maximum correlation value is taken as the starting point of the half-frame signal. The CP module retrieves data from the DDR3 memory module sequentially based on the enable signal and calculation results, removes the cyclic prefix from the data signal, and outputs the results to the subsequent module for demodulation. In this context, FIFO stands for First In First Out, FPGA stands for Field Programmable Gate Array, RAM stands for Random Access Memory, CP stands for Cyclic Prefix, PSS stands for Master Synchronization Signal, and FFT stands for Fast Fourier Transform.

6. The system according to claim 5, characterized in that, The CP module performs the following steps: (11) Assuming the current symbol start position, determine the current sliding window start point; (12) Read the sliding window data corresponding to the two symbols from RAM, perform conjugate multiplication and summation on the two sliding window data to obtain the correlation value; (13) Traverse the subsequent symbols, calculate the correlation value of multiple adjacent symbols in the manner of (12), and take the average value of all correlation values ​​calculated at the current symbol start position as the correlation result of the current symbol start position; (14) Move the symbol start position back by one sampling point, slide the sliding window, and perform the above (12) and (13) to obtain the correlation result of the current symbol start position; (15) Calculate the correlation result of all assumed symbol start positions within the sliding window range; (16) Select the symbol start position corresponding to the maximum correlation result and output it to the PSS module.

7. The system according to claim 5, characterized in that, The overall control module sets the length of the sliding window to a fixed CP length, caches the symbol start position of the CP module, and adjusts the sliding range of the sliding window. The overall control module sets the sliding range of the sliding window as follows: the sliding range of the sliding window corresponding to the first symbol start position is the sum of the length of the first symbol and the CP length; the sliding range of the sliding window corresponding to the start positions of other symbols is the range of 40 sampling points to the left and right of the sum of the previous symbol start position plus the length of the previous symbol and the CP length. After receiving the symbol start position sent by the CP module, the overall control module provides the sliding range of the sliding window corresponding to the next symbol start position.

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