Display panel and display device

Abstract

The application discloses a display panel and a display device. The display area of the display panel comprises a plurality of light-emitting areas. At least part of the light-emitting areas comprises a first light-emitting sub-area and a second light-emitting sub-area located at the periphery of the first light-emitting sub-area. The display panel comprises a substrate, a light-emitting layer located at one side of the substrate and comprising pixel units located at the light-emitting areas, and a driving layer located between the substrate and the light-emitting layer and comprising pixel driving circuits located at the first light-emitting sub-area and electrically connected with the pixel units and peripheral circuits located at the second light-emitting sub-area. The driving layer further comprises shielding lines located at the second light-emitting sub-area. The pixel driving circuits and the peripheral circuits are distributed with the projections of the shielding lines on the substrate between the projections of the pixel driving circuits and the peripheral circuits on the substrate. Through the above design, the frame of the display panel can be reduced, and the mutual interference between the pixel driving circuits and the peripheral circuits can be reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Narrow bezels have become a key development focus for display products. While existing technologies can reduce bezel size to some extent by narrowing the package width and optimizing the layout of the peripheral cabling, the demand for display product performance is increasing, and ultra-narrow bezels or even bezel-less designs have become the focus of current technology development. Summary of the Invention

[0003] This application provides a display panel and display device that can reduce the bezel of the display panel and reduce mutual interference between the pixel driving circuit and the peripheral circuit.

[0004] A first aspect of this application provides a display panel, the display area of ​​which includes a plurality of light-emitting areas, at least a portion of which includes a first light-emitting sub-area and a second light-emitting sub-area located around the first light-emitting sub-area. The display panel includes: a substrate; a light-emitting layer located on one side of the substrate, including pixel units located in the light-emitting areas; and a driving layer located between the substrate and the light-emitting layer, including a pixel driving circuit located in the first light-emitting sub-area and electrically connected to the pixel units, and a peripheral circuit located in the second light-emitting sub-area; wherein the driving layer further includes a shielding line located in the second light-emitting sub-area, and the orthographic projection of the shielding line on the substrate is distributed between the orthographic projections of the pixel driving circuit and the peripheral circuit on the substrate.

[0005] In the same light-emitting area, the orthogonal projection of the pixel driving circuit and the peripheral circuit onto the substrate covers the orthogonal projection of the pixel unit onto the substrate.

[0006] Preferably, the plurality of light-emitting areas are arranged in an array in both the row and column directions.

[0007] Preferably, the light-emitting layer includes a plurality of pixel units located in the light-emitting area and the driving layer includes a plurality of pixel driving circuits located in the light-emitting area. In the same light-emitting area, the plurality of pixel units are arranged only in the column direction and the plurality of pixel driving circuits are arranged only in the column direction. At the same time, each sub-pixel unit in the pixel unit corresponds one-to-one with each sub-pixel driving circuit in the pixel driving circuit, and the sub-pixel unit is electrically connected to the corresponding sub-pixel driving circuit.

[0008] The shielding wire has a fixed potential.

[0009] Preferably, the shielded wire is electrically connected to the VDD signal line, VSS signal line, VGH signal line, or VGL signal line.

[0010] The peripheral circuit includes a first signal line, a second signal line, and a microcircuit. The first signal line and the microcircuit are located outside the first side of the first light-emitting sub-region, and the second signal line is located outside the second side of the first light-emitting sub-region. The first side and the second side are connected, and the extension directions of the first signal line and the second signal line intersect.

[0011] Preferably, the first signal line includes at least one of a Data signal line, a Vref signal line, a CLK signal line, an In signal line, or a Demux signal line, the second signal line includes at least one of a Data signal line, a Vref signal line, a CLK signal line, an In signal line, or a Demux signal line, and the microcircuit includes at least one of an ESD circuit, a GIP circuit, or a Demux circuit.

[0012] Wherein, the orthogonal projection of the shielding line on the substrate is distributed between the second signal line and the orthogonal projection of the pixel driving circuit on the substrate, and the shielding line is disposed in the same layer as the second signal line; and / or, the orthogonal projection of the shielding line on the substrate is distributed between the orthogonal projections of the pixel driving circuit and the microcircuit on the substrate, and the shielding line is disposed in the same layer as at least a portion of the microcircuit; and / or, the orthogonal projection of the shielding line on the substrate is distributed between the pixel driving circuit and the orthogonal projection of the first signal line on the substrate, and the shielding line is disposed in the same layer as the first signal line; and / or, the orthogonal projection of the shielding line on the substrate is distributed between the orthogonal projections of the microcircuit and the first signal line on the substrate, and the shielding line is disposed in the same layer as the first signal line.

[0013] The driving layer includes a first metal layer and a second metal layer, which are stacked sequentially in a direction away from the substrate. At least a portion of the pixel driving circuit, at least a portion of the microcircuit, and the first signal line are formed in the first metal layer, and the second signal line is formed in the second metal layer. The second metal layer further has a first connection line electrically connecting the pixel driving circuit and the pixel unit.

[0014] Preferably, the second metal layer is further formed with a second connecting line, which electrically connects the first signal line to the microcircuit.

[0015] The display area is divided into multiple sub-display areas, and the light-emitting areas in the same sub-display area are distributed with the same type of microcircuit.

[0016] Preferably, the plurality of sub-display areas includes at least a first sub-display area, a second sub-display area, a third sub-display area, a fourth sub-display area, and a fifth sub-display area. The second, third, fourth, and fifth sub-display areas are sequentially arranged around the first sub-display area. The second and fourth sub-display areas are arranged opposite to each other, and the third and fifth sub-display areas are arranged opposite to each other. Specifically, ESD microcircuits are distributed in the light-emitting areas of the second sub-display area, GIP microcircuits are distributed in the light-emitting areas of the third sub-display area, Demux microcircuits are distributed in the light-emitting areas of the fourth and fifth sub-display areas.

[0017] The display panel further includes a shielding layer located between the light-emitting layer and the driving layer. The shielding layer has vias, and the pixel driving circuit is electrically connected to the pixel unit through the vias.

[0018] Preferably, the shielding layer has a fixed potential.

[0019] Preferably, the shielding layer is electrically connected to the VDD signal line, VSS signal line, VGH signal line, or VGL signal line.

[0020] Wherein, the orthogonal projection of the pixel unit on the substrate covers the orthogonal projection of the via on the substrate.

[0021] Preferably, the display panel further includes a first planarization layer located between the shielding layer and the light-emitting layer.

[0022] A second aspect of this application provides a display device, which includes the display panel in any of the above embodiments.

[0023] The beneficial effects are: by compressing the pixel driving circuit in the light-emitting area, the pixel driving circuit is located in the first light-emitting sub-area, and the peripheral circuit is placed in the second light-emitting sub-area. This can greatly reduce the bezel of the display panel, and even achieve a bezel-less design. Secondly, there are shielding lines projected onto the substrate between the orthogonal projections of the pixel driving circuit and the peripheral circuit on the substrate, which can ensure that the pixel driving circuit and the peripheral circuit do not interfere with each other. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0025] Figure 1 This is a schematic diagram of the display area of ​​the display panel in this application;

[0026] Figure 2 This is a schematic diagram of the structure of the display panel of this application;

[0027] Figure 3 yes Figure 2 A top view of the stacked and layered structure of the light-emitting layer and driving layer in the central light-emitting region;

[0028] Figure 4 This is a schematic diagram of the structure of a display panel according to an embodiment of the prior art;

[0029] Figure 5 This is a top view schematic diagram showing the changes in the display panel driving layer of this application compared to the prior art;

[0030] Figure 6 yes Figure 2 A top-view structural diagram of the middle driving layer;

[0031] Figure 7 yes Figure 2 A top view of the electrical connections between the stacked and layered light-emitting layer and the driving layer;

[0032] Figure 8 yes Figure 1 A schematic diagram of the division method of the central display area;

[0033] Figure 9 yes Figure 2 A top view of the middle shielding layer;

[0034] Figure 10 This is a schematic diagram of one embodiment of the display device of this application. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0036] It should be noted that the terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0037] See Figure 1 This application provides a display panel 10, the display area AA of the display panel 10 includes a plurality of light-emitting areas LA, at least some of the light-emitting areas LA include a first light-emitting sub-area LA1 and a second light-emitting sub-area LA2 located on the periphery of the first light-emitting sub-area LA1. The second light-emitting sub-area LA2 may be located on one side of the first light-emitting sub-area LA1 or a combination of multiple sides of the first light-emitting sub-area LA1. Of course, it is possible to select some light-emitting areas LA to include the first light-emitting area LA1 and the second light-emitting area LA2, or it is possible to select all light-emitting areas LA to include the first light-emitting area LA1 and the second light-emitting area LA2.

[0038] See Figure 2 and Figure 3 The display panel 10 includes a substrate 110, an emissive layer 120, and a driving layer 130. The emissive layer 120 is located on one side of the substrate 110 and includes a pixel unit 1201 located in the emissive region LA. The driving layer 130 is located between the substrate 110 and the emissive layer 120 and includes a pixel driving circuit 1301 located in the first emissive sub-region LA1 and electrically connected to the pixel unit 1201, and a peripheral circuit 1302 located in the second emissive sub-region LA2.

[0039] Specifically, pixel unit 1201 is located in light-emitting area LA, and light-emitting area LA includes at least one pixel unit 1201. One pixel unit 1201 may include multiple sub-pixel units of different colors, such as at least one of red, green, or blue sub-pixel units. This application exemplifies three sub-pixel units as one pixel unit 1201, and describes four pixel units 1201 in light-emitting area LA as an example. Correspondingly, to maintain consistency with the number of pixel units 1201, pixel driving circuit 1301 also corresponds to four pixel units 1201, and to each of their sub-pixel units. Driving layer 130 may include multiple conductive layers and dielectric layers, used to form pixel driving circuit 1301 and peripheral circuit 1302.

[0040] In the prior art, reference Figure 4 A bezel area BA is provided around the display area AA of the display panel 10. Pixel units 1201 and pixel driving circuits 1301 are disposed in the light-emitting areas LA. The orthogonal projections of pixel units 1201 and their corresponding pixel driving circuits 1301 on the substrate 110 overlap. The display area AA, composed of multiple light-emitting areas LA, is used for normal display. Peripheral circuits are provided in the bezel area BA. These peripheral circuits include ESD circuits, GIP circuits, or Demux circuits, as well as signal lines such as VDD and VSS. The ESD circuit is an electrostatic discharge protection circuit, the GIP circuit is a gate driving circuit, and the Demux circuit is a demultiplexer. VDD and VSS are positive and negative electrical signals electrically connected to the pixel units 1201, respectively. Of course, other peripheral circuits can also be used, not limited to the above. This results in an increase in the width of the bezel area BA. Since the bezel area BA cannot display anything, a wider bezel area BA leads to a poor user experience.

[0041] Please refer to Figure 5 In this application, the pixel driving circuit 1301 located in the driving layer 130 is compressed. Within a light-emitting area LA, it is compressed along the row direction and / or column direction, so that the orthographic projection of the pixel driving circuit 1301 on the substrate 110 is reduced, and all the pixel driving circuits 1301 in the light-emitting area LA are clustered together. The area including all the pixel driving circuits 1301 in the light-emitting area LA can be defined as the first light-emitting sub-area LA1, and the area surrounding the first light-emitting sub-area LA1 (i.e., the empty space obtained by compressing the pixel driving circuits 1301 in the light-emitting area LA) is defined as the second light-emitting sub-area LA2. The second light-emitting sub-area LA2 can be used to place various peripheral circuits located in the display panel bezel area BA in the prior art. In this application, the bezel area BA can be omitted to achieve a bezel-less effect.

[0042] The driving layer 130 further includes a shielding line 1303 (thick solid line in the figure) located in the second light-emitting sub-region LA2. The shielding line 1303 is distributed between the orthogonal projections of the pixel driving circuit 1301 and the peripheral circuit 1302 on the substrate 110.

[0043] Furthermore, considering that the peripheral circuit 1302 in the frame area BA is placed in the second light-emitting sub-region LA2 and is very close to the pixel driving circuit 1301 located in the first light-emitting sub-region LA1, there will be mutual coupling during circuit operation, which will affect both the peripheral circuit 1302 and the pixel driving circuit 1301. Therefore, a shielding line 1303 is provided in the driving layer 130. The orthogonal projection of the shielding line 1303 on the substrate 110 is located between the orthogonal projections of the peripheral circuit 1302 and the pixel driving circuit 1301 on the substrate 110. Through the equipotential of the shielding line 1303, the circuit interference signals of the peripheral circuit 1302 and the pixel driving circuit 1301 are shielded, which can ensure the stable and reliable operation of the peripheral circuit 1302 and the pixel driving circuit 1301.

[0044] Please refer to Figure 3 In the same light-emitting area LA, the orthographic projections of the pixel driving circuit 1301 and the peripheral circuit 1302 onto the substrate 110 cover the orthographic projection of the pixel unit 1201 onto the substrate 110. Through this design, it can be ensured that within the same light-emitting area LA, the pixel driving circuit 1301, the peripheral circuit 1302, and the pixel unit 1201 have a corresponding relationship; that is, the pixel driving circuit 1301, the peripheral circuit 1302, and the pixel unit 1201 in adjacent light-emitting areas LA do not overlap, thus avoiding mutual interference between different light-emitting areas LA.

[0045] Of course, in some other embodiments, after the pixel unit 1201 is compressed, the orthographic projection of the pixel unit 1201 on the substrate 110 can completely overlap with the orthographic projection of the pixel driving circuit 1301 on the substrate 110.

[0046] In one implementation, please refer to Figure 1 Multiple light-emitting areas (LAs) are arranged in an array along both the row and column directions. This ensures the uniformity of the display effect across the entire display panel 10.

[0047] In some other implementations, the multiple light-emitting regions (LAs) may not be arranged in an array manner in the row and column directions.

[0048] refer to Figure 3The light-emitting layer 120 includes a plurality of pixel units 1201 located in the light-emitting region LA, and the driving layer 130 includes a plurality of pixel driving circuits 1301 located in the light-emitting region LA. In the same light-emitting region LA, the plurality of pixel units 1201 are arranged only in the column direction, and the plurality of pixel driving circuits 1301 are arranged only in the column direction. At the same time, each sub-pixel unit 1201A in the pixel unit 1201 corresponds one-to-one with each sub-pixel driving circuit 1301A in the pixel driving circuit 1301, and the sub-pixel unit 1201A is electrically connected to the corresponding sub-pixel driving circuit 1301A.

[0049] Specifically, each sub-pixel driving circuit 1301A in the same light-emitting area LA corresponds one-to-one with a sub-pixel unit 1201A. Because the pixel driving circuit 1301 is compressed in both the row and column directions, the orthographic projections of the pixel driving circuit 1301 and its corresponding pixel unit 1201 on the substrate 110 are misaligned. Therefore, the wiring distance required for electrical connections between each sub-pixel driving circuit 1301A and its corresponding sub-pixel unit 1201A varies. Arranging the pixel driving circuit 1301 and its corresponding pixel unit 1201 only in the column direction simplifies the wiring for electrical connections between each sub-pixel driving circuit 1301A and its corresponding sub-pixel unit 1201A, while ensuring the uniformity of the arrangement of the peripheral circuit 1302, the shielding line 1303, and the pixel driving circuit 1301. It should be noted that the column direction is not limited to a specific direction; it can be understood that in different embodiments, the column direction can represent any direction.

[0050] Furthermore, the shielding wire 1303 has a fixed potential.

[0051] Specifically, the shielding wire 1303 can be electrically connected to a fixed potential point, so that the shielding wire 1303 has a fixed potential. This fixed potential can be a ground potential or a fixed value potential with positive or negative charge. This can ensure the shielding effect of the shielding wire 1303 between the pixel driving circuit 1301 and the pixel unit 1201.

[0052] Of course, in some other implementations, the shielding wire 1303 can also be at a non-fixed potential, as long as it can achieve the shielding effect.

[0053] In one application scenario, shielded wire 1303 is electrically connected to VDD signal line, VSS signal line, VGH signal line or VGL signal line.

[0054] Specifically, the VDD signal line is the signal line connected to the anode of pixel unit 1201, the VSS signal line is the signal line connected to the cathode of pixel unit 1201, the VGH signal line is the high-level signal line, and the VGL signal line is the low-level signal line. All of these signals are existing signals on the display panel 10, and their potentials are fixed. No additional fixed-potential signal lines are needed. Connecting any one of them electrically to the shielding line 1303 will achieve the shielding effect. Of course, it is also possible to add a new fixed-potential signal line for shielding; this application does not limit this.

[0055] Please refer to Figure 6 The peripheral circuit 1302 includes a first signal line 13021 (a thin solid line in the row direction in the figure), a second signal line 13022 (a thin solid line in the column direction in the figure), and a microcircuit 13023. The first signal line 13021 and the microcircuit 13023 are located outside the first side A of the first light-emitting sub-region LA1, and the second signal line 13022 is located outside the second side B of the first light-emitting sub-region LA1. The first side A and the second side B are connected, and the extension directions of the first signal line 13021 and the second signal line 13022 intersect.

[0056] Specifically, for ease of explanation, this application takes four adjacent light-emitting areas LA in the row direction as an example. The first signal line 13021 and the microcircuit 13023 are located in the area of ​​the pixel driving circuit 1301 compressed along the column direction in the second light-emitting sub-area LA2. Between adjacent light-emitting areas LA in the row direction, adjacent first signal lines 13021 are connected in series with each other, and adjacent microcircuits 13023 are also connected in series with each other to form a path. Correspondingly, the second signal line 13022 intersecting with the first signal line 13021 is located in the area of ​​the pixel driving circuit 1301 compressed along the row direction in the second light-emitting sub-area LA2. Between adjacent light-emitting areas LA in the column direction (not shown in the figure), adjacent second signal lines 13022 are connected in series with each other to form a path. By placing the microcircuit 13023 uniformly on one side of the first light-emitting sub-region LA1 through the above design, the integration of the microcircuit 13023 can be improved and the design redundancy of the microcircuit 13023 can be reduced. Furthermore, by utilizing the first signal line 13021 and the second signal line 13022 placed in other spaces, the transmission distance of the circuit can be increased, which further helps to shorten the display bezel of the display panel 10.

[0057] In some other embodiments, the microcircuit 13023 may also be optionally disposed on multiple sides of the first light-emitting sub-region LA1.

[0058] Furthermore, the first signal line 13021 includes at least one of the following: a Data signal line, a Vref signal line, a CLK signal line, an In signal line, or a Demux signal line; the second signal line 13022 includes at least one of the following: a Data signal line, a Vref signal line, a CLK signal line, an In signal line, or a Demux signal line; and the microcircuit 13023 includes at least one of the following: an ESD circuit, a GIP circuit, or a Demux circuit.

[0059] Specifically, the Data signal line is the signal line for transmitting data signals of pixel unit 1201, the Vref signal line is the reference voltage signal line, the CLK signal line is the clock signal signal line, the In signal line is the start-up voltage signal line, and the Demux signal line is the transmission signal line of the Demux circuit. These signal lines are all placed in the bezel area BA in the prior art. In this application, these signal lines are placed within the second light-emitting sub-area LA2 as the first signal line 13021 and / or the second signal line 13022. The ESD circuit, GIP circuit, and Demux circuit are also placed in the bezel area BA as microcircuits 13023 in the prior art. In this application, these microcircuits 13023 can be placed within the second light-emitting sub-area LA2. Of course, the type and number of placements can be set according to actual conditions. Through the above design, the bezel of the display panel 10 can be reduced, and even bezel-less can be achieved.

[0060] Of course, it is understood that the first signal line 13021, the second signal line 13022, and the microcircuit 13023 of this application may be other signal lines or microcircuits in some other embodiments, and this application does not impose any restrictions.

[0061] Please continue to refer to this. Figure 6 The second signal line 13022 and the pixel driving circuit 1301 are distributed between the orthogonal projections of the shielding line 1303 on the substrate 110, and the shielding line 1303 is disposed on the same layer as the second signal line 13022.

[0062] Specifically, the orthogonal projection of the shielding line 1303 on the substrate 110 is located between the orthogonal projections of the second signal line 13022 and the pixel driving circuit 1301 on the substrate 110. This can provide good circuit shielding for the second signal line 13022 and the pixel driving circuit 1301. Furthermore, the shielding line 1303 can be fabricated together with the second signal line 13022, which reduces the fabrication cost.

[0063] Furthermore, between the orthographic projections of the pixel driving circuit 1301 and the microcircuit 13023 on the substrate 110, there is an orthographic projection of the shielding line 1303 on the substrate 110, and the shielding line 1303 is at least partially disposed on the same layer as the microcircuit 13023.

[0064] Specifically, the orthogonal projection of the shielding line 1303 on the substrate 110 is located between the orthogonal projections of the pixel driving circuit 1301 and the microcircuit 13023 on the substrate 110. This can provide good circuit shielding for the pixel driving circuit 1301 and the microcircuit 13023. Furthermore, the shielding line 1303 can be fabricated together with the microcircuit 13023, which reduces the fabrication cost.

[0065] Furthermore, between the orthographic projections of the pixel driving circuit 1301 and the first signal line 13021 on the substrate 110, there is an orthographic projection of the shielding line 1303 on the substrate 110, and the shielding line 1303 is disposed on the same layer as the first signal line 13021.

[0066] Specifically, the orthogonal projection of the shielding line 1303 on the substrate 110 is located between the orthogonal projections of the pixel driving circuit 1301 and the first signal line 13021 on the substrate 110. This can provide good circuit shielding for the pixel driving circuit 1301 and the first signal line 13021. Furthermore, the shielding line 1303 can be fabricated together with the first signal line 13021, which reduces the fabrication cost.

[0067] Furthermore, between the orthographic projections of the microcircuit 13023 and the first signal line 13021 on the substrate 110, there is an orthographic projection of the shielding line 1303 on the substrate 110, and the shielding line 1303 is disposed on the same layer as the first signal line 13021.

[0068] Specifically, the orthogonal projection of the shielding line 1303 on the substrate 110 is located between the orthogonal projections of the microcircuit 13023 and the first signal line 13021 on the substrate 110. This can provide good circuit shielding for the microcircuit 13023 and the first signal line 13021. Furthermore, the shielding line 1303 can be fabricated together with the first signal line 13021, which reduces the fabrication cost.

[0069] Please see Figure 2 and Figure 7 The driving layer 130 includes a first metal layer 131 and a second metal layer 132, which are stacked sequentially in a direction away from the substrate 110. At least a portion of the pixel driving circuit 1301, at least a portion of the microcircuit 13023, and a first signal line 13021 are formed in the first metal layer 131, and a second signal line 13022 is formed in the second metal layer 132. The second metal layer 132 further has a first connection line 1321 that electrically connects the pixel driving circuit 1301 and the pixel unit 1201.

[0070] Specifically, at least a portion of the pixel driving circuit 1301 and at least a portion of the microcircuit 13023 are located in the first metal layer 131. The first signal line 13021 is located in the first metal layer 131. The second metal layer 132 is close to the light-emitting layer 120 relative to the first metal layer 131. One end of the first connecting line 1321 in the second metal layer 132 is electrically connected to the pixel driving circuit 1301, and the other end is electrically connected to the pixel unit 1201. This ensures that the pixel driving circuit 1301 can drive the pixel unit 1201 normally.

[0071] In one embodiment, due to the compression of the pixel driving circuit 1301, there is a misalignment between the pixel unit 1201 and the corresponding pixel driving circuit 1301. Therefore, the length of the first connection line 1321 between each pixel unit 1201 and the corresponding pixel driving circuit 1301 is different. The first connection line 1321 closer to the second light-emitting sub-region LA2 is longer. Therefore, the longer the first connection line 1321 is, the wider it is appropriately, which reduces the transmission resistance to a certain extent and can improve the display uniformity of the entire display panel 10.

[0072] Further, see Figure 6 The second metal layer 132 is further formed with a second connection line 1322, which electrically connects the first signal line 13021 and the microcircuit 13023.

[0073] Specifically, a second connecting line 1322 is provided in the second metal layer 132. One end of the second connecting line 1322 is electrically connected to the first signal line 13021, and the other end is electrically connected to the microcircuit 13023, so that the first signal line 13021 and the microcircuit 13023 can be connected.

[0074] Of course, in some other embodiments, the first signal line 13021 and the microcircuit 13023 can also be directly electrically connected through a via.

[0075] Furthermore, in this embodiment, the first signal line 13021 and the pixel driving circuit 1301, and the pixel driving circuit 1301 and the microcircuit 13023 can also be electrically connected through connecting lines; the second signal line 13022 and the first signal line 13021, and the second signal line 13022 and the microcircuit 13023 can be directly electrically connected through vias.

[0076] Please see Figure 8 The display area AA is divided into multiple sub-display areas, and the light-emitting areas LA in the same sub-display area are distributed with the same type of microcircuit 13023.

[0077] Specifically, placing microcircuits 13023 of the same type in the same sub-display area can reduce signal interference between different types of microcircuits 13023.

[0078] Of course, in some other embodiments, various types of microcircuits 13023 can also be placed in the same sub-display area.

[0079] Furthermore, the multiple sub-display areas include at least a first sub-display area AA1, a second sub-display area AA2, a third sub-display area AA3, a fourth sub-display area AA4, and a fifth sub-display area AA5. The second sub-display area AA2, the third sub-display area AA3, the fourth sub-display area AA4, and the fifth sub-display area AA5 are arranged sequentially around the first sub-display area AA1. The second sub-display area AA2 and the fourth sub-display area AA4 are arranged opposite each other, and the third sub-display area AA3 and the fifth sub-display area AA5 are arranged opposite each other. Among them, the light-emitting area LA of the second sub-display area AA2 is equipped with ESD microcircuits, the light-emitting area LA of the third sub-display area AA3 is equipped with GIP microcircuits, the light-emitting area LA of the fourth sub-display area AA4 is equipped with Demux microcircuits, and the light-emitting area LA of the fifth sub-display area AA5 is equipped with GIP microcircuits.

[0080] Specifically, the design of the microcircuit 13023 in the aforementioned second sub-display area AA2, third sub-display area AA3, fourth sub-display area AA4, and fifth sub-display area AA5 is consistent with existing technologies. Figure 4 The difference lies in placing the microcircuit 13023 in the frame area BA to the corresponding light-emitting area LA according to the principle of proximity, which can reduce the complexity of design and process adjustment.

[0081] Of course, in other embodiments, the microcircuit 13023 can also be arranged in other ways, and this application does not impose any restrictions.

[0082] Further, please refer to Figure 2 , Figure 7 and Figure 8 The display panel 10 also includes a shielding layer 140 located between the light-emitting layer 120 and the driving layer 130. The shielding layer 140 is provided with a via 1401, and the pixel driving circuit 1301 is electrically connected to the pixel unit 1201 through the via 1401.

[0083] Specifically, the shielding layer 140 is provided with a via 1401, which serves as an electrical connection channel between the pixel driving circuit 1301 and the pixel unit 1201. The shielding layer 140 is not electrically connected to the pixel driving circuit 1301 and the pixel unit 1201. In this way, the shielding layer 140 can shield the electrical signals between the pixel unit 1201 and the peripheral circuit 1302, effectively blocking the interference of the peripheral circuit 1302 to the pixel unit 1201.

[0084] Of course, in some other embodiments, the shielding layer 140 may not be provided.

[0085] Furthermore, the shielding layer 140 has a fixed potential. This ensures effective shielding of signals between the pixel unit 1201 and the peripheral circuit 1302.

[0086] Furthermore, the shielding layer 140 is electrically connected to the VDD signal line, VSS signal line, VGH signal line, or VGL signal line. These signal lines are fixed-potential signal lines in the prior art; utilizing the signal lines in the prior art for the display panel 10 reduces manufacturing costs.

[0087] Please see Figure 9 The orthogonal projection of pixel unit 1201 on substrate 110 covers the orthogonal projection of via 1401 on substrate 110.

[0088] Specifically, the vias 1401 in the shielding layer 140 correspond one-to-one with the positions of the pixel units 1201. In this way, the shielding layer 140 in the area outside the pixel units 1201 can cover the uneven reflection caused by the uneven distribution of metal wiring in the driving layer 130 due to the design of various circuits. This design can improve the uneven reflection of the entire surface.

[0089] See Figure 2 The display panel 10 further includes a first planarization layer 150, which is located between the shielding layer 140 and the light-emitting layer 120.

[0090] Specifically, covering the shielding layer 140 with a first planarization layer 150 can planarize the unevenness of the film layers stacked below the shielding layer 140, eliminate the impact of unevenness on the pixel unit 1201, and improve the consistency of the display effect of the display panel 10.

[0091] Please see Figure 10 This application also provides a display device 400, which includes a display panel 410. The display panel 410 has the same structure as the display panel 10 in any of the above embodiments. For detailed structure, please refer to the above embodiments, which will not be repeated here.

[0092] Specifically, the display device 400 can be any electronic device such as a laptop, desktop computer, tablet computer, mobile phone, smartwatch, or virtual display terminal, without any restrictions.

[0093] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes a plurality of light-emitting areas, at least a portion of which include a first light-emitting sub-area and a second light-emitting sub-area located around the first light-emitting sub-area. The display panel includes: Substrate; A light-emitting layer, located on one side of the substrate, includes pixel units located in the light-emitting area; A driving layer, located between the substrate and the light-emitting layer, includes a pixel driving circuit located in the first light-emitting sub-region and electrically connected to the pixel unit, and a peripheral circuit located in the second light-emitting sub-region; The driving layer further includes a shielding line located in the second light-emitting sub-region, and the shielding line is distributed between the orthogonal projections of the pixel driving circuit and the peripheral circuit on the substrate.

2. The display panel according to claim 1, characterized in that, In the same light-emitting area, the orthogonal projection of the pixel driving circuit and the peripheral circuit onto the substrate covers the orthogonal projection of the pixel unit onto the substrate.

3. The display panel according to claim 2, characterized in that, The multiple light-emitting areas are arranged in an array in both the row and column directions.

4. The display panel according to claim 2, characterized in that, The light-emitting layer includes a plurality of pixel units located in the light-emitting area, and the driving layer includes a plurality of pixel driving circuits located in the light-emitting area. In the same light-emitting area, the plurality of pixel units are arranged only in the column direction, and the plurality of pixel driving circuits are arranged only in the column direction. At the same time, each sub-pixel unit in the pixel unit corresponds one-to-one with each sub-pixel driving circuit in the pixel driving circuit, and the sub-pixel unit is electrically connected to the corresponding sub-pixel driving circuit.

5. The display panel according to claim 1, characterized in that, The shielding wire has a fixed potential.

6. The display panel according to claim 5, characterized in that, The shielded wire is electrically connected to the VDD signal line, VSS signal line, VGH signal line, or VGL signal line.

7. The display panel according to claim 1, characterized in that, The peripheral circuit includes a first signal line, a second signal line, and a microcircuit. The first signal line and the microcircuit are located outside the first side of the first light-emitting sub-region, and the second signal line is located outside the second side of the first light-emitting sub-region. The first side and the second side are connected, and the extension directions of the first signal line and the second signal line intersect.

8. The display panel according to claim 7, characterized in that, The first signal line includes at least one of a Data signal line, a Vref signal line, a CLK signal line, an In signal line, or a Demux signal line; the second signal line includes at least one of a Data signal line, a Vref signal line, a CLK signal line, an In signal line, or a Demux signal line; and the microcircuit includes at least one of an ESD circuit, a GIP circuit, or a Demux circuit.

9. The display panel according to claim 7, characterized in that, The shielding line is distributed between the second signal line and the orthogonal projection of the pixel driving circuit on the substrate, and the shielding line is disposed on the same layer as the second signal line. And / or, the orthogonal projection of the shielding line on the substrate is distributed between the orthogonal projections of the pixel driving circuit and the microcircuit on the substrate, and the shielding line is disposed on the same layer as at least a portion of the microcircuit; And / or, the shielding line is distributed between the pixel driving circuit and the first signal line on the substrate, and the shielding line is disposed on the same layer as the first signal line. And / or, the shielding line is distributed between the orthogonal projection of the microcircuit and the first signal line on the substrate, and the shielding line is disposed on the same layer as the first signal line.

10. The display panel according to claim 7, characterized in that, The driving layer includes a first metal layer and a second metal layer, which are stacked sequentially in a direction away from the substrate. At least a portion of the pixel driving circuit, at least a portion of the microcircuit, and the first signal line are formed in the first metal layer, and the second signal line is formed in the second metal layer; The second metal layer is further formed with a first connection line, which electrically connects the pixel driving circuit and the pixel unit.

11. The display panel according to claim 10, characterized in that, The second metal layer is further formed with a second connection line, which electrically connects the first signal line to the microcircuit.

12. The display panel according to claim 7, characterized in that, The display area is divided into multiple sub-display areas, and the light-emitting areas in the same sub-display area are distributed with the same type of microcircuit.

13. The display panel according to claim 12, characterized in that, The plurality of sub-display areas includes at least a first sub-display area, a second sub-display area, a third sub-display area, a fourth sub-display area, and a fifth sub-display area. The second, third, fourth, and fifth sub-display areas are arranged sequentially around the first sub-display area. The second and fourth sub-display areas are arranged opposite to each other, and the third and fifth sub-display areas are arranged opposite to each other. ESD microcircuits are distributed in the light-emitting areas of the second sub-display area, GIP microcircuits are distributed in the light-emitting areas of the third sub-display area, Demux microcircuits are distributed in the light-emitting areas of the fourth sub-display area, and GIP microcircuits are distributed in the light-emitting areas of the fifth sub-display area.

14. The display panel according to claim 1, characterized in that, Further includes: A shielding layer is located between the light-emitting layer and the driving layer. The shielding layer has a via, and the pixel driving circuit is electrically connected to the pixel unit through the via.

15. The display panel according to claim 14, characterized in that, The shielding layer has a fixed potential.

16. The display panel according to claim 15, characterized in that, The shielding layer is electrically connected to the VDD signal line, VSS signal line, VGH signal line, or VGL signal line.

17. The display panel according to claim 14, characterized in that, The orthogonal projection of the pixel unit on the substrate covers the orthogonal projection of the via on the substrate.

18. The display panel according to claim 17, characterized in that, The display panel further includes a first planarization layer located between the shielding layer and the light-emitting layer.

19. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 18.

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