Switching circuit and power supply circuit

Abstract

A switching circuit and a power supply circuit capable of reducing power consumption are provided. A switching circuit (25) includes: an electric field effect switching element (M1) that can be switched between an on state and an off state in accordance with a potential (VC1) of a control terminal (TP1); and a control circuit (18a) that, when maintaining one of the on state and the off state of the switching element (M1), supplies a first level potential to the control terminal (TC1) that causes the switching element (M1) to be in the one state, and when changing the switching element (M1) from the one state to the other of the on state and the off state, charges or discharges the control terminal (node N1) via a resistor (M2, M3), then floats the control terminal (node N1), and supplies a second level potential that causes the switching element (M1) to be in the other state.

Description

Technical Field

[0001] This invention relates to switching circuits and power supply circuits. Background Technology

[0002] A power supply circuit is known to convert the voltage of electricity generated by an energy-generating element, such as an energy harvesting element, and store the electricity in an energy storage device, such as a capacitor. In such a power supply circuit, the switching of the voltage for converting the electricity is realized by a field-effect transistor (FET) and a control circuit that controls the gate voltage of the FET (e.g., Patent Document 1).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2014-33494 Summary of the Invention

[0006] The problem to be solved by the present invention

[0007] In Patent Document 1, a gate voltage for turning on the MOSFET (M1) is generated by resistive voltage division of the voltage between ground and the node between the power generation element and the MOSFET (M1) using resistors R2 and R3 (see Patent Document 1). Figure 1 However, during the period when the MOSFET (M1) is in the on state, current continues to flow through resistors R2 and R3, resulting in high power consumption. Therefore, the use of the power supply circuit of Patent Document 1 in circuits where low power consumption is desired (e.g., circuits using so-called energy harvesting elements as power supply elements) affects power consumption. This effect is not only observed in the circuit of Patent Document 1, but also in circuits with similar switching functions.

[0008] The present invention was made in view of the above-mentioned problems, and its object is to provide a switching circuit and a power supply circuit that can reduce power consumption.

[0009] Problem-solving methods

[0010] The present invention is a switching circuit comprising: a field-effect switching element configured to switch between an on state and an off state according to the potential of a control terminal; and a control circuit configured to provide a first level potential to the control terminal when the switching element is held in one of the on state and the off state, and to float the control terminal after charging or discharging it via a resistor when the switching element is switched from one state to the other state, and to provide a second level potential to the control terminal, wherein the first level causes the switching element to enter one state and the second level causes the switching element to enter the other state.

[0011] In the above configuration, a configuration in which the control circuit floats the control terminal when it provides a first-level potential to the control terminal can be adopted.

[0012] In the above configuration, a configuration in which the switching element is an element that turns on and off the electromotive force provided by the power generating element can be adopted.

[0013] In the above configuration, a configuration in which the switching element is a power supply element to the sensor circuit can be adopted.

[0014] In the above configuration, a holding circuit configured to maintain the potential of the control terminal within a predetermined range can be used.

[0015] In the above configuration, a configuration in which the holding circuit includes a diode connected to the control terminal can be adopted.

[0016] In the above configuration, the following configuration can be adopted: the switching element is a first FET, which has a source connected to a first terminal, a drain connected to a second terminal, and a gate connected to a first node capacitively connected to a first control terminal.

[0017] In the above configuration, the following configuration can be adopted: a second FET is provided having a source connected to a first node, a drain connected to a first terminal, and a gate, wherein one state is a turn-off state, and when the control circuit switches the first FET from a turn-off state to a turn-on state, the state between the source and drain of the second FET is switched to a turn-off state to connect the first node to a reference potential via a resistor, and then the first node is disconnected from the first terminal and the reference potential and a second level potential is provided to the first control terminal.

[0018] In the above configuration, the following configuration can be adopted: a third FET is provided having a source connected to a reference potential, a drain connected to a first node, and a gate, and the resistor is a resistor between the source and drain of the third FET, and when the first node is connected to the reference potential via a second FET, a saturation current flows through the third FET.

[0019] In the above configuration, the following configuration can be adopted: a forward-biased rectifier element is provided from the first node to the second node capacitively connected to the second control terminal, the second FET is N-type and the gate of the second FET is connected to the second node, the first FET is P-type, and the first node is connected to the reference potential via the rectifier element, the second node and a resistor.

[0020] In the above configuration, the following configuration can be adopted: a rectifier element with a positive direction from a second node capacitively connected to a second control terminal to a first node is provided, the second FET is P-type and connected to the second node capacitively connected to the second control terminal, the first FET is N-type, and the first node is connected to a reference potential via the rectifier element, the second node, and a resistor.

[0021] In the above configuration, the control circuit can be configured such that when the first FET is held in the on state, it provides a second level potential to the first control terminal and a third level potential to the second control terminal, and when the first FET switches from the on state to the off state, it provides a fourth level potential to the second control terminal, then provides a first level potential to the first control terminal and a third level potential to the second control terminal, the third level potential causes the second FET to enter the off state, and the fourth level potential causes the second FET to enter the on state.

[0022] In the above configuration, the control circuit can be configured such that when the first FET is switched from the on state to the off state, it provides a third-level potential to the second control terminal and then provides a first-level potential to the first control terminal.

[0023] In the above configuration, the following configuration can be adopted: a determining circuit is provided, which is configured to determine, when the first FET is held in the off state, whether the input voltage input to the first terminal has changed from the input voltage when the first FET was switched from the on state to the off state by a predetermined voltage, and when the control circuit determines that the input voltage has changed by the predetermined voltage, provide a second level to the first control terminal and a fourth level to the second control terminal, and then provide a first level to the first control terminal and a third level to the second control terminal.

[0024] In the above configuration, the following configuration can be provided: the determining circuit includes a comparator configured to compare the voltage at a third node capacitively connected to the first terminal with a constant voltage, and output the comparison result to the control circuit.

[0025] In the above configuration, a configuration in which the input voltage to the first terminal is higher than the reference potential and the first FET is a PFET can be used.

[0026] In the above configuration, a configuration in which the input voltage to the first terminal is lower than the reference potential and the first FET is an NFET can be used.

[0027] In the above configuration, a configuration in which the power generating element is a vibration power generating element can be adopted.

[0028] The present invention is a power supply circuit including the above-described switching circuit.

[0029] Invention Effects

[0030] This invention can provide a switching circuit and a power supply circuit that can reduce power consumption. Attached Figure Description

[0031] [ Figure 1 ] Figure 1 This is an example of the use of Figure 3 The circuit diagram of the first embodiment of the power supply circuit of the switching circuit is illustrated in detail.

[0032] [ Figure 2 ] Figure 2 This is an example of the structure. Figure 1 The diagram shows the timing of the switching on / off of the voltage conversion circuit and the current IL flowing through the inductor.

[0033] [ Figure 3 ] Figure 3 This is a detailed circuit diagram of the switching circuit constituting the power supply circuit of the first embodiment, and is an example. Figure 1 The circuit diagram shows the details of the switch and its control circuit, which is represented as HSW.

[0034] [ Figure 4 ] Figure 4 This is an example Figure 3 The diagram shows the timing of voltage and on / off states in the switching circuit over time.

[0035] [ Figure 5 ] Figure 5 This is a detailed circuit diagram of the switching circuit constituting the power supply circuit of the second embodiment, and is an example. Figure 1 The circuit diagram shows the details of the switch and its control circuit, which is represented as HSW.

[0036] [ Figure 6 ] Figure 6 This is an example Figure 5 The diagram shows the timing of voltage and on / off states in the switching circuit over time.

[0037] [ Figure 7 ] Figure 7 This is a detailed circuit diagram of the switching circuit constituting the power supply circuit according to the third embodiment, and is an example. Figure 1 The circuit diagram shows the details of the switch and its control circuit, which is represented as HSW.

[0038] [ Figure 8 ] Figure 8 This is an example Figure 7 The timing diagram shows the changes in voltage, current, and on / off state over time in the switching circuit shown.

[0039] [ Figure 9 ] Figure 9 This is a detailed circuit diagram of the switching circuit constituting the power supply circuit according to the fourth embodiment, and is an example. Figure 1 The circuit diagram shows the details of the switch and its control circuit, which is represented as HSW.

[0040] [ Figure 10 ] Figure 10 (a) is a block diagram illustrating an embodiment of the power supply circuit of the present invention, wherein a switching circuit according to any one of the first to fourth embodiments and their variations is used in the voltage conversion circuit 64 of the power supply circuit, and Figure 10 (b) is a block diagram illustrating a sensor circuit system that uses a switching circuit according to any one of the first to fourth embodiments and variations thereof. Detailed Implementation

[0041] In the following description, embodiments will be described with reference to the accompanying drawings.

[0042] First Implementation Method

[0043] Figure 1 This is an example of the use of Figure 3 The circuit diagram of the first embodiment of the power supply circuit for the switching circuit is illustrated in detail below. Figure 1 In this circuit, the output current of the power generating element 10 is input to the input terminal Tin of the voltage conversion circuit 12. When a power generating element with an output current of alternating current is used as the power generating element 10, the output current of the power generating element 10 is rectified by the rectifier circuit 11 and input to the input terminal Tin.

[0044] The power generating element 10 is, for example, an energy harvesting element such as a vibration power generating element. The vibration power generating element is, for example, a piezoelectric element using piezoelectric materials or a MEMS element using microelectromechanical systems (MEMS). The vibration power generating element is installed, for example, on roads, bridges, etc., and generates electricity through vibrations caused by passing pedestrians or vehicles. When a vibration power generating element is used as the power generating element 10, the generated electricity is AC micro-electricity and varies with the state of vibration. When a piezoelectric element is used, its output voltage is typically relatively higher than the several volts required for electronic circuit operation. In the first embodiment, due to the rectifier circuit 11, the input to the input terminal Tin is positive relative to ground.

[0045] Nodes N01 to N04 are provided between the input terminal Tin and the output terminal Tout of the voltage conversion circuit 12. In this embodiment, the voltage conversion circuit 12 steps down the relatively high voltage from the power generation element 10 and outputs the stepped-down voltage to the output terminal Tout. The switch HSW is a high-side switch provided on the high-voltage side (referred to as the high side) of the voltage conversion circuit 12. Terminal Tsw1, which is one end of the switch HSW, is connected to node N01, and terminal Tsw2, which is the other end, is connected to node N02. One end of the inductor L1 is connected to node N02, and the other end is connected to node N03. One end of the switch SW3 is connected to node N03, and the other end is connected to node N04. One end of the capacitor C01 on the primary side of the voltage conversion circuit 12 is connected to node N01, and the other end is connected to ground (reference potential). One end of the capacitor C02 on the secondary side of the voltage conversion circuit 12 is connected to node N04, and the other end is connected to ground. One end of the switch SW1 is connected to node N02, and the other end is connected to ground. One end of switch SW2 is connected to node N03, and the other end is connected to ground.

[0046] Control unit 14 outputs control signals Sh and S1 to S3 to switches HSW and SW1 to SW3, respectively. Switches HSW and SW1 to SW3 are turned on or off based on control signals Sh and S1 to S3, respectively. In this embodiment, control unit 14 generates control signal Sh with a constant period. The frequency of control signal Sh is sufficiently higher than the frequency of the AC component included in the electromotive force output from power generating element 10 and rectifier circuit 11. The frequency of control signal Sh is taken into account to perform impedance matching for efficiently transmitting the electromotive force output from power generating element 10 and rectifier circuit 11 to voltage conversion circuit 12. Control unit 14 can detect voltages Vin and Vout and output control signals Sh and S1 to S3 based on voltages Vin and Vout.

[0047] When a positive current relative to ground is input from the power generating element 10 to the input terminal Tin via the rectifier circuit 11, capacitor C01 is charged. The potential of capacitor C01 at node N01 relative to ground is called the input voltage Vin. Through the operation of the voltage conversion circuit 12, namely the operation of switches HSW and SW1, SW2, and SW3 in the voltage conversion circuit 12 (which will be described later), the charge of capacitor C01 is transferred to capacitor C02. The potential of capacitor C02 at node N04 relative to ground is called the voltage Vout.

[0048] Figure 2 This is an example of the structure. Figure 1 The diagram shows the timing of the switching on / off of the voltage conversion circuit and the current IL flowing through the inductor. Figure 2 The value of the input voltage Vin is given. Figure 1 The values ​​of the on and off states of each switch, the current IL flowing through inductor L1, and the output voltage Vout are shown. Figure 2 The time t00 is a specific timing during the operation of the power supply circuit, and at time t00, the current from the power generating element 10 is stored in capacitor C01, whose voltage Vin is voltage Vin1. Through the voltage conversion operation described later, charge is also stored in capacitor C02, whose voltage Vout is voltage Vout1. At time t00, the control unit 14 keeps switches HSW and SW1 to SW3 in the off state.

[0049] After the charge stored in capacitor C01 increases due to the current generated by power generating element 10 and the voltage Vin exceeds a predetermined threshold voltage, control unit 14 turns on switches HSW and SW2 at time t01 and keeps switches SW1 and SW3 off. As a result, current IL begins to flow from capacitor C01 through node N01, switch HSW, inductor L1, and switch SW2 to ground. Control unit 14 can detect the voltage Vin at input terminal Tin and turn on switches HSW and SW2 when the voltage Vin exceeds the predetermined threshold voltage, or turn on switches HSW and SW2 at predetermined intervals. Between time t01 and time t02, as the charge in capacitor C01 is released, current IL gradually increases and voltage Vin gradually decreases. Magnetic field energy is stored in inductor L1.

[0050] At time t02, voltage Vin changes to voltage Vin2. Voltage Vout is voltage Vout1. When current IL changes to IL1 at time t02, control unit 14 turns off switches HSW and SW2 and turns on switches SW1 and SW3. Control unit 14 can detect the voltage Vin at input terminal Tin and turn off switches HSW and SW2 and turn on switches SW1 and SW3 when voltage Vin changes to Vin2, or it can turn off switches HSW and SW2 and turn on switches SW1 and SW3 at predetermined intervals. Between time t02 and time t03, due to the magnetic field energy stored in inductor L1, current IL flows from ground through switch SW1, inductor L1, and switch SW3, and voltage Vout increases as capacitor C02 is charged.

[0051] At time t03, control unit 14 turns off switches SW1 and SW3, and keeps switches HSW and SW2 off. Control unit 14 can detect the voltage Vout at the output terminal Tout, and turn off switches SW1 and SW3 when the voltage Vout reaches a predetermined threshold voltage, or it can turn off switches SW1 and SW3 at predetermined intervals. After time t03, the current IL is 0, the voltage Vin is Vin2, and the voltage Vout is Vout2. Voltages Vout1 and Vout2 can be lower or higher than voltages Vin1 and Vin2. Voltages Vout1 and Vout2 can be set by appropriately setting the capacitance values ​​of capacitors C01 and C02 and the on / off timing of switches HSW and SW1 to SW3.

[0052] Figure 3 This is a detailed circuit diagram of the switching circuit constituting the power supply circuit of the first embodiment, and is an example. Figure 1 The diagram below shows the details of the HSW switch and its control circuitry. In the following text, a FET with a P-type channel conductivity is referred to as a PFET, and a FET with an N-type channel conductivity is referred to as an NFET. The on / off state of PFET M1 corresponds to the on / off state of the HSW switch. Figure 3As shown, in the switching circuit 25 of the first embodiment, the source of PFET M1 (first FET) is connected to terminal Tsw1 (second terminal), the drain is connected to terminal Tsw2 (second terminal), and the gate is connected to node N1 (first node). One end of capacitor C1 (first capacitor) is input with control signal VC1 (first control signal), and the other end is connected to node N1. That is, the gate is capacitively connected to control terminal TC1 (first control terminal). The source of NFET M2 (second FET) is connected to node N1, the drain is connected to terminal Tsw1, and the gate is connected to control terminal TC2, which is input with control signal VC2, via capacitor C2 (second capacitor). The source of NFET M3 (third FET) is connected to ground (reference potential), the drain is connected to node N1, and the gate is connected to control terminal TC3, which is input with control signal VC3. Figure 1 The control signal Sh output by the control unit 14 is input to the control circuit 18a. The control circuit 18a controls the state of PFET M1, NFET M2 and NFET M3 by changing the levels of control signals VC1, VC2 and VC3 based on the timing of the control signal Sh.

[0053] Figure 4 This is an example Figure 3 The timing diagram shows the voltage and on / off state of the switching circuit as a function of time. Figure 4 As shown, control circuit 18a sets control signal VC1 to a high level H (voltage X), control signal VC2 to a high level H, and control signal VC3 to a low level L between time t10 and time t11. Time t10 to time t11 is the period during which switch HSW is kept off. Since NFET M2 is in the on state, voltage G1 is voltage Vin, and PFET M1 is in the off state.

[0054] Figure 1 The control unit 14 detects the voltage Vin at the input terminal Tin, and... Figure 2When the voltage Vin exceeds a predetermined threshold voltage at time t01, an indication to switch HSW from the off state to the on state is output as a control signal Sh. Control unit 14 can output the control signal Sh at predetermined intervals to switch HSW from the off state to the on state. When the control signal Sh issues the instruction to switch HSW from the off state to the on state, control circuit 18a performs the operation of switching PFET M1 from the off state to the on state between time t11 and time t13. At time t11, control circuit 18a sets control signal VC2 to a low level L, sets control signal VC3 to a high level H, and holds control signal VC1 at a high level H. As a result, NFET M2 is turned off, and NFET M3 is turned on. Current Im3 flows from node N1 to ground. When the voltage difference between node N1 and ground is in the saturation region (drain current saturation region) of NFET M3, the current Im3 is essentially constant and independent of the voltage difference between node N1 and ground. Therefore, in Figure 4 Between time t11 and time t12, the voltage G1 at node N1 gradually decreases due to the current Im3.

[0055] When it is determined that a predetermined time period has elapsed since time t11, control circuit 18a sets control signal VC3 to low level L, holds control signal VC1 at high level H, and holds control signal VC2 at low level L at time t12. NFET M3 is turned off. Between time t12 and time t13, voltage G1 is essentially constant. When it is determined that a predetermined time period has elapsed since time t12, control circuit 18a sets control signal VC1 to low level L, holds control signal VC3 at low level L, and holds control signal VC2 at low level L at time t13. As a result, voltage G1 drops from voltage Vin by voltage difference X (the difference between the high level H and low level L of control signal VC1) and becomes voltage Vin-X. PFET M1 is turned on. Due to the current IP flowing through... Figure 1 The inductor L1 in the circuit causes the current IP to gradually increase after time t12. Therefore, while PFET M1 remains on, NFET M2 is off. After time t12, node N1 is in a floating state. However, if the time interval between time t12 and time t13 is short, such as about a few microseconds, fluctuations in voltage G1 will not cause significant problems. To set voltage G1 to voltage Vin-X, the timing of setting control signal VC1 to low level L is preferably after the timing of setting control signal VC3 to low level L.

[0056] As described above, in the first embodiment, when PFET M1 is turned on from the off state, the control circuit 18a charges or discharges node N1 through the resistor (NFET M3). Thereafter, node N1 is floated (time t12), and after a predetermined time, the control signal VC1 is set to a low level L (a second level that turns on PFET M1) (time t13). This turns on PFET M1. Although current flows through NFET M3 between time t11 and time t12, the potential of node N1 is floated because NFET M3 is in the off state after time t13. Therefore, no current flows between terminal Tsw1 and ground. Thus, unlike in Patent Document 1, when current flows through MOSFET (M1) (see Patent Document 1), the current does not flow through the resistor (NFET M3). Figure 1 Compared to the case where current continuously flows through resistors R2 and R3 during the on-state period, power consumption can be reduced.

[0057] When control circuit 18a changes the state of PFET M1 from the off state to the on state, control circuit 18a turns off NFET M2, disconnecting node N1 from terminal Tsw1 (time t11), and then connects node N1 to ground through NFET M3 (between time t11 and time t12). Afterwards, control circuit 18a disconnects node N1 from ground (time t12) and provides a low level L to control terminal TC1 (time t13). As a result, voltage G1 can be stably set to voltage Vin-X by the decrease in voltage G1 due to the capacitive connection of capacitor C1 and the decrease in voltage G1 due to the current Im3 of NFET M3. Therefore, PFET M1 can stably switch from the off state to the on state. This allows voltage conversion circuit 12 to operate stably when it is needed, thereby improving conversion efficiency.

[0058] Here, in this embodiment, the PFET can be used as a third FET corresponding to the NFET M3. To use the PFET as the third FET, the control signal VC3 for turning on the first switch is set to voltage G1-X. Since voltage G1... Figure 4The curve shows the change, thus providing a generation circuit for generating a control signal VC3 that follows the change of voltage G1. On the other hand, when using an NFET as a third FET corresponding to NFET M3, it is only necessary to set the control signal VC3 to a constant voltage (high level H) relative to ground when the third FET is turned on, and the control signal VC3 can be easily generated. Therefore, the first switch can be stably turned on at a predetermined timing. When an NFET is used for the first switch, the above generation circuit is not required compared to the case of using a PFET, and the power consumption of the generation circuit does not increase the power consumption of the entire power supply circuit. When an NFET is used for the third FET, the control circuit 18a is configured to output the control signal VC3 when the control signal VC3 is at a high level H (first level), and the voltage value of the control signal VC3 is set such that the saturation current flows between the source and drain of NFET M3. This configuration allows the current Im3 to be constant independently of the voltage difference between node N1 and ground. Therefore, by setting the interval between time t11 and time t12, the voltage G1 at time t12 can be made to decrease substantially from the voltage G1 at time t11, independent of the voltage value of Vin. Thus, the voltage G1 at time t13 can be set to be substantially Vin-X, independent of the voltage value of Vin. Therefore, PFET M1 can stably switch from the off state to the on state. This allows the voltage conversion circuit 12 to operate when needed, thereby improving conversion efficiency.

[0059] In this embodiment, the PFET can be used as a second FET corresponding to the NFET M2. To use the PFET as the second FET, a generation circuit is provided to generate a voltage Vin-X as a control signal VC2 for turning on the second FET. On the other hand, when the NFET is used as the second switch corresponding to the NFET M2, it is only necessary to set the control signal VC2 to voltage G1 or a constant voltage relative to ground (high level H) when the second FET is turned on, and the control signal VC2 can be easily generated. Therefore, the second FET can be stably turned on at a predetermined timing. When the NFET is used as the second FET, compared to using a PFET, the aforementioned generation circuit is not required, and the power consumption of the generation circuit does not increase the power consumption of the entire power supply circuit.

[0060] In the first embodiment described above, Figure 3 The PFET M1 is the first FET, which has a first terminal Tsw1 connected to the power generating element 10, a second terminal Tsw2, a source connected to the first terminal Tsw1, a drain connected to the second terminal Tsw2, and a gate connected to the first node N1 capacitively connected to the first control terminal TC1.

[0061] When the first FET M1 is held in one of the states of cutoff and on, the control circuit provides a first level to the first control terminal TC1 to cause the first FET M1 to enter the state of cutoff, and charges or discharges the first node N1 through a resistor, and then floats the first node N1. When the state of the first FET M1 is changed from the state of cutoff to the state of on, the control circuit provides a second level to the first control terminal TC1 to cause the first FET M1 to enter the other state. The control circuit is composed of NFET M2 and NFET M3, and the control circuit 18a provides VC1, VC2 and VC3.

[0062] In this embodiment, the control signal Sh has a constant period, and its frequency is sufficiently higher than the frequency of the AC component included in the electromotive force output from the power generating element 10 and the rectifier circuit 11. However, the power consumption of FETs M1 to M3 increases proportionally with the increase in the frequency of the control signal Sh. Therefore, in order to transfer the power generated by the power generating element 10 to the capacitor CO2 in the subsequent stage as efficiently as possible, the frequency of the control signal Sh is preferably low.

[0063] Although the control signal Sh is generated with a constant period in the first embodiment described above, it can also be generated when the comparator detects that the voltage of the secondary-side capacitor C02 (node ​​N04) has reached a predetermined voltage required to drive the load, instead of a constant period. Alternatively, the control signal Sh can be generated when the comparator detects that the voltage of the primary-side capacitor C01 (node ​​N01) has reached a predetermined voltage. Figure 4 In the middle, after switch SW5 is turned off, control signal VC3 can become high level H.

[0064] In a first variation of the first embodiment, control terminal TC2 and NFET M2 are capacitively connected to each other. As a result, when control circuit 18a switches control signal VC2 from low level L to high level H, the gate voltage G2 of NFET M2 becomes high level H. This turns on NFET M2. However, since the gate of NFET M2 is floating, voltage G2 is unstable.

[0065] Second Implementation Method

[0066] In the first embodiment, depending on circuit constants such as the period during which the control signal VC1 switches between high and low levels or the saturation current value between the source and drain of NFET M3, there may be a situation where voltage G2 is unstable during a specific period when the gate of NFET M2 is floating. In this case, there is a possibility that the operation of the switch HSW (PFET M1) is unstable and the power supply circuit as a whole does not exhibit the desired performance. In the second embodiment, a switching circuit that performs the desired performance as a power supply circuit even under these circumstances will be described.

[0067] Figure 5 This is a detailed circuit diagram of the switching circuit constituting the power supply circuit of the second embodiment, and is an example. Figure 1 The diagram shows the details of the HSW switch and its control circuit. Figure 5 As shown, in the switching circuit 26 of the second embodiment, the control signal VC2 is input to one end of capacitor C2 (the second capacitor), and its other end is connected to node N2 (the second node). The anode of diode D (rectifier element) is connected to node N1, and the cathode is connected to node N2 between NFET M2 and capacitor C2. The direction from node N1 to node N2 is positive. The drain of NFET M3 is connected to node N1 via node N2 and diode D. The source of NFET M2 (the second FET) is connected to node N1, the drain is connected to terminal Tsw1, and the gate is capacitively connected to node N1, which is connected to control terminal TC2 (the second control terminal). Other configurations of the power supply circuit are the same as those in the first embodiment, and their description is omitted.

[0068] Figure 6 This is an example Figure 5 The timing diagram shows the voltage and on / off state of the switching circuit as a function of time. Figure 6 As shown, control circuit 18b sets control signal VC1 to a high level H (voltage X), control signal VC2 to a low level L, and control signal VC3 to a low level L between the time t10 and time t11 when switch HSW remains in the off state. In the same state as after time t16, voltage G1 is set to voltage Vin. Voltage G2 is voltage Vin - ΔV. ΔV is the forward voltage drop of diode D.

[0069] When the control signal Sh indicates that the switch HSW is switching from the off state to the on state, the control circuit 18b performs the operation of switching the PFET M1 from the off state to the on state between time t11 and time t13. At time t11, the control circuit 18b raises the control signal VC3 to a high level H, while keeping the control signals VC1 and VC2 at a high level H and a low level L, respectively. As a result, the NFET M3 is turned on, and the current Im3 flows from nodes N2 and N1 to ground. Between time t11 and time t12, the voltage G2 drops due to the current Im3, and the current flows from node N1 through diode D to node N2, thereby causing the voltage G1 to drop.

[0070] At time t12, control circuit 18b sets control signal VC3 to low level L and holds control signals VC1 and VC2 at high level H and low level L, respectively. NFET M3 is turned off. Voltage G2 becomes VG2. Voltage G1 becomes VG2 + ΔV. Between time t12 and time t13, voltage G1 remains substantially constant. At time t13, control circuit 18b sets control signal VC1 to low level L and holds control signals VC2 and VC3 at low level L. As a result, voltage G1 becomes voltage Vin-X. PFET M1 is turned on and current IP flows. Between time t13 and time t14, when switch HSW remains on, control circuit 18b sets control signals VC1 to VC3 to low level L.

[0071] Figure 1 The control unit 14 detects the voltage Vin at the input terminal Tin, and... Figure 2 When the voltage Vin reaches a predetermined voltage at time t02, an instruction as a control signal Sh is output to switch the switch HSW from the ON state to the OFF state. Control unit 14 can output the control signal Sh at predetermined intervals to switch the switch HSW from the ON state to the OFF state. When the control signal Sh instructs the switch HSW to switch from the ON state to the OFF state, control circuit 18b performs the operation of switching PFET M1 from the ON state to the OFF state between time t14 and time t16. At time t14, control circuit 18b sets control signal VC2 to a high level H and holds control signals VC1 and VC3 at a low level L. Between time t14 and time t15, the voltage G2 of node N2, which is capacitively connected to control terminal TC2, rises. Since NFET M2 is turned on, voltage G1 gradually increases. When voltage G1 becomes equal to or greater than the threshold voltage of PFET M1, PFET M1 is turned off and the current IP becomes 0. When the voltage G1 becomes equal to or greater than the threshold voltage of PFET M1 later than time t14, PFET M1 is turned on later than time t14.

[0072] At time t15, control circuit 18b sets control signal VC2 to low level L and holds control signals VC1 and VC3 at low level L. Voltage G2 drops. When voltage G2 becomes lower than voltage G1-ΔV, current flows from node N1 through diode D to node N2. As a result, voltage G1 decreases slightly, voltage G2 increases slightly, and voltages G1 and G2 become balanced.

[0073] At time t16, control circuit 18b sets control signal VC1 to a high level H and holds control signals VC2 and VC3 at a low level L. The voltage G1 at node N1, capacitively connected to control terminal TC1, increases. Current flows from node N1 through diode D to node N2, and voltage G2 rises. Since NFET M2 is fully turned on, voltage G1 becomes voltage Vin. Voltage G2 becomes voltage Vin-ΔV. Since voltage G2 stabilizes, voltage G1 stabilizes, and PFET M1 is stabilized in the off state.

[0074] In the second embodiment, in addition to charging or discharging node N2 via a resistor (i.e., the resistor between the source and drain of NFET M2) when the state of PFET M1 changes from the off state to the on state (between time t14 and time t15), the control circuit 18b also charges or discharges node N2 when the state of PFET M1 changes from the on state to the off state. Thereafter, the control circuit 18b floats node N2 (at time t15) and provides a low level L to the control terminal TC2 (at time t16). As described above, in the second embodiment, when PFET M1 remains in either the off state or the on state, the control circuit 18b provides a first level (the level that causes PFET M1 to enter either the off state or the on state) to the control terminal TC1. When the state of PFET M1 changes from one of the off and on states to the other of the off and on states, the control circuit 18b charges or discharges node N1 via a resistor (between times t11 and t12, and between times t14 and t15). Afterward, the control circuit 18b floats node N1 (at times t12 and t15) and provides a second level (the level that causes PFET M1 to enter the other of the off and on states) to the control terminal TC1 (at times t13 and t16).

[0075] As described above, PFET M1 (the switching element) is an electric field-controlled switching element that switches between an on-state and an off-state based on the potential (voltage G1) of the gate, which serves as the control terminal. When PFET M1 is in its current state, the control circuit 18b provides the gate with a first-level potential that causes PFET M1 to enter one of the off-state or on-state. When the state of PFET M1 changes from one of the on-state to the other, the gate is charged or discharged through a resistor, then floated, and a second-level potential that causes PFET M1 to enter the other state is provided. Therefore, when PFET M1 is held in the on-state or off-state, node N1 is floated, thereby reducing power consumption.

[0076] In the second embodiment, capacitor C2, diode D, and NFET M2 are provided as a holding circuit to maintain voltage G1 within a predetermined range. Therefore, when PFET M1 switches from the off state to the on state, if NFET M3 is turned on from time t11 to time t12, current flows from node N1 to ground via diode D and node N2, thereby reducing voltages G1 and G2. Therefore, regardless of the voltage value of Vin, NFET M2 can switch from the on state to the off state, and PFET M1 can switch from the off state to the on state.

[0077] When PFET M1 remains on during times t13 and t14, control circuit 18b provides a low level L (second level) to control terminal TC1 and a low level L (third level that turns NFET M3 off) to control terminal TC2. When control circuit 18b changes the state of PFET M1 from on to off from time t14 to time t16, control circuit PFET M1 provides a high level H (fourth level that turns NFET M3 on) to control terminal TC2, then provides a low level (third level) to control terminal TC2, and then provides a high level H (first level) to control terminal TC1. When control signal VC2 becomes high level H and voltage G2 rises, NFET M2 is turned on to increase voltages G1 and G2. Thereafter, by setting control signal VC1 to high level H, voltage G1 can be further increased. This allows voltage G1 to stabilize at voltage Vin, and voltage G2 to stabilize at Vin-ΔV.

[0078] When the state of PFET M1 is changed from the on state to the off state, the control circuit 18b provides a low level L (third level) to the control terminal TC2 at time t15, and then provides a high level H (first level) to the control terminal TC1 at time t16 after a predetermined time period. Therefore, after the transient response of the voltage G2 via capacitor C2 stabilizes, the high level H (second level) can be provided to the control terminal TC1. Thus, voltages G1 and G2 become more stable. Therefore, when PFET M1 switches from the on state to the off state, PFET M1 can switch to the off state stably. Therefore, unwanted current can be prevented from flowing through the voltage conversion circuit 12, and the conversion efficiency in the voltage conversion circuit 12 can be improved.

[0079] The high level H of control signal VC2 is, for example, 2V, and the high level H of control signal VC1 is, for example, 1V. As described above, the high level H of control signal VC2 is preferably higher than the high level H of control signal VC1. This configuration allows voltage G2 to increase further between time t14 and time t15. As a result, PFET M1 can be turned off more stably, thereby improving the conversion efficiency in voltage conversion circuit 12.

[0080] Third Implementation Method

[0081] Figure 7 This is a detailed circuit diagram of the switching circuit constituting the power supply circuit according to the third embodiment, and is an example. Figure 1 The circuit diagram shown below details the switch and its control circuit, denoted as HSW. In the first and second embodiments, the control signal Sh has a constant period, and its frequency is sufficiently higher than the frequency of the AC component included in the electromotive force output from the power generating element 10 and the rectifier circuit 11. The power consumption of FETs M1 to M3 increases proportionally with the increase in the frequency of the control signal Sh. Therefore, in order to transfer the power generated in the power generating element 10 to the capacitor CO2 in the subsequent stage as efficiently as possible, the frequency of the control signal Sh is preferably low. However, during periods when the electromotive force of the power generating element 10 is large and the switch HSW is in the off state, i.e., during periods when the voltage that does not cause current to flow between the source and drain of FET M1 is set in node N1 to provide voltage in the floating state, when the voltage Vin rises significantly (e.g., rises by 0.3V or more) and becomes the voltage that causes a microcurrent to flow between the source and drain of FET M1, the charge of capacitor C01 and the microcurrent do not contribute to the voltage conversion, and the voltage conversion efficiency may decrease.

[0082] Given this possibility, in order to further improve voltage conversion efficiency, such as Figure 7 As shown, in the switching circuit 27 of the third embodiment, the determining circuit 15 includes a comparator 16, an NFET M4, and a capacitor C3, and outputs a reset signal Vr to the control circuit 18c when the voltage Vin changes to Vref or greater. Similar to the control signal Sh in the second embodiment, this reset signal Vr resets the gate potential of the PFET M1 to the same potential as the voltage Vin. Figure 7 In the circuit, one end of capacitor C3 is connected to node N4, between the source of PFET M1 and terminal Tsw1, and the other end is connected to node N3 (the third node). That is, node N3 is capacitively connected to terminal Tsw1. The source of NFET M4 is connected to ground, its drain is connected to node N3, and its gate is connected to the control terminal TC4, which receives the input control signal VC4. Comparator 16 has a positive input terminal connected to node N3, a negative input terminal receiving the input reference voltage Vref, and an output terminal outputting a reset signal Vr. Comparator 16 outputs a high level H as the reset signal Vr when the voltage Vm at node N3 is equal to or higher than the reference voltage Vref, and outputs a low level L as the reset signal Vr when the voltage Vm is lower than the reference voltage Vref. The reference voltage Vref is, for example, 0.3V.

[0083] The control signal Sh output from the control unit 14 and the reset signal Vr output from the comparator 16 are input to the control circuit 18c. The control circuit 18c outputs control signals VC1 to VC4 based on the control signal Sh and the reset signal Vr. Other configurations are the same as those in the second embodiment, and their description will be omitted.

[0084] Figure 8 This is an example Figure 7 The diagram shows the timing of voltage, current, and on / off states over time in the switching circuit. Figure 8 As shown, the input current Iin from the rectifier circuit 11 to terminal Tsw1 varies according to the amount of power generated by the power generating element 10. However, here, the input current Iin is set to a very small Iin1 until time t20, and is set to Iin2 after time t20. In this timing diagram, the current Iin1 has almost no effect on the voltage Vin, etc. Therefore, the voltage Vin is basically constant from time t10 to time t13 and from time t14 to time t20. Between time t13 and time t14, charge moves from capacitor C1 to capacitor C2, thereby slightly reducing the voltage Vin. Other variations of control signals VC1 to VC3, voltages G1 and G2, and current Ip between time t10 and time t16 are consistent with those in the second embodiment. Figure 6The same applies, and its description will be omitted. Since NFET M4 is turned on at a predetermined timing, as described later, the voltage Vm is 0 at time t10. The control signal VC4 is low L between time t10 and time t16, and the reset signal Vr remains low L.

[0085] After time t20, as the current Iin from the power generating element 10 rises to Iin2 and the voltage Vin gradually increases from Vin0, the voltage at node N4 gradually increases. The voltage Vm at node N3, which is capacitively connected to node N4, gradually increases from 0.

[0086] At time t21, control circuit 18c detects the voltage Vin at terminal Tsw1. When the voltage Vin exceeds the voltage Vin0 + Vref, the voltage Vm exceeds the reference voltage Vref, and comparator 16 outputs a high level H as a reset signal Vr. When the reset signal Vr becomes high level H, control circuit 18c sets control signal VC1 to low level L and control signal VC2 to high level H, while keeping control signals VC3 and VC4 at low level L. The voltage G1 at node N1, which is capacitively connected to control terminal TC1, decreases. The voltage G2 at node N2, which is capacitively connected to control terminal TC2, increases. Note that the timing of setting control signal VC1 to low level L and the timing of setting control signal VC2 to high level H can be slightly different from each other, as long as the above operations are possible.

[0087] Between times t21 and t22, current flows from node N1 to node N2 via diode D, and voltages G1 and G2 rise slightly. At time t22, control circuit 18c sets control signal VC2 to low level L and holds control signals VC1, VC3, and VC4 at low level L. Voltage G2 at node N2, which is capacitively connected to control terminal TC2, drops. Current flows from node N1 to node N2 via diode D, and voltage G1 drops slightly. At time t23, control circuit 18c sets control signals VC1 and VC4 to high level H and holds control signals VC2 and VC3 at low level L. Similar to the case where voltage G1 becomes the voltage Vin0 of voltage Vin at time t16, voltage G1 becomes Vin0 + Vref, which is the voltage of voltage Vin. NFET M4 is turned on, and voltage Vm at node N3 becomes 0V. The timing for setting control signal VC1 to a high level H and the timing for setting control signal VC4 to a high level H can be slightly different from each other, as long as the voltage Vm at node N3 can be appropriately set to 0V. At time t24, control circuit 18c sets control signal VC4 to a low level L, holds control signal VC1 at a high level H, and holds control signals VC2 and VC3 at a low level L.

[0088] exist Figure 5 In the switching circuit of the second embodiment described above, at time t16, when the voltage Vin is Vin0 and PFET M1 switches from the on state to the off state, the voltage G1 is Vin0, the voltage difference between the source and gate of PFET M1 is essentially zero, and PFET M1 is in the off state. Thereafter, after time t20, even if the voltage Vin is not high, the voltage G1 remains Vin0. Therefore, the gate voltage becomes lower than the source voltage of PFET M1. Therefore, there is a possibility that PFET M1 will be turned on. When PFET M1 is turned on, current flows through PFET M1, and the conversion efficiency of the voltage conversion circuit 12 decreases.

[0089] Comparator 16 compares the voltage Vm at node N3 with the reference voltage Vref and outputs the comparison result to control circuit 18c. This allows determination circuit 15 to determine whether the voltage Vin has changed from the constant voltage corresponding to the reference voltage Vref from the voltage Vin0 to a higher voltage (a voltage further away from the reference potential 0V).

[0090] In the third embodiment, when PFET M1 is in the off state, the determining circuit 15 determines whether the voltage Vin has changed from a constant voltage (Vref) to a higher voltage (a voltage further away from the reference potential 0V) from the voltage Vin0 (the voltage at which PFET M1 last switched from the on state to the off state). When it is determined that the voltage Vin has changed from the constant voltage (Vref), the control circuit 18c provides a low level L (second level) to the control terminal TC1 and a high level H (fourth level) to the control terminal TC2, then provides a high level H (first level) to the control terminal TC1 and a low level L (third level) to the control terminal TC2. Therefore, when the voltage Vin becomes higher than the reference voltage Vref by more than the voltage Vin0, the voltage G1 at the gate of PFET M1 can be reset to the voltage Vin. Therefore, during the period when the voltage Vin becomes higher than the voltage Vin0 and FET M1 is initially controlled to be in the off state, a microcurrent can be prevented from flowing between the source and drain of FET M1, thereby preventing the charge from flowing out of the primary capacitor. This prevents a decrease in the conversion efficiency of the voltage conversion circuit 12.

[0091] In the third embodiment, the control signal Sh has a constant period, and as mentioned above, its frequency is preferably low. However, when the control signal Sh and the reset signal Vr are generated substantially simultaneously, the operation of the control signal Sh takes precedence.

[0092] Fourth Implementation Method

[0093] The fourth embodiment is an example where the input voltage Vin from the power generating element 10 is lower than the ground potential. Figure 9 This is a detailed circuit diagram of the switching circuit constituting the power supply circuit of the fourth embodiment, and is an example. Figure 1 The diagram shows the details of the HSW switch and its control circuit. Figure 9 As shown, the switching circuit 28 of the fourth embodiment uses NFET M1a, PFET M2a, PFET M3a and PFET M4a, respectively, to replace the switching circuit of the third embodiment. Figure 7 The PFETs M1, M2, M3, and M4 are shown. The cathode of diode D is connected to node N1, and its anode is connected to node N2, with the direction from node N2 to node N1 being positive. The negative input terminal of comparator 16a is connected to node N3, and the reference voltage Vref is input to the positive input terminal. The control circuit is represented by 18d. Other configurations are similar to... Figure 7 The configuration of the third embodiment shown is the same, and its description is omitted. The high level H and low level L of control signals VC1 to VC4 are... Figure 8 The opposite is true. Voltage X, voltage Vin0, and reference voltage Vref are negative.

[0094] In the first to third embodiments, when the input voltage Vin is higher than the ground voltage (reference potential), the first FET is a PFET M1, and the second and third FETs are NFETs M2 and M3, respectively. The first and fourth levels are high levels H, and the second and third levels are low levels L. On the other hand, when the input voltage Vin is lower than the ground voltage (reference potential), the first FET is an NFET M1a, and the second and third FETs are PFETs M2a and M3a, respectively. The first and fourth levels are low levels L, and the second and third levels are high levels H. As described above, each of the second and third FETs is an NFET or a PFET having a channel conductivity type opposite to that of the first FET.

[0095] In the first to fourth embodiments, the PFET is in the off state when the gate voltage (the voltage between the gate and the source) is 0V, and turns on when the gate voltage becomes lower than the negative threshold voltage. The NFET is in the off state when the gate voltage is 0V, and turns on when the gate voltage becomes higher than the positive threshold voltage. The PFET and NFET are, for example, metal-oxide-semiconductor (MOS) FETs using silicon. The diode D is, for example, a diode in which the FET is connected to a diode. Although the FET has been described as an example of a switching element, switching elements can be applied to the first to fourth embodiments as long as the switching element is a field-effect element that operates in a floating state using the potential of the control terminal (gate). The switching element only needs to be a field-effect switching element in which the potential applied to the control terminal switches the conductive channel between an on state and an off state according to the electric field formed in the conductive channel. For example, a bipolar transistor or an insulated-gate bipolar transistor (IGBT) combined with a FET can be used.

[0096] The high and low levels of control signals VC1 to VC4 only need to make the high level higher than the low level in the same control signal, and the voltages of the high levels of different control signals can be different from each other, and the low levels can be different from each other.

[0097] exist Figure 1 The use of switches from the first to fourth embodiments in the voltage conversion circuit 12 allows for stable control of the switching of the voltage conversion circuit 12. Although Figure 1 An example of a buck / boost converter circuit as a power supply circuit is shown, but the power supply circuit can be a buck converter circuit, a boost converter circuit, or an inverting voltage converter circuit. The power supply circuit can also be a power conversion circuit that converts alternating current to direct current, etc.

[0098] Figure 10 (a) is a block diagram illustrating an embodiment of the power supply circuit according to the invention, wherein a switching circuit according to any one of the first to fourth embodiments and variations thereof is used in the voltage conversion circuit 64. Figure 10 As shown in (a), the system includes a power generation element 60, rectifier circuits 61 and 62, a matching circuit 63, a voltage conversion circuit 64, a charging management circuit 65, an energy storage device 66, a cold start circuit 67, and a boost circuit 68.

[0099] Power generating element 60 is, for example, Figure 1The power generating element 10 produces a microcurrent of AC power. Rectifier circuit 61 is, for example, a diode bridge, and rectifier circuit 62 is, for example, a synchronous rectifier circuit. Matching circuit 63 matches the output impedance of rectifier circuits 61 and 62 with the input impedance of voltage conversion circuit 64. Voltage conversion circuit 64 is, for example, a... Figure 1 The voltage conversion circuit 12 is a DC-DC converter. The charging management circuit 65 stores electricity in one of a plurality of energy storage devices 66. The energy storage device 66 is, for example, a capacitor. The charging management circuit 65 monitors the voltage across the terminals of the plurality of energy storage devices and uses the generated power to charge the appropriate energy storage device. When the energy storage device 66 is almost uncharged, the cold start circuit 67 charges the energy storage device 66 using the output current of the rectifier circuit 61. The boost circuit 68 is, for example, a charge pump and generates voltage for the rectifier circuit 62, the voltage conversion circuit 64, etc.

[0100] The operation of the system will now be described. When the power generating element 60 generates a small amount of power in a state where the energy storage device 66 is almost not charged, the rectifier circuit 61 rectifies the small amount of power. The rectifier circuit 61 can perform rectification without an external power supply such as a diode bridge. The current rectified by the rectifier circuit 61 reaches the charging management circuit 65 via the cold start circuit 67 and is stored in the energy storage device 66. When the energy storage device 66 is charged to a sufficient voltage, the boost circuit 68 boosts the voltage of the energy storage device 66 to the voltage used by the rectifier circuit 62 and the voltage conversion circuit 64. The voltage of the energy storage device 66 is, for example, 1V, and the voltage output from the boost circuit 68 is, for example, 2V. When the rectifier circuit 62 and the voltage conversion circuit 64 operate using the voltage of the energy storage device 66, the boost circuit 68 can be omitted.

[0101] Matching circuit 63 increases the input voltage when the electrical force and current generated by power generating element 60 are large, and decreases the input voltage when the electrical force and current generated by power generating element 60 are small. Therefore, the output impedance of power generating element 60 matches the input impedance of rectifier circuits 61 and 62. Matching circuit 63 switches between rectifier circuits 61 and 62 according to the input voltage. For example, when rectifier circuits 61 and 62 are a diode bridge and a synchronous rectifier circuit, respectively, the losses due to the diode forward voltage increase when the input voltage becomes equal to or lower than 1V. Therefore, rectifier circuit 62 is used. When the input voltage is equal to or higher than 1V, rectifier circuit 61 is used.

[0102] Voltage conversion circuit 64 converts the input voltage set by matching circuit 63 into a voltage for charging energy storage device 66. The voltage of energy storage device 66 is, for example, 1V or 3.3V. Charging management circuit 65 monitors the voltages of multiple energy storage devices 66 and uses the generated power to charge the appropriate energy storage device 66.

[0103] In a system using the power generating element 60 that produces this micro-electricity, the input voltage of the voltage conversion circuit 64 changes. For this reason, the switch HSW (see [link to switch 64]) acts as the high-side switch of the voltage conversion circuit 64. Figure 1 The circuit cannot operate stably, and the conversion efficiency in the voltage conversion circuit 64 may decrease. By using a switching circuit according to any one of the first to fourth embodiments as the switch HSW of the voltage conversion circuit, the switch HSW can be stably controlled, and the decrease in the conversion efficiency of the voltage conversion circuit 64 can be reduced.

[0104] Figure 10 (b) is a block diagram illustrating a sensor circuit system that uses a switching circuit according to any one of the first to fourth embodiments and their variations. Figure 10 As shown in (b), the switching elements of the switching circuit 71 in the first to fourth embodiments turn the power supply from the power source 70 to the sensor circuit 72 on and off. As described above, the switching elements of the switching circuits in the first to fourth embodiments are not limited to elements that turn the electromotive force provided by the power generation element on and off. The switching circuits in the first to fourth embodiments can be used in circuits other than power supply circuits, such as Internet of Things (IoT) devices or edge devices with low power consumption.

[0105] While the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and alterations can be made within the scope of the spirit of the invention as described in the claims.

[0106] Explanation of reference numerals in the attached figures

[0107] 10 Power generation components

[0108] 12 Voltage Conversion Circuit

[0109] 14 Control Unit

[0110] 16 Comparators

[0111] 18a to 18d control circuit

Claims

1. A switching circuit, the switching circuit comprising: A first FET has a source connected to a first terminal, a drain connected to a second terminal, and a gate connected to a first node capacitively connected to a first control terminal. The first FET switches between an on state and an off state according to the potential of the gate. The second FET has a source connected to the first node, a drain connected to the first terminal, and a gate; as well as The control circuit, while maintaining the first FET in the off state, provides a first-level potential to the first node to keep the first FET in the off state; when switching the first FET from the off state to the on state, it causes the state between the source and drain of the second FET to enter the off state; and connects the first node to a reference potential via a resistor, charges or discharges the first node, then disconnects the first node from the first terminal and the reference potential to make the first node float, and provides a second-level potential to the first control terminal to keep the first FET in the on state.

2. The switching circuit according to claim 1, further comprising: The third FET has a source connected to the reference potential, a drain connected to the first node, and a gate. The resistor is a resistor between the source and drain of the third FET, and when the first node is connected to the reference potential via the second FET, a saturation current flows through the third FET.

3. The switching circuit according to claim 1, further comprising: In a rectifier element, the direction from the first node to the second node capacitively connected to the second control terminal is positive. The second FET is N-type, and its gate is connected to the second node. Wherein, the first FET is P-type, and The first node is connected to the reference potential via the rectifier element, the second node, and the resistor.

4. The switching circuit according to claim 1, further comprising: In a rectifier element, the direction from the second node, which is capacitively connected to the second control terminal, to the first node is positive. The second FET is P-type, and its gate is connected to the second node. Wherein, the first FET is N-type, and The first node is connected to the reference potential via the rectifier element, the second node, and the resistor.

5. The switching circuit of claim 3, wherein, When the first FET remains in the ON state, the control circuit provides a second-level potential to the first control terminal and a third-level potential to the second control terminal. When the first FET switches from the ON state to the OFF state, it provides a fourth-level potential to the second control terminal. Then, it provides the first-level potential to the first control terminal and the third-level voltage to the second control terminal. The third level causes the second FET to enter the OFF state, and the fourth level causes the second FET to enter the ON state.

6. The switching circuit of claim 5, wherein, When the control circuit switches the first FET from the on state to the off state, it provides the third level potential to the second control terminal and then provides the first level potential to the first control terminal.

7. The switching circuit according to claim 5, further comprising: A determining circuit is configured to determine, when the first FET remains in the off state, whether the input voltage to the first terminal has changed by a predetermined voltage from the input voltage at the time the first FET last switched from the on state to the off state. When the control circuit determines that the input voltage has changed the predetermined voltage, it provides the second level potential to the first control terminal and the fourth level potential to the second control terminal. Then, it provides the first level potential to the first control terminal and the third level potential to the second control terminal.

8. The switching circuit of claim 7, wherein, The determining circuit includes a comparator configured to compare the voltage at a third node capacitively connected to the first terminal with a constant voltage, and output the comparison result to the control circuit.

9. The switching circuit of claim 1, wherein, The input voltage to the first terminal is higher than the reference potential, and the first FET is a PFET.

10. The switching circuit of claim 1, wherein, The input voltage to the first terminal is lower than the reference potential, and the first FET is an NFET.

11. The switching circuit according to claim 1, further comprising a diode connected to the first node to maintain the potential of the first node within a predetermined range.

12. A switching circuit, the switching circuit comprising: A first FET has a source connected to a first terminal, a drain connected to a second terminal, and a gate connected to a first node capacitively connected to a first control terminal. The first FET switches between an on state and an off state according to the potential of the gate. The second FET has a source connected to the first node, a drain connected to the first terminal, and a gate connected to the second node capacitively connected to the second control terminal. as well as A control circuit that controls the first FET and the second FET. When the control circuit maintains the first FET in the on state, it provides a first-level potential from the first control terminal to the first node to enable the first FET to be in the on state. When the first FET is switched from the on state to the off state, it provides a potential from the second control terminal to the second node to enable the state between the source and drain of the second FET to be in the on state, thereby connecting the first node and the second node to the first terminal via a resistor to charge or discharge the first node and the second node. Then, it provides a potential from the second control terminal to the second node to enable the state between the source and drain of the second FET to be in the off state, thereby disconnecting the first node and the second node from the first terminal and making the first node and the second node float. After the floating is performed, a second-level potential is provided to the first control terminal to enable the first FET to be in the off state.

13. The switching circuit according to claim 1 or 12, wherein, The first FET turns on and off the electromotive force provided by the power generation element.

14. The switching circuit of claim 13, wherein, The power generating element is a vibration power generating element.

15. The switching circuit of claim 1 or 12, wherein, The first FET turns the power supply to the sensor circuit on and off.

16. A power supply circuit, the power supply circuit comprising the switching circuit according to claim 1 or 12.

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