Ternary content addressable memory

Abstract

A ternary content addressable memory is provided in a stacked memory device including a first memory cell string and a second memory cell string. The first memory cell string is coupled between a match line and a first source line and receives a plurality of first word line signals. The first memory cell string has a first memory cell string select switch. The first memory cell string select switch is controlled by a first search signal. The second memory cell string is coupled between the match line and the first source line and receives a plurality of second word line signals. The second memory cell string has a second memory cell string select switch. The second memory cell string select switch is controlled by a second search signal.

Description

Technical Field

[0001] This invention relates to a tri-state content-addressable memory, and more particularly to a tri-state content-addressable memory that can improve search bandwidth. Background Technology

[0002] In traditional technology, tri-state content-addressable memory (TMAC) can be constructed using NOR gate flash memory cell pairs. These NOR gate flash memory cell pairs utilize word lines or bit lines to receive search signals. This architecture requires relatively high voltage for read operations. Furthermore, in TMAC architectures using NOR gate flash memory cells, when many source line switches are activated, mismatched memory cell pairs can generate a large current within the TMAC. In actual circuit operation, this excessive current is clamped by surrounding bit lines and source line switches, leading to incorrect search results. Summary of the Invention

[0003] This invention provides a variety of tri-state content addressable memories, which can improve the bandwidth of data search operations.

[0004] The tri-state content-addressable memory of the present invention includes a first memory cell string and a second memory cell string. The first memory cell string is coupled between a match line and a first source line and receives a plurality of first word line signals. The first memory cell string has a first memory cell string selection switch; the first memory cell string selection switch is controlled by a first search signal. The second memory cell string is coupled between a match line and the first source line and receives a plurality of second word line signals. The second memory cell string has a second memory cell string selection switch, the second memory cell string selection switch being controlled by a second search signal.

[0005] Another tri-state content-addressable memory of the present invention includes multiple pairs of memory cell strings. Each pair of memory cell strings receives multiple search data. Each pair of memory cell strings includes a first memory cell string and a second memory cell string. The first memory cell string is coupled between a match line and a first source line and receives multiple first word line signals. The first memory cell string has a first memory cell string selection switch; the first memory cell string selection switch is controlled by a first search signal. The second memory cell string is coupled between a match line and a first source line and receives multiple second word line signals. The second memory cell string has a second memory cell string selection switch, which is controlled by a second search signal.

[0006] Based on the above, the tri-state content-addressable memory of the present invention performs the search operation of search data through pairs of first and second memory cell strings. Specifically, the first and second memory cell strings receive pairs of first and second search signals using first and second memory cell string selection switches, respectively. The tri-state content-addressable memory of the present invention can utilize multiple pairs of memory cell strings to perform the search operation of multiple pieces of search data, effectively improving the bandwidth of the search operation. Attached Figure Description

[0007] Figure 1 A schematic diagram illustrating a three-state content-addressable memory according to an embodiment of the present invention is shown.

[0008] Figures 2A to 2F A schematic diagram of the search operation of the three-state content addressable memory according to an embodiment of the present invention.

[0009] Figure 3 A schematic diagram illustrating another embodiment of the three-state content-addressable memory of the present invention is shown.

[0010] Figure 4 A schematic diagram illustrating an implementation of the multi-phase search operation of a three-state content-addressable memory according to an embodiment of the present invention is shown.

[0011] Figure 5 A schematic diagram illustrating a three-state content-addressable memory according to another embodiment of the present invention is shown.

[0012] Figure 6 Illustration of the present invention Figure 5 A schematic diagram of another implementation of the page buffer in a tri-state content-addressable memory.

[0013] Figure 7 A schematic diagram illustrating an implementation of an approximate search mode for a three-state content addressable memory according to an embodiment of the present invention is shown.

[0014] Explanation of reference numerals in the attached figures

[0015] 100, 300, 400, 500: Tri-state content-addressable memory

[0016] 110, 120, 311, 312, 321, 322, 411, 412, 421, 422, 511, 512, 521, 522: String of storage cells

[0017] 310, 320, 410, 420, 510, 520: String pairs of storage cells

[0018] 430: Controller

[0019] 551: Page Buffer

[0020] 5511: Counter

[0021] CSL: Source Line

[0022] DZR1: Reference Direction

[0023] Group 1~Group 4: Groups

[0024] ML: Matching line

[0025] ROUT: Similarity

[0026] SB1, SB2, SB1~SB-32: Search signals

[0027] SD1, SD2: Search data

[0028] SLT1, SLT2: Source line switches

[0029] SSL1, SSL1B: Memory Serial Select Line

[0030] SSW1, SSW2: Memory cell string selection switches

[0031] WL0a~WLna, WL0b~WLnb: Word lines

[0032] SMC1, SMC2: Selected memory unit

[0033] PB-1~PB-512: Page Buffer

[0034] PH1, PH2: Phase Detailed Implementation

[0035] Please refer to Figure 1 , Figure 1 A schematic diagram illustrating a tri-state content-addressable memory according to an embodiment of the present invention is shown. The tri-state content-addressable memory 100 includes memory cell strings 110 and 120. Memory cell strings 110 and 120 form memory cell string pairs. Memory cell string 110 is coupled between a mating line ML and a source line CSL, and memory cell string 110 has a plurality of memory cells. Each memory cell is coupled to a plurality of word lines WL0a to WLna. Memory cell string 110 has a memory cell string selection switch SSW1 and a source line switch SLT1, wherein the plurality of memory cells of memory cell string 110 are connected in series between the memory cell string selection switch SSW1 and the source line switch SLT1, are coupled to the mating line ML through the memory cell string selection switch SSW1, and are coupled to the source line CSL through the source line switch SLT1.

[0036] Additionally, a memory cell string 120 is coupled between the mating line ML and the source line CSL, and the memory cell string 120 has multiple memory cells. Each memory cell is coupled to multiple word lines WL0b to WLnb. The memory cell string 120 has a memory cell string selection switch SSW2 and a source line switch SLT2, wherein the multiple memory cells of the memory cell string 120 are connected in series between the memory cell string selection switch SSW2 and the source line switch SLT2, coupled to the mating line ML through the memory cell string selection switch SSW2, and coupled to the source line CSL through the source line switch SLT2.

[0037] In this embodiment, the control terminals of memory cell string selection switches SSW1 and SSW2 are coupled to memory cell string selection lines SSL1 and SSL1B, respectively, and receive search signals SB1 and SB2, respectively. Search signals SB1 and SB2 can be generated based on search data SD1. For example, if search data SD1 is a logic high or logic low level, search signals SB1 and SB2 can be complementary logic levels; if search data SD1 is a foreign card signal (or negligible), search signals SB1 and SB2 can be the same logic low level. Source line switches SLT1 and SLT2 are controlled by the control signal GSL.

[0038] In other embodiments, word lines WL0a to WLna coupled to memory cell string 110 and word lines WL0b to WLnb coupled to memory cell string 120 may be the same word lines.

[0039] During a search operation, one of the word lines WL0a to WLna is designated as the selected word line, receiving an enabled word line signal, while the other unselected word lines receive a word line signal equal to the applied voltage. Similarly, one of the word lines WL0b to WLnb is designated as the selected word line, receiving an enabled word line signal, while the other unselected word lines receive a word line signal equal to the applied voltage.

[0040] Meanwhile, storage cell string 110 generates a first comparison result based on the data in the selected storage cell and search signal SB1, while storage cell string 120 generates a second comparison result based on the data in the selected storage cell and search signal SB2. The matching signal on the matching line ML is then determined based on the first and second comparison results.

[0041] Please note that storage cell strings 110 and 120 can be arranged in a stacked storage cell array, such as a stacked flash memory cell array.

[0042] For details on the implementation of the search action, please refer to [link / reference]. Figures 2A to 2FThis is a schematic diagram illustrating the search operation of a tri-state content-addressable memory according to an embodiment of the present invention. In this embodiment, the memory cell string 110 can determine whether to provide a first current between the match line ML and the source line CSL based on the generated first comparison result. Similarly, the memory cell string 120 can determine whether to provide a second current between the match line ML and the source line CSL based on the generated second comparison result. Wherein, in Figure 2A In this configuration, the threshold voltage of the selected memory cell SMC1 is in a high-voltage state, while the threshold voltage of the selected memory cell SMC2 is in a low-voltage state. That is, the data stored in the selected memory cell SMC1 is at a logic high level (H), while the data stored in the selected memory cell SMC2 is at a logic low level (L). When the search data SD1 is at the search level ("1"), the search signals SB1 and SB2 can be at logic high level (H) and logic low level (L), respectively. At this time, the memory cell string selection switch SSW2 can be turned off, causing the memory cell string 120 to be disconnected and not providing the aforementioned second current. The memory cell string selection switch SSW1 can be turned on, and because the data stored in the selected memory cell SMC1 is at a logic high level (H), the memory cell string 110 is disconnected and not providing the aforementioned first current. In this embodiment, the selected memory cells SMC1 and SMC2 are combined to store data equal to a logic high level ("1").

[0043] In this embodiment, search signals SB1 and SB2 match the data stored in the selected memory cells SMC1 and SMC2, respectively, therefore the search result should be a match. Since memory cell strings 110 and 120 do not provide the first and second currents, the sensing circuit coupled to the matching line ML will not sense any current and will determine the current search result as a match. In other embodiments, the voltage level of the matching signal on the matching line ML will not change. By observing that the voltage level of the matching signal on the matching line ML remains unchanged, it can be determined that the search action was a match.

[0044] Incidentally, before the search operation, the matching signal on the matching line ML can be pre-charged to a relatively high reference voltage value. When the memory cell strings 110 and 120 do not provide the first current and the second current during the search operation, the matching signal on the matching line ML can be maintained equal to this reference voltage value.

[0045] exist Figure 2BIn this configuration, the data stored in the selected memory cell SMC1 is at a logic high level (H), while the data stored in the selected memory cell SMC2 is at a logic low level (L). When the search data SD1 is at the search data level ("0"), the search signals SB1 and SB2 can be at logic low level (L) and logic high level (H), respectively. At this time, the memory cell string selection switch SSW1 can be turned off, causing the memory cell string 110 to be disconnected and not providing the first current mentioned above. The memory cell string selection switch SSW2 can be turned on, and because the data stored in the selected memory cell SMC2 is at a logic low level (L), the memory cell string 120 can provide the second current mentioned above. In this embodiment, the selected memory cells SMC1 and SMC2 are combined to store data equal to a logic high level ("1").

[0046] In this embodiment, search signals SB1 and SB2 do not match the data stored in the selected memory cells SMC1 and SMC2, respectively, therefore the search result should be unmatched. A sensing circuit coupled to the matching line ML can sense the current and determine that the current search result is unmatched. In other embodiments, based on the fact that the memory cell string 120 can provide a second current, the voltage level of the matching signal on the matching line ML can be pulled down to a relatively low reference voltage value (e.g., equal to the ground voltage). The state of the voltage level of the matching signal on the matching line ML being pulled low indicates that the search action was unmatched.

[0047] exist Figure 2C In the process, selected memory cells SMC1 and SMC2 are combined to store data equal to a logic low level ("0"), where selected memory cells SMC1 and SMC2 store data at logic low level (L) and logic high level (H), respectively. When search data SD1 is at search data level ("1"), search signals SB1 and SB2 can be at logic high level (H) and logic low level (L), respectively. At this time, memory cell string selection switch SSW2 can be turned off, thus cutting off memory cell string 120 and not providing the aforementioned second current. Memory cell string selection switch SSW1 can be turned on, and because the data stored in selected memory cell SMC1 is at logic low level (L), memory cell string 110 can provide the aforementioned first current.

[0048] In this embodiment, search signals SB1 and SB2 do not match the data stored in the selected memory cells SMC1 and SMC2, respectively, therefore the search result should be unmatched. A sensing circuit coupled to the matching line ML can sense the current and determine that the current search result is unmatched. In other embodiments, based on the first current provided by the memory cell string 110, the voltage level of the matching signal on the matching line ML can be pulled down to a relatively low reference voltage value (e.g., equal to the ground voltage). The state of the voltage level of the matching signal on the matching line ML being pulled low indicates that the search action was unmatched.

[0049] exist Figure 2D In the process, selected memory cells SMC1 and SMC2 are combined to store data equal to a logic low level ("0"), where selected memory cells SMC1 and SMC2 store data at logic low level (L) and logic high level (H), respectively. When the search data SD1 is at the search data level ("0"), search signals SB1 and SB2 can be at logic low level (L) and logic high level (H), respectively. At this time, the memory cell string selection switch SSW1 can be turned off, causing memory cell string 110 to be disconnected and not providing the aforementioned first current. The memory cell string selection switch SSW2 can be turned on, and because the data stored in selected memory cell SMC2 is at a logic high level (H), memory cell string 120 is turned off and not providing the aforementioned second current.

[0050] In this embodiment, search signals SB1 and SB2 match the data stored in the selected memory cells SMC1 and SMC2, respectively, therefore the search result should be a match. The sensing circuit coupled to the matching line ML will not sense any current and will determine that the current search result is a match. In other embodiments, since memory cell strings 110 and 120 do not provide the first and second currents, the voltage level of the matching signal on the matching line ML remains equal to a relatively high reference voltage value. The fact that the voltage level of the matching signal on the matching line ML is not pulled low indicates that the search action was a match.

[0051] exist Figure 2E In the process, storage cells SMC1 and SMC2 are selected to store any storage data level. When the search data SD1 is the external card signal (X), the search signals SB1 and SB2 can both be at logic low level (L). At this time, the storage cell string selection switches SSW1 and SSW2 are both turned off, thus cutting off storage cell strings 110 and 120 and not providing the first and second currents mentioned above.

[0052] In this embodiment, regardless of the data stored in the selected memory cells SMC1 and SMC2, the search result is always a match. The sensing circuit coupled to the matching line ML will not sense any current and will determine that the current search result is a match. In other embodiments, since memory cell strings 110 and 120 do not provide the first and second currents, the voltage level of the matching signal on the matching line ML remains equal to a relatively high reference voltage value. The fact that the voltage level of the matching signal on the matching line ML is not pulled low indicates that the search operation was a match.

[0053] exist Figure 2F In the process, storage cells SMC1 and SMC2 are selected to store data for the external card signal. At this time, both storage cells SMC1 and SMC2 store data equal to logic high level (H). Regardless of whether the search data SD1 is search data level ("1"), search data level ("0"), or external card signal (X) (search signals SB1 and SB2 can be logic low level (L) or logic high level (H)), storage cell strings 110 and 120 do not provide the aforementioned first current and second current.

[0054] In this embodiment, regardless of the logic levels of search signals SB1 and SB2, the search result is a match. The sensing circuit coupled to the matching line ML will not sense any current and will determine that the current search result is a match. In other embodiments, since memory cell strings 110 and 120 do not provide the first and second currents, the voltage level of the matching signal on the matching line ML remains equal to a relatively high reference voltage value. The fact that the voltage level of the matching signal on the matching line ML is not pulled low indicates that the search operation was a match.

[0055] The truth table for the tri-state content-addressable memory 100 can be found in Table 1 below:

[0056] Table 1:

[0057]

[0058]

[0059] It is worth mentioning that in this embodiment of the invention, the memory cell string only provides current when the search result is mismatched. When the search result matches, the memory cell string does not provide current. Therefore, read interference caused by the current generated when the search result matches does not occur in this embodiment. Furthermore, the current state in the mismatched state is not something the designer needs to concern themselves with. In addition, in this embodiment, the read operation performed on the memory cells in the memory cell string is the same as the read operation of a typical Single Level Cell (SLC) memory cell, and does not produce the so-called back-pattern loading effect.

[0060] Furthermore, based on the characteristic of the storage cell string that it only provides current when the search results are mismatched in the embodiments of the present invention, when judging the matching status of multiple data search actions, the total amount of current generated by the storage cell string can be used to simply determine the number of mismatched results in the search results.

[0061] Please refer to the following: Figure 3 , Figure 3 This diagram illustrates another embodiment of the tri-state content-addressable memory (TRM) of the present invention. In this embodiment, the TRM 300 includes multiple memory cell string pairs 310 and 320. Memory cell string pair 310 includes memory cell strings 311 and 312, and memory cell string pair 320 includes memory cell strings 321 and 322. Memory cell strings 311, 312, 321, and 322 are coupled to the same matching line ML. Memory cell strings 311 and 312 are used to perform a search operation for search data SD1, and memory cell strings 321 and 322 are used to perform a search operation for search data SD2. When memory cell strings 311 and 312 perform a search operation for search data SD1, memory cell strings 321 and 322 do not perform any operation; conversely, when memory cell strings 321 and 322 perform a search operation for search data SD2, memory cell strings 311 and 312 do not perform any operation.

[0062] In this embodiment, when performing a search operation on multiple bits, the search operations on multiple search data SD1 to SD2 can be performed sequentially according to the reference direction DZR1.

[0063] It is worth noting that when the search operation performed on search data SD1 results in a match, the voltage value of the matching signal on the matching line ML can remain unpulled down. In this way, the tri-state content-addressable memory 300 can quickly execute the search operation for the next piece of data (search data SD2). Conversely, if the search operation performed on search data SD2 results in a mismatch, the voltage value of the matching signal on the matching line ML can be pulled down, and the tri-state content-addressable memory 300 can stop subsequent search operations.

[0064] The circuit architecture of the storage cell strings 311, 312, 321, and 322 in this embodiment is the same as that of the storage cell strings in the previous embodiment, and will not be described in detail here.

[0065] Furthermore, the storage unit strings 310 and 320 can receive multiple search data SD1 and SD2 at different time phases.

[0066] Please refer to the following: Figure 4 , Figure 4 A schematic diagram illustrating an implementation of a multi-phase search operation for a three-state content-addressable memory according to an embodiment of the present invention is shown. Figure 4 In this embodiment, the tri-state content-addressable memory 400 includes multiple memory cell string pairs 410 and 420. Memory cell string pair 410 includes memory cell strings 411 and 412, and memory cell string pair 420 includes memory cell strings 421 and 422. Memory cell strings 411, 412, 421, and 422 are coupled to the same mating line ML. In this embodiment, the controller 430 is coupled to memory cell strings 411, 412, 421, and 422 and is used to provide search data SD1 and SD2.

[0067] In this embodiment, the search operation can be performed in a multi-phase manner. Specifically, in the first phase PH1, the controller 430 can provide search data SD1 to storage unit strings 411 and 412, and cause storage unit strings 411 and 412 to perform a search operation on the search data SD1. In the first phase PH1, storage unit strings 421 and 422 do not perform a search operation and can be in an idle state.

[0068] Next, in the second phase PH2 following the first phase PH1, the controller 430 can provide search data SD2 to the storage unit strings 421 and 422, and cause the storage unit strings 421 and 422 to perform a search operation on the search data SD2. In the second phase PH2, the storage unit strings 411 and 412 do not perform a search operation and can be in an idle state.

[0069] It is worth noting that in a stacked NAND flash memory architecture, setting the word line signals received by the memory cell takes a lot of time. Therefore, in this embodiment, by using a multi-phase search method, multiple search operations can be completed without repeatedly setting the word line signals, which can effectively improve the bandwidth of data search.

[0070] On the other hand, in this embodiment of the invention, the search data SD1 to SD2 generated by the controller 430 can be adjusted according to different search modes. When the search mode is a precise search mode, the controller 430 can make each of the generated search data SD1 to SD2 a precise logic level 1 or logic level 0. Conversely, when the search mode is an approximate search mode, the controller 430 can make at least one of the generated search data SD1 to SD2 a foreign card signal.

[0071] Here, the controller 430 can set specific search data as a foreign card signal, or it can randomly select one or more of the search data SD1 to SD2 that are already foreign card signals, without any specific restrictions.

[0072] It is worth mentioning that users can choose to put the tri-state content addressable memory 400 into precise search mode or approximate search mode according to their actual needs, without any fixed restrictions.

[0073] Here, the controller 430 can be any control logic circuit with computing capabilities, such as a memory control circuit well known to those skilled in the art, and its hardware architecture is not limited.

[0074] Please refer to the following: Figure 5 , Figure 5 A schematic diagram illustrating a tri-state content-addressable memory according to another embodiment of the present invention is shown. The tri-state content-addressable memory 500 includes multiple memory cell pairs 510 and 520 and a page buffer 551. Memory cell pairs 510 include memory cell strings 511 and 512, and memory cell pairs 520 include memory cell strings 521 and 522. The architecture of memory cell strings 511, 512, 521, and 522 is similar to... Figure 1The storage cell strings 110 and 120 in the embodiment are the same, and will not be described in detail here. Page buffer 551 is coupled to the matching line ML. Page buffer 551 has a sensing amplifier circuit and multi-level cache storage elements. The sensing amplifier circuit is used to sense the matching signal on the matching line ML to determine whether the search result is a match or a mismatch. The multi-level cache storage elements in page buffer 551 are used to store multiple cache values ​​and a final cache value. The cache values ​​correspond to the search results of the search action performed by the tri-state content addressable memory 500 in each phase, and the final cache value corresponds to the final search results of the search actions in multiple phases.

[0075] In this embodiment, during the search operation of the first phase PH1, storage unit strings 511 and 512 can perform a search operation on the search data SD1 and store the search result as a first cache value L1. For example, both the cache value and the final cache value can have an initial value of logic high. When the search result of the search operation of storage unit strings 511 and 512 on the search data SD1 during the search operation of the first phase PH1 is a match, the first cache value L1 can be changed to a logic low level.

[0076] In this embodiment, the page buffer 551 records the first cache value L1, the second cache value L2, and the final cache value L3 as an example. The initial cache value L2 is set to a logic high level. After the first cache value L1 is set, the final cache value L3 can be generated by performing a logical operation on the first cache value L1 and the second cache value L2. Specifically, the final cache value L3 can be generated by performing a logical AND operation between the inverse of the first cache value L1 and the second cache value L2. That is, when the first cache value L1 is at a logic low level and the second cache value L2 is at a logic high level, the final cache value L3 can be at a logic high level.

[0077] In this embodiment, the page buffer 551 can set the second cache value L2 according to the final cache value L3. That is, in phase PH1, the second cache value L2 is maintained at a logic high level.

[0078] Next, the search operation of the second phase PH2 is executed, in which storage unit strings 521 and 522 can perform a search operation on the search data SD2 and set the first cache value L1 to the new search result. When the search operation of the first phase PH1 is inconsistent, the search operation of storage unit strings 521 and 522 on the search data SD2 can be changed to a logic high level.

[0079] Since the first cached value L1 changes to a logic high level, according to the logic operation performed by page buffer 551, the final cached value L3 can be changed to a logic low level.

[0080] Next, page buffer 551 can set the second cache value L2 according to the final cache value L3. That is, in phase PH2, the second cache value L2 can be changed to be equal to logic low level.

[0081] As explained above, whether the final cache value L3 is logic low indicates whether any inconsistent search results occurred during the multi-phase search operation of the tri-state content-addressable memory 500. When the final cache value L3 remains logic high, it means that no inconsistent search results occurred during the multi-phase search operation of the tri-state content-addressable memory 500. Conversely, if the final cache value L3 is equal to logic low, it indicates that an inconsistent search result occurred during the multi-phase search operation of the tri-state content-addressable memory 500.

[0082] Please refer to the following: Figure 6 , Figure 6 Illustration of the present invention Figure 5 This is a schematic diagram of another embodiment of the page buffer in a tri-state content-addressable memory. In this embodiment, the page buffer 551 further includes a counter 5511. The counter 5511 can receive a first cache value L1 and count the number of times the first cache value L1 equals a specific logic level (logic low or logic high) occurs in a plurality of search operations.

[0083] When counter 5511 calculates the number of times the first cache value L1 equals a logic high level in multiple search actions, it can determine the number of times that multiple search data SD1, SD2 match the data (the target data being searched) stored in the memory cell strings 511 to 522, and thereby calculate the similarity ROUT between multiple search data SD1, SD2 and the target data being searched.

[0084] Conversely, when counter 5511 calculates the number of times the first cache value L1 equals a logic high level in multiple search actions, it can determine the number of times that multiple search data SD1, SD2 match the data (the target data being searched) stored in the memory cell strings 511 to 522, and thereby calculate the degree of dissimilarity between multiple search data SD1, SD2 and the target data being searched.

[0085] The 5511 counter can be implemented using any form of logic counting circuit without any restrictions.

[0086] An overflow event can be triggered if the count result of counter 5511 equals a preset threshold. When the count action of counter 5511 overflows, the search action for the current page buffer 551 can be stopped to reduce power consumption.

[0087] In some embodiments, if the count result of the corresponding page buffer 551 is less than a preset threshold, it can be determined that the data stored in the corresponding storage unit is reliable, and the stored data can be sent to a memory and / or a processor for subsequent processing.

[0088] Please refer to the above again. Figure 5 ,exist Figure 5 In this embodiment, the tri-state content-addressable memory 500 may have multiple matching lines and multiple page buffers corresponding to the multiple matching lines. Taking an example where the number of page buffers is N and each page buffer can search M search data, the search bandwidth of the tri-state content-addressable memory 500 may be equal to N×M / Tread, where Tread is the computation time required for the search operation.

[0089] Please refer to Figure 7 , Figure 7 A schematic diagram illustrating an implementation of an approximate search mode for a three-state content-addressable memory according to an embodiment of the present invention is shown. In this embodiment, the controller (such as...) Figure 4 The controller 430 can, either predeterminedly or randomly, make at least one search signal a foreign card signal (X). Figure 7 In this configuration, search signals SB-9 and SB-25 are selected as the foreign card signal (X), while each of the remaining search signals SB-1 to SB-8, SB-10 to SB-24, and SB-26 to SB-32 is set to either logic state 0 or logic state 1. For search signals SB-1 to SB-32, input signals with logic 1 or 0 can be set according to the search level of the search data and input to the tri-state content-addressable memory units corresponding to different groups Group1 to Group4. Page buffers PB-1 to PB-512 each include multiple counters to count the number of discrepancies.

[0090] In this embodiment, the tri-state content-addressable memory can generate a final matching result by selecting page buffers PB-1 to PB-512 so that the data completely matches the input signal in the presence of the foreign card signal (without generating current). In this case, the count result of the completely matching page buffer (e.g., page buffer PB-60) is equal to 0.

[0091] In other embodiments, the tri-state content-addressable memory of this embodiment can generate a final matching result by comparing the count value of the counting result with a preset threshold (e.g., equal to 2). If each count result is not greater than 2, the corresponding page buffers (e.g., page buffers PB-1, PB-2, PB-60, PB-511, and PB-512) are considered to meet the requirements. Data stored in the memory cells of the corresponding page buffers PB-1, PB-2, PB-60, PB-511, and PB-512 can be sent to a memory and / or a processor for subsequent processing. In the search signal, the number of external card signals and the threshold used to compare the count results can be adjusted by the user.

[0092] In summary, this invention utilizes paired memory cell strings to construct a tri-state content-addressable memory (TRM), and employs a memory cell string selection switch within the memory cell string to receive search signals. Under these conditions, the TRM of this invention can perform continuous search operations on multiple data items by receiving multiple search signals in a single word line setting operation, effectively improving the data search bandwidth of the TRM and enhancing the operating efficiency of electronic devices.

Claims

1. A tri-state content-addressable memory, characterized in that, include: Multiple pairs of storage units, each receiving multiple search data, each pair of storage units includes: A first memory cell string is coupled between a matching line and a first source line and receives multiple first word line signals. The first memory cell string has a first memory cell string selection switch, which is controlled by a first search signal. as well as A second memory cell string is coupled between the matching line and a first source line and receives multiple second word line signals. The second memory cell string has a second memory cell string selection switch, which is controlled by a second search signal. The first search signal and the second search signal are generated based on the corresponding search data.

2. The tri-state content-addressable memory according to claim 1, characterized in that, Each search data is set to a first logic level, a second logic level, or an external card signal.

3. The tri-state content-addressable memory according to claim 2, characterized in that, When each search data is set to the first logic level or the second logic level, the corresponding first search signal and the corresponding second search signal are complementary. When each search data is set to the foreign card signal, the corresponding first search signal and the corresponding second search signal are both at the first logic level.

4. The tri-state content-addressable memory according to claim 3, characterized in that, At least one of these search data points is the wildcard signal.

5. The tri-state content-addressable memory according to claim 4, characterized in that, Also includes: A controller selects at least one of these search data as the foreign card signal.

6. The tri-state content-addressable memory according to claim 5, characterized in that, The controller uses a random mechanism to select at least one of these search data as the foreign card signal.

7. The tri-state content-addressable memory according to claim 1, characterized in that, Also includes: A page buffer, coupled to each of the memory cell pairs, records multiple first cached values ​​and a final cached value for the hierarchical level. The first cached value records in the page buffer correspond to the search results for each search data, and the final cached value record is the final search result.

8. The tri-state content-addressable memory according to claim 7, characterized in that, The page buffer performs logical operations on these first cached values ​​to produce the final search result.

9. The tri-state content-addressable memory according to claim 8, characterized in that, The page buffer also includes: A counter is used to count the number of times the final cache value equals a specific logic level.

10. The tri-state content-addressable memory according to claim 1, characterized in that, A first selected word line among these first word line signals corresponds to a first selected memory cell, and a second selected word line among these second word line signals corresponds to a second selected memory cell. The first selected word line generates a first comparison result based on the data in the first selected memory cell and the first search signal. The first selected word line generates a second comparison result based on the data in the second selected memory cell and the second search signal. A matching signal on the matching line is determined based on the first comparison result and the second comparison result.

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