Power supply device and method and storage system comprising the same

Abstract

The present disclosure relates to a power supply device and method and a storage system including the same. A power supply device can include a power management circuit, a switching circuit, and a power controller. The power controller is configured to sequentially drive the power management circuit according to a driving sequence, and control the switching circuit to apply an output voltage of a power management circuit, which is a normally operated power management circuit among the power management circuits, to an output terminal as the driven power management circuit.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2022-0063482, filed on May 24, 2022, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure generally relate to electronic devices, and more specifically to means and methods for supplying power and storage systems including such means. Background Technology

[0004] Electronic devices may include power management circuitry configured to convert a power voltage supplied from an external device into an internal voltage with the level required to operate the internal circuitry. The power management circuitry can then supply this internal voltage to the internal circuitry.

[0005] At least one power management circuit can be provided to each internal circuit in the internal circuitry. The power management circuit can supply power to the internal circuitry when the electronic device is started.

[0006] The internal voltage can be supplied to all internal circuits, enabling the electronic device to operate normally. Therefore, the normal operation of the electronic device can be determined based on the quality of the power management circuit. Summary of the Invention

[0007] According to various embodiments of this disclosure, a power supply device can be provided. The power supply device may include: power management circuits configured to receive external power voltages to generate output voltages having the same or different levels; a switching circuit electrically connected between the power management circuits and output terminals, the number of output terminals being less than the number of power management circuits; and a power controller configured to sequentially drive the power management circuits according to a driving sequence, and to control the switching circuits to apply the output voltage of the power management circuits that constitute normal operation of the driven power management circuits to the output terminals.

[0008] According to various embodiments of this disclosure, a power supply method can be provided. In this power supply method, a power management circuit is provided, the number of which is greater than the number of output terminals; the power management circuits are driven sequentially according to a driving sequence; an output voltage is generated from a power management circuit that is operating normally as a driven power management circuit; and the output voltage is applied to the output terminals.

[0009] According to various embodiments of the present disclosure, a storage system may be provided. The storage system may include: at least one memory device; a controller configured to exchange data with the memory device in response to a request from an external device; output terminals including a plurality of internal circuits of the memory device and the controller electrically connected to the output terminals; and a power supply device configured to sequentially drive power management circuitry, the power management circuitry receiving power voltages from external devices to generate output voltages having the same or different levels, and the power supply device being configured to apply the output voltages of the power management circuitry as normal operation of the driven power management circuitry to the output terminals, the number of power management circuitry being greater than the number of output terminals.

[0010] According to various embodiments of the present disclosure, a power supply device may be provided. The power supply device may include: a first power management circuit selectively activated to generate first and second output voltages; first and second switches selectively activated to transmit the first and second output voltages to first and second output nodes, respectively; a second power management circuit selectively activated to generate a second output voltage; a third switch selectively activated to transmit the second output voltage from the second power management circuit to a second output node; and a power controller configured to selectively activate each of the first and second power management circuits and the first to third switches, such that: the first and second output voltages generated from the respective first and second power management circuits are output to the respective first and second output nodes, or the second output voltage generated from one of the first and second power management circuits is output to the second output node. Attached Figure Description

[0011] The above and other aspects, features, and advantages of the subject matter of this disclosure will become more clearly apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a view illustrating a power supply device according to an embodiment of the present disclosure;

[0013] Figure 2 This is a view illustrating a power controller according to an embodiment of the present disclosure;

[0014] Figure 3 This is a view illustrating the operation of a power supply device according to an embodiment of the present disclosure;

[0015] Figure 4 This is a flowchart illustrating a power supply method according to an embodiment of the present disclosure;

[0016] Figure 5 This is a view illustrating a storage system according to an embodiment of the present disclosure;

[0017] Figure 6 and Figure 7 This is a diagram illustrating a data processing system according to an embodiment of the present disclosure;

[0018] Figure 8 This is a diagram illustrating a network system including a data storage device according to an embodiment of the present disclosure; and

[0019] Figure 9 This is a block diagram illustrating a non-volatile memory device included in a data storage device according to an embodiment of the present disclosure. Detailed Implementation

[0020] Various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The drawings are schematic illustrations of various embodiments and intermediate structures. Therefore, variations in the configuration and shape of the illustrations are expected, for example, due to manufacturing techniques and / or tolerances. Consequently, the described embodiments should not be construed as limited to the specific configurations and shapes illustrated herein, but may include deviations in configuration and shape without departing from the spirit and scope of the present disclosure as defined in the appended claims.

[0021] This invention is described herein with reference to cross-sectional and / or planar diagrams of embodiments thereof. However, the embodiments of the invention should not be construed as limiting the inventive concept. Although several embodiments of the invention will be shown and described, those skilled in the art will appreciate that changes may be made to these embodiments without departing from the principles and spirit of the invention.

[0022] Figure 1 This is a view illustrating a power supply device according to an embodiment of the present disclosure.

[0023] refer to Figure 1 The power supply device 10 may include a power controller 110, multiple power management circuits 120-1 to 120-m, and a switching circuit 130.

[0024] The power controller 110 can receive an external power voltage VES. The power controller 110 can control the power management circuits 120-1 to 120-m and the switching circuit 130.

[0025] Each of the power management circuits 120-1 to 120-m can receive external power voltages VES1 to VESm with the same or different levels. Each of the power management circuits 120-1 to 120-m can switch the levels of the external power voltages VES1 to VESm according to the control of the power controller 110 to generate output voltages OUT1 to OUTm with the same or different levels.

[0026] According to the control of the power controller 110, the switching circuit 130 can apply the output voltages OUT1 to OUTm of the power management circuits 120-1 to 120-m as internal voltages VIS1 to VISn to the corresponding output terminals VOUT1 to VOUTn.

[0027] The operation of the power supply device 10 is described in detail below.

[0028] When a power supply process can be initiated, the power controller 110 can drive all or part of the power management circuits 120-1 to 120-m according to a predetermined drive sequence.

[0029] In various embodiments, the power controller 110 may store a drive sequence for each of the power management circuits 120-1 to 120-m. Based on this drive sequence, the power controller 110 may sequentially transmit target voltage levels OUT_LEVEL1 to OUT_LEVELm to the power management circuits 120-1 to 120-m. The power controller 110 may transmit an enable signal EN to the power management circuits 120-1 to 120-m that are being driven. The power controller 110 may receive a response signal RESP to the enable signal EN to determine whether the power management circuits 120-1 to 120-m can operate normally. The power controller 110 may be electrically connected to each of the power management circuits 120-1 to 120-m via an interface based on a System Management Bus (SMBus) protocol, an Inter-Integrated Circuit (I2C) protocol, a modified Inter-Integrated Circuit (I3C) protocol, etc.

[0030] Power management circuits 120-1 to 120-m can receive external power voltages VES1 to VESm with the same or different levels to generate output voltages OUT1 to OUTm with target voltage levels OUT_LEVEL1 to OUT_LEVELm set by power controller 110. Each power management circuit in 120-1 to 120-m can transmit a response signal RESP to the enable signal EN of power controller 110. Power controller 110 can determine whether power management circuits 120-1 to 120-m can operate normally based on the receipt of the response signal RESP.

[0031] By sequentially driving the power management circuits 120-1 to 120-m according to the driving sequence, the switching circuit 130 can apply output voltages OUT1 to OUTm to the corresponding output terminals VOUT1 to VOUTn. These output voltages OUT1 to OUTm can be generated from the normally operating power management circuits 120-1 to 120-m. Electronic devices that can receive voltage from the power supply device 10 can be electrically connected to the output terminals VOUT1 to VOUTn. Each internal circuit in the internal circuitry can be electrically connected to at least one output terminal VOUT1 to VOUTn to receive internal voltages VIS1 to VISn applied to the output terminals VOUT1 to VOUTn.

[0032] The power controller 110 can control the switching circuit 130 based on the normal operation of the power management circuits 120-1 to 120-m. In various embodiments, the power controller 110 can control the switching circuit 130 such that the output voltages OUT1 to OUTm of the normal power management circuits 120-1 to 120-m can be applied to the output terminals VOUT1 to VOUTn, and the output voltages OUT1 to OUTm of the abnormal power management circuits 120-1 to 120-m can not be applied to the switching circuit 130.

[0033] In various embodiments, the number of power management circuits 120-1 to 120-m can be greater than the number of output terminals VOUT1 to VOUTn. That is, the number "m" can be greater than the number "n". When the number of power management circuits 120-1 to 120-m in normal operation may have changed to the number of output terminals VOUT1 to VOUTn according to the drive sequence, that is, when the internal voltages VIS1 to VISn can be applied to all output terminals VOUT1 to VOUTn, the power supply process can be terminated.

[0034] When the number of power management circuits 120-1 to 120-m that may be required by all internal circuits of an electronic device from which voltage can be applied to the power supply device 10 is 'n' (where 'n' is a natural number), that is, when the number of output terminals VOUT1 to VOUTn is 'n', the power supply device 10 may include a number of 'm' power management circuits 120-1 to 120-m. Here, 'm' is greater than 'n'. In one embodiment, the number of 'n' power management circuits among all power management circuits 120-1 to 120-m may be referred to as normal power management circuits 1201. Furthermore, the remaining power management circuits 120-1 to 120-m among all power management circuits 120-1 to 120-m may be referred to as reserve power management circuits 1203.

[0035] According to various embodiments, the power supply device 10 may include more power management circuits 120-1 to 120-m than the output terminals VOUT1 to VOUTn. Therefore, when an abnormal power management circuit is detected, the power controller can drive the power management circuits 120-1 to 120-m according to a drive sequence. However, the detected abnormal power management circuit may be negligible. The negligible power management circuit may not be used. Instead, the subsequent normal power management circuit can be used instead of the negligible power management circuit.

[0036] Figure 2 This is a view illustrating a power controller according to an embodiment of the present disclosure.

[0037] refer to Figure 2 The power controller 110 may include a sequence controller 111, an output level setter 113, a state determiner 115, and a switch controller 117.

[0038] A unique identifier (PID) can be assigned to each of the multiple power management circuits 120-1 to 120-m. X The sequence controller 111 can store the drive sequence for each of the power management circuits 120-1 to 120-m. When the sequence control signal CON is enabled, the sequence controller 111 can output the identifiers (PIDs) of the power management circuits 120-1 to 120-m to be driven in sequence, in response to the sequence control signal CON. X .

[0039] Output level setter 113 can set the level by the identifier PID X The indicated power management circuits 120-1 to 120-m provide target voltage levels OUT_LEVEL1 to OUT_LEVELx (where x is a natural number in the range 1≤x≤m).

[0040] The state determiner 115 can send a signal to the identifier PID. X The indicated power management circuits 120-1 to 120-m transmit an enable signal EN. The state determiner 115 can determine whether the power management circuits 120-1 to 120-m are operating normally based on the response signal RESP transmitted from them. When the response signal RESP is transmitted in response to the enable signal EN, the state determiner 115 can determine that the power management circuits 120-1 to 120-m are operating normally and can output a sequence control signal CON. The sequence control signal CON is provided to the sequence controller 111 to subsequently drive the power management circuits 120-1 to 120-m sequentially.

[0041] The switch controller 117 can be based on the identifiers PID of the power management circuits 120-1 to 120-m. X It operates in conjunction with the sequence control signal CON and generates switch control signals ON / OFF. The switch controller 117 can transmit the switch control signals ON / OFF to the switch circuit 130. In an example embodiment, the switch controller 117 can output an ON signal or an OFF signal depending on whether the sequence control signal CON is activated.

[0042] In the example embodiment, when the power management circuits 120-1 to 120-m to be driven sequentially transmit the response signal RESP, it is determined that normal operation is possible. For example, when the sequence control signal CON is activated, the switch controller 117 can control the switch circuit 130 to apply the output voltages OUT1 to OUTm to the output terminals VOUT1 to VOUTn. Conversely, when the power management circuits 120-1 to 120-m may malfunction, for example, when the sequence control signal CON is not activated, the switch controller 117 can control the switch circuit 130 so that the output voltages OUT1 to OUTm are not applied to the output terminals VOUT1 to VOUTn. When the internal voltages VIS1 to VIS3 can be supplied to all output terminals VOUT1 to VOUT3, the power management circuits that have not yet been driven and are in standby mode are not driven, and the power supply process terminates.

[0043] Figure 3 This is a view illustrating the operation of a power supply device according to an embodiment of the present disclosure.

[0044] Figure 3 A power supply device 10-1 is shown, which includes three normal power management circuits 1201 configured to supply voltage to three output terminals VOUT1 to VOUTn and a standby power management circuit 1203.

[0045] The power supply process with a drive sequence can be described in detail, in which the first power management circuit 120-1, the second power management circuit 120-2, the third power management circuit 120-3, and the fourth power management circuit 120-4 can be stored sequentially.

[0046] To drive the first power management circuit 120-1, the power controller 110 can provide a target voltage level OUT_LEVEL1 to the first power management circuit 120-1. When the first power management circuit 120-1 is operating normally, it can convert the external power voltage VES1 according to the target voltage level OUT_LEVEL1 to generate the output voltage OUT1.

[0047] The power controller 110 can transmit an enable signal EN to the first power management circuit 120-1 and receive a response signal RESP in response to the transmitted enable signal EN. When the first power management circuit 120-1 is operating normally, the response signal RESP can be transmitted to the power controller 110. Conversely, when the first power management circuit 120-1 is not operating normally, the response signal RESP may not be transmitted to the power controller 110.

[0048] When the first power management circuit 120-1 can operate normally, the power controller 110 can generate a switch control signal ON / OFF to control the switch SW11, thereby applying the output voltage OUT1 of the first power management circuit 120-1 to the first output terminal VOUT1.

[0049] Conversely, when the first power management circuit 120-1 malfunctions, the power controller 110 can generate a switch control signal ON / OFF to control the switch SW11, so that the output voltage OUT1 of the first power management circuit 120-1 is not applied to the first output terminal VOUT1. Therefore, the first internal circuit coupled to the first output terminal VOUT1 does not receive the first internal voltage VIS1.

[0050] According to the drive sequence, the power controller 110 can drive the second power management circuit 120-2. Based on the normal operation of the first power management circuit 120-1 and the subsequent normal operation of the second power management circuit 120-2, the power controller 110 can control the switching circuit 130.

[0051] In various embodiments, when the second power management circuit 120-2 can be operated normally after the first power management circuit 120-1 has been operated normally, the power controller 110 can control switches SW21 and SW22 to apply the output voltage OUT2 of the second power management circuit 120-2 as the internal voltage VIS2 to the second output terminal VOUT2. For example, switch SW21 can be turned off and switch SW22 can be turned on.

[0052] According to the drive sequence, power controller 110 can drive the third power management circuit 120-3. When the third power management circuit 120-3 operates normally, the output voltage OUT3 of the third power management circuit 120-3, which is the internal voltage VIS3, can be applied to the output terminal VOUT3. Because the internal voltages VIS1 to VIS3 can be supplied to all output terminals VOUT1 to VOUT3, power controller 110 can terminate the power supply process. Conversely, when the third power management circuit 120-3 does not operate normally, power controller 110 can drive the fourth power management circuit 120-4.

[0053] In various embodiments, when the first power management circuit 120-1 can be determined to be abnormal and the second power management circuit 120-2 can operate normally, the power controller 110 can control switches SW21 and SW22 to apply the output voltage OUT2 of the second power management circuit 120-2 as an internal voltage VIS1 to the first output terminal VOUT1. For example, switch SW21 can be turned on and switch SW22 can be turned off. That is, when the first power management circuit 120-1 can be determined to be abnormal, the power controller 110 can control the second power management circuit 120-2 to generate an output voltage OUT2 with a first target voltage level OUT_LEVEL1.

[0054] According to the drive sequence, the power controller 110 can drive the third power management circuit 120-3. The on / off state of switches SW31 and SW32 coupled to the third power management circuit 120-3 can be controlled based on the normal operation of the previous second power management circuit 120-2 and the subsequent normal operation of the third power management circuit 120-3.

[0055] In various embodiments, when the second power management circuit 120-2 is determined to be abnormal after the first power management circuit 120-1 has been operating normally, the power controller 110 can control switches SW21 and SW22 to prevent the use of the output voltage OUT2 of the second power management circuit 120-2. For example, switches SW21 and SW22 can be turned off. The power controller 110 can drive the third power management circuit 120-3 according to a drive sequence and control the switching circuit 130.

[0056] Similarly, based on the normal operation of the (m-1)th power management circuit and the mth power management circuit 120-m, the mth power management circuit 120-m can be controlled. For example, as Figure 3 As shown, the fourth power management circuit 120-4 can be the m-th power management circuit 120-m driven exactly after the third power management circuit 120-3. When the internal voltage VIS3 can be applied to the third output terminal VOUT3 by the third power management circuit 120-3, the power controller 110 may not drive the fourth power management circuit 120-4. Conversely, when the internal voltage VIS3 is not applied to the third output terminal VOUT3 by the third power management circuit 120-3, the power controller 110 may control the switching circuit 130 to apply the output voltage of the fourth power management circuit 120-4 to the third output terminal VOUT3. In various embodiments, the switching circuit 130 may transmit the output voltage of the fourth power management circuit 120-4 to the third output terminal VOUT3.

[0057] During the above process, all or part of the power management circuits 120-1, 120-2, 120-3 and 120-4 can be driven sequentially to apply internal voltages VIS1 to VIS3 to all output terminals VOUT1 to VOUT3.

[0058] Figure 4 This is a flowchart illustrating a power supply method according to an embodiment of the present disclosure.

[0059] refer to Figure 4 In operation S101, the power supply device 10 can initiate the power supply process by supplying an external power voltage in operation S101.

[0060] In operation S103, the power supply device 10 can select one of the power management circuits based on the drive sequence of the power management circuits.

[0061] In operation S105, the power supply device 10 can set the target voltage level of the selected power management circuit.

[0062] In operation S107, the power supply device 10 can transmit an enable signal to the selected power management circuit.

[0063] In operation S109, based on the transmission of the response signal of the selected power management circuit to the enable signal, the power supply device 10 can determine whether the selected power management circuit can operate normally.

[0064] When the power management circuit selected in operation S109 can operate normally (yes), in operation S111, the power supply device 10 can apply the output voltage of the corresponding power management circuit to the output terminal.

[0065] When power can be supplied to all output terminals during operation S113 (yes), the power supply device 10 can terminate the power supply process.

[0066] If the power management circuit selected in operation S109 may malfunction (No), and if in operation S113 there is still a possibility that no power is being supplied to its output terminal (No), the power supply device 10 may select the next power management circuit according to the drive sequence. The power supply device 10 may perform the above process in operation S103.

[0067] Figure 5 This is a view illustrating a storage system according to an embodiment of the present disclosure.

[0068] refer to Figure 5The storage system 1000 may include a host device 1100 and a data storage device 1200. In various embodiments, the data storage device 1200 may include a solid-state drive (SSD).

[0069] The data storage device 1200 may include a controller 1210, non-volatile memory devices 1220-0 to 1220-k, a buffer memory device 1230, a power supply 1240, a signal connector 1101, and a power connector 1103.

[0070] The controller 1210 can control the operation of the data storage device 1200. The controller 1210 may include a host interface circuit, a control circuit, a random access memory as operational memory, an error correction code (ECC) circuit, and a memory interface circuit.

[0071] Data storage device 1200 can receive command signal CMD and address signal ADDR through signal connector 1101. Data storage device 1200 can receive data DT from host device 1100 / transmit data DT to host device 1100 through signal connector 1101. Depending on the interface type between host device 1100 and data storage device 1200, signal connector 1101 may include various connectors.

[0072] The controller 1210 can analyze and process signals input from the host device 1100. The controller can control background function blocks according to the firmware or software used to drive the data storage device 1200.

[0073] Buffer memory device 1230 can temporarily store data stored in non-volatile memory devices 1220-0 to 1220-k. Buffer memory device 1230 can also temporarily store data read from non-volatile memory devices 1220-0 to 1220-k. Under the control of controller 1210, data temporarily stored in buffer memory device 1230 can be transferred to host device 1100 or non-volatile memory devices 1220-0 to 1220-k.

[0074] Non-volatile memory devices 1220-0 to 1220-k can be used as storage media for data storage device 1220. Each of the non-volatile memory devices 1220-0 to 1220-k can be connected to controller 1210 through multiple channels CH0 to CHk. At least one non-volatile memory device can be connected to one channel. Non-volatile memory devices connected to one channel can be connected to the same signal bus and the same data bus.

[0075] Power supply 1240 can convert the levels of external power voltages VES1 to VESt to generate internal voltages VIS1 to VISn. The external power voltages VES1 to VESt can be input via power connector 1103, which includes multiple power lines PL1 to PLt. The internal voltages VIS1 to VISn generated by power supply 1240 can be supplied to controller 1210, the memory cell array NVM CORE and input / output circuitry NVM I / O of non-volatile memory devices 1220-0 to 1220-k, buffer memory device 1230, and other circuitry. Power supply 1240 may include auxiliary power supply 1241. In the event of a potential sudden power outage, auxiliary power supply 1241 can supply power to data storage device 1200 to properly shut it down. Auxiliary power supply 1241 may include, but is not limited to, high-capacity capacitors.

[0076] The power supply 1240 may include Figures 1 to 3 The power supply device 10 in the middle. The internal voltages VIS1 to VIS3 generated from the power supply 1240 can be used as power voltages for circuits configured to receive the internal voltages.

[0077] Depending on the power supply type of the host device 1100, the power connector 1103 may include various connectors.

[0078] Figure 6 This is a diagram illustrating a data processing system 3000 according to an embodiment of the present disclosure. Reference Figure 6 The data processing system 3000 may include a host device 3100 and a storage system 3200.

[0079] The host device 3100 can be configured as a board, such as a printed circuit board. Although not shown, the host device 3100 may include internal function blocks for performing the functions of the host device.

[0080] The host device 3100 may include connection terminals 3110, such as sockets, slots, or connectors. The memory system 3200 may mate with the connection terminals 3110.

[0081] The memory system 3200 can be configured as a board, such as a printed circuit board. The memory system 3200 can be referred to as a memory module or a memory card. The memory system 3200 may include a controller 3210, a buffer memory device 3220, non-volatile memory devices 3231 and 3232, a power management integrated circuit (PMIC) 3240, and a connection terminal 3250.

[0082] The controller 3210 can control the overall operation of the memory system 3200. The controller 3210 can communicate with... Figure 1 and Figure 2 The controller 110 shown is configured in the same way.

[0083] Buffer memory device 3220 can temporarily store data to be stored in non-volatile memory devices 3231 and 3232. Furthermore, buffer memory device 3220 can temporarily store data read from non-volatile memory devices 3231 and 3232. Under the control of controller 3210, data temporarily stored in buffer memory device 3220 can be transferred to host device 3100 or non-volatile memory devices 3231 and 3232.

[0084] Non-volatile memory devices 3231 and 3232 can be used as storage media in memory system 3200.

[0085] The PMIC 3240 can supply power input via connection terminal 3250 to the internal storage system 3200. The PMIC 3240 can manage the power of the storage system 3200 according to the control of the controller 3210. The PMIC 3240 is configured to... Figures 1 to 3 The power supply device 10 described herein.

[0086] Connection terminal 3250 can be coupled to connection terminal 3110 of host device 3100. Through connection terminal 3250, signals such as commands, addresses, and data, as well as power, can be transmitted between host device 3100 and memory system 3200. Depending on the interface scheme between host device 3100 and memory system 3200, connection terminal 3250 can be configured in one or more of various types. As shown, connection terminal 3250 can be located on one side of memory system 3200.

[0087] Figure 7 This is a diagram illustrating a data processing system 4000 according to an embodiment of the present disclosure. Reference Figure 7 The data processing system 4000 may include a host device 4100 and a storage system 4200.

[0088] The host device 4100 may be configured as a board, such as a printed circuit board. Although not shown, the host device 4100 may include internal function blocks for performing the functions of the host device.

[0089] The memory system 4200 can be configured in a surface mount type package. The memory system 4200 can be mounted to the host device 4100 via solder balls 4250. The memory system 4200 may include a controller 4210, a buffer memory device 4220, and a non-volatile memory device 4230.

[0090] The controller 4210 can control the overall operation of the memory system 4200. The controller 4210 may include... Figures 1 to 3 The power supply device 10 described herein.

[0091] Buffer memory device 4220 can temporarily store data to be stored in non-volatile memory device 4230. Furthermore, buffer memory device 4220 can temporarily store data read from non-volatile memory device 4230. Under the control of controller 4210, data temporarily stored in buffer memory device 4220 can be transferred to host device 4100 or non-volatile memory device 4230.

[0092] The non-volatile memory device 4230 can be used as the storage medium of the memory system 4200.

[0093] Figure 8 This is a diagram illustrating a network system 5000 including a data storage device according to an embodiment of the present disclosure. Reference Figure 8 The network system 5000 may include a server system 5300 and multiple client systems 5410, 5420 and 5430 coupled through the network 5500.

[0094] Server system 5300 can provide data services in response to requests from multiple client systems 5410 to 5430. For example, server system 5300 can store data provided by multiple client systems 5410 to 5430. As another example, server system 5300 can provide data to multiple client systems 5410 to 5430.

[0095] Server system 5300 may include host device 5100 and storage system 5200. Storage system 5200 may include... Figures 1 to 3 The power supply device 10 described herein.

[0096] Figure 9 This is a block diagram illustrating a non-volatile memory device 300 according to an embodiment of the present disclosure, the non-volatile memory device 300 being included in a data storage device such as a data storage device 1200. Reference Figure 9 The non-volatile memory device 300 may include a memory cell array 310, a row decoder 320, a data read / write block 330, a column decoder 340, a voltage generator 350, and control logic 360.

[0097] The memory cell array 310 may include memory cells MC, which are arranged in the region where word lines WL1 to WLm and bit lines BL1 to BLn intersect.

[0098] The memory cell array 310 may include a three-dimensional memory array. For example, the three-dimensional memory array has a stacked structure in a direction perpendicular to a flat surface of the semiconductor substrate. Furthermore, a three-dimensional memory array refers to a structure including NAND strings, in which memory cells are stacked perpendicular to a flat surface of the semiconductor substrate.

[0099] The structure of a three-dimensional memory array is not limited to the embodiments indicated above. Memory array structures with both horizontal and vertical orientations can be formed in a highly integrated manner. In one embodiment, in a NAND string of a three-dimensional memory array, memory cells are arranged in both horizontal and vertical directions relative to the surface of the semiconductor substrate. The memory cells can be spaced differently to provide different levels of integration.

[0100] The row decoder 320 can be coupled to the memory cell array 310 via word lines WL1 to WLm. The row decoder 320 can operate under the control of control logic 360. The row decoder 320 can decode addresses provided by external devices (not shown). The row decoder 320 can select and drive word lines WL1 to WLm based on the decoding result. For example, the row decoder 320 can provide word line voltages provided by voltage generator 350 to word lines WL1 to WLm.

[0101] Data read / write block 330 can be coupled to memory cell array 310 via bit lines BL1 to BLn. Data read / write block 330 may include read / write circuits RW1 to RWn corresponding to bit lines BL1 to BLn, respectively. Data read / write block 330 can be operated under the control of control logic 360. Depending on the operating mode, data read / write block 330 can operate as a write driver or a sense amplifier. For example, data read / write block 330 can operate as a write driver that stores data provided by an external device into memory cell array 310 during a write operation. As another example, data read / write block 330 can operate as a sense amplifier that reads data from memory cell array 310 during a read operation.

[0102] The column decoder 340 can operate under the control of the control logic 360. The column decoder 340 can decode addresses provided by external devices. Based on the decoding results, the column decoder 340 can couple the read / write circuits RW1 to RWn of the data read / write block 330, corresponding to bit lines BL1 to BLn respectively, to the data input / output lines or data input / output buffers.

[0103] Voltage generator 350 can generate voltages to be used in the internal operation of non-volatile memory device 300. The voltages generated by voltage generator 350 can be applied to memory cells of memory cell array 310. For example, a programming voltage generated during a programming operation can be applied to the word line of the memory cell to which a programming operation is to be performed. As another example, an erase voltage generated during an erase operation can be applied to the well region of the memory cell to which an erase operation is to be performed. As yet another example, a read voltage generated during a read operation can be applied to the word line of the memory cell to which a read operation is to be performed.

[0104] Control logic 360 can control the overall operation of non-volatile memory device 300 based on control signals provided by external devices. For example, control logic 360 can control the operation of non-volatile memory device 300, such as read, write and erase operations of non-volatile memory device 300.

[0105] The embodiments described above are intended to illustrate the invention and not limit it. Various alternatives and equivalents are possible. The invention is not limited to the embodiments described herein. The invention is also not limited to any particular type of semiconductor device. Other additions, deletions, or modifications that are obvious from this disclosure are intended to fall within the scope of the appended claims. Furthermore, embodiments may be combined to form additional embodiments.

Claims

1. A power supply device, comprising: The power management circuits are configured to receive external power voltages to generate output voltages with the same or different levels. A switching circuit is electrically connected between the power management circuit and the output terminals, wherein the number of output terminals is less than the number of power management circuits. as well as A power controller is configured to drive the power management circuit sequentially according to a drive sequence, and to control the switching circuit to apply the output voltage of the power management circuit, which is the normal operating voltage of the driven power management circuit, to the output terminal.

2. The power supply device according to claim 1, The power controller sequentially drives the power management circuit by transmitting a target voltage level to the power management circuit to be driven based on the driving sequence. The output voltage corresponds to the target voltage level.

3. The power supply device of claim 2, wherein the power controller is further configured to transmit an enable signal to the driven power management circuit and determine whether the driven power management circuit is operating normally based on a response signal from the driven power management circuit to the enable signal.

4. The power supply device of claim 1, wherein the power controller is configured to sequentially drive the power management circuit until the output voltage is applied to all output terminals.

5. The power supply device according to claim 1, wherein when the power controller sequentially drives the power management circuit, the power controller is configured to control the switching circuit based on the normal operation of the previously driven power management circuit and the normal operation of the currently driven power management circuit.

6. A method for supplying power, the method comprising: A power management circuit is provided, the number of which is greater than the number of output terminals; The power management circuit is driven sequentially according to the driving sequence; The power management circuit generates an output voltage as the power management circuit is driven during normal operation. as well as The output voltage is applied to the output terminal.

7. The method according to claim 6, The sequential driving of the power management circuit includes: The power controller transmits the target voltage level to the power management circuit to be driven based on the drive sequence, and... The output voltage corresponds to the target voltage level.

8. The method according to claim 7, further comprising: The power controller transmits an enable signal to the driven power management circuit; as well as Based on the response signal from the driven power management circuit to the enable signal, it is determined whether the driven power management circuit is operating normally.

9. The method of claim 6, wherein the power management circuit is driven sequentially until the output voltage is applied to all output terminals.

10. The method of claim 6, further comprising: Based on whether the previously driven power management circuit is operating normally and whether the currently driven power management circuit is operating normally, the power controller determines the output terminal to apply the output voltage of the currently driven power management circuit.

11. A data storage system, comprising: At least one memory device; The controller is configured to exchange data with the memory device in response to a request from an external device; The output terminal includes multiple internal circuits of the memory device and the controller electrically connected to the output terminal; as well as A power supply device is configured to sequentially drive power management circuits that receive power voltages from the external device to generate output voltages having the same or different levels, and the power supply device is configured to apply the output voltages of the power management circuits as normal operation of the driven power management circuits to the output terminals, wherein the number of power management circuits is greater than the number of output terminals.

12. The data storage system according to claim 11, The power supply device is configured to sequentially drive the power management circuit by transmitting a target voltage level to the power management circuit to be driven based on a drive sequence. The output voltage corresponds to the target voltage level.

13. The data storage system according to claim 12, wherein the power supply device is further configured to: The enable signal is transmitted to the driven power management circuit; and Based on the response signal from the driven power management circuit to the enable signal, it is determined whether the driven power management circuit is operating normally.

14. The data storage system of claim 11, wherein the power supply device is configured to sequentially drive the power management circuit until the output voltage is applied to all output terminals.

15. The data storage system of claim 11, wherein the power supply device determines an output terminal to apply an output voltage of the currently driven power management circuit based on whether the previously driven power management circuit is operating normally and whether the currently driven power management circuit is operating normally.

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