A method and components for in-memory computing of edge-floating gate transistors

Abstract

This invention provides an in-memory computing method and component for edge-gate transistors. The method includes: during storage, the edge-gate transistor performs a write operation by moving electrons into a third gate and an erase operation by moving electrons out of the third gate; determining the storage state based on the current flowing between the first and second electrodes; during computation, the edge-gate transistor determines the logic input based on the voltage applied to the first gate and the voltages of the first and second electrodes; and determining the logic output based on the storage state and the current flowing between the first and second electrodes. This method enables edge-gate transistors to integrate storage and logic computation functions, improving the applicability of transistor devices and realizing in-memory computation within a single device.

Description

Technical Field

[0001] This invention relates to the field of transistor device technology, and in particular to an in-memory computing method and components for edge-floating gate transistors. Background Technology

[0002] In the past development of CMOS (Complementary Metal Oxide Semiconductor) memory, the unbalanced development speed of processors and memory has resulted in the current situation where storage speed lags far behind processor computing speed. Consequently, problems such as the memory wall, bandwidth wall, and power wall have emerged during the redistribution of storage and computing.

[0003] To overcome the bottlenecks of the von Neumann computing architecture and reduce the overhead of data movement in the "storage-memory-processing unit" process, academia and industry have tried various methods. One relatively direct approach is near-memory computing, which reduces the path between memory and processing units. However, this does not address the fundamental separation of data storage and data processing, and therefore cannot fundamentally solve the bottlenecks of the von Neumann computing architecture.

[0004] Therefore, how to further reduce the overhead caused by data migration in the "storage-computation" process and develop the in-memory logic computing capabilities within storage devices is a key issue that urgently needs to be addressed by those in this field. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides an in-memory computing method and component for edge-floating gate transistors. This method enables edge-floating gate transistors to integrate storage functions as well as AND or OR logic calculation functions, improving the applicability of transistor devices and realizing in-memory computing functions within a single device.

[0006] This invention provides a method for in-memory computing using an edge-gate transistor. The edge-gate transistor includes, from bottom to top, a first gate, a first dielectric layer, a second gate, a second dielectric layer, and a third gate; it also includes a stepped third dielectric layer, with the lower stepped surface of the third dielectric layer disposed above the first dielectric layer and the upper stepped surface of the third dielectric layer disposed above the third gate; a stepped channel layer disposed above the third dielectric layer; a first electrode disposed on the lower stepped surface of the channel layer; and a second electrode disposed on the upper stepped surface of the channel layer. Each of the first gate, the second gate, and the third gate can control the selection of a segment of the channel region of the channel layer. The method for in-memory computing using the edge-gate transistor includes: during storage, the edge-gate transistor performs a write operation by moving electrons into the third gate and an erase operation by moving electrons out of the third gate; determining the storage state based on the current flowing between the first electrode and the second electrode; during computation, the edge-gate transistor determines the logic input based on the voltage applied to the first gate and the voltages of the first electrode and the second electrode; and based on the storage state, determining the logic output based on the current flowing between the first electrode and the second electrode.

[0007] According to the present invention, an in-memory computing method for an edge-floating gate transistor is provided. When the edge-floating gate transistor is stored, a write operation is completed by electrons moving into the third gate and an erase operation is completed by electrons moving out of the third gate. The method includes: using a tunneling mechanism to allow electrons to tunnel from the channel layer through the third dielectric layer to the third gate to complete the write operation, and allowing electrons to tunnel from the third gate through the third dielectric layer to the channel layer to complete the erase operation.

[0008] According to the present invention, an in-memory computing method for an edge-floating gate transistor is provided. During storage, the edge-floating gate transistor completes the write operation by moving electrons into the third gate and completes the erase operation by moving electrons out of the third gate. The method includes: moving electrons from the second gate through the second dielectric layer to the third gate to complete the write operation by using a conductive filament mechanism, and moving electrons from the third gate through the second dielectric layer to the second gate to complete the erase operation.

[0009] According to the present invention, an in-memory computing method for an edge-gate transistor is provided. When the edge-gate transistor is stored, the storage state is determined according to the current flowing between the first electrode and the second electrode, including: a first storage state in which the absolute value of the current flowing between the first electrode and the second electrode is not greater than a preset current threshold, corresponding to the completion of a write operation; and a second storage state in which the absolute value of the current flowing between the first electrode and the second electrode is greater than the preset current threshold, corresponding to the completion of an erase operation.

[0010] According to a memory computing method for an edge-gate transistor provided by the present invention, when the edge-gate transistor performs calculations, determining the logic input based on the voltage applied to the first gate, the voltages of the first electrode, and the second electrode includes: a first logic input value corresponding to a voltage of the first gate not less than a first preset voltage threshold, and a second logic input value corresponding to a voltage of the first gate less than the first preset voltage threshold, wherein the first logic input value is opposite to the second logic input value; a third logic input value corresponding to a voltage of the second electrode relative to the first electrode greater than a second preset voltage threshold, and a fourth logic input value corresponding to a voltage of the second electrode relative to the first electrode not greater than the second preset voltage threshold, wherein the third logic input value is opposite to the fourth logic input value.

[0011] According to the present invention, an in-memory computing method for an edge-gate transistor is provided. During computation, the edge-gate transistor determines a logic output based on the storage state and the current flowing between the first electrode and the second electrode. This includes performing an AND logic operation in the first storage state, performing an OR logic operation in the second storage state, and a first logic output value corresponding to a current absolute value flowing between the first electrode and the second electrode being greater than a preset current threshold, and a second logic output value corresponding to a current absolute value flowing between the first electrode and the second electrode being less than the preset current threshold. The first logic output value is the opposite of the second logic output value.

[0012] The present invention also provides an in-memory computing device for an edge-gate transistor, comprising: a storage unit, configured to perform a write operation by moving electrons into the third gate and an erase operation by moving electrons out of the third gate during storage of the edge-gate transistor; and to determine a storage state based on the current flowing between the first electrode and the second electrode; and a computing unit, configured to determine a logic input based on the voltage applied to the first gate and the voltages of the first electrode and the second electrode during computing of the edge-gate transistor; and to determine a logic output based on the storage state and the current flowing between the first electrode and the second electrode.

[0013] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the in-memory computing method of any of the edge floating gate transistors described above.

[0014] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the in-memory computing method of the edge floating gate transistor as described above.

[0015] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the in-memory computing method of any of the edge floating gate transistors described above.

[0016] This invention provides a method and component for integrated in-memory computing using an edge-gate transistor. The method includes: during storage, the edge-gate transistor performs a write operation by moving electrons into a third gate and an erase operation by moving electrons out of the third gate; determining the storage state based on the current flowing between the first and second electrodes; during computation, the edge-gate transistor determines the logic input based on the voltage applied to the first gate and the voltages of the first and second electrodes; and determining the logic output based on the storage state and the current flowing between the first and second electrodes. This method enables the edge-gate transistor to integrate storage and logic computation functions, improving the applicability of transistor devices and realizing in-memory computation within a single device. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a schematic flowchart of an in-memory computing method for edge-floating gate transistors provided by the present invention;

[0019] Figure 2 This is a schematic diagram of the structure of an edge-floating gate transistor provided by the present invention;

[0020] Figure 3 This is a schematic diagram of the structure of an in-memory computing device with an edge-floating gate transistor provided by the present invention;

[0021] Figure 4 This is a schematic diagram of the structure of the electronic device provided by the present invention.

[0022] Figure label:

[0023] 1: First gate; 2: First dielectric layer; 3: Second gate; 4: Second dielectric layer; 5: Third gate; 6: Third dielectric layer; 7: Channel layer; 8: First electrode; 9: Second electrode. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0025] The following is combined Figures 1-4 This invention describes an in-memory computing method and components for an edge-floating gate transistor.

[0026] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating an in-memory computing method for edge-floating gate transistors provided by the present invention.

[0027] Please refer to Figure 2 , Figure 2 This is a schematic diagram of an edge-floating gate transistor provided by the present invention.

[0028] This invention provides an in-memory computing method for an edge-floating gate transistor. The edge-floating gate transistor includes, from bottom to top, a first gate 1, a first dielectric layer 2, a second gate 3, a second dielectric layer 4, and a third gate 5; it also includes a stepped third dielectric layer 6, with the lower stepped surface of the third dielectric layer 6 above the first dielectric layer 2 and the upper stepped surface of the third dielectric layer 6 above the third gate 5; a stepped channel layer 7 disposed above the third dielectric layer 6; a first electrode 8 disposed on the lower stepped surface of the channel layer 7; and a second electrode 9 disposed on the upper stepped surface of the channel layer 7. Each of the first gate 1, the second gate 3, and the third gate 5 can control the selection of a segment of the channel region of the channel layer 7.

[0029] In-memory computing methods for edge-floating gate transistors include:

[0030] 101: During storage, the edge floating gate transistor completes the write operation by moving electrons into the third gate 5 and completes the erase operation by moving electrons out of the third gate 5; the storage state is determined according to the current flowing between the first electrode 8 and the second electrode 9.

[0031] In a preferred embodiment, during storage, the edge floating gate transistor performs a write operation by moving electrons into the third gate 5 and an erase operation by moving electrons out of the third gate 5. This includes: using a tunneling mechanism to allow electrons to tunnel from the channel layer 7 through the third dielectric layer 6 to the third gate 5 to complete the write operation, and allowing electrons to tunnel from the third gate 5 through the third dielectric layer 6 to the channel layer 7 to complete the erase operation.

[0032] In a preferred embodiment, during storage, the edge floating gate transistor completes the write operation by moving electrons into the third gate 5 and completes the erase operation by moving electrons out of the third gate 5, including: moving electrons from the second gate 3 through the second dielectric layer 4 to the third gate 5 to complete the write operation by using a conductive filament mechanism, and moving electrons from the third gate 5 through the second dielectric layer 4 to the second gate 3 to complete the erase operation.

[0033] In a preferred embodiment, the edge floating gate transistor determines the storage state based on the current of the first electrode 8 and the second electrode 9 during storage, including: a first storage state where the absolute value of the current flowing between the first electrode 8 and the second electrode 9 is not greater than a preset current threshold, corresponding to the completion of a write operation; and a second storage state where the absolute value of the current flowing between the first electrode 8 and the second electrode 9 is greater than the preset current threshold, corresponding to the completion of an erase operation.

[0034] Specifically, in the process of realizing in-memory computing, the edge-floating gate transistor uses the first gate 1 as a substrate, the second gate 3 as a control gate, and the third gate 5 as a floating gate. The channel layer 7 can change the carrier concentration under the control of an electric field, serving as the channel of the field-effect transistor. The first electrode 8 and the second electrode 9 can extract the electrical signal of the channel layer 7. The edge-floating gate transistor completes the write operation by moving electrons into the third gate 5 and implements AND logic control; the edge-floating gate transistor completes the erase operation by moving electrons out of the third gate 5 and implements OR logic control.

[0035] Through a tunneling mechanism, electrons tunnel from the channel layer 7 through the vertical third dielectric layer 6 to the third gate 5 to complete the writing process, and electrons tunnel from the third gate 5 through the vertical third dielectric layer 6 to the channel layer 7 to complete the erasure process.

[0036] Through the conductive filament mechanism, the third gate 5, the second dielectric layer 4 and the second gate 3 constitute a volatile resistive random access memory. At this time, a conductive filament is formed in the second dielectric layer 4, so that electrons can move through the second gate 3 and the second dielectric layer 4 to the third gate 5 to complete the writing, and electrons can move through the third gate 5 and the second dielectric layer 4 to the second gate 3 to complete the erasure.

[0037] It is understandable that the tunneling mechanism is related to the thickness of the third dielectric layer 6, and the conductive filament mechanism is related to the thickness of the second dielectric layer 4. By adjusting the thickness of the two dielectric layers, the degree of influence of the two mechanisms can be changed.

[0038] Furthermore, when the edge floating gate transistor performs the storage function: after completing the write operation, it is in the first storage state of its memory, such as the "0" state; after completing the erase operation, it is in the second storage state of its memory, such as the "1" state.

[0039] Furthermore, when the edge-floating gate transistor implements the storage function, its storage state is read in the following manner: the first gate 1 and the second gate 3 are both fixed biased, and the voltage V1 of the first gate 1 is not less than the forward bias voltage V0; the third gate 5 is in a floating state; the first electrode 8 and the second electrode 9 are both connected to preset fixed voltage values, and the voltage V2 of the second electrode 9 relative to the first electrode 8 is less than 0; the storage state of the edge-floating gate transistor is determined by reading the absolute value I of the current passing through the first electrode 8 and the second electrode 9; if the absolute value of the current passing through the first electrode 8 and the second electrode 9 is greater than a preset current threshold, a "1" state is read; otherwise, a "0" state is read. Preferably, the preset current threshold can be 1 nA.

[0040] 102: When performing calculations, the edge floating gate transistor determines the logic input based on the voltage applied to the first gate 1 and the voltages of the first electrode 8 and the second electrode 9; and determines the logic output based on the current flowing between the first electrode 8 and the second electrode 9, according to the storage state.

[0041] In a preferred embodiment, the edge floating gate transistor determines the logic input based on the voltage applied to the first gate 1, the voltage of the first electrode 8, and the voltage of the second electrode 9 during calculation. This includes: a first logic input value corresponding to a voltage of the first gate 1 not less than a first preset voltage threshold, and a second logic input value corresponding to a voltage of the first gate 1 less than the first preset voltage threshold, wherein the first logic input value is opposite to the second logic input value; a third logic input value corresponding to a voltage of the second electrode 9 relative to the first electrode 8 greater than a second preset voltage threshold, and a fourth logic input value corresponding to a voltage of the second electrode 9 relative to the first electrode 8 not greater than the second preset voltage threshold, wherein the third logic input value is opposite to the fourth logic input value.

[0042] In a preferred embodiment, the edge floating gate transistor determines the logic output based on the storage state and the current flowing between the first electrode 8 and the second electrode 9 during calculation. This includes: performing an AND logic operation in the first storage state, performing an OR logic operation in the second storage state, and a first logic output value corresponding to the absolute value of the current flowing between the first electrode 8 and the second electrode 9 being greater than a preset current threshold, and a second logic output value corresponding to the absolute value of the current flowing between the first electrode 8 and the second electrode 9 being less than the preset current threshold. The first logic output value is the opposite of the second logic output value.

[0043] When an edge-floating gate transistor performs an AND logic operation, a write operation must have been completed; when an edge-floating gate transistor performs an OR logic operation, an erase operation must have been completed.

[0044] When implementing the AND function, the second gate 3 is fixedly biased, the third gate 5 is in a floating state, the first gate 1 is connected to voltage V1, and V1≥0V, and the voltage of the second electrode 9 relative to the first electrode 8 is V2.

[0045] When the "OR" function is implemented, the second gate 3 is fixedly biased, the third gate 5 is in a floating state, the first gate 1 is connected to voltage V1, and V1≥0V, and the voltage of the first electrode 8 relative to the second electrode 9 is V2.

[0046] Using V1 and V2 as logic inputs, V1 corresponds to the first logic input value when it is not less than the first preset voltage threshold V0, for example, inputting logic "1". V1 corresponds to the third logic input value when it is less than V0, for example, inputting logic "0". V2 corresponds to the third logic input value when it is greater than the second preset voltage threshold, for example, the second preset voltage threshold is 0, so inputting logic "1". V2 corresponds to the fourth logic input value when it is not greater than the second preset voltage threshold, for example, inputting logic "0".

[0047] And read the absolute value I of the current flowing between the first electrode 8 and the second electrode 9;

[0048] The absolute value I of the current flowing between the first electrode 8 and the second electrode 9 is used as the logic output. When I is greater than the preset current threshold, it corresponds to the first logic output value, such as outputting logic "1". When I is less than the preset current threshold, it corresponds to the second logic output value, such as inputting logic "0".

[0049] It is understandable that after the edge floating gate transistor completes the write operation by moving electrons into the third gate 5, the electrons moving into the third gate 5 turn off the channel region selected by the third gate 5; after the edge floating gate transistor completes the erase operation by moving electrons out of the third gate 5, the channel region selected by the third gate 5 turns on.

[0050] Specifically, after the write operation is completed, when implementing the AND logic control:

[0051] If V1≥V0 and V2>0, then the input logic is “1, 1”;

[0052] At this time, the channel region controlled by the first gate 1 has a high carrier concentration and is turned on. After the write operation, the channel region controlled by the third gate 5 has a low carrier concentration, but because V2 > 0, the channel layer 7 as a whole forms a semiconductor homojunction with low carrier concentration / high carrier concentration, thereby enabling I to be greater than the preset current threshold, that is, the output logic is "1".

[0053] If V1≥V0 and V2<0, then the input logic is "1, 0";

[0054] At this time, since V2 < 0, the channel layer 7 forms a semiconductor homojunction with low carrier concentration / high carrier concentration, which makes I unable to exceed the preset current threshold, i.e., the output logic is "0".

[0055] When V1 < V0, regardless of whether V2 > 0 or V2 < 0, the channel regions selected by the first gate 1 and the third gate 5 are both in the closed state, so the channel layer 7 as a whole cannot be turned on, and therefore I cannot be greater than the preset value.

[0056] Regardless of whether the input logic is "0, 1" or "0, 0", the output logic is always "0".

[0057] This enables the control of the "AND" logic.

[0058] Additionally, after the erase operation is completed, when implementing the "OR" logic control:

[0059] After the erase operation, the channel region controlled by the third gate 5 has a high carrier concentration. This region is turned on. When V1≥V0, regardless of whether V2>0 or V2<0, since the channel regions selected by the third gate 5 and the first gate 1 are both in the open state, I can be greater than the preset value.

[0060] Regardless of whether the input logic is "1, 1" or "1, 0", the output logic is always "1".

[0061] If V1 < V0 and V2 > 0, then the input logic is "0, 1";

[0062] At this time, V1 < V0, the channel region controlled by the first gate 1 has a low carrier concentration, but because V2 > 0, the channel layer 7 as a whole forms a semiconductor homojunction with high carrier concentration / low carrier concentration, thereby enabling I to be greater than the current threshold preset value, that is, the output logic is "1".

[0063] If V1 < V0 and V2 < 0, then the input logic is "0, 0";

[0064] At this time, because V2 < 0, the channel layer 7 forms a semiconductor homojunction with high carrier concentration / low carrier concentration, which makes I unable to exceed the preset current threshold, i.e., the output logic is "0".

[0065] This enables the control of the "OR" logic.

[0066] Preferably, when the edge floating gate transistor implements AND logic control, the second gate 3 is fixedly biased at 0V, the second electrode 9 is connected to a constant voltage V2, and the first electrode 8 is connected to a 0V voltage.

[0067] Preferably, when the edge floating gate transistor implements "OR" logic control, the second gate 3 is fixedly biased at 0V, the first electrode 8 is connected to a constant voltage V2, and the second electrode 9 is connected to a 0V voltage.

[0068] Understandably, in the memory "0" state, the channel region selected by the second gate 3 is in a closed state, enabling "AND" logic control. Therefore, when V1 ≥ V0 and V2 < 0, i.e., the logic input is "1, 0", the output is "0", meaning the current flowing between the first electrode 8 and the second electrode 9 approaches zero. In the memory "1" state, the channel region selected by the second gate 3 is in a closed state, enabling "OR" logic control. Therefore, when V1 ≥ V0 and V2 < 0, i.e., the logic input is "1, 0", the output is "1", meaning the current flowing between the first electrode 8 and the second electrode 9 approaches non-zero. This allows for the distinguishing between the "0" and "1" states.

[0069] It is understandable that the first electrode 8 is the drain and the second electrode 9 is the source; or, the first electrode 8 is the source and the second electrode 9 is the drain.

[0070] In summary, the method for achieving in-memory computing using edge-floating gate transistors provided by this invention enables edge-floating gate transistors to integrate storage functions as well as AND and OR logic computation functions, thereby improving the applicability of transistor devices.

[0071] In addition, the first gate 1 may be made of metal, doped semiconductor material and conductive non-metal, preferably made of heavily doped silicon material.

[0072] The first dielectric layer 2 can be made of materials such as metal oxides, non-metal oxides, two-dimensional insulating films, and flexible insulating films, and is preferably made of silicon oxide.

[0073] The second gate 3 can be made of materials such as carbon nanotubes, graphene, metals, doped semiconductor materials, and conductive non-metals, preferably made of single-layer graphene with a thickness of less than 1 nm.

[0074] The second dielectric layer 4 can be made of metal oxide, non-metal oxide, two-dimensional insulating film and / or flexible insulating film material, preferably made of alumina material.

[0075] Preferably, the third gate 5 can be made of materials such as carbon nanotubes, graphene, metals, doped semiconductor materials and / or conductive non-metals, and is preferably made of palladium.

[0076] Preferably, the third dielectric layer 6 is made of metal oxide, non-metal oxide, two-dimensional insulating film and / or flexible insulating film material, and preferably hafnium oxide material.

[0077] Preferably, the channel layer 7 is made of bulk semiconductor materials such as silicon and germanium, two-dimensional semiconductor thin films, carbon nanotubes or oxide semiconductors with semiconductor properties, and more preferably, it is made of two-dimensional molybdenum disulfide material.

[0078] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of an in-memory computing device with an edge-floating gate transistor provided by the present invention.

[0079] The present invention also provides an in-memory computing device for an edge-gate transistor, comprising: a storage unit 301, used for performing a write operation by moving electrons into the third gate 3 and an erase operation by moving electrons out of the third gate 3 during storage of the edge-gate transistor; and determining the storage state based on the current flowing between the first electrode 8 and the second electrode 9; and a computing unit 302, used for determining the logic input based on the voltage applied to the first gate 1 and the voltages of the first electrode 8 and the second electrode 9 during computing of the edge-gate transistor; and determining the logic output based on the current flowing between the first electrode 8 and the second electrode 9 based on the storage state.

[0080] For a description of the in-memory computing device with an edge-floating gate transistor provided by the present invention, please refer to the above method embodiments; the present invention will not be described again here.

[0081] Figure 4 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 4As shown, the electronic device may include: a processor 401, a communication interface 402, a memory 403, and a communication bus 404. The processor 401, communication interface 402, and memory 403 communicate with each other via the communication bus 404. The processor 401 can call logic instructions in the memory 403 to execute an in-memory computing method using an edge-floating gate transistor. The edge-floating gate transistor includes, from bottom to top, a first gate 1, a first dielectric layer 2, a second gate 3, a second dielectric layer 4, and a third gate 5; it also includes a stepped third dielectric layer 6, with the lower stepped surface of the third dielectric layer 6 above the first dielectric layer 2 and the upper stepped surface of the third dielectric layer 6 above the third gate 5; a stepped channel layer 7 disposed above the third dielectric layer 6; a first electrode 8 disposed on the lower stepped surface of the channel layer 7; and a second electrode disposed on the upper stepped surface of the channel layer 7. 9; The first gate 1, the second gate 3, and the third gate 5 can each control the selection of a segment of the channel region of the channel layer 7; The in-memory computing method of the edge floating gate transistor includes: when storing data, the edge floating gate transistor completes the write operation by moving electrons into the third gate 5 and completes the erase operation by moving electrons out of the third gate 5; the storage state is determined based on the current flowing between the first electrode 8 and the second electrode 9; when computing data, the edge floating gate transistor determines the logic input based on the voltage applied to the first gate 1 and the voltages of the first electrode 8 and the second electrode 9; and the logic output is determined based on the storage state and the current flowing between the first electrode 8 and the second electrode 9.

[0082] Furthermore, the logical instructions in the aforementioned memory 403 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0083] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the in-memory computing method for edge-gate transistors provided by the above methods. The edge-gate transistor includes a first gate 1, a first dielectric layer 2, a second gate 3, a second dielectric layer 4, and a third gate 5 arranged sequentially from bottom to top; it also includes a stepped third dielectric layer 6, with the lower stepped surface of the third dielectric layer 6 disposed above the first dielectric layer 2 and the upper stepped surface of the third dielectric layer 6 disposed above the third gate 5; a stepped channel layer 7 disposed above the third dielectric layer 6; and a channel layer 7 disposed above the third dielectric layer 6. A first electrode 8 on the lower step surface of layer 7; a second electrode 9 disposed on the upper step surface of channel layer 7; a first gate 1, a second gate 3, and a third gate 5 each capable of controlling the selection of a segment of channel region of channel layer 7; an edge-floating gate transistor in-memory computing method, comprising: when storing data, the edge-floating gate transistor performs a write operation by moving electrons into the third gate 5 and an erase operation by moving electrons out of the third gate 5; determining the storage state based on the current flowing between the first electrode 8 and the second electrode 9; when computing data, the edge-floating gate transistor determines the logic input based on the voltage applied to the first gate 1 and the voltages of the first electrode 8 and the second electrode 9; and determining the logic output based on the storage state and the current flowing between the first electrode 8 and the second electrode 9.

[0084] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements an in-memory computing method for an edge-floating gate transistor provided by the above methods. The edge-floating gate transistor includes, from bottom to top, a first gate 1, a first dielectric layer 2, a second gate 3, a second dielectric layer 4, and a third gate 5; it also includes a stepped third dielectric layer 6, the lower stepped surface of which is disposed above the first dielectric layer 2, and the upper stepped surface of which is disposed above the third gate 5; a stepped channel layer 7 disposed above the third dielectric layer 6; and a first electrode 8 disposed on the lower stepped surface of the channel layer 7. A second electrode 9 is disposed on the upper step surface of the channel layer 7; the first gate 1, the second gate 3, and the third gate 5 can each control the selection of a segment of the channel region of the channel layer 7; a memory-computing method for an edge-floating gate transistor includes: when storing data, the edge-floating gate transistor performs a write operation by moving electrons into the third gate 5 and an erase operation by moving electrons out of the third gate 5; the storage state is determined based on the current flowing between the first electrode 8 and the second electrode 9; when computing data, the edge-floating gate transistor determines the logic input based on the voltage applied to the first gate 1 and the voltages of the first electrode 8 and the second electrode 9; and the logic output is determined based on the storage state and the current flowing between the first electrode 8 and the second electrode 9.

[0085] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0086] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for in-memory computing using an edge-floating gate transistor, characterized in that, The edge-mounted floating gate transistor includes a first gate, a first dielectric layer, a second gate, a second dielectric layer, and a third gate arranged sequentially from bottom to top; it also includes a stepped third dielectric layer, wherein the lower stepped surface of the third dielectric layer is disposed above the first dielectric layer, and the upper stepped surface of the third dielectric layer is disposed above the third gate; A stepped channel layer disposed above the third medium layer; The first electrode is disposed on the lower step surface of the channel layer; A second electrode is disposed on the upper step surface of the channel layer; the first gate, the second gate, and the third gate are each capable of controlling the selection of a segment of the channel region of the channel layer; The in-memory computing method for the edge-floating gate transistor includes: During storage, the edge floating gate transistor completes the write operation by moving electrons into the third gate and completes the erase operation by moving electrons out of the third gate; the storage state is determined based on the current flowing between the first electrode and the second electrode. During computation, the edge floating gate transistor determines the logic input based on the voltage applied to the first gate and the voltages of the first and second electrodes; and determines the logic output based on the current flowing between the first and second electrodes according to the storage state.

2. The in-memory computing method for edge-floating gate transistors according to claim 1, characterized in that, During storage, the edge-mounted floating gate transistor performs a write operation by moving electrons into the third gate and an erase operation by moving electrons out of the third gate, including: The writing process involves electrons tunneling from the channel layer through the third dielectric layer to the third gate via a tunneling mechanism, and the erasure process involves electrons tunneling from the third gate through the third dielectric layer to the channel layer via a tunneling mechanism.

3. The in-memory computing method for edge-floating gate transistors according to claim 1, characterized in that, During storage, the edge-mounted floating gate transistor performs a write operation by moving electrons into the third gate and an erase operation by moving electrons out of the third gate, including: Electrons are moved from the second gate through the second dielectric layer to the third gate to complete the writing process via a conductive filament mechanism, and electrons are moved from the third gate through the second dielectric layer to the second gate to complete the erasure process.

4. The in-memory computing method for edge-floating gate transistors according to any one of claims 1 to 3, characterized in that, When the edge-mounted floating-gate transistor is stored, the storage state is determined based on the current flowing between the first electrode and the second electrode, including: The first storage state corresponds to the completion of the write operation when the absolute value of the current flowing between the first electrode and the second electrode is not greater than a preset current threshold, and the second storage state corresponds to the completion of the erase operation when the absolute value of the current flowing between the first electrode and the second electrode is greater than the preset current threshold.

5. The in-memory computing method for edge-floating gate transistors according to claim 4, characterized in that, When the edge-floating gate transistor performs calculations, determining the logic input based on the voltage applied to the first gate, the voltages of the first electrode, and the second electrode includes: When the voltage of the first gate is not less than the first preset voltage threshold, it corresponds to the first logic input value; when the voltage of the first gate is less than the first preset voltage threshold, it corresponds to the second logic input value; the first logic input value is the opposite of the second logic input value. The third logic input value is corresponding to the voltage of the second electrode relative to the first electrode being greater than the second preset voltage threshold, and the fourth logic input value is corresponding to the voltage of the second electrode relative to the first electrode not being greater than the second preset voltage threshold. The third logic input value is the opposite of the fourth logic input value.

6. The in-memory computing method for edge-floating gate transistors according to claim 5, characterized in that, During computation, the edge-floating gate transistor determines the logic output based on the storage state and the current flowing between the first and second electrodes, including: An AND logic operation is performed in the first storage state, and an OR logic operation is performed in the second storage state. When the absolute value of the current flowing between the first electrode and the second electrode is greater than the preset current threshold, a first logic output value is corresponding to the first logic output value. When the absolute value of the current flowing between the first electrode and the second electrode is less than the preset current threshold, a second logic output value is corresponding to the second logic output value. The first logic output value is the opposite of the second logic output value.

7. A memory computing device with an edge-floating gate transistor, characterized in that, The edge-mounted floating gate transistor includes a first gate, a first dielectric layer, a second gate, a second dielectric layer, and a third gate arranged sequentially from bottom to top; it also includes a stepped third dielectric layer, wherein the lower stepped surface of the third dielectric layer is disposed above the first dielectric layer, and the upper stepped surface of the third dielectric layer is disposed above the third gate; A stepped channel layer disposed above the third medium layer; The first electrode is disposed on the lower step surface of the channel layer; A second electrode is disposed on the upper step surface of the channel layer; the first gate, the second gate, and the third gate are each capable of controlling the selection of a segment of the channel region of the channel layer; The in-memory computing device of the edge-floating gate transistor includes: The storage unit is used to perform a write operation by moving electrons into the third gate and an erase operation by moving electrons out of the third gate during storage of the edge floating gate transistor; the storage state is determined based on the current flowing between the first electrode and the second electrode. A computing unit is configured to, during computation, determine logic inputs based on the voltage applied to the first gate and the voltages of the first and second electrodes of the edge floating gate transistor; and determine logic outputs based on the current flowing between the first and second electrodes according to the storage state.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the in-memory computing method of the edge floating gate transistor as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the in-memory computing method for the edge floating gate transistor as described in any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the in-memory computing method for the edge floating gate transistor as described in any one of claims 1 to 6.

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