Display panel and display device

Abstract

The display panel and the display device are provided, and the display panel comprises a substrate, a display area and a non-display area; the non-display area comprises a gate driving circuit comprising a plurality of register areas, each register area is arranged along a first direction, and each register area extends along a second direction; each register area comprises an input transistor and an output transistor; the input transistor in the same register area is located between the output transistor and the display area in the orthographic projection of the substrate.

Description

Technical Field

[0001] This invention relates to the field of display technology, and particularly to display panels and display devices. Background Technology

[0002] A liquid crystal display (LCD) is a type of display device, with the liquid crystal display panel and backlight module being its key components. Because the liquid crystal display panel may be used in high-brightness conditions, such as outdoors, a backlight module is required to provide a high-brightness light source.

[0003] Gate Driver on Array (GOA) technology integrates thin-film transistors (TFTs) from the gate driver circuit onto the array substrate of the liquid crystal display panel to drive the panel. Because light refracts within the liquid crystal layer, the portion of the gate driver circuit closest to the display area is affected by light, leading to increased leakage current in the TFTs. This results in decreased image quality and reduced reliability of the display panel. Summary of the Invention

[0004] The display panel provided in this embodiment includes:

[0005] The substrate includes the display area and the non-display area;

[0006] The non-display area includes:

[0007] A gate driving circuit includes multiple register regions, each register region being arranged along a first direction and each register region extending along a second direction;

[0008] Each register region includes an input transistor and an output transistor;

[0009] The orthographic projection of the input transistor in the same register region onto the substrate lies between the orthographic projection of the output transistor onto the substrate and the orthographic projection of the display area onto the substrate.

[0010] In some possible implementations, the gate drive circuit further includes: a plurality of first cascaded signal lines extending along the first direction;

[0011] The orthographic projection of the output transistor onto the substrate and the orthographic projection of the input transistor onto the substrate are located on different sides of the plurality of first cascaded signal lines, respectively.

[0012] In some possible implementations, each register region further includes a cascaded transistor for providing a cascaded signal to the input transistor via the first cascaded signal line;

[0013] The orthographic projection of the cascaded transistor onto the substrate lies between the orthographic projection of the first cascaded signal line onto the substrate and the orthographic projection of the output transistor onto the substrate.

[0014] In some possible implementations, the gate drive circuit further includes: a plurality of cascaded shift register units, each shift register unit including the input transistor and the output transistor; the input transistor and the output transistor in each shift register unit are disposed in different register regions.

[0015] In some possible implementations, the plurality of shift register units includes a first shift register unit and a second shift register unit, wherein the first shift register unit and the second shift register unit are cascaded.

[0016] The input transistor in the first shift register unit is located in the register region where the second shift register unit is located.

[0017] In some possible implementations, the input transistor includes: a first channel region and a second channel region arranged along the first direction, wherein the width of the first channel region in the first direction is different from the width of the second channel region in the first direction, and the length of the first channel region in the second direction is different from the length of the second channel region in the second direction.

[0018] In some possible implementations, the edge of the first channel region near the display area is aligned with the edge of the second channel region near the display area along the first direction.

[0019] In some possible implementations, the gate drive circuit further includes: a first connection hole and a second connection hole;

[0020] The cascaded transistor is connected to the first terminal of the input transistor through the first connection hole;

[0021] The cascaded transistor is connected to the gate of the input transistor through the second connection hole;

[0022] The first connection hole and the second connection hole are located between the first channel region and the first cascaded signal line in the orthographic projection of the substrate.

[0023] In some possible implementations, the orthographic projection of the first connection hole on the substrate and the orthographic projection of the second connection hole on the substrate are located on one side of the orthographic projection of the second channel region on the substrate.

[0024] In some possible implementations, the shift register unit further includes: a capacitor;

[0025] The orthographic projection of the capacitor onto the substrate lies between the orthographic projections of the input transistor onto the substrate and the orthographic projections of the output transistor onto the substrate.

[0026] In some possible implementations, the capacitor has a first notch;

[0027] The projection of the second electrode of the input transistor onto the substrate overlaps with the projection of the first notch onto the substrate.

[0028] The orthographic projection of the gate of the output transistor onto the substrate overlaps with the orthographic projection of the first notch onto the substrate.

[0029] The gate of the output transistor is coupled to the second terminal of the input transistor.

[0030] In some possible implementations, the gate drive circuit further includes: a third connection hole;

[0031] The orthographic projection of the third connecting hole on the substrate overlaps with the orthographic projection of the first notch on the substrate.

[0032] In some possible implementations, the gate drive circuit further includes: a plurality of second cascaded signal lines and a plurality of clock signal lines extending along the second direction;

[0033] The orthographic projection of the clock signal line onto the substrate lies between the orthographic projection of the second cascaded signal line onto the substrate and the orthographic projection of the output transistor onto the substrate.

[0034] In some possible implementations, the spacing between adjacent clock signal lines and the second cascaded signal lines along the first direction is not less than 10 micrometers.

[0035] In some possible implementations, the channel width of the input transistor is greater than the channel width of the output transistor, and the channel width of the input transistor is greater than the channel width of the cascaded transistor.

[0036] This disclosure also provides a display device, including the display panel described above. Attached Figure Description

[0037] Figure 1 Some structural schematic diagrams of the display panel provided in the embodiments of this disclosure;

[0038] Figure 2 These are some other structural schematic diagrams of the display panel provided in the embodiments of this disclosure;

[0039] Figure 3 Further structural schematic diagrams of the display panel provided in embodiments of this disclosure;

[0040] Figure 4 These are schematic diagrams of some structural layouts of the display panel provided in embodiments of this disclosure;

[0041] Figure 5 Further structural schematic diagrams of the display panel provided in embodiments of this disclosure;

[0042] Figure 6 Other structural layout diagrams of the display panel provided in embodiments of this disclosure;

[0043] Figure 7 Further structural schematic diagrams of the display panel provided in embodiments of this disclosure;

[0044] Figure 8 Further schematic diagrams of the structural layout of the display panel provided in embodiments of this disclosure;

[0045] Figure 9 Other equivalent circuit diagrams provided for embodiments of this disclosure;

[0046] Figure 10 Some equivalent circuit diagrams provided for embodiments of this disclosure;

[0047] Figure 11 Further schematic diagrams of the structural layout of the display panel provided in embodiments of this disclosure;

[0048] Figure 12 Further schematic diagrams of the structural layout of the display panel provided in embodiments of this disclosure;

[0049] Figure 13 Further equivalent circuit diagrams are provided for embodiments of this disclosure;

[0050] Figure 14 Further schematic diagrams of the structural layout of the display panel provided in embodiments of this disclosure;

[0051] Figure 15 Further schematic diagrams of the structural layout of the display panel provided in embodiments of this disclosure;

[0052] Figure 16 Further schematic diagrams of the structural layout of the display panel provided in embodiments of this disclosure;

[0053] Figure 17 Further schematic diagrams of the structural layout of the display panel provided in embodiments of this disclosure;

[0054] Figure 18 Further schematic diagrams of the structural layout of the display panel provided in embodiments of this disclosure;

[0055] Figure 19 Some equivalent circuit diagrams are provided for embodiments of this disclosure. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Furthermore, the embodiments and features in the embodiments of the present invention can be combined with each other without conflict. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0057] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0058] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0059] For example, such as Figure 1 and Figure 2As shown, a liquid crystal display (LCD) panel generally includes a substrate 100 and a color filter substrate 200 disposed opposite each other, and a liquid crystal layer 300 disposed between the substrate 100 and the color filter substrate 200, wherein the liquid crystal layer 300 contains a plurality of liquid crystal particles. When the display panel is displaying an image, voltages are applied to the pixel electrodes on the substrate and the common electrode on the color filter substrate to control the deflection of the liquid crystal particles. The light source for the display panel is provided by a backlight module 400. When the light source enters the liquid crystal layer 300, the light is refracted in the liquid crystal layer 300, causing the gate driving circuit 10 near the display area AA to be affected by the refracted light. This results in an increase in the leakage current of the output transistor M2 near the display area AA, leading to problems such as decreased image quality and reduced reliability.

[0060] In view of the above problems, this disclosure provides a display panel, such as... Figure 3 and Figure 4 As shown, it includes:

[0061] The substrate 100 includes a display area AA and a non-display area BB;

[0062] The non-display area BB includes:

[0063] The gate driving circuit 10 includes a plurality of register regions 20, each register region 20 being arranged along a first direction F1 and each register region 20 extending along a second direction F2;

[0064] Each register region 20 includes an input transistor M1 and an output transistor M2;

[0065] The orthographic projection of the input transistor M1 in the same register region 20 onto the substrate 100 lies between the orthographic projection of the output transistor M2 onto the substrate 100 and the orthographic projection of the display area AA onto the substrate 100.

[0066] This embodiment of the disclosure places the orthographic projection of the input transistor in the same register region onto the substrate between the orthographic projection of the output transistor on the substrate and the orthographic projection of the display area on the substrate. In other words, by placing the output transistor away from the display area, the output transistor is less affected by light, thereby reducing leakage current and improving display quality and reliability.

[0067] It should be noted that the input transistor provides the necessary signals to the gate drive circuit, while the output transistor provides the necessary signals to the display panel. Therefore, the input transistor is located close to the display area, and even if leakage current occurs in the input transistor, it will not directly affect the image quality of the display panel. Furthermore, in the existing technology, the input transistor is relatively close to the output transistor, so changing the position of the input transistor will not have a significant impact on the wiring and space of the display panel.

[0068] In some embodiments of this disclosure, such as Figure 5 and Figure 6 As shown, the gate drive circuit 10 further includes: multiple first cascaded signal lines IN1, which extend along a first direction F1; the orthographic projection of the output transistor M2 on the substrate 100 and the orthographic projection of the input transistor M1 on the substrate 100 are located on different sides of the multiple first cascaded signal lines IN1, respectively.

[0069] For example, by setting the orthographic projection of the output transistor on the substrate and the orthographic projection of the input transistor on the substrate to be located on different sides of multiple first cascaded signal lines, the space of the display panel can be saved to a great extent, thereby maximizing space utilization.

[0070] In some embodiments of this disclosure, such as Figure 5 and Figure 6 As shown, each register region 20 also includes a cascaded transistor M3, which is used to provide a cascaded signal to the input transistor M1 through the first cascaded signal line IN1; the orthographic projection of the cascaded transistor M3 on the substrate 100 is located between the orthographic projection of the first cascaded signal line IN1 on the substrate 100 and the orthographic projection of the output transistor M2 on the substrate 100.

[0071] For example, by placing the cascaded transistor between the first cascaded signal line and the output transistor, this disclosure can reduce the distance between the cascaded transistor and the input transistor, thereby further reducing the trace length and saving space.

[0072] For example, such as Figures 3 to 6 As shown, the non-display area BB also includes a common signal line COM, which is used to provide a common signal for the display area AA.

[0073] In some embodiments of this disclosure, the gate drive circuit further includes: a plurality of cascaded shift register units, each shift register unit including an input transistor M1 and an output transistor M2; the input transistor and the output transistor in each shift register unit are disposed in different register regions.

[0074] In some embodiments of this disclosure, a plurality of shift register units include a first shift register unit and a second shift register unit, which are cascaded together; the input transistor M1 in the first shift register unit is located in the register region where the second shift register unit is located.

[0075] For example, this disclosure cascades a first shift register unit and a second shift register unit; the input transistor in the first shift register unit is located in the register region where the second shift register unit is located. This reduces the trace length required for cascading the first shift register unit and the second shift register unit, thereby saving space and maximizing space utilization.

[0076] For example, such as Figure 7 As shown, the gate drive circuit 10 further includes: a plurality of cascaded shift register units (e.g., Figure 7 In the numbers 30-1, 30-2, 30-3, and 30-4, each shift register unit (e.g., ...) Figure 7 30-1, 30-2, 30-3, and 30-4 in the diagram include an input transistor M1 and an output transistor M2; each shift register unit (e.g., Figure 7 The input transistor M1 and output transistor M2 in (30-1, 30-2, 30-3, 30-4) are located in different register regions (e.g. Figure 7 In 20-1, 20-2, 20-3, 20-4).

[0077] For example, the nth shift register unit is cascaded with the (n+1)th shift register unit. Then, the input transistor M1 of shift register unit 30-2 is located in register region 20-1, and the output transistor M2 of shift register unit 30-2 is located in register region 20-2; the input transistor M1 of shift register unit 30-3 is located in register region 20-2, and the output transistor M2 of shift register unit 30-3 is located in register region 20-3; the input transistor M1 of shift register unit 30-4 is located in register region 20-3, and the output transistor M2 of shift register unit 30-4 is located in register region 20-4. Alternatively, if the nth shift register unit is cascaded with the (n+5)th shift register unit, then the input transistor M1 of shift register unit 30-n is located in register region 20-(n-5), and the output transistor M2 of shift register unit 30-n is located in register region 20-n.

[0078] For example, such as Figure 7As shown, shift register unit 30-1 includes a first shift register unit (not shown in the figure) and a second shift register unit 302-1; shift register unit 30-2 includes a first shift register unit 301-2 and a second shift register unit 302-2; shift register unit 30-3 includes a first shift register unit 301-3 and a second shift register unit 302-3; and shift register unit 30-4 includes a first shift register unit 301-4 and a second shift register unit 302-4. The first shift register unit 301-2 and the second shift register unit 302-1 are cascaded together, with the input transistor M1 of the first shift register unit 301-2 located in register region 20-1 where the second shift register unit 302-1 is located; the first shift register unit 301-3 and the second shift register unit 302-2 are cascaded together, with the input transistor M1 of the first shift register unit 301-3 located in register region 20-2 where the second shift register unit 302-2 is located; the first shift register unit 301-4 and the second shift register unit 302-3 are cascaded together, with the input transistor M1 of the first shift register unit 301-4 located in register region 20-3 where the second shift register unit 302-3 is located.

[0079] For example, such as Figure 8 The structural layout shown and as follows Figure 9The equivalent circuit diagram shown may further include: a fourth transistor M4, a fifth transistor M5, a fifth auxiliary transistor M5', a sixth transistor M6, a sixth auxiliary transistor M6', a seventh transistor M7, an eighth transistor M8, an eighth auxiliary transistor M8', a ninth transistor M9, a ninth auxiliary transistor M9', a tenth transistor M10, a tenth auxiliary transistor M10', an eleventh transistor M11, an eleventh auxiliary transistor M11', a twelfth transistor M12, a fourteenth transistor M14, a fourteenth auxiliary transistor M14', and a capacitor C; wherein, the gate of the input transistor M1 is coupled to the cascaded input signal terminal IP, and the first terminal of the input transistor M1 is coupled to the cascaded input signal terminal IP. The second terminal of input transistor M1 is coupled to the first node N1; the gate of output transistor M2 is coupled to the first node N1, the first terminal of output transistor M2 is coupled to the clock signal terminal CLK, and the second terminal of output transistor M2 is coupled to the output signal terminal OT; the gate of cascaded transistor M3 is coupled to the first node N1, the first terminal of cascaded transistor M3 is coupled to the clock signal terminal CLK, and the second terminal of cascaded transistor M3 is coupled to the cascaded output signal terminal OP; the gate of the seventh transistor M7 is coupled to the frame start signal terminal STV, the first terminal of the seventh transistor M7 is coupled to the first node N1, and the second terminal of the seventh transistor M7 is coupled to the first reference voltage terminal VSS1; the gate of the fourth transistor M4 is coupled to the reset signal terminal RST. The first terminal of transistor M4 is coupled to the first node N1, and the second terminal of the fourth transistor M4 is coupled to the first reference voltage terminal VSS1; the gate of the fourteenth transistor M14 is coupled to the first terminal of the input transistor M1, the first terminal of the fourteenth transistor M14 is coupled to the second node N2, and the second terminal of the fourteenth transistor M14 is coupled to the first reference voltage terminal VSS1; the gate of the fourteenth auxiliary transistor M14' is coupled to the first terminal of the input transistor M1, the first terminal of the fourteenth auxiliary transistor M14' is coupled to the third node N3, and the second terminal of the fourteenth auxiliary transistor M14' is coupled to the first reference voltage terminal VSS1; the gate of the tenth transistor M10 is coupled to the second node N2, and the first terminal of the tenth transistor M10 is coupled to the first node N1. 1. The second terminal of the tenth transistor M4 is coupled to the first reference voltage terminal VSS1; the gate of the tenth auxiliary transistor M10' is coupled to the third node N3, the first terminal of the tenth auxiliary transistor M10' is coupled to the first node N1, and the second terminal of the tenth auxiliary transistor M10' is coupled to the first reference voltage terminal VSS1; the gate of the eighth transistor M8 is coupled to the first node N1, the first terminal of the eighth transistor M8 is coupled to the gate of the ninth transistor M9, and the second terminal of the eighth transistor M8 is coupled to the first reference voltage terminal VSS1; the gate of the sixth transistor M6 is coupled to the first node N1, the first terminal of the sixth transistor M6 is coupled to the third node N3, and the second terminal of the sixth transistor M6 is coupled to the first reference voltage terminal VSS1.The gate of the eighth auxiliary transistor M8' is coupled to the first node N1, the first terminal of the eighth auxiliary transistor M8' is coupled to the gate of the ninth auxiliary transistor M9', and the second terminal of the eighth auxiliary transistor M8' is coupled to the first reference voltage terminal VSS1; the gate of the sixth auxiliary transistor M6' is coupled to the first node N1, the first terminal of the sixth auxiliary transistor M6' is coupled to the second node N2, and the second terminal of the sixth auxiliary transistor M6' is coupled to the first reference voltage terminal VSS1; the gate of the eleventh transistor M11 is coupled to the third node N3, the first terminal of the eleventh transistor M11 is coupled to the output signal terminal OT, and the second terminal of the eleventh transistor M11 is coupled to the second terminal of the twelfth transistor M12; the gate of the eleventh auxiliary transistor M11' is coupled to the second node N2, the first terminal of the eleventh auxiliary transistor M11' is coupled to the output signal terminal OT, and the second terminal of the eleventh auxiliary transistor M11' is coupled to the second terminal of the twelfth transistor M12; the gate of the twelfth transistor M12 is coupled to the reset terminal. The signal terminal RST is coupled; the first terminal of the twelfth transistor M12 is coupled to the cascaded output signal terminal OP; the gate of the fifth transistor M5 is coupled to the third reference voltage terminal VDD1, the first terminal of the fifth transistor M5 is coupled to the third reference voltage terminal VDD1, and the second terminal of the fifth transistor M5 is coupled to the gate of the ninth transistor M9; the first terminal of the ninth transistor M9 is coupled to the third reference voltage terminal VDD1, and the second terminal of the ninth transistor M9 is coupled to the third node N3; the gate of the fifth auxiliary transistor M5' is coupled to the fourth reference voltage terminal VDD2, the first terminal of the fifth auxiliary transistor M5' is coupled to the fourth reference voltage terminal VDD2, and the second terminal of the fifth auxiliary transistor M5' is coupled to the gate of the ninth auxiliary transistor M9'; the first terminal of the ninth auxiliary transistor M9' is coupled to the fourth reference voltage terminal VDD2, and the second terminal of the ninth auxiliary transistor M9' is coupled to the second node N2; the first electrode of capacitor C is coupled to the first node N1, and the second electrode of capacitor C is coupled to the output signal terminal OT.

[0080] By way of example, this disclosure can also be applied to other equivalent circuit diagrams, such as Figure 10The equivalent circuit diagram shown may further include: a fourth transistor M4, a fifth transistor M5, a fifth auxiliary transistor M5', a sixth transistor M6, a sixth auxiliary transistor M6', a seventh transistor M7, an eighth transistor M8, an eighth auxiliary transistor M8', a ninth transistor M9, a ninth auxiliary transistor M9', a tenth transistor M10, a tenth auxiliary transistor M10', an eleventh transistor M11, an eleventh auxiliary transistor M11', a twelfth transistor M12, a twelfth auxiliary transistor M12', and a capacitor C; wherein, the gate of the input transistor M1 is coupled to the cascaded input signal terminal IP, the first terminal of the input transistor M1 is coupled to the cascaded input signal terminal IP, and the second terminal of the input transistor M1... The gate of the output transistor M2 is coupled to the first node N1; the first terminal of the output transistor M2 is coupled to the clock signal terminal CLK, and the second terminal of the output transistor M2 is coupled to the output signal terminal OT; the gate of the cascaded transistor M3 is coupled to the first node N1; the first terminal of the cascaded transistor M3 is coupled to the clock signal terminal CLK, and the second terminal of the cascaded transistor M3 is coupled to the cascaded output signal terminal OP; the gate of the seventh transistor M7 is coupled to the frame start signal terminal STV; the first terminal of the seventh transistor M7 is coupled to the first node N1, and the second terminal of the seventh transistor M7 is coupled to the first reference voltage terminal VSS1; the gate of the fourth transistor M4 is coupled to the reset signal terminal RST, and the first terminal of the fourth transistor M4 is coupled to the first reference voltage terminal VSS1; The gate of the tenth transistor M10 is coupled to the first node N1, and the second terminal of the fourth transistor M4 is coupled to the first reference voltage terminal VSS1. The gate of the tenth auxiliary transistor M10' is coupled to the third node N3, and the first terminal of the tenth auxiliary transistor M10' is coupled to the first terminal of the tenth transistor M10. The second terminal of the tenth auxiliary transistor M10' is coupled to the first reference voltage terminal VSS1. The gate of the eighth transistor M8 is coupled to the first node N1, and the first terminal of the eighth transistor M8 is coupled to the gate of the ninth transistor M9. The second terminal of transistor M8 is coupled to the first reference voltage terminal VSS1; the gate of the sixth transistor M6 is coupled to the first node N1, the first terminal of the sixth transistor M6 is coupled to the second node N2, and the second terminal of the sixth transistor M6 is coupled to the first reference voltage terminal VSS1; the gate of the eighth auxiliary transistor M8' is coupled to the first node N1, the first terminal of the eighth auxiliary transistor M8' is coupled to the gate of the ninth auxiliary transistor M9', and the second terminal of the eighth auxiliary transistor M8' is coupled to the first reference voltage terminal VSS1; the gate of the sixth auxiliary transistor M6' is coupled to the first node N1, the first terminal of the sixth auxiliary transistor M6' is coupled to the third node N3, and the second terminal of the sixth auxiliary transistor M6' is coupled to the first reference voltage terminal VSS1;The gate of the eleventh auxiliary transistor M11' is coupled to the third node N3, the first terminal of the eleventh auxiliary transistor M11' is coupled to the output signal terminal OT, and the second terminal of the eleventh auxiliary transistor M11' is coupled to the second reference voltage terminal VSS2; the gate of the twelfth auxiliary transistor M12' is coupled to the third node N3, the first terminal of the twelfth auxiliary transistor M12' is coupled to the cascaded output signal terminal OP, and the second terminal of the twelfth auxiliary transistor M12' is coupled to the first reference voltage terminal VSS1; the gate of the twelfth transistor M12 is coupled to the second node N2, the first terminal of the twelfth transistor M12 is coupled to the cascaded output signal terminal OP, and the second terminal of the twelfth auxiliary transistor M12' is coupled to the first reference voltage terminal VSS1; the gate of the eleventh transistor M11 is coupled to the second node N2, the first terminal of the eleventh transistor M11 is coupled to the output signal terminal OT, and the second terminal of the eleventh auxiliary transistor M11' is coupled to the second reference voltage terminal VSS2. The fifth transistor M5 is coupled to the third reference voltage terminal VSS2; the gate of the fifth transistor M5 is coupled to the third reference voltage terminal VDD1, the first electrode of the fifth transistor M5 is coupled to the third reference voltage terminal VDD1, and the second electrode of the fifth transistor M5 is coupled to the gate of the ninth transistor M9; the first electrode of the ninth transistor M9 is coupled to the third reference voltage terminal VDD1, and the second electrode of the ninth transistor M9 is coupled to the second node N2; the gate of the fifth auxiliary transistor M5' is coupled to the fourth reference voltage terminal VDD2, the first electrode of the fifth auxiliary transistor M5' is coupled to the fourth reference voltage terminal VDD2, and the second electrode of the fifth auxiliary transistor M5' is coupled to the gate of the ninth auxiliary transistor M9'; the first electrode of the ninth auxiliary transistor M9' is coupled to the fourth reference voltage terminal VDD2, and the second electrode of the ninth auxiliary transistor M9' is coupled to the third node N3; the first electrode of capacitor C is coupled to the first node N1, and the second electrode of capacitor C is coupled to the output signal terminal OT.

[0081] For example, depending on the direction of signal flow, the first electrode of the transistor mentioned in this embodiment can be used as its source and the second electrode can be used as its drain; or, the first electrode can be used as its drain and the second electrode as its source, without making a specific distinction here.

[0082] It should be noted that the transistors mentioned in the embodiments of this disclosure can be thin film transistors (TFTs) or metal oxide semiconductor field-effect transistors (MOSs), and are not limited here.

[0083] In some embodiments of this disclosure, such as Figure 11As shown, the input transistor M1 includes a first channel region G1 and a second channel region G2 arranged along a first direction F1. The width of the first channel region G1 in the first direction F1 is different from the width of the second channel region G2 in the first direction F1, and the length of the first channel region G1 in the second direction F2 is different from the length of the second channel region G2 in the second direction F2.

[0084] For example, this disclosure can save space and maximize space utilization by making the width of the first channel region different from the width of the second channel region and the length of the first channel region different from the length of the second channel region.

[0085] In some embodiments of this disclosure, such as Figure 11 As shown, the edge of the first channel region G1 near the display area AA is aligned with the edge of the second channel region G2 near the display area AA along the first direction F1.

[0086] In some embodiments of this disclosure, such as Figure 11 As shown, the gate drive circuit 10 further includes: a first connection hole K1 and a second connection hole K2;

[0087] The cascaded transistor M3 is connected to the first terminal of the input transistor M1 through the first connection hole K1;

[0088] The cascaded transistor M3 is connected to the gate of the input transistor through the second connection hole K2;

[0089] The orthographic projection of the first connection hole K1 on the substrate 100 and the orthographic projection of the second connection hole K2 on the substrate 100 are located between the orthographic projection of the first channel region G1 on the substrate 100 and the orthographic projection of the first cascaded signal line IN1 on the substrate 100.

[0090] For example, the first connecting hole may include one, two, three, four, five, etc., depending on the requirements, and is not limited here. The second connecting hole may include four, five, six, seven, eight, etc., depending on the requirements, and is not limited here.

[0091] In some embodiments of this disclosure, such as Figure 11 As shown, the orthographic projection of the first connection hole K1 on the substrate 100 and the orthographic projection of the second connection hole K2 on the substrate 100 are located on one side of the orthographic projection of the second channel region G2 on the substrate.

[0092] For example, such as Figure 12 The structural layout shown and as follows Figure 13The equivalent circuit diagram shown may further include the following gate drive circuit: a fourth transistor M4, a fifth transistor M5, a fifth auxiliary transistor M5', a sixth transistor M6, a sixth auxiliary transistor M6', a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a ninth auxiliary transistor M9', a tenth transistor M10, a tenth auxiliary transistor M10', an eleventh transistor M11, an eleventh auxiliary transistor M11', a twelfth transistor M12, a twelfth auxiliary transistor M12', and a capacitor C; wherein, the gate of the input transistor M1 is coupled to the cascaded input signal terminal IP, the first terminal of the input transistor M1 is coupled to the output signal terminal OT, and the second terminal of the input transistor M1 is coupled to the first node N1; The gate of output transistor M2 is coupled to the first node N1, the first terminal of output transistor M2 is coupled to the clock signal terminal CLK, and the second terminal of output transistor M2 is coupled to the output signal terminal OT. The gate of cascaded transistor M3 is coupled to the first node N1, the first terminal of cascaded transistor M3 is coupled to the clock signal terminal CLK, and the second terminal of cascaded transistor M3 is coupled to the cascaded output signal terminal OP. The gate of fourth transistor M4 is coupled to the clock signal terminal CLK, the first terminal of fourth transistor M4 is coupled to the first node N1, and the second terminal of fourth transistor M4 is coupled to the first reference voltage terminal VSS1. The gate of seventh transistor M7 is coupled to the reset signal terminal RST, and the first terminal of seventh transistor M7 is coupled to the output signal terminal OT. The second terminal of the seventh transistor M7 is coupled to the first reference voltage terminal VSS1; the gate of the eighth transistor M8 is coupled to the reset signal terminal RST, the first terminal of the eighth transistor M8 is coupled to the first node N1, and the second terminal of the eighth transistor M8 is coupled to the first reference voltage terminal VSS1; the gate of the fifth transistor M5 is coupled to the third reference voltage terminal VDD1, the first terminal of the fifth transistor M5 is coupled to the third reference voltage terminal VDD1, and the second terminal of the fifth transistor M5 is coupled to the gate of the sixth transistor M6; the first terminal of the sixth transistor M6 is coupled to the third reference voltage terminal VDD1, and the second terminal of the sixth transistor M6 is coupled to the first terminal of the eleventh transistor M11; the gate of the eleventh transistor M11 is coupled to the tenth transistor... The gate of transistor M10 is coupled to the first reference voltage terminal VSS1; the second terminal of the eleventh transistor M11 is coupled to the first reference voltage terminal VSS1; the first terminal of the tenth transistor M10 is coupled to the second terminal of the fifth transistor M5; the second terminal of the tenth transistor M4 is coupled to the first reference voltage terminal VSS1; the gate of the twelfth transistor M12 is coupled to the second terminal of the sixth transistor M6; the first terminal of the twelfth transistor M12 is coupled to the cascaded output signal terminal OP; the second terminal of the twelfth transistor M12 is coupled to the first reference voltage terminal VSS1; the gate of the ninth transistor M9 is coupled to the second terminal of the sixth transistor M6; the first terminal of the ninth transistor M9 is coupled to the first node N1; the second terminal of the ninth transistor M9 is coupled to the first reference voltage terminal VSS1.The gate of the ninth auxiliary transistor M9' is coupled to the second terminal of the sixth auxiliary transistor M6', the first terminal of the ninth auxiliary transistor M9' is coupled to the first node N1, and the second terminal of the ninth auxiliary transistor M9' is coupled to the first reference voltage terminal VSS1; the gate of the twelfth auxiliary transistor M12' is coupled to the second terminal of the sixth auxiliary transistor M6', the first terminal of the twelfth auxiliary transistor M12' is coupled to the cascaded output signal terminal OP, and the second terminal of the twelfth auxiliary transistor M12' is coupled to the first reference voltage terminal VSS1; the gate of the eleventh auxiliary transistor M11' is coupled to the gate of the tenth auxiliary transistor M10', the first terminal of the eleventh auxiliary transistor M11' is coupled to the second terminal of the sixth auxiliary transistor M6', and the second terminal of the eleventh auxiliary transistor M11' is coupled to the first node N1. A reference voltage terminal VSS1 is coupled; the gate of the sixth auxiliary transistor M6' is coupled to the second terminal of the fifth auxiliary transistor M5', and the first terminal of the sixth auxiliary transistor M6' is coupled to the fourth reference voltage terminal VDD2; the gate of the fifth auxiliary transistor M5' is coupled to the fourth reference voltage terminal VDD2, and the first terminal of the fifth auxiliary transistor M5' is coupled to the first terminal of the tenth auxiliary transistor M10'; the gate of the tenth auxiliary transistor M10' is coupled to the gate of the eleventh auxiliary transistor M11', and the second terminal of the tenth auxiliary transistor M10' is coupled to the first reference voltage terminal VSS1; the first electrode of capacitor C is coupled to the first node N1, and the second electrode of capacitor C is coupled to the output signal terminal OT.

[0093] In some embodiments of this disclosure, such as Figure 14 As shown, the shift register unit 20 further includes a capacitor C; wherein the orthogonal projection of the capacitor C onto the substrate 100 is located between the orthogonal projections of the input transistor M1 onto the substrate 100 and the output transistor M2 onto the substrate 100.

[0094] In some embodiments of this disclosure, such as Figure 14 As shown, capacitor C has a first notch 00; the orthographic projection of the second electrode of input transistor M1 onto substrate 100 overlaps with the orthographic projection of the first notch 00 onto substrate 100; the orthographic projection of the gate of output transistor M2 onto substrate 100 overlaps with the orthographic projection of the first notch 00 onto substrate 100; the gate of output transistor M2 is coupled to the second electrode of input transistor M1.

[0095] For example, this disclosure can further save space and maximize space utilization by making the capacitor have a first notch, and setting the second terminal of the input transistor at the notch and the gate of the output transistor at the notch.

[0096] In some embodiments of this disclosure, such as Figure 14As shown, the gate drive circuit 10 further includes a third connection hole K3; wherein the orthographic projection of the third connection hole K3 on the substrate 100 overlaps with the orthographic projection of the first notch 00 on the substrate 100.

[0097] In some embodiments of this disclosure, such as Figure 14 As shown, the gate drive circuit 10 further includes: multiple second cascaded signal lines IN2 and multiple clock signal lines clk extending along the second direction F2; wherein, the orthogonal projection of the clock signal line clk onto the substrate 100 is located between the orthogonal projection of the second cascaded signal line IN2 onto the substrate 100 and the orthogonal projection of the output transistor M2 onto the substrate 100.

[0098] In some embodiments of this disclosure, such as Figure 14 As shown, the spacing between adjacent clock signal lines clk and the second cascaded signal line IN2 along the first direction F1 is not less than 10 micrometers.

[0099] For example, by ensuring that the spacing between adjacent clock signal lines and second cascaded signal lines along the first direction is not less than one micrometer, this disclosure can prevent the clock signal lines from coupling with the second cascaded signal lines, avoid affecting the gate drive circuit, and thus improve display quality.

[0100] For example, such as Figures 15 to 18 The structural layout shown and as follows Figure 19The equivalent circuit diagram shown may further include the following gate drive circuit: fourth transistor M4, fifth transistor M5, fifth auxiliary transistor M5', sixth transistor M6, sixth auxiliary transistor M6', seventh transistor M7, eighth transistor M8, eighth auxiliary transistor M8', ninth transistor M9, ninth auxiliary transistor M9', tenth transistor M10, tenth auxiliary transistor M10', eleventh transistor M11, eleventh auxiliary transistor M11', twelfth transistor M12, twelfth auxiliary transistor M12', sixteenth transistor M16, sixteenth auxiliary transistor M16', and capacitor C; wherein, the gate of input transistor M1 is coupled to the cascaded input signal terminal IP, and the first electrode of input transistor M1... The gate of the cascaded transistor M2 is coupled to the cascaded input signal terminal IP, and the second terminal of the input transistor M1 is coupled to the first node N1; the gate of the output transistor M2 is coupled to the first node N1, the first terminal of the output transistor M2 is coupled to the clock signal terminal CLK, and the second terminal of the output transistor M2 is coupled to the output signal terminal OT; the gate of the cascaded transistor M3 is coupled to the first node N1, the first terminal of the cascaded transistor M3 is coupled to the clock signal terminal CLK, and the second terminal of the cascaded transistor M3 is coupled to the cascaded output signal terminal OP; the gate of the seventh transistor M7 is coupled to the frame start signal terminal STV, the first terminal of the seventh transistor M7 is coupled to the first node N1, and the second terminal of the seventh transistor M7 is coupled to the first reference voltage terminal VSS1; the gate of the fourth transistor M4 is coupled to the first reference voltage terminal VSS1; the gate of the fourth transistor M4 is coupled to the first node N1, the second terminal of the seventh transistor M7 is coupled to the first reference voltage terminal VSS1; the gate of the fourth transistor M4 is coupled to the first node N1, the second terminal of the seventh transistor M7 is coupled to the first node N1, and the second terminal of the seventh transistor M7 is coupled to the first reference voltage terminal VSS1; the gate of the fourth transistor M4 is coupled to the first node N1, the second terminal of the seventh transistor M7 ... The gate of the tenth transistor M10 is coupled to the reset signal terminal RST. The first terminal of the fourth transistor M4 is coupled to the first node N1, and the second terminal of the fourth transistor M4 is coupled to the first reference voltage terminal VSS1. The gate of the tenth transistor M10 is coupled to the second node N2. The first terminal of the tenth transistor M10 is coupled to the first terminal of the tenth auxiliary transistor M10', and the second terminal of the tenth transistor M10 is coupled to the first reference voltage terminal VSS1. The gate of the tenth auxiliary transistor M10' is coupled to the third node N3, and the second terminal of the tenth auxiliary transistor M10' is coupled to the first reference voltage terminal VSS1. The gate of the eighth transistor M8 is coupled to the first node N1, and the first terminal of the eighth transistor M8 is coupled to the gate of the fifth transistor M5. The second terminal of the sixth transistor M6 is coupled to the first reference voltage terminal VSS1; the gate of the sixth transistor M6 is coupled to the first node N1, the first terminal of the sixth transistor M6 is coupled to the second node N2, and the second terminal of the sixth transistor M6 is coupled to the first reference voltage terminal VSS1; the gate of the sixteenth transistor M16 is coupled to the cascaded input signal terminal IP, the first terminal of the sixteenth transistor M16 is coupled to the second node N2, and the second terminal of the sixteenth transistor M16 is coupled to the first reference voltage terminal VSS1; the gate of the eighth auxiliary transistor M8' is coupled to the first node N1, the first terminal of the eighth auxiliary transistor M8' is coupled to the gate of the fifth auxiliary transistor M5', and the second terminal of the eighth auxiliary transistor M8' is coupled to the first reference voltage terminal VSS1;The gate of the sixth auxiliary transistor M6' is coupled to the first node N1, the first terminal of the sixth auxiliary transistor M6' is coupled to the third node N3, and the second terminal of the sixth auxiliary transistor M6' is coupled to the first reference voltage terminal VSS1; the gate of the sixteenth auxiliary transistor M16' is coupled to the cascaded input signal terminal IP, the first terminal of the sixteenth auxiliary transistor M16' is coupled to the third node N3, and the second terminal of the sixteenth auxiliary transistor M16' is coupled to the first reference voltage terminal VSS1; the gate of the eleventh auxiliary transistor M11' is coupled to the third node N3, and the eleventh auxiliary transistor M11'... The first terminal of the eleventh auxiliary transistor M11' is coupled to the output signal terminal OT, and the second terminal of the eleventh auxiliary transistor M11' is coupled to the second reference voltage terminal VSS2; the gate of the twelfth auxiliary transistor M12' is coupled to the third node N3, the first terminal of the twelfth auxiliary transistor M12' is coupled to the cascaded output signal terminal OP, and the second terminal of the twelfth auxiliary transistor M12' is coupled to the first reference voltage terminal VSS1; the gate of the twelfth transistor M12 is coupled to the second node N2, the first terminal of the twelfth transistor M12 is coupled to the cascaded output signal terminal OP, and the second terminal of the twelfth auxiliary transistor M12' is coupled to the second reference voltage terminal VSS1; the gate of the twelfth transistor M12 is coupled to the second node N2, and the first terminal of the twelfth transistor M12 is coupled to the cascaded output signal terminal OP, and the second terminal of the twelfth auxiliary transistor M12' is coupled to the second reference voltage terminal VSS1. The eleventh transistor M11 is coupled to the first reference voltage terminal VSS1; the gate of the eleventh transistor M11 is coupled to the second node N2, the first terminal of the eleventh transistor M11 is coupled to the output signal terminal OT, and the second terminal of the eleventh transistor M11 is coupled to the second reference voltage terminal VSS2; the gate of the ninth transistor M9 is coupled to the third reference voltage terminal VDD1, the first terminal of the ninth transistor M9 is coupled to the third reference voltage terminal VDD1, and the second terminal of the ninth transistor M9 is coupled to the gate of the fifth transistor M5; the first terminal of the fifth transistor M5 is coupled to the third reference voltage terminal VDD1, and the fifth transistor... The second terminal of transistor M5 is coupled to the second node N2; the gate of the ninth auxiliary transistor M9' is coupled to the fourth reference voltage terminal VDD2, the first terminal of the ninth auxiliary transistor M9' is coupled to the fourth reference voltage terminal VDD2, the second terminal of the ninth auxiliary transistor M9' is coupled to the gate of the fifth auxiliary transistor M5'; the first terminal of the fifth auxiliary transistor M5' is coupled to the fourth reference voltage terminal VDD2, and the second terminal of the fifth auxiliary transistor M5' is coupled to the third node N3; the first electrode of capacitor C is coupled to the first node N1, and the second electrode of capacitor C is coupled to the output signal terminal OT.

[0101] In some embodiments of this disclosure, such as Figures 3 to 19 As shown, the channel width of the input transistor M1 is greater than the channel width of the output transistor M2, and the channel width of the input transistor M1 is greater than the channel width of the cascaded transistor M3.

[0102] This disclosure improves display quality by making the channel width of the input transistor greater than that of the output transistor, and the channel width of the input transistor greater than that of the cascaded transistors. Even if the channel width of the input transistor is large, the leakage current of the input transistor can be reduced, thereby reducing the influence of the light from the display area on the input transistor and improving the display quality.

[0103] It should be noted that the channel width of a transistor affects the leakage current of the transistor; a larger channel width can further reduce the leakage current of the transistor.

[0104] For example, the channel width of the input transistor can be 4.3µm, etc., and can be set according to the requirements. No limit is set here.

[0105] For example, the output transistor and cascaded transistors can be 4.0um, etc., and can be set according to the requirements. No limit is set here.

[0106] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel described above in the embodiments of the present invention. The principle by which this display device solves the problem is similar to that of the aforementioned display panel; therefore, the implementation of this display device can refer to the implementation of the aforementioned display panel, and the repeated parts will not be described again here.

[0107] In specific implementations, in the embodiments of the present invention, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting the present invention.

[0108] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0109] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A display panel, characterized in that, include: The substrate includes the display area and the non-display area; The non-display area includes: A gate driving circuit includes multiple register regions, each register region being arranged along a first direction and each register region extending along a second direction; Each of the aforementioned register regions includes an input transistor and an output transistor; The orthographic projection of the input transistor in the same register region onto the substrate is located between the orthographic projection of the output transistor onto the substrate and the orthographic projection of the display area onto the substrate. The gate driving circuit further includes: a plurality of first cascaded signal lines, wherein the first cascaded signal lines extend along the first direction; The orthographic projection of the output transistor onto the substrate and the orthographic projection of the input transistor onto the substrate are respectively located on different sides of the plurality of first cascaded signal lines; The input transistor includes: a first channel region and a second channel region arranged along the first direction, wherein the width of the first channel region in the first direction is different from the width of the second channel region in the first direction, and the length of the first channel region in the second direction is different from the length of the second channel region in the second direction. The edge of the first channel region near the display area is aligned with the edge of the second channel region near the display area along the first direction.

2. The display panel as described in claim 1, characterized in that, Each of the register regions further includes a cascaded transistor for providing a cascaded signal to the input transistor via the first cascaded signal line; The orthographic projection of the cascaded transistor onto the substrate lies between the orthographic projection of the first cascaded signal line onto the substrate and the orthographic projection of the output transistor onto the substrate.

3. The display panel as described in claim 2, characterized in that, The gate drive circuit further includes: a plurality of cascaded shift register units, each of the shift register units including the input transistor and the output transistor; the input transistor and the output transistor in each of the shift register units are disposed in different register regions.

4. The display panel as described in claim 3, characterized in that, The plurality of shift register units includes a first shift register unit and a second shift register unit, wherein the first shift register unit and the second shift register unit are cascaded. The input transistor in the first shift register unit is located in the register region where the second shift register unit is located.

5. The display panel as described in any one of claims 2-4, characterized in that, The gate driving circuit further includes: a first connection hole and a second connection hole; The cascaded transistor is connected to the first terminal of the input transistor through the first connection hole; The cascaded transistor is connected to the gate of the input transistor through the second connection hole; The first connection hole and the second connection hole are located between the first channel region and the first cascaded signal line in the orthographic projection of the substrate.

6. The display panel as described in claim 5, characterized in that, The first connecting hole and the second connecting hole are projected onto the substrate in the orthographic projection of the substrate, and are located on one side of the second channel region in the orthographic projection of the substrate.

7. The display panel as described in claim 3 or 4, characterized in that, The shift register unit also includes: a capacitor; The orthographic projection of the capacitor onto the substrate lies between the orthographic projections of the input transistor onto the substrate and the orthographic projections of the output transistor onto the substrate.

8. The display panel as described in claim 7, characterized in that, The capacitor has a first notch; The projection of the second electrode of the input transistor onto the substrate overlaps with the projection of the first notch onto the substrate. The orthographic projection of the gate of the output transistor onto the substrate overlaps with the orthographic projection of the first notch onto the substrate. The gate of the output transistor is coupled to the second terminal of the input transistor.

9. The display panel as described in claim 8, characterized in that, The gate driving circuit further includes: a third connection hole; The orthographic projection of the third connecting hole on the substrate overlaps with the orthographic projection of the first notch on the substrate.

10. The display panel as described in claim 8 or 9, characterized in that, The gate drive circuit further includes: multiple second-cascaded signal lines and multiple clock signal lines extending along the second direction; The orthographic projection of the clock signal line onto the substrate lies between the orthographic projection of the second cascaded signal line onto the substrate and the orthographic projection of the output transistor onto the substrate.

11. The display panel as claimed in claim 10, characterized in that, The spacing between adjacent clock signal lines and the second cascaded signal lines along the first direction is not less than 10 micrometers.

12. The display panel as claimed in claim 11, characterized in that, The channel width of the input transistor is greater than the channel width of the output transistor, and the channel width of the input transistor is greater than the channel width of the cascaded transistor.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1-12.

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