Nano-ampere current source with process voltage temperature compensation capability and design method

Abstract

The application discloses a nano-ampere current source with process voltage temperature compensation capability and a design method, comprising a current bias circuit and an adaptive constant current bias voltage generating circuit; the current bias circuit is used for realizing nano-ampere sub-threshold current bias; the bias voltage generating circuit is used for extracting the characteristics of a target circuit under different processes, power supply voltages and temperature conditions, so as to obtain a corresponding bias voltage variation characteristic curve and guide the construction of the current bias circuit. The nano-ampere current source with process voltage temperature compensation capability can not only provide accurate current bias for a sub-threshold circuit, but also has the ability to resist process, power supply voltage and temperature fluctuations, and can avoid the use of large-size current mirror MOS tubes, thereby saving the layout area.

Description

Technical Field

[0001] This invention relates to the field of CMOS integrated circuits, and more particularly to a nanoampere-level current source and its design method with process voltage and temperature compensation capability. Background Technology

[0002] With the widespread adoption of portable electronic devices and the rapid development of IoT technology, power consumption has become an increasingly prominent issue. In the field of CMOS integrated circuit design, biasing the MOSFET in the circuit to a subthreshold operating state is an effective way to reduce power consumption in order to achieve low-power circuit module design. When the MOSFET is in a subthreshold state, its gate-source voltage is less than the threshold voltage, and the channel current is generally in the nA range. At this time, the circuit device still has amplification characteristics and can work normally.

[0003] MOSFETs in subthreshold operating state are not stable. When the gate-source voltage decreases and the channel current is in the pA range, the MOSFET enters the cutoff state, and the device loses its amplification function. When the gate-source voltage increases and the MOSFET enters the saturation region, the channel current increases rapidly to the μA level. Although the circuit device still has amplification characteristics at this time, it can no longer meet the requirements of low power consumption applications.

[0004] Existing subthreshold current biasing circuits are implemented using current mirrors, which typically employ a large-scale mirror structure, requiring a significant amount of layout area. Furthermore, because the current mirror transistor operates in the saturation region while the target bias transistor operates in the subthreshold region, their operating states differ, resulting in less than ideal current biasing accuracy. Some subthreshold current biasing circuits use voltage biasing; however, a fixed voltage bias is easily affected by process technology, power supply voltage, and temperature. When aiming for a 10nA current bias, the current value may be lower than 1nA or higher than 100nA under different process voltage temperatures (PVTs), exhibiting poor robustness. Summary of the Invention

[0005] The technical problem to be solved by this invention is to provide a nanoampere-level current source and its design method that has process voltage and temperature compensation capability, addressing the various shortcomings of existing subthreshold current bias circuits.

[0006] To solve the above-mentioned technical problems, embodiments of the present invention provide a current source circuit, including: a current bias circuit and an adaptive constant current bias voltage generation circuit;

[0007] The current bias circuit is used to implement nanoampere-level subthreshold current bias, including: a process voltage and temperature sampling module, a bias calculation module, and a target bias module;

[0008] The process voltage and temperature sampling module is used to detect changes in process, power supply voltage, and temperature, obtain a reference sampling voltage, and transmit the reference sampling voltage to the bias calculation module.

[0009] The bias operation module is used to perform level transformation on the reference sampling voltage to obtain an intermediate voltage, and output the intermediate voltage to the target bias module;

[0010] The target bias module is used to achieve nanoampere-level subthreshold current bias based on the intermediate voltage;

[0011] The bias voltage generation circuit is used to extract the process, power supply voltage, and temperature characteristics of the target bias module to obtain the corresponding bias voltage change characteristic curve, which guides the construction of the current bias module; it includes: a simulated target bias module and a constant current bias voltage module;

[0012] The constant current bias voltage module is used to collect the bias voltage change rate under the conditions of process, power supply voltage and temperature changes, and the output terminal is connected to the simulated target bias module.

[0013] The simulated target bias module has the same structure as the target bias module and is used to simulate the electrical characteristics of the target bias module under constant current conditions. Its output terminal is connected to the constant current bias voltage module.

[0014] Preferably, the process voltage and temperature sampling module includes: a microampere-level current bias, a first MOSFET, and a unity-gain amplifier; the source of the first MOSFET is connected to the power supply voltage; the gate and drain of the first MOSFET are connected and connected to the input terminal of the current bias and the input terminal of the unity-gain amplifier; the output terminal of the unity-gain amplifier is connected to the bias operation module; the unity-gain amplifier is used to gain the output signal.

[0015] Preferably, the unity-gain amplifier includes a first operational amplifier; the non-inverting input terminal of the first operational amplifier is connected to the gate of the first MOS transistor; the inverting input terminal of the first operational amplifier is shorted to the output terminal of the first operational amplifier; the output terminal of the first operational amplifier is connected to the bias operation module, and outputs the reference sampling voltage to the bias operation module.

[0016] Preferably, the bias operation module includes four resistors and a second operational amplifier; the reference sampling voltage is transmitted to the non-inverting input of the second operational amplifier through the first resistor; the first reference voltage is transmitted to the non-inverting input of the second operational amplifier through the second resistor; the second reference voltage is transmitted to the inverting input of the second operational amplifier through the third resistor; the inverting input of the second operational amplifier is shorted to the output of the second operational amplifier through the fourth resistor; the output of the second operational amplifier is connected to the target bias module and outputs an intermediate voltage to the target bias module.

[0017] Preferably, the target bias module includes a second MOS transistor and a third MOS transistor; the gate of the second MOS transistor is connected to the output terminal of the bias operation module to receive the intermediate voltage; the source of the second MOS transistor is connected to the power supply voltage, and the drain is connected to the drain of the third MOS transistor; the gate of the third MOS transistor is connected to a third reference voltage.

[0018] Preferably, the simulated target bias module includes a fourth MOS transistor and a fifth MOS transistor; the fourth MOS transistor has the same structure as the second MOS transistor; and the fifth MOS transistor has the same structure as the third MOS transistor.

[0019] Preferably, the source of the fourth MOS transistor is connected to the power supply voltage, and its drain is connected to the drain of the fifth MOS transistor; the source of the fifth MOS transistor is connected to the input terminal of the constant current bias voltage module, and its gate is connected to the third reference voltage; the gate of the fourth MOS transistor is connected to the output terminal of the constant current bias voltage module.

[0020] Preferably, the constant current bias voltage module includes a fifth resistor and a third operational amplifier; one end of the fifth resistor is connected to the output terminal of the analog target bias module, and the other end is grounded; the non-inverting input terminal of the third amplifier is connected to the output terminal of the analog target bias module, the inverting input terminal is connected to a fourth reference voltage, and the output terminal is connected to the input terminal of the analog target bias module.

[0021] Preferably, the adaptive constant current bias voltage generating circuit has a feedback function; when the current in the constant current bias voltage module increases, the output voltage of the constant current bias voltage module will increase; the output voltage of the simulated target bias module will decrease, thereby suppressing the increase of the current in the constant current bias voltage module; and vice versa; thus realizing feedback to the adaptive constant current bias voltage generating circuit.

[0022] This invention also provides a design method for a nanoampere-level current source with process voltage and temperature compensation capability, applied to the aforementioned nanoampere-level current source, comprising the following steps:

[0023] S1: Target bias voltage characteristic extraction: By scanning under different temperatures, power supply voltages, and process conditions using the adaptive constant current bias voltage generation circuit, the constant current bias voltage characteristics of the target circuit can be extracted, and the rate of change curve of the bias voltage under constant current conditions can be obtained.

[0024] S2: Process voltage and temperature sampling MOSFET design: Select the same type of MOSFET as the target bias module as the MOSFET of the process voltage and temperature sampling module. Based on the temperature scan bias voltage change rate curve, the power supply voltage scan bias voltage change rate curve, and the process scan bias voltage change curve, select an appropriate MOSFET size for the process voltage and temperature sampling module so that the reference sampling voltage has the same voltage change rate as the target MOSFET under process scan and power supply voltage scan conditions.

[0025] S3: Bias selection for bias operation module: By comparing the DC operating point of the reference sampling voltage with that of the target bias voltage, the fixed bias voltage at the input terminal of the bias operation module is selected so that the output bias voltage is consistent with the adaptive constant current bias voltage.

[0026] Implementing the embodiments of the present invention has the following beneficial effects:

[0027] (1) This embodiment of the invention uses a bias voltage generation circuit to obtain the constant current bias voltage characteristics of the target circuit under different process, power supply voltage, and temperature conditions. The bias voltage characteristics are then used to adjust the process voltage and temperature sampling module and the bias calculation module. This embodiment of the invention can provide accurate current bias for subthreshold circuits, while also possessing the ability to resist process, power supply voltage, and temperature fluctuations. It exhibits strong robustness and maintains normal operating performance under different process, power supply voltage, and temperature conditions, achieving low power consumption and resource overhead. It also avoids the use of large-size current mirror MOSFETs, saving layout area. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the current bias circuit structure provided in the first embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of the adaptive constant current bias voltage generation circuit structure provided in the first embodiment of the present invention;

[0031] Figure 3This is a flowchart of a nanoampere-level current source design method with process voltage and temperature compensation capability provided in the second embodiment of the present invention;

[0032] Figure 4 This is a temperature scanning bias voltage change rate curve provided in the third embodiment of the present invention;

[0033] Figure 5 This is a power supply voltage scanning bias voltage change rate curve provided in the third embodiment of the present invention;

[0034] Figure 6 This is a process scan bias voltage variation curve provided in the third embodiment of the present invention;

[0035] Figure 7 This is the current bias diagram after PVT compensation provided in the third embodiment of the present invention. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] Example 1

[0038] Please see Figure 1 , Figure 2 This invention provides a nano-ampere-level current source with process voltage and temperature compensation capability. The nano-ampere-level current source with process voltage and temperature compensation capability includes a current bias circuit and an adaptive constant current bias voltage generation circuit. The current bias circuit is used to achieve nano-ampere (nA) level subthreshold current bias. The current bias circuit includes a process voltage and temperature (PVT) sampling module 10, a bias voltage calculation module 20, and a target bias module 30. The PVT sampling module 10 is used to detect changes in process voltage, power supply voltage, and temperature to obtain a reference sampling voltage V0, and transmits the reference sampling voltage V0 to the bias voltage calculation module 20. The bias voltage calculation module 20 is used to perform level transformation on the reference sampling voltage V0 to obtain an intermediate voltage VB, and outputs the intermediate voltage VB to the target bias module 30. The target bias module 30 is used to achieve nA level subthreshold current bias based on the intermediate voltage VB.

[0039] The adaptive constant current bias voltage generation circuit is used to extract the characteristics of the target circuit under different process, power supply voltage, and temperature conditions to obtain the corresponding bias voltage change characteristic curve, guiding the construction of the current bias circuit. The bias voltage generation circuit includes a simulated target bias module 40 and a constant current bias voltage module 50. The constant current bias voltage module 50 is used to collect the bias voltage change rate under varying process, power supply voltage, and temperature conditions, and its output terminal is connected to the simulated target bias module 40. The simulated target bias module 40 has the same structure as the target bias module 30 and is used to simulate the electrical characteristics of the target bias module 30 under constant current conditions. The output terminal of the simulated target bias module 40 is connected to the constant current bias voltage module 50.

[0040] Please see again Figure 1 The PVT sampling module 10 includes a microamp (μA) level current biaser (I0), a first MOSFET (M1), and a unity-gain amplifier 110. The source of the first MOSFET (M1) is connected to the power supply voltage VDD. The gate and drain of the first MOSFET are connected to the input terminals of the current biaser I0 and the unity-gain amplifier 110. The output terminal of the unity-gain amplifier 110 is connected to the bias operation module 20, outputting the reference sampling voltage V0 to the bias operation module 20. The unity-gain amplifier 110 is used to amplify the output signal. The unity-gain amplifier 110 includes a first operational amplifier (OPA1). The non-inverting input terminal of the first operational amplifier is connected to the gate of the first MOSFET. The inverting input terminal of the first operational amplifier is shorted to the output terminal of the first operational amplifier.

[0041] The bias operation module 20 includes four resistors (R0-R3) and a second operational amplifier (OPA2). The reference sampling voltage V0 is transmitted to the non-inverting input (VP) of the second operational amplifier through the first resistor R0. The first reference voltage V1 is transmitted to the non-inverting input of the second operational amplifier through the second resistor R1. The second reference voltage V2 is transmitted to the inverting input (VN) of the second operational amplifier through the third resistor R2. The inverting input of the second operational amplifier is shorted to the output of the second operational amplifier through the fourth resistor R3. The output of the second operational amplifier is connected to the target bias module 30, outputting an intermediate voltage VB to the target bias module 30.

[0042] The target bias module 30 is a common-source amplifier circuit structure with current source bias. The current in the circuit is determined by the bias voltage of the current-biased MOSFET. It includes a second MOSFET (M2) and a third MOSFET (M3). The gate of the second MOSFET is connected to the output terminal of the bias operation module to receive the intermediate voltage VB. The source of the second MOSFET is connected to the power supply voltage VDD, and its drain is connected to the drain of the third MOSFET. The gate of the third MOSFET is connected to the third reference voltage VIN.

[0043] Please see again Figure 2 The constant current bias voltage module 50 includes a fifth resistor (R4) and a third operational amplifier (OPA3). One end of the fifth resistor is connected to the output terminal of the analog target bias module 40, receiving the output voltage VP3 of the analog target bias module 40, and the other end is grounded. The non-inverting input terminal of the third amplifier is connected to the output terminal of the analog target bias module 40, receiving the output voltage VP3 of the analog target bias module 40. The inverting input terminal of the third amplifier is connected to the fourth reference voltage V3, and the output terminal is connected to the input terminal of the analog target bias module 40. The fifth resistor is a sampling resistor, a large-value resistor, which cannot be directly implemented in integrated circuit design. The selection of the sampling resistor R4 and the fourth reference voltage V3 in the constant current bias voltage module 50 determines the magnitude of the expected bias current IB. According to Ohm's law and the characteristics of the operational amplifier, the value of the bias current IB is V3 / R4.

[0044] The simulated target bias module 40 has the same structure as the target bias module 30, including a fourth MOSFET (M4) and a fifth MOSFET (M5). The fourth MOSFET has the same structure as the second MOSFET; the fifth MOSFET has the same structure as the third MOSFET. The source of the fourth MOSFET is connected to the power supply voltage VDD, and the drain is connected to the drain of the fifth MOSFET. The source of the fifth MOSFET is connected to the input terminal of the constant current bias voltage module 50, and the gate is connected to the third reference voltage VIN. The gate of the fourth MOSFET is connected to the output terminal of the constant current bias voltage module 50 to receive the bias voltage VFB. Since the simulated target bias module 40 has the same structure as the target bias module 30, when the intermediate voltage VB is equal to the bias voltage VFB, the currents conducted by the second MOSFET and the fourth MOSFET are equal, both being IB. Therefore, under different process, power supply voltage, and temperature conditions, the characteristics of the target circuit can be determined, and the intermediate voltage VB can be constructed based on the bias voltage VFB, thus achieving nA-level subthreshold current bias of the target circuit.

[0045] Furthermore, the bias voltage generation circuit has a feedback structure, providing feedback functionality and current stabilization capability. When the current across the sampling resistor R4 in the constant current bias voltage module 50 increases, the non-inverting input voltage VP3 of the third operational amplifier OPA3 increases, thus increasing the output bias voltage VFB of the third operational amplifier. The absolute value of the gate-source voltage of the fourth MOS transistor M4 in the analog target bias module 40 decreases, thereby reducing the bias current. This effect, superimposed on the sampling resistor R4, suppresses the increase in current. When the current across the sampling resistor R4 in the constant current bias voltage module 50 decreases, the non-inverting input voltage VP3 of the third operational amplifier OPA3 decreases, thus reducing the output bias voltage VFB of the third operational amplifier. The absolute value of the gate-source voltage of the fourth MOS transistor M4 in the analog target bias module 40 increases, thus increasing the bias current. This effect, superimposed on the sampling resistor R4, suppresses the decrease in current. This achieves the feedback function of the bias voltage generation circuit, enhancing current stability.

[0046] Example 2

[0047] Please see Figure 3 The present invention also provides a design method for a nanoampere-level current source with process voltage and temperature compensation capability, which is applied to the nanoampere-level current source with process voltage and temperature compensation capability in the above embodiment 1. The design method specifically includes the following steps:

[0048] S1: Target bias voltage characteristic extraction: By scanning under different temperatures, power supply voltages, and process conditions using the adaptive constant current bias voltage generation circuit, the constant current bias voltage characteristics of the target circuit can be extracted, and the rate of change curve of the bias voltage under constant current conditions can be obtained.

[0049] S2: PVT Sampling MOSFET Design: Select the same type of MOSFET as the target bias module as the MOSFET of the PVT sampling module. Based on the temperature scan bias voltage change rate curve, the power supply voltage scan bias voltage change rate curve, and the process scan bias voltage change curve, select an appropriate PVT sampling module MOSFET size so that the reference sampling voltage has the same voltage change rate as the target MOSFET under process scan and power supply voltage scan conditions.

[0050] S3: Bias selection for bias operation module: By comparing the DC operating point of the reference sampling voltage with that of the target bias voltage, the fixed bias voltage at the input terminal of the bias operation module is selected so that the output bias voltage is consistent with the adaptive constant current bias voltage.

[0051] In short, the bias voltage characteristics of the target circuit under constant current conditions are first obtained by using an adaptive constant current bias voltage generation circuit that cannot be installed in the field of integrated circuit design. Then, the construction of the PVT sampling module and bias calculation module is guided by the voltage characteristics. Finally, the intermediate voltage VB is transmitted to the target bias module to achieve nA-level subthreshold current bias of the target circuit.

[0052] Example 3

[0053] Please see Figures 4-7 The present invention also provides a nanoampere-level current source with process voltage temperature compensation capability. The structure of the nanoampere-level current source with process voltage temperature compensation capability is the same as in Embodiment 1, wherein the fourth reference voltage V3 is 100mV, the sampling resistor R4 is 10MΩ, and the bias current IB is 10nA. A temperature scan is performed on the adaptive constant current bias voltage generation circuit within the range of -40℃ to 125℃ to obtain... Figure 4 The temperature-scanned bias voltage change rate curve is shown. This curve reflects the relationship between the bias voltage change rate d(VFB) / dT in the constant current bias voltage module 50 under constant current conditions and temperature. The change rate is less than 2% within the range of -40℃ to 125℃, which can be considered as the bias voltage change rate d(VFB) / dT in the constant current bias voltage module 50 remaining essentially constant with temperature. (The last sentence appears to be incomplete and possibly refers to a different curve.) Figure 4 The rate of change at T=27℃ in the temperature scanning voltage change rate curve is used as a reference, and the bias voltage VFB can be approximated as having a linear relationship with temperature. Furthermore, by performing a temperature scan on the PVT sampling module 10 within the range of -40℃ to 125℃, the relationship curve of the reference sampling voltage change rate d(VREF) / dT versus temperature in the PVT sampling circuit 1 can be obtained. This curve is affected by the width W of the first MOS transistor M1 in the PVT sampling module 10. Adjusting the number of parallel connections of the first MOS transistor M1 can adjust the total width without changing the size of individual MOS transistors, thereby adjusting the relationship curve of the reference sampling voltage change rate d(VREF) / dT versus temperature. This ensures that the value of the reference sampling voltage change rate d(VREF) / dT versus temperature at the reference temperature T=27℃ is equal to the value of the bias voltage change rate d(VFB) / dT versus temperature at T=27℃. This allows the bias voltage VFB to guide the construction of the PVT sampling module 10.

[0054] The adaptive constant current bias voltage generation circuit is scanned with a power supply voltage VDD within the range of 2.25V to 2.75V to obtain... Figure 5The curve shown is a power supply voltage scan bias voltage change rate curve. This curve reflects the relationship between the bias voltage change rate d(VFB) / d(VDD) in the constant current bias voltage module 50 and the power supply voltage under constant current conditions. The change rate is less than 1% in the range of 2.25V to 2.75V, which indicates that the bias voltage change rate d(VFB) / d(VDD) in the constant current bias voltage module 50 remains essentially constant with changes in the power supply voltage. (The last sentence appears to be incomplete and possibly refers to a different curve.) Figure 5 The rate of change of VDD = 2.5V in the power supply voltage scan rate of change curve is used as a reference, and the bias voltage VFB and the power supply voltage VDD can be approximately considered to have a linear relationship. By scanning the power supply voltage within the range of 2.25V to 2.75V on the PVT sampling module 10, the relationship curve of the reference sampling voltage change rate d(VREF) / d(VDD) versus the power supply voltage in the PVT sampling module 10 can be obtained. Since the gate-source voltage of the first MOS transistor M1 in the PVT sampling module 10 is constant under constant current bias, the value of d(VREF) / d(VDD) can be considered to be 1 at different voltages.

[0055] The adaptive constant current bias voltage generation circuit was scanned under three process angles (SS, TT, FF) to obtain... Figure 6 The process scan bias voltage variation curve is shown. Let the horizontal axis corresponding to the SS process angle be -1, the TT process angle be 0, and the FF process angle be 1. By performing linear fitting on these three process points, the bias voltage variation rate with the process can be obtained. The error between the fitted curve and the original process point is less than 0.1%, indicating that the bias voltage variation rate d(VFB) / d(Process) in the constant current bias voltage module 50 remains essentially constant with process changes. The bias voltage VFB and the power supply voltage VDD can be approximated as having a linear relationship. The PVT sampling module 10 performs process scans under SS, TT, and FF conditions, and the curve showing the relationship between the reference sampling voltage VREF in the PVT sampling module 10 and the process variation can be fitted. The curve is affected by the length L of the first MOSFET M1 in the PVT sampling module 10. By adjusting the length of the first MOSFET M1, the slope of the curve showing the relationship between the reference sampling voltage VREF and the process can be changed, thereby making the rate of change of the reference sampling voltage d(VREF) / d(Process) in the PVT sampling module 10 equal to the rate of change of the bias voltage d(VFB) / d(Process) in the constant current bias voltage module 50. This allows the bias voltage VFB to guide the construction of the PVT sampling module 10.

[0056] The above process involves scanning the rate of change of the bias voltage VFB in the constant current bias voltage module 50 under different conditions of temperature T, power supply voltage VDD, and process, to obtain a linear relationship between the rate of change of the bias voltage and temperature, power supply voltage, and process. This guides the design of the size of the first MOSFET M1 in the PVT sampling module 10, ensuring that the reference sampling voltage VREF has the same rate of change as the bias voltage VFB in the constant current bias voltage module 50. As can be seen from the current stability characteristics of the adaptive constant current bias voltage generation circuit, the reference sampling voltage VREF in the PVT sampling module 10 also possesses the ability to compensate for process, power supply voltage, and temperature variations.

[0057] The above design process yields a reference sampling voltage VREF with PVT compensation capability. Since the on-current of the first MOSFET M1 in the PVT sampling circuit is not equal to the on-current of the MOSFET M4 in the target bias circuit module 4, the absolute values ​​of the reference sampling voltage VREF and the bias voltage VFB are not equal. Under standard conditions, i.e., TT process corner, 2.5V power supply voltage, and 27℃, the reference sampling voltage VREF is denoted as VREF*, and the bias voltage VFB is denoted as VFB*. The difference between them is as follows: ΔV = VFB* - VREF*. The bias voltage calculation module 20 is used to compensate for this difference ΔV.

[0058] The bias operation module 20 includes four resistors (R0-R3) and a second operational amplifier (OPA2), forming an operational amplifier addition and subtraction circuit. For ease of calculation, this embodiment selects four resistors with equal values, i.e., R0 = R1 = R2 = R3. Choosing other resistor values ​​is still within the scope of this invention. At this time, the output voltage of the bias operation module 20 is: VB = V0 + V1 - V2. By selecting the first reference voltage V1 and the second reference voltage V2, and ensuring their difference satisfies the difference between the reference sampling voltage VREF and the bias voltage VFB, i.e., V1 - V2 = ΔV, the intermediate voltage VB is made equal to the bias voltage VFB. Through the bias adjustment of the bias operation module 20, the intermediate voltage VB drives the gate of the second MOS transistor M2 in the target bias module 30. The conduction current IB of the second MOS transistor M2 in the target bias module 30 is equal to the current IB in the constant current bias voltage module 5, thus providing PVT compensation capability.

[0059] The relationship between the given first reference voltage V1 and the second reference voltage V2 only defines the difference between them. In this invention, the first reference voltage V1 is selected as the value of the reference sampling voltage VREF under standard conditions, i.e., TT process corner, 2.5V power supply voltage, and 27℃, denoted as VREF*. Selecting this value helps reduce the output drive capability of the operational amplifier in the unity-gain amplifier 110. The value of voltage V2 is: 2(VREF*) - VFB*.

[0060] Please see Figure 7 Under the process corners of SS, TT, and FF MOS devices, temperature (-40℃, 27℃, 125℃) and power supply voltage (2.25V, 2.5V, 2.75V) were sampled at each process. After PVT compensation, the nA-level bias current fluctuation was less than 10%, demonstrating a good compensation effect.

[0061] Furthermore, the MOSFET can be either a PMOS or an NMOS transistor. The choice of either a PMOS or NMOS transistor is within the scope of this invention.

[0062] In summary, this embodiment of the invention uses a bias voltage generation circuit to obtain the constant current bias voltage characteristics of the target circuit under different process conditions, power supply voltages, and temperatures. The PVT sampling module 10 and the bias calculation module 20 are then adjusted based on these bias voltage characteristics. This enables the nA-level subthreshold current bias circuit with PVT compensation capability to possess high reliability and excellent compensation characteristics, making it suitable for large-scale subthreshold circuit array applications. This ensures the circuit maintains normal operating performance under different process conditions, power supply voltages, and temperatures, achieving low power consumption and resource overhead.

[0063] The above description discloses only one preferred embodiment of the present invention, and should not be construed as limiting the scope of the present invention. Those skilled in the art will understand that all or part of the processes of the above embodiments can be implemented, and equivalent changes made in accordance with the claims of the present invention are still within the scope of the invention.

Claims

1. A nanoampere-level current source with process voltage and temperature compensation capability, characterized in that, include: Current bias circuit and adaptive constant current bias voltage generation circuit; The current bias circuit is used to implement nanoampere-level subthreshold current bias, including: a process voltage and temperature sampling module, a bias calculation module, and a target bias module; The process voltage and temperature sampling module is used to detect changes in process, power supply voltage, and temperature, obtain a reference sampling voltage, and transmit the reference sampling voltage to the bias calculation module. The bias operation module is used to perform level transformation on the reference sampling voltage to obtain an intermediate voltage, and output the intermediate voltage to the target bias module; The target bias module is used to achieve nanoampere-level subthreshold current bias based on the intermediate voltage; The bias voltage generation circuit is used to extract the process, power supply voltage, and temperature characteristics of the target bias module to obtain the corresponding bias voltage change characteristic curve, which guides the construction of the current bias circuit; it includes: a simulated target bias module and a constant current bias voltage module; The constant current bias voltage module is used to collect the bias voltage change rate under the conditions of process, power supply voltage and temperature changes, and the output terminal is connected to the simulated target bias module. The simulated target bias module has the same structure as the target bias module and is used to simulate the electrical characteristics of the target bias module under constant current conditions. Its output terminal is connected to the constant current bias voltage module.

2. The nanoampere-level current source according to claim 1, characterized in that, The process voltage and temperature sampling module includes: a microampere-level current bias, a first MOSFET, and a unity-gain amplifier; the source of the first MOSFET is connected to the power supply voltage; the gate and drain of the first MOSFET are connected and connected to the input terminal of the current bias and the input terminal of the unity-gain amplifier; the output terminal of the unity-gain amplifier is connected to the bias operation module; the unity-gain amplifier is used to gain the output signal.

3. The nanoampere-level current source according to claim 2, characterized in that, The unity-gain amplifier includes a first operational amplifier; the non-inverting input of the first operational amplifier is connected to the gate of the first MOS transistor; the inverting input of the first operational amplifier is shorted to the output of the first operational amplifier; the output of the first operational amplifier is connected to the bias operation module, and outputs the reference sampling voltage to the bias operation module.

4. The nanoampere-level current source according to claim 1, characterized in that, The bias operation module includes four resistors and a second operational amplifier; the reference sampling voltage is transmitted to the non-inverting input of the second operational amplifier through the first resistor; the first reference voltage is transmitted to the non-inverting input of the second operational amplifier through the second resistor; the second reference voltage is transmitted to the inverting input of the second operational amplifier through the third resistor; the inverting input of the second operational amplifier is shorted to the output of the second operational amplifier through the fourth resistor; the output of the second operational amplifier is connected to the target bias module and outputs an intermediate voltage to the target bias module.

5. The nanoampere-level current source according to claim 1, characterized in that, The target bias module includes a second MOS transistor and a third MOS transistor; the gate of the second MOS transistor is connected to the output terminal of the bias operation module to receive the intermediate voltage; the source of the second MOS transistor is connected to the power supply voltage, and the drain is connected to the drain of the third MOS transistor; the gate of the third MOS transistor is connected to a third reference voltage.

6. The nanoampere-level current source according to claim 5, characterized in that, The simulated target bias module includes a fourth MOS transistor and a fifth MOS transistor; the fourth MOS transistor has the same structure as the second MOS transistor; and the fifth MOS transistor has the same structure as the third MOS transistor.

7. The nanoampere-level current source according to claim 6, characterized in that, The source of the fourth MOS transistor is connected to the power supply voltage, and its drain is connected to the drain of the fifth MOS transistor; the source of the fifth MOS transistor is connected to the input terminal of the constant current bias voltage module, and its gate is connected to the third reference voltage; the gate of the fourth MOS transistor is connected to the output terminal of the constant current bias voltage module.

8. The nanoampere-level current source according to claim 1, characterized in that, The constant current bias voltage module includes a fifth resistor and a third operational amplifier; one end of the fifth resistor is connected to the output of the analog target bias module, and the other end is grounded; the non-inverting input of the third operational amplifier is connected to the output of the analog target bias module, the inverting input is connected to the fourth reference voltage, and the output is connected to the input of the analog target bias module.

9. The nanoampere-level current source according to claim 1, characterized in that, The adaptive constant current bias voltage generating circuit has a feedback function; when the current in the constant current bias voltage module increases, the output voltage of the constant current bias voltage module will increase; the output voltage of the simulated target bias module will decrease, thereby suppressing the increase of the current in the constant current bias voltage module; and vice versa; thus realizing feedback to the adaptive constant current bias voltage generating circuit.

10. A design method for a nanoampere-level current source with process voltage and temperature compensation capability, applied to any nanoampere-level current source of claims 1-9 above, comprising the following steps: S1: Target bias voltage characteristic extraction: By scanning under different temperatures, power supply voltages, and process conditions using the adaptive constant current bias voltage generation circuit, the constant current bias voltage characteristics of the target circuit can be extracted, and the rate of change curve of the bias voltage under constant current conditions can be obtained. S2: Process voltage and temperature sampling MOSFET design: Select the same type of MOSFET as the target bias module as the MOSFET of the process voltage and temperature sampling module. Based on the temperature scan bias voltage change rate curve, the power supply voltage scan bias voltage change rate curve, and the process scan bias voltage change curve, select an appropriate MOSFET size for the process voltage and temperature sampling module so that the reference sampling voltage has the same voltage change rate as the target MOSFET under process scan and power supply voltage scan conditions. S3: Bias selection for bias operation module: By comparing the DC operating point of the reference sampling voltage with that of the target bias voltage, the fixed bias voltage at the input terminal of the bias operation module is selected so that the output bias voltage is consistent with the adaptive constant current bias voltage.

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