A three-layer parallel enhanced GaN-HFET and a method for manufacturing the same
By using a three-layer parallel enhanced GaN-HFET structure, the problems of large size and low power density of GaN HFET devices are solved, achieving higher current carrying capacity and reliability, making it suitable for the field of power electronic devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGZHOU YANGJIE ELECTRONIC TECH CO LTD
- Filing Date
- 2023-08-31
- Publication Date
- 2026-05-29
AI Technical Summary
Existing GaN HFET devices have advantages in high frequency and heat resistance, but their large size and low power density make it difficult to meet the integration requirements of microelectronic devices.
A three-layer parallel enhancement GaN-HFET structure is adopted. By growing a gradient AlGaN transition layer and a GaN high-resistivity layer on a silicon substrate, combined with high-energy ion implantation and a silicon nitride protective layer, the vertical structure and electrical isolation of the device are achieved, thereby enhancing the current carrying capacity of the device.
It achieves higher current carrying capacity under the same voltage and size, improving the reliability and power density of the device, which is superior to traditional Si MOS and SiC MOS devices.
Smart Images
Figure CN117153683B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a three-layer parallel enhancement-mode GaN-HFET and its fabrication method. Background Technology
[0002] Gallium nitride (GaN) is a wide-bandgap semiconductor and a typical representative of third-generation semiconductors. GaN's breakdown electric field is 11 times that of silicon, its bandgap is 3.1 times that of silicon, its heterojunction electron mobility is 1.4 times that of silicon, and its electron saturation drift velocity is 2.7 times that of silicon. Therefore, GaN materials possess characteristics such as high temperature resistance, high voltage resistance, and high frequency performance. Compared with first-generation silicon-based semiconductors, GaN devices have higher voltage withstand capabilities, faster switching frequencies, and lower on-resistance, making them widely used in power electronics.
[0003] Gallium nitride (GaN) material growth is divided into bulk crystal growth and epitaxial growth of crystalline thin films. Bulk crystal growth mainly includes ammonothermal growth, high-pressure growth, and sodium fusion growth, all of which have very low growth rates. Therefore, the mainstream technology for preparing GaN materials is currently heteroepitaxial growth of GaN thin films (from a few micrometers to a few millimeters) on other substrates. Epitaxial growth techniques mainly include MOCVD (Metal-Organic Chemical Vapor Deposition), MBE (Hydride Vapor Phase Epitaxy), and HVPE (Molecular Beam Epitaxy). MOCVD uses a thermal decomposition reaction to perform vapor phase epitaxy on a substrate, growing various compound semiconductors and thin single-crystal materials, and is suitable for generating heterostructure materials. It has advantages such as easy growth control and mass production capability. MBE uses molecular beam or atomic beam deposition on the surface of a heated crystalline substrate for epitaxial deposition, offering the best quality and a hydrogen-free environment. HVPE involves flowing HCl through metallic gallium to form GaCl vapor, which flows to the substrate and reacts with NH3 to deposit GaN. It has the advantages of the fastest growth rate and simplest growth technology.
[0004] The most commonly used substrate materials for GaN heteroepitaxial growth are sapphire, SiC, and Si. Considering factors such as heat dissipation and substrate cost, power devices often choose Si as the substrate material. Because of the large lattice mismatch between Si and GaN, current methods such as transition layers, insertion layers, and in-situ passivation are used to release the stress in the epitaxial material.
[0005] Early GaN materials were primarily used in LED light-emitting devices, laser devices, and photodetectors. It wasn't until 1994, when M.K. Khan discovered that AlGaN and GaN could produce a high-concentration two-dimensional electron gas (2DEG), that things changed. This is because AlGaN and GaN materials have a wide overall bandgap and strong voltage withstand capability; furthermore, the conduction band gradient at the AlGaN and GaN interface exhibits strong piezoelectric and spontaneous polarization effects, which are conducive to forming deep and narrow quantum wells and accumulating high-density 2DEG. Due to their distribution and transport characteristics, 2DEGs have significantly higher mobilities and saturation velocities than bulk electrons. Therefore, GaN began to be used in ultra-high frequency and high-speed applications. This modulation-doped heterojunction is the basic structure of the heterojunction field-effect transistor (HFET). The drain and source of the device then form ohmic contacts with the 2DEG, and the gate forms a Schottky contact, using the gate voltage to control the switching on and off of the 2DEG. This is because depletion-type devices have drawbacks such as false turn-on, insecurity, and system instability.
[0006] Due to the inherent risks of depletion-mode devices, such as false turn-on, safety concerns, complex circuit design, and system instability, E-Mode HFETs are becoming increasingly important in power device applications. Currently, the mainstream fabrication methods for enhancement-mode HEMTs include grooved structures, P-type gates, F-ion implantation, and polarization cancellation processes.
[0007] Taking P-type gate technology as an example, the fabrication of the mainstream GaN HFET involves the following steps.
[0008] First, on a silicon substrate, a buffer layer of AlGaN, a high-resistivity breakdown layer of GaN, a GaN channel layer, an AlGaN barrier layer, and a P-type GaN cap layer are grown. The fabrication process includes etching the drain and source regions, depositing ohmic metal in the drain and source regions, implanting H ions into all P-GaN regions except under the gate, depositing Schottky metal in the gate region, and then performing passivation and PAD windowing.
[0009] Although GaN HFET devices offer superior performance compared to traditional Si devices, several challenges still limit their application. For power devices, size and power density are critical considerations. GaN HFETs are based on heterojunctions of AlGaN and GaN. Currently, the AlGaN barrier layer and GaN channel layer fabricated via heteroepitaxy are planar layers, resulting in horizontal GaN HFET devices. Compared to Si MOSFETs and SiC MOSFETs with vertical structures at the same voltage, they offer advantages in high frequency and heat resistance. However, these devices tend to be larger and have lower power densities, conflicting with the trend towards smaller, more integrated microelectronic devices. Summary of the Invention
[0010] To address the above problems, this invention provides a three-layer parallel enhanced GaN-HFET structure with the same voltage rating and size but higher current throughput, and a method for its fabrication.
[0011] A method for fabricating a three-layer parallel enhancement-mode GaN-HFET includes the following steps:
[0012] S100, a silicon substrate is selected and P-type doped;
[0013] S200, a graded AlGaN transition layer grown heteroepitaxially on a silicon substrate;
[0014] According to the order of growth, the first transition layer material is Al. 0.8 Ga 0.2 N, the second transition layer material Al 0.5 Ga 0.5 N and the third transition layer material Al 0.2 Ga 0.8 N;
[0015] S300, a GaN high-resistivity layer is heteroepitaxially grown on the third transition layer material Al0.2Ga0.8N;
[0016] S400, GaN channel layer is grown on GaN high resistivity layer;
[0017] S500, an AlGaN barrier layer is grown on the GaN channel layer;
[0018] S600, depositing a P-type GaN cap layer on an AlGaN barrier layer;
[0019] S700, the device terminal region is implanted with high-energy F ions;
[0020] Disrupt the lattice atoms of the P-GaN layer, AlGaN barrier layer, GaN channel layer and GaN high-resistivity layer at the terminal to isolate the terminal from the source region.
[0021] S800, ohmic metal is prepared in the source and drain regions;
[0022] S900, Schottky metal is fabricated in the gate region;
[0023] S1000 protects the P-Gan in the gate region and passivates the P-Gan in the remaining part of the source region by implanting H ions.
[0024] S1100, deposit a silicon nitride protective layer and perform planarization treatment;
[0025] S1200, repeat steps S300~S1000 in sequence to create the second layer structure;
[0026] S1300: The gate, source, and drain are simultaneously etched into square vias at the terminal position. Metal is then filled into the etched vias to form the first metal via, followed by planarization.
[0027] S1400, deposit silicon nitride protective layer and perform planarization treatment;
[0028] S1500, repeat step S1200 to create the third layer structure;
[0029] S1600: The gate, source, and drain are simultaneously etched into vias at the terminal positions, metal is filled into the vias, a second metal via is made, and then planarization is performed.
[0030] S1700, deposit silicon nitride protective layer and perform planarization treatment;
[0031] S1800, deposited PI gel passivation layer.
[0032] Specifically, in step S100, a single-crystal silicon substrate with a thickness of 1 mm is selected and boron diffusion is performed to achieve a resistivity of 1 Ω*cm, thereby transforming the single-crystal silicon into a P-type silicon substrate.
[0033] Specifically, in step S200, the thickness of the first transition layer is 0.4 μm, the ALN content is 80%, and the GaN content is 20%; the thickness of the second transition layer is 0.3 μm, the ALN content is 50%, and the GaN content is 50%; and the thickness of the third transition layer is 0.3 μm, the ALN content is 20%, and the GaN content is 80%.
[0034] Specifically, in step S300, the GaN high-resistivity layer has a thickness of 4 μm, is doped with C, and has a resistivity of 10⁻⁶. 9 Ω*cm.
[0035] Specifically, in step S400, an n-type GaN channel layer with a thickness of 0.4 μm is grown by heteroepitaxial growth. The GaN channel layer is doped with Si with a doping concentration of 3e15.
[0036] Specifically, in step S500, an AlGaN barrier layer with a thickness of 0.05 μm is heteroepitaxially grown on the GaN channel layer using MOCVD technology; the AlGaN barrier layer is doped with Si with a doping concentration of 2e16.
[0037] Specifically, in step S600, a 0.1 μm thick P-type GaN cap layer is grown heteroepitaxially using MOCVD technology, with Mg as the dopant element and a concentration of 2e18.
[0038] Specifically, in step S800, the source region uses Ti / Al / Ti as the ohmic metal with a total thickness of 300nm, an annealing temperature of 550℃, and an annealing time of 70s.
[0039] Specifically, in step S900, the gate region uses Ti / Al / Ti as the Schottky metal with a total thickness of 400nm, an annealing temperature of 450℃, and an annealing time of 130s.
[0040] Specifically, in step S1300, after the terminal region is not connected to the current and the gate, source, and drain metals of the second layer structure are completed, small holes with a length and width of 1um are etched in the terminal region to the surface of the first layer metal. Then, metal is filled and the terminal region of the surface is etched. The metals deposited on the second layer metal surface are connected to the gate, source, and drain metals, and then planarization is performed.
[0041] The technical solution of this invention is as follows: A three-layer stacked heterojunction structure is fabricated, utilizing a high-resistivity gallium nitride layer at the bottom and a silicon nitride protective layer at the top of each layer to isolate the electrical properties of different layers, ensuring that the electrical properties of different layers do not affect each other. Each layer has complete gate, drain, and source regions. By creating two square metal vias at the terminals for the gate, source, and drain, the gate, drain, and source of the three-layer structure are interconnected. Furthermore, the H-ion passivation P-GaN process avoids etching damage caused by the etching process, greatly improving the reliability of the device. The YJGAN65030C1 device fabricated using this structure has a withstand voltage of 680V (refer to...). Figure 18 As shown;), it has a current carrying capacity of 30A (refer to...). Figure 19 (As shown). Compared with SJ Si mos and SiC mos of the same pressure resistance and size on the market, it has a significant advantage in current carrying capacity. Attached Figure Description
[0042] Figure 1 This is a structural diagram of step S100.
[0043] Figure 2 This is a structural diagram of step S200.
[0044] Figure 3 This is a structural diagram of step S300.
[0045] Figure 4 This is a structural diagram of step S400.
[0046] Figure 5 This is a structural diagram of step S500.
[0047] Figure 6 This is a structural diagram of step S600.
[0048] Figure 7 This is a structural diagram of step S700.
[0049] Figure 8 This is a structural diagram of step S800.
[0050] Figure 9 This is a structural diagram of step S900.
[0051] Figure 10 This is a structural diagram of step S1000.
[0052] Figure 11 This is a structural diagram of step S1100.
[0053] Figure 12 This is a structural diagram of step S1200.
[0054] Figure 13 This is a structural diagram of step S1300.
[0055] Figure 14 This is a structural diagram of step S1400.
[0056] Figure 15 This is a structural diagram of step S1500.
[0057] Figure 16 This is a structural diagram of step S1600.
[0058] Figure 17 This is a structural diagram of step S1700.
[0059] Figure 18 This is a schematic diagram of the structure of the PI passivation layer deposited in step S1700.
[0060] Figure 19 This is the withstand voltage test diagram for the YJGAN65030C1 device at 680V.
[0061] Figure 20 This is a test diagram of the 30A current carrying capacity of the YJGAN65030C1 device. Detailed Implementation
[0062] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0063] A method for fabricating a three-layer parallel enhancement-mode GaN-HFET includes the following steps:
[0064] S100, a silicon substrate is selected and P-type doped, refer to... Figure 1 As shown;
[0065] S200, a gradient AlGaN transition layer grown heteroepitaxially on a silicon substrate, reference. Figure 2 As shown;
[0066] According to the order of growth, the first transition layer material is Al. 0.8 Ga 0.2 N, the second transition layer material Al 0.5 Ga 0.5 N and the third transition layer material Al 0.2 Ga 0.8 N;
[0067] S300, refer to Figure 3 As shown, a GaN high-resistivity layer was heteroepitaxially grown on the third transition layer material Al0.2Ga0.8N using MOCVD process.
[0068] S400, growing a GaN channel layer on a GaN high-resistivity layer, reference. Figure 4 As shown;
[0069] S500, an AlGaN barrier layer is grown on the GaN channel layer, as referenced. Figure 5 As shown;
[0070] S600, depositing a P-type GaN cap layer on the AlGaN barrier layer, reference Figure 6 As shown;
[0071] S700, the device terminal region is implanted with high-energy F ions; the source region is the middle region of the device, and the terminal is the edge region of the device that surrounds the source region. High-energy F ion implantation is used to destroy the lattice isolation of the terminal region to ensure that the hetero interface in this region does not generate two-dimensional electron gas.
[0072] First, photoresist is used to protect the source region. Then, a high-energy particle implanter is used to implant F ions into the terminal region, destroying the lattice atoms of the P-GaN layer, AlGaN barrier layer, GaN channel layer, and GaN high-resistivity layer at the terminal, thus isolating the terminal from the source region; (Refer to...) Figure 7 As shown;
[0073] S800, ohmic metal fabrication in the source and drain regions; reference Figure 8 As shown;
[0074] S900, Schottky metal (or gate metal) is fabricated in the gate region; see reference. Figure 9 As shown;
[0075] S1000 protects the P-Gan in the gate region and passivates the P-Gan in the remaining part of the source region by implanting H ions.
[0076] The P-GaN gate region is protected with photoresist, and then H ions are implanted into the uncoated P-GaN regions using an ion implanter. This causes the Mg and H ions in the uncoated P-GaN regions to react and form H-Mg complexes. (Ref.) Figure 10 As shown;
[0077] S1100, deposit a silicon nitride protective layer and perform planarization; refer to Figure 11 As shown;
[0078] S1200, repeat steps S300~S1000 sequentially to create the second layer structure; refer to Figure 12 As shown;
[0079] In S1300, square vias are simultaneously etched at the terminal positions of the gate, source, and drain. Metal is then filled into these vias to form the first metal via, creating the first connection metal. Planarization is then performed. (Refer to...) Figure 13 As shown;
[0080] S1400, deposit a silicon nitride protective layer and perform planarization; refer to Figure 14 As shown;
[0081] S1500, repeat step S1200 to create the third layer structure; refer to... Figure 15 As shown;
[0082] In S1600, the gate, source, and drain electrodes are simultaneously etched into vias at the terminal positions. Metal is then filled into these vias to create a second metal via, forming the first interconnecting metal. Planarization is then performed. (Refer to...) Figure 16 As shown;
[0083] S1700, deposit a silicon nitride protective layer and perform planarization. (Refer to...) Figure 17 As shown;
[0084] S1800, deposited PI gel passivation layer. (Refer to...) Figure 18 As shown;
[0085] Further specifying, in step S100, a single-crystal silicon substrate with a thickness of 1 mm is selected and boron diffusion is performed to achieve a resistivity of 1 Ω*cm, thereby transforming the single-crystal silicon into a P-type silicon substrate.
[0086] Further specifying, in step S200, the thickness of the first transition layer is 0.4 μm, the ALN content is 80%, and the GaN content is 20%; the thickness of the second transition layer is 0.3 μm, the ALN content is 50%, and the GaN content is 50%; the thickness of the third transition layer is 0.3 μm, the ALN content is 20%, and the GaN content is 80%.
[0087] Further specifying, in step S300, the GaN high-resistivity layer has a thickness of 4 μm, is doped with C, and has a resistivity of 10⁻⁶. 9 Ω*cm.
[0088] Further specifying, in step S400, an n-type GaN channel layer with a thickness of 0.4 μm is grown by heteroepitaxial growth, and the doping element of the GaN channel layer is Si with a doping concentration of 3e15.
[0089] Further specifying, in step S500, an AlGaN barrier layer with a thickness of 0.05 μm is heteroepitaxially grown on the GaN channel layer using MOCVD process; the AlGaN barrier layer is doped with Si with a doping concentration of 2e16.
[0090] Further specifying, in step S600, a 0.1 μm thick P-type GaN cap layer is grown heteroepitaxially using MOCVD process, with Mg as the dopant element and a concentration of 2e18.
[0091] Further specifying, in step S800, the source region uses Ti / Al / Ti as the ohmic metal with a total thickness of 300nm, an annealing temperature of 550℃, and an annealing time of 70s.
[0092] Further specifying, in step S900, the gate region uses Ti / Al / Ti as the Schottky metal, with a total thickness of 400nm, an annealing temperature of 450℃, and an annealing time of 130s.
[0093] Further specifying step S1300, after the terminal region is not connected to the current and the gate, source, and drain metals of the second layer structure are completed, small holes with a length and width of 1um are etched in the terminal region to the surface of the first layer metal, then the metal is filled, and the terminal region of the surface is etched to connect with the metals deposited on the second layer metal surface and the gate, source, and drain metals, and then planarization is performed.
[0094] Further specifying step S1600, after the terminal region is not connected to the current and the gate, source, and drain metals of the third layer structure are completed, small holes with a length and width of 1um are etched in the terminal region to the surface of the second layer metal, then the metal is filled, and the terminal region of the surface is etched to connect the metal deposited on the surface of the third layer metal with the metals deposited on the gate, source, and drain, and then planarization is performed.
[0095] Due to spontaneous polarization and piezoelectric polarization, a high concentration of two-dimensional electron gas is generated at the interface between the AlGaN barrier layer and the GaN channel layer, which is the basis of the GaN-HFET structure. The P-type GaN cap layer is used to transform the HFET from a depletion-mode device to an enhancement-mode device. The gate, source, and drain metal electrodes are used to make ohmic contacts, Schottky contacts, and electrical conduction. The GaN high-resistivity layer is used to ensure that the device will not break down vertically and that the electrical properties between different heterojunction layers will not affect each other. The SiN protective layer has the functions of protection and electrical isolation.
[0096] Regarding the information disclosed in this case, the following points need to be clarified:
[0097] (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design.
[0098] (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments;
[0099] The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.
Claims
1. A method for fabricating a three-layer parallel enhancement-mode GaN-HFET, characterized in that, Includes the following steps: S100, a silicon substrate is selected and P-type doped; S200, a graded AlGaN transition layer grown heteroepitaxially on a silicon substrate; According to the order of growth, the first transition layer material is Al. 0.8 Ga 0.2 N, the second transition layer material Al 0.5 Ga 0.5 N and the third transition layer material Al 0.2 Ga 0.8 N; where the thickness of the first transition layer is 0.4 μm, the thickness of the second transition layer is 0.3 μm, and the thickness of the third transition layer is 0.3 μm; S300, a GaN high-resistivity layer is heteroepitaxially grown on the third transition layer material Al0.2Ga0.8N; the GaN high-resistivity layer has a thickness of 4 μm, is doped with C, and has a resistivity of 10⁻⁶. 9 Ω・cm; S400, a GaN channel layer is grown on a GaN high-resistivity layer. The GaN channel layer has a thickness of 0.4 μm and is doped with Si at a concentration of 3e. 15 ; S500, an AlGaN barrier layer is grown on the GaN channel layer. The AlGaN barrier layer has a thickness of 0.05 μm and is doped with Si at a concentration of 2e⁻. 16 The thickness ratio of the GaN high-resistivity layer, GaN channel layer, and AlGaN barrier layer is 80:8:
1. S600, depositing a P-type GaN cap layer on the AlGaN barrier layer, the P-type GaN cap layer having a thickness of 0.1 μm, and being doped with Mg at a doping concentration of 2e. 18 ; S700 uses high-energy F ions to implant high-energy F ions into the device terminal region, destroying the lattice atoms of the P-GaN layer, AlGaN barrier layer, GaN channel layer and GaN high-resistivity layer at the terminal, thus isolating the terminal from the source region. S800, ohmic metal is prepared in the source and drain regions with a total thickness of 300nm, and ohmic contacts are formed by annealing at 550℃ for 70s. S900, Schottky metal is fabricated in the gate region with a total thickness of 400nm, and Schottky contacts are formed by annealing at 450℃ for 130s. S1000 protects the P-Gan in the gate region and passivates the P-Gan in the remaining part of the source region by implanting H ions. S1100, deposit a silicon nitride protective layer and perform planarization treatment; S1200, repeat steps S300~S1000 in sequence to create the second layer structure; S1300: The gate, source, and drain are simultaneously etched into square vias at the terminal position. Metal is then filled into the etched vias to form the first metal via, followed by planarization. Specifically, in step S1300, after the terminal region is not connected to the current and the gate, source, and drain metals of the second layer structure are completed, small holes with a length and width of 1um are etched in the terminal region to the surface of the first layer metal. Then, metal is filled and the terminal region of the surface is etched. The metals deposited on the second layer metal surface are connected to the gate, source, and drain metals, and then planarization is performed. S1400, deposit silicon nitride protective layer and perform planarization treatment; S1500, repeat step S1200 to create the third layer structure; S1600: The gate, source, and drain are simultaneously etched into vias at the terminal positions, metal is filled into the vias, a second metal via is made, and then planarization is performed. Specifically, in step S1600, after the terminal region is not connected to the current and the gate, source and drain metals of the third layer structure are completed, small holes with a length and width of 1um are etched in the terminal region to the surface of the second layer metal. Then, metal is filled and the terminal region of the surface is etched to connect the metal deposited on the surface of the third layer metal with the metal deposited on the gate, source and drain. Then, planarization is performed. S1700, deposit silicon nitride protective layer and perform planarization treatment; S1800, deposited PI gel passivation layer; A three-layer heterojunction structure is fabricated by stacking three layers upwards. The lower high-resistivity gallium nitride layer and the upper silicon nitride protective layer of each layer isolate the electrical properties of different layers, so that the electrical properties of different layers do not affect each other. Each layer has a complete gate, drain and source region. By making two square metal vias at the end of the gate, source and drain, the gate, drain and source of the three-layer structure are interconnected.
2. The method for fabricating a three-layer parallel enhancement-mode GaN-HFET according to claim 1, characterized in that, In step S100, a single-crystal silicon substrate with a thickness of 1 mm is selected and boron diffusion is performed to achieve a resistivity of 1 Ω*cm, thereby transforming the single-crystal silicon into a P-type silicon substrate.
3. The method for fabricating a three-layer parallel enhancement-mode GaN-HFET according to claim 1, characterized in that, In step S200, the thickness of the first transition layer is 0.4 μm, the ALN content is 80%, and the GaN content is 20%; the thickness of the second transition layer is 0.3 μm, the ALN content is 50%, and the GaN content is 50%; the thickness of the third transition layer is 0.3 μm, the ALN content is 20%, and the GaN content is 80%.
4. The method for fabricating a three-layer parallel enhancement-mode GaN-HFET according to claim 1, characterized in that, In step S300, the GaN high-resistivity layer has a thickness of 4 μm, is doped with C, and has a resistivity of 10⁻⁶. 9 Ω*cm.
5. The method for fabricating a three-layer parallel enhancement-mode GaN-HFET according to claim 1, characterized in that, In step S400, an n-type GaN channel layer with a thickness of 0.4 μm is grown by heteroepitaxial growth. The GaN channel layer is doped with Si with a doping concentration of 3e15.
6. The method for fabricating a three-layer parallel enhancement-mode GaN-HFET according to claim 1, characterized in that, In step S500, an AlGaN barrier layer with a thickness of 0.05 μm is heteroepitaxially grown on the GaN channel layer using MOCVD process; the AlGaN barrier layer is doped with Si with a doping concentration of 2e16.
7. The method for fabricating a three-layer parallel enhancement-mode GaN-HFET according to claim 1, characterized in that, In step S600, a 0.1 μm thick P-type GaN cap layer is heteroepitaxially grown using MOCVD technology, with Mg as the dopant element and a concentration of 2e18.
8. The method for fabricating a three-layer parallel enhancement-mode GaN-HFET according to claim 1, characterized in that, In step S800, the source region uses Ti / Al / Ti as the ohmic metal with a total thickness of 300 nm, an annealing temperature of 550 °C, and an annealing time of 70 s.
9. The method for fabricating a three-layer parallel enhancement-mode GaN-HFET according to claim 1, characterized in that, In step S900, the gate region uses Ti / Al / Ti as the Schottky metal with a total thickness of 400nm, an annealing temperature of 450℃, and an annealing time of 130s.