Switching converter and control circuit and control method thereof

Abstract

This invention discloses a switching converter and its control circuit and method. The mode switching circuit in the control circuit includes: a first detection module for comparing a loop error signal with a set first reference signal to generate a first enable signal; a second detection module for detecting the system duty cycle and, when the system duty cycle is greater than a set duty cycle, comparing the peak inductor current in the switching converter with a preset peak current to generate a second enable signal; and a switching control module for controlling the switching converter to switch from the normal operating mode to the light-load operating mode when either the first enable signal or the second enable signal is valid. By employing a combination of two detection modes, the light and heavy load conditions of the switching converter can be more accurately determined, thereby avoiding abnormal operation of the switching converter due to misjudgment, ensuring that the system can still enter the light-load operating mode under a large duty cycle, and improving the stability and reliability of the switching converter.

Description

Technical Field

[0001] This invention relates to the field of power supply technology, and more specifically, to a switching converter and its control circuit and control method. Background Technology

[0002] In recent years, with the rise of various battery-powered wearable devices and IoT devices, more demands have been placed on power chips, requiring them to have higher efficiency and longer battery life. For example, in wearable devices, sensor devices are used for relatively short periods, and the system is often under light load or even no load. Therefore, efficiency under extremely light loads is particularly important for these devices, as it directly affects the device's battery life.

[0003] DC-DC converters are commonly used as power supply devices in these types of electronic products. DC-DC products have high conversion efficiency and are controlled using PWM (Pulse Width Modulation). PWM control offers advantages such as fixed operating frequency, low output voltage ripple, good stability, and mature control methods. However, because the power transistors in the converter must be turned on and off in every switching cycle, the switching losses of the power transistors are relatively large. This results in lower overall converter efficiency under light load or standby conditions, severely limiting the application range of PWM control.

[0004] In existing technologies, PFM (Pulse Frequency Modulation) control and PSM (Pulse PSM Modulation) control are commonly used to prevent the efficiency of DC-DC converters from decreasing when switching from heavy load to light load. The essence of both PFM and PSM control is to reduce the actual switching frequency, thereby improving efficiency under light load conditions.

[0005] In existing technologies, for systems and electronic devices with a wide operating range and constantly changing light and heavy loads, DC-DC converters with PWM / PSM or PWM / PFM hybrid operating modes are used in power management to improve efficiency and circuit performance under light and heavy loads. However, current mode control methods still have many problems to be solved. For example, existing peak current-mode DC-DC converters typically determine when the system enters light load operating mode based on the loop error signal output by the error amplifier. However, in peak current mode, the loop error signal output by the error amplifier usually contains a ramp component. This results in a large ramp component in the output signal of the error amplifier at large duty cycles, which in turn prevents the system from correctly switching to light load operating mode, reducing system efficiency. Summary of the Invention

[0006] In view of the above problems, the purpose of this invention is to provide a switching converter and its control circuit and control method. When the system duty cycle is small, the timing for the system to enter the light-load operating mode is determined based on the system loop error signal. When the system duty cycle is large, the timing for the system to enter the light-load operating mode is determined based on the peak value of the inductor current of the circuit. This ensures that the switching converter can switch to the light-load operating mode in a timely manner under any duty cycle condition, thereby improving system stability and efficiency.

[0007] According to a first aspect of the present invention, a control circuit for a switching converter is provided, comprising: an error amplifier configured to compare a feedback voltage of the output voltage of the switching converter with a reference voltage to generate a loop error signal; and a mode switching circuit configured to generate a mode switching signal to control the switching converter to operate in a normal operating mode or a light-load operating mode, wherein the mode switching circuit comprises: a first detection module configured to compare the loop error signal with a preset first reference signal to generate a first enable signal; a second detection module configured to detect a system duty cycle and, when the system duty cycle is greater than a preset duty cycle, compare a peak inductor current in the switching converter with a preset peak current to generate a second enable signal; and a switching control module configured to generate the mode switching signal in a first state when one of the first enable signal and the second enable signal is valid, to control the switching converter to switch from the normal operating mode to the light-load operating mode.

[0008] Optionally, the first detection module is configured to generate a valid first enable signal when the loop error signal is less than the first reference signal, and the second detection module is configured to generate a valid second enable signal if the system duty cycle is greater than the set duty cycle when the peak value of the inductor current is less than the preset peak current in N consecutive switching cycles, where N is an integer greater than 1.

[0009] Optionally, the second detection module includes: a first comparator configured to compare a current sampling signal related to the peak inductor current with a second reference signal related to the preset peak current, and generate a valid first control signal when the current sampling signal is less than the second reference signal; a duty cycle detection unit configured to detect the duty cycle of the main power transistor in the switching converter, and generate a valid second control signal when the duty cycle is greater than the preset duty cycle; and a cycle counting unit configured to continuously count according to the valid first control signal, and generate a valid second enable signal according to the valid second control signal when the count value reaches N.

[0010] Optionally, the second detection module further includes: a first adder configured to superimpose a ramp signal with a current signal characterizing the preset peak current to obtain the second reference signal, wherein the peak value of the ramp signal is positively correlated with the on-time of the main power transistor.

[0011] Optionally, the duty cycle detection unit includes: a charge / discharge module configured to generate a triangular wave signal; a second comparator configured to compare the triangular wave signal with a third reference signal and generate a first clock signal based on the comparison result; a third comparator configured to compare the triangular wave signal with a fourth reference signal and generate a second clock signal based on the comparison result, wherein the fourth reference signal is equal to the product of the third reference signal and a preset proportional coefficient; and an AND gate configured to perform an AND logic operation on the second clock signal and a main control signal to obtain the second control signal.

[0012] Optionally, the charging and discharging module includes: a current source and a capacitor connected in series between the power supply voltage and ground, the intermediate node of the current source and the capacitor being used to generate the triangular wave signal; and a transistor, the first terminal of the transistor being connected to the intermediate node, the second terminal of the transistor being connected to ground, and the control terminal of the transistor being used to receive the first clock signal.

[0013] Optionally, the control circuit further includes: a current sampling circuit configured to sense the high-side current of the power circuit of the switching converter to obtain a current feedback signal; and a second adder for superimposing the current feedback signal with the ramp signal to obtain the current sampling signal.

[0014] According to a second aspect of the present invention, a control method for a switching converter is provided, the switching converter being operable in a normal operating mode and a light-load operating mode, the control method comprising: comparing a feedback voltage of the output voltage of the switching converter with a reference voltage to generate a loop error signal; comparing the loop error signal with a preset first reference signal to generate a first enable signal; detecting a system duty cycle, and if the system duty cycle is greater than a preset duty cycle, comparing a peak inductor current in the switching converter with a preset peak current to generate a second enable signal; and when one of the first enable signal and the second enable signal is valid, generating a mode switching signal of a first state to control the switching converter to switch from the normal operating mode to the light-load operating mode.

[0015] Optionally, the step of comparing the loop error signal with a set first reference signal to generate a first enable signal includes: generating a valid first enable signal when the loop error signal is less than the first reference signal; the step of detecting the system duty cycle and comparing the peak value of the inductor current in the switching converter with a preset peak current to generate a second enable signal includes: generating a valid second enable signal if the system duty cycle is greater than the set duty cycle when the peak value of the inductor current is less than the preset peak current in N consecutive switching cycles, where N is an integer greater than 1.

[0016] Optionally, the step of generating a valid second enable signal if the system duty cycle is greater than the set duty cycle when the peak value of the inductor current is less than the preset peak current in N consecutive switching cycles includes: comparing a current sampling signal related to the peak value of the inductor current with a second reference signal related to the preset peak current, and generating a valid first control signal when the current sampling signal is less than the second reference signal; detecting the duty cycle of the main power transistor in the switching converter, and generating a valid second control signal when the duty cycle is greater than the preset duty cycle; and continuously counting according to the valid first control signal, and generating a valid second enable signal according to the valid second control signal when the count value reaches N.

[0017] According to a third aspect of the present invention, a switching converter is provided, comprising: a power circuit including a main power transistor, a rectifier transistor, and an inductor; and a control circuit described above, wherein the control circuit converts an input voltage into an output voltage by repeatedly switching the main power transistor and the rectifier transistor alternately on / off and using the inductor to perform energy conversion.

[0018] In summary, the switching converter, its control circuit, and control method of this invention determine the timing of the system entering a light-load operating mode based on the system's loop error signal when the system's duty cycle is small, and determine the timing of the system entering a light-load operating mode based on the peak value of the circuit's inductor current when the system's duty cycle is large. By combining these two detection modes, the light and heavy load conditions of the switching converter can be determined more accurately, thereby avoiding abnormal operation of the switching converter due to misjudgment and improving the stability and reliability of the switching converter. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0020] Figure 1 This is a schematic circuit diagram of a switching converter according to an embodiment of the present invention.

[0021] Figure 2 The diagram shows the working waveform of the second detection module in an embodiment of the present invention when the system duty cycle is greater than the preset duty cycle.

[0022] Figure 3 This is a schematic circuit diagram of a duty cycle detection unit according to an embodiment of the present invention.

[0023] Figure 4 The diagram shows the working waveform of the duty cycle detection unit according to an embodiment of the present invention. Detailed Implementation

[0024] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0025] It should be understood that, in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0026] This invention can be presented in various forms, some of which will be described below.

[0027] Figure 1 This is a schematic circuit diagram of a switching converter according to an embodiment of the present invention. Figure 1As shown, the buck converter 100 includes a power circuit and a control circuit 110. The power circuit is the output circuit of a typical peak current-mode synchronous rectification buck switching regulator, which steps down the input voltage VIN applied to the input terminal to provide an output voltage VOUT. However, this invention is not limited to this; the various concepts disclosed herein can be used in conjunction with any type of DC-DC converter architecture, such as buck converters, boost converters, flyback converters, and buck-boost converters, based on the topology of the power circuit. Furthermore, although complementary PWM control of the high-side and low-side switching devices is utilized in the illustrations of this embodiment, the concepts described herein can be implemented in power converters using only a single switching device, and / or in power converters applying more than two pulse width modulations.

[0028] like Figure 1 As shown, the power circuit includes a switching transistor S1 (also known as a high-side switching transistor), a switching transistor S2 (also known as a low-side switching transistor), and an inductor L1. The drains of the high-side switching transistor S1 and the low-side switching transistor S2 are connected to each other, and their common terminal forms a switching node LX. The source of the low-side switching transistor S2 is connected to ground, and the source of the high-side switching transistor S1 is connected to the input voltage VIN. The first terminal of the inductor L1 is connected to the switching node LX, and the second terminal of the inductor L1 is connected to the output voltage VOUT. It should be understood that in this embodiment, switching transistor S1 is the main power transistor, and switching transistor S2 is the rectifier transistor. Switches S1 and S2 can be any type of field-effect transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). Without departing from the scope of the teachings of this invention, they can also be other types of field-effect transistors and other types of transistors known to those skilled in the art.

[0029] The switching converter 100 also includes an output capacitor Co, which is positioned between the output terminal and ground of the switching converter 100 to generate an output voltage VOUT across it. A voltage divider network composed of resistors Ra and Rb is used to obtain the feedback voltage V of the output voltage VOUT. FB .

[0030] The control circuit 110 generates drive signals applied to the gates of switching transistors S1 and S2 to control their switching states, thereby providing energy to the load. In this embodiment, the control circuit 110 repeatedly turns switching transistors S1 and S2 on / off alternately, using inductor L1 for energy conversion. This results in the input voltage VIN being stepped down. The stepped-down voltage is then smoothed through inductor L1 and output capacitor Co, and output as the output voltage VOUT.

[0031] The control circuit 110 of the switching converter 100 can be integrated into an LSI chip on a semiconductor substrate. In this embodiment, the switching transistors S1 and S2 can be located outside the control circuit 110, but they can also be located inside the control circuit.

[0032] The switching converter of this invention can operate in multiple operating modes. Furthermore, the switching converter of this embodiment can operate in a combination of normal operating mode and light-load operating mode. When the load on the switching converter is heavy, the switching converter operates in normal operating mode; when the load on the switching converter is light, the switching converter operates in light-load operating mode. Even further, the normal operating mode of this embodiment is pulse width modulation mode (hereinafter referred to as PWM mode), and the light-load operating mode is pulse frequency modulation mode (hereinafter referred to as PFM mode) or pulse cycle modulation mode (hereinafter referred to as PSM mode). When the load on the switching converter is heavy, the switching converter operates in PWM mode; when the load on the switching converter is light, the switching converter operates in PFM mode or PSM mode.

[0033] In this embodiment, the control circuit 110 of the switching converter 100 further includes an error amplifier 121, a peak comparator 122, a logic control circuit 124, an oscillator circuit 125, and a mode switching circuit 140.

[0034] The positive input terminal of the error amplifier 121 is used to receive the feedback voltage V. FB The negative input terminal of error amplifier 121 is used to receive a reference voltage V. REF Error amplifier 121 is configured to convert the feedback voltage V FB With the reference voltage V REF In comparison, to generate the loop error signal V ERR Signal V ERR Indicates feedback voltage V FB With reference voltage V REF The difference between them.

[0035] The positive input of peak comparator 122 is used to receive a current sampling signal V related to the peak inductor current in the power circuit. IPK The negative input of the peak comparator 122 is used to receive the loop error signal V. ERR The peak comparator 122 is configured to convert the loop error signal V ERR With the current sampling signal V IPK In comparison, a peak current control signal TRIP is generated.

[0036] Furthermore, the current sampling signal V IPKThe signal is a sawtooth wave. Furthermore, the control circuit 110 also includes a current sampling circuit 123 and an adder 125. The current sampling circuit 123 is configured to sense the high-side current of the power circuit to obtain a current feedback signal V. sense The adder 125 is configured to add the current feedback signal to a ramp signal V. slope The current sampling signal V is obtained by superimposing the two signals. IPK Furthermore, the ramp signal V slope The peak value is related to the on-time of the high-side switch S1 in the power circuit. Furthermore, the ramp signal V... slope The peak value is positively correlated with the conduction time of the high-side switch S1.

[0037] The mode switching circuit 130 is configured to generate a mode switching signal MODE to control the switching converter 100 to operate in normal working mode or light load working mode. Further, the mode switching circuit 130 includes a first detection module 131, a second detection module 132, and a switching control module 133. The first detection module 131 is configured to detect the loop error signal V... ERR The signal is compared with a set first reference signal Vt to generate a first enable signal V. en1 The second detection module 132 is configured to detect the duty cycle of the main power transistor (i.e., the high-side switch S1) in the switching converter 100, and when the duty cycle is greater than a set duty cycle, compare the peak value of the inductor current in the switching converter with a preset peak current to generate a second enable signal V. en2 The switching control module 133 is configured to respond to the first enable signal V. en1 and the second enable signal V en2 When one of them is active, a mode switching signal MODE for the first state is generated to control the switching converter 100 to switch from the normal operating mode to the light-load operating mode; and when the first enable signal V is active... en1 and the second enable signal V en2 If all are invalid, a second state mode switching signal MODE is generated to control the switch converter 100 to switch from the light load operating mode to the normal operating mode.

[0038] Furthermore, the first detection module 131 includes a comparator, the positive input of which is used to receive the first reference signal Vt1, and the negative input of which is used to receive the loop error signal Vt1. ERR The output of the comparator is used to output the first enable signal V. en1 Wherein, when the loop error signal V ERRWhen the signal is less than the first reference signal Vt1, the comparator outputs a high-level (i.e., valid) first enable signal V. en1 When the loop error signal V ERR When the value is greater than the first reference signal Vt1, the comparator outputs a low-level (i.e., invalid) first enable signal V. en1 .

[0039] Furthermore, the second detection module 132 is configured to first detect the peak value of the inductor current of the power circuit. If the peak value of the inductor current is less than the preset peak current in N consecutive switching cycles, the system duty cycle is detected. If the system duty cycle is greater than the preset duty cycle, a high-level (i.e., valid) second enable signal V is generated. en2 Otherwise, a low-level (i.e., invalid) second enable signal V is generated. en2 .

[0040] Furthermore, the second detection module 132 includes an adder 101, a comparator 102, a duty cycle detection unit 103, and a cycle counting unit 104. The adder 101 is configured to process the ramp signal V... slope With the signal V characterizing the preset peak current p0 The signals are superimposed to obtain a second reference signal Vt2. The positive input of comparator 102 is used to receive the second reference signal Vt2, and the negative input of comparator 102 is used to receive the current sampling signal V. IPK The output of the comparator 102 is used to output the first control signal V. comp Wherein, when the current sampling signal V IPK When the value is less than the second reference signal Vt2, the comparator 102 outputs a high-level (i.e., valid) first control signal V. comp When the current sampling signal V IPK When the value is greater than the second reference signal Vt2, the comparator 102 outputs a low-level (i.e., invalid) first control signal V. comp The duty cycle detection unit 103 is configured to generate a first clock signal clk and detect the system duty cycle of the switching converter 100 (i.e., the duty cycle of the main power transistor S1). When the duty cycle is greater than a preset duty cycle (e.g., 50%), a valid second control signal DUTY_half is generated. The cycle counting unit 104 is used to receive the second control signal DUTY_half and the first control signal V. comp Configured to respond to the effective first control signal V comp Perform continuous counting, and generate a valid second enable signal V when the count value reaches N and the second control signal DUTY_half is valid.en2 .

[0041] Logic control circuit 124 implements the system's logic control functions. Its inputs are connected to the peak comparator 122 and the output of the duty cycle detection unit 103. The output of logic control circuit 124 is connected to the gates of low-side switch S1 and high-side switch S2, and operates these transistors so that the power circuit outputs power to the load in normal operating mode or light-load operating mode. For example, logic control circuit 124 generates complementary high-side driver signals HSDR and LSDR, and generates gate control signals based on these two signals to drive the gates of high-side switch S2 and low-side switch S1. In an exemplary embodiment, control circuit 110 further includes high-side drivers 126 and low-side drivers 127 corresponding to high-side switch S2 and low-side switch S1, with the high-side driver signals HSDR and LSDR provided as inputs to high-side drivers 126 and low-side drivers 127.

[0042] Depending on the output of the logic control circuit 124, current will flow from the input voltage VIN through the inductor L1, and through either the high-side switch S2 (during a portion of the cycle when power is supplied) or the low-side switch S1 (during a portion of the cycle when power is not supplied). When the low-side switch S1 is on (and therefore during the portion of the cycle when power is not supplied), the input voltage VIN charges the inductor L1, thus increasing the current in the inductor L1; when the high-side switch S2 is on (and therefore during the portion of the cycle when power is supplied), the current stored in the inductor L1 flows to the load, thus decreasing the current in the inductor L1.

[0043] The logic control circuit 124 is also configured to control the operation of the power circuit between a normal operating mode and a light-load operating mode based on the mode switching signal MODE output by the mode switching circuit 130. For example, when the mode switching signal MODE is in a first state (e.g., high level), the logic control circuit 124 controls the power circuit to operate in the light-load operating mode; when the mode switching signal MODE is in a second state (e.g., low level), the logic control circuit 124 controls the power circuit to operate in the normal operating mode.

[0044] Figure 2 The diagram shows the waveform of the second detection module in an embodiment of the present invention when the system duty cycle is greater than a preset duty cycle. Figure 2 In the middle, V p0 V is the constant voltage value corresponding to the preset peak current. IPK For current sampling signal, V slopeA ramp signal is defined as the peak value of which is proportional to the conduction time of the main power transistor S1, and Vsense is the voltage value corresponding to the inductor current obtained from the sampling.

[0045] As mentioned earlier, in the second detection module 132, the positive input terminal of the comparator 102 receives the second reference signal Vt2, and the second reference signal Vt2 = V p0 +V slope The negative input terminal of comparator 102 receives the current sampling signal V. IPK And the current sampling signal V IPK =V slope +V sense V sense As a current feedback signal obtained by sensing the high-side current of the power circuit, the output of comparator 102 is used to output a first control signal V. comp When signal V p0 >V IPK -V slope At that time, the first control signal V comp Valid (i.e., high level); when signal V p0 <V IPK -V slope At that time, the first control signal V comp Invalid (i.e., low level).

[0046] like Figure 2 As shown, when the switching converter is in normal operating mode, the cycle counting unit 104 measures the first control signal V. comp The level state is detected when the first control signal V comp When the signal is low, the cycle counting unit 104 is reset, and the count value of the cycle counting unit 104 is 0; when the first control signal V... comp When the toggle switches to a high level, the cycle counting unit 104 starts counting continuously. When the count value of the cycle counting unit 104 reaches N, the cycle counting unit 104 starts detecting the level of the second control signal DUTY_half. If the second control signal DUTY_half is high, a valid second enable signal V is generated. en2 The control switchover is switched to a light-load operating mode. When the switchover is in light-load operating mode, the cycle counting unit 104 continues to monitor the first control signal V. comp The level state is detected when the first control signal V comp When the toggle switches to low, the cycle counting unit 104 resets again, clearing the count value to zero and simultaneously generating an invalid second enable signal V. en2 The control switch converter is switched to normal operating mode.

[0047] Figure 3This is a schematic circuit diagram of a duty cycle detection unit according to an embodiment of the present invention. Figure 3 As shown, in an exemplary embodiment, the duty cycle detection unit 103 includes a charge / discharge module 1031, a comparator 1032, a comparator 1033, and an AND gate circuit 1034.

[0048] The charging / discharging module 1031 is configured to generate a triangular wave signal V. ramp For example, the charging / discharging module 1031 includes a current source I1, a capacitor C1, and a transistor M1. The current source I1 and the capacitor C1 are connected in series between the power supply voltage VDD and ground. The current source I1 is used to charge the capacitor C1 to generate the triangular wave signal V at the midpoint between them. ramp Transistor M1 is, for example, an N-type MOSFET, with its first terminal (e.g., drain) connected to the intermediate node between current source I1 and capacitor C1, its second terminal (e.g., source) connected to ground, and its control terminal connected to the output of comparator 1032.

[0049] Comparator 1032 is configured to convert the triangular wave signal V ramp A fixed first clock signal clk is generated based on the comparison result with a third reference signal VB. For example, adjacent pulses in the first clock signal clk define a clock cycle. During each clock cycle, current source I1 charges capacitor C1, causing the triangular wave signal V... ramp Gradually increase, when the triangular wave signal V ramp When the signal rises to the third reference signal VB, the first clock signal clk generates a valid pulse signal. Simultaneously, this pulse signal turns on transistor M1, thereby discharging capacitor C1 to convert the triangular wave signal V... ramp Pull down to ground. When the triangular wave signal V... ramp After being pulled down to the ground, the triangular wave signal V ramp The current is less than the third reference signal VB, therefore the first clock signal clk is set low again, transistor M1 is turned off, which in turn causes current source I1 to recharge capacitor C1, and the triangular wave signal V... ramp It rises again, entering the next clock cycle.

[0050] In one exemplary implementation, such as Figure 1 As shown, the first clock signal clk is provided to the logic control circuit 124. The logic control circuit 124 is configured to control the turn-on time of the main power transistor S1 according to the effective pulse of the first clock signal clk when the switching converter 100 is in normal operating mode, and to control the turn-off time of the main power transistor S1 according to the effective peak current control signal TRIP.

[0051] The comparator 1033 is configured to convert the triangular wave signal V ramp A second clock signal clk_half is generated based on the comparison result with the fourth reference signal VC. For example, the fourth reference signal VC is equal to the product of the third reference signal VB and a preset scaling factor; in one exemplary embodiment, the scaling factor is equal to 50%. When the triangular wave signal V... ramp When the signal rises to the fourth reference signal VC, the comparator 1033 outputs a high-level second clock signal clk_half.

[0052] The first input of AND gate 1034 is used to receive the signal HSON, which characterizes the conduction time of the main power transistor S1. The second input of AND gate 1034 is used to receive the second clock signal clk_half. AND gate 1034 is configured to perform an AND logic operation between the main power transistor S1 on signal HSON and the second clock signal clk_half to obtain the second control signal DUTY_half. Specifically, when the second clock signal clk_half is high, if the main power transistor S1 on signal HSON is also high, then the second control signal DUTY_half is also high, indicating that the duty cycle of the main power transistor S1 is at least greater than 50% in this clock cycle; otherwise, the second control signal DUTY_half is low, indicating that the duty cycle of the main power transistor S1 is less than 50% in this clock cycle.

[0053] Figure 4 The diagram shows the operating waveform of the duty cycle detection unit according to an embodiment of the present invention. Figure 4 The triangular wave signal V is shown in the figure. ramp Waveforms of the first clock signal clk, the second clock signal clk_half, the master control signal HSON, and the second control signal DUTY_half are shown below. Figure 3 and Figure 4 The working principle of the duty cycle detection unit 103 in this embodiment will be explained.

[0054] In the peak current mode switching converter of this embodiment, the logic control circuit 124 typically controls the turn-on time of the main power transistor S1 based on the effective pulse of the first clock signal clk, and controls the turn-off time of the main power transistor S1 based on the peak value of the inductor current (i.e., the peak current control signal TRIP). Figure 4 As shown, at time t1, when the effective pulse of the first clock signal clk arrives, the main control signal HSON flips to a high level, and the main power transistor S1 is turned on. At this time, the triangular wave signal V... ramp Pulled down to ground due to the triangular wave signal V rampSince the clock signals are less than the third reference signal VB and the fourth reference signal VC, both the first clock signal clk and the second clock signal clk_half toggle to low. Therefore, transistor M1 turns off, and current source I1 begins charging capacitor C1, resulting in a triangular wave signal V. ramp The value gradually increases. At time t2, the triangular wave signal V... ramp The fourth reference signal VC is equal to the second clock signal clk_half, which flips to a high level. Since the main control signal HSON is still high at this time, it indicates that the duty cycle of the main power transistor S1 is greater than 50%. Therefore, the duty cycle detection unit 103 outputs a valid (i.e., high-level) second control signal DUTY_half. At time t3, the triangular wave signal V... ramp When the signal rises to the third reference signal VB, the first clock signal clk generates a narrow pulse, which turns on the main power transistor S1 again, and simultaneously generates the triangular wave signal V. ramp Pull down to ground and enter the next clock cycle. At time t4, the triangular wave signal V... ramp The signal rises again to the fourth reference signal VC, and the second clock signal clk_half flips to a high level. At this time, the main control signal HSON has already flipped to a low level, indicating that the duty cycle of the main power transistor S1 is less than 50%. Therefore, the duty cycle detection unit 103 outputs an invalid (i.e., low-level) second control signal DUTY_half.

[0055] In summary, the switching converter, its control circuit, and control method of this invention determine the timing of the system entering a light-load operating mode based on the system's loop error signal when the system's duty cycle is small, and determine the timing of the system entering a light-load operating mode based on the peak value of the circuit's inductor current when the system's duty cycle is large. By combining these two detection modes, the light and heavy load conditions of the switching converter can be determined more accurately, thereby avoiding abnormal operation of the switching converter due to misjudgment and improving the stability and reliability of the switching converter.

[0056] Under light load conditions, the power conversion efficiency of switching converters is usually low, which can lead to increased switching converter temperature and accelerated component aging. Therefore, this solution can switch the switching converter to a low-power mode in a timely manner under light load conditions, thereby reducing the power consumption and temperature of the switching converter and extending the life of components.

[0057] Furthermore, the solution provided in this embodiment of the invention employs two detection modes to determine the light and heavy load conditions of the switching converter, which can adapt to different load requirements, improve the adjustability and compatibility of the system, and adapt to different application scenarios.

[0058] In the above description, well-known structural elements and steps have not been described in detail. However, those skilled in the art should understand that the corresponding structural elements and steps can be implemented through various technical means. Furthermore, in order to form the same structural elements, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0059] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A control circuit for a switching converter, comprising: An error amplifier is configured to compare the feedback voltage of the output voltage of the switching converter with a reference voltage to generate a loop error signal; as well as A mode switching circuit is configured to generate a mode switching signal to control the switching converter to operate in normal operating mode or light-load operating mode. The mode switching circuit includes: The first detection module is configured to compare the loop error signal with a set first reference signal to generate a first enable signal; The second detection module is configured to detect the system duty cycle, and when the system duty cycle is greater than a set duty cycle, compare the peak value of the inductor current in the switching converter with a preset peak current to generate a second enable signal; and The switching control module is configured to generate the mode switching signal of the first state when one of the first enable signal and the second enable signal is valid, so as to control the switching converter to switch from the normal operating mode to the light-load operating mode.

2. The control circuit of claim 1, wherein, The first detection module is configured to generate a valid first enable signal when the loop error signal is less than the first reference signal. The second detection module is configured to generate a valid second enable signal if the system duty cycle is greater than the preset duty cycle when the peak value of the inductor current is less than the preset peak current in N consecutive switching cycles, where N is an integer greater than 1.

3. The control circuit of claim 2, wherein, The second detection module includes: A first comparator is configured to compare a current sampling signal related to the peak value of the inductor current with a second reference signal related to the preset peak current, and generate a valid first control signal when the current sampling signal is less than the second reference signal; A duty cycle detection unit is configured to detect the duty cycle of the main power transistor in the switching converter, and generate a valid second control signal when the duty cycle is greater than a preset duty cycle; and The cycle counting unit is configured to continuously count according to a valid first control signal, and generate a valid second enable signal according to a valid second control signal when the count value reaches the N.

4. The control circuit according to claim 3, wherein, The second detection module also includes: The first adder is configured to superimpose a ramp signal with a current signal representing the preset peak current to obtain the second reference signal. The peak value of the ramp signal is positively correlated with the conduction time of the main power transistor.

5. The control circuit of claim 3, wherein, The duty cycle detection unit includes: The charging / discharging module is configured to generate a triangular wave signal; The second comparator is configured to compare the triangular wave signal with the third reference signal and generate a first clock signal based on the comparison result. A third comparator is configured to compare the triangular wave signal with a fourth reference signal, and generate a second clock signal based on the comparison result, wherein the fourth reference signal is equal to the product of the third reference signal and a preset scaling factor; and An AND gate is configured to perform an AND logic operation on the second clock signal and the main control signal to obtain the second control signal.

6. The control circuit of claim 5, wherein, The charging / discharging module includes: A current source and a capacitor are connected in series between the power supply voltage and ground, with the intermediate node of the current source and the capacitor used to generate the triangular wave signal; and A transistor, wherein a first terminal of the transistor is connected to the intermediate node, a second terminal of the transistor is connected to ground, and a control terminal of the transistor is used to receive the first clock signal.

7. The control circuit according to claim 4 further includes: A current sampling circuit is configured to sense the high-side current of the power circuit of the switching converter to obtain a current feedback signal. as well as The second adder is used to superimpose the current feedback signal and the ramp signal to obtain the current sampling signal.

8. A control method for a switching converter, the switching converter being operable in a normal operating mode and a light-load operating mode, the control method comprising: The feedback voltage of the output voltage of the switching converter is compared with a reference voltage to generate a loop error signal; The loop error signal is compared with a set first reference signal to generate a first enable signal; The system duty cycle is detected. If the system duty cycle is greater than the set duty cycle, the peak value of the inductor current in the switching converter is compared with the preset peak current to generate a second enable signal. as well as When one of the first enable signal and the second enable signal is valid, a mode switching signal of the first state is generated to control the switching converter to switch from the normal operating mode to the light load operating mode.

9. The control method according to claim 8, wherein The step of comparing the loop error signal with a set first reference signal to generate a first enable signal includes: When the loop error signal is less than the first reference signal, a valid first enable signal is generated. The step of detecting the duty cycle of the system, and if the system duty cycle is greater than a set duty cycle, comparing the peak value of the inductor current in the switching converter with a preset peak current to generate a second enable signal includes: If the peak value of the inductor current is less than the preset peak current in N consecutive switching cycles, and the system duty cycle is greater than the set duty cycle, then a valid second enable signal is generated, where N is an integer greater than 1.

10. The control method according to claim 9, wherein The step of generating a valid second enable signal when the peak inductor current is less than the preset peak current in N consecutive switching cycles, and the system duty cycle is greater than the set duty cycle, includes: The current sampling signal related to the peak inductor current is compared with the second reference signal related to the preset peak current, and a valid first control signal is generated when the current sampling signal is less than the second reference signal; The duty cycle of the main power transistor in the switching converter is detected, and a valid second control signal is generated when the duty cycle is greater than the preset duty cycle; and Continuous counting is performed based on the valid first control signal, and a valid second enable signal is generated based on the valid second control signal when the count value reaches N.

11. A switching converter, comprising: a power circuit including a main power tube, a rectifier tube and an inductor; and The control circuit of any one of claims 1-7, which converts an input voltage into an output voltage by repeatedly turning on / off the main power tube and the rectifier tube alternately to convert energy with the inductor.

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