Voltage regulator and reference voltage generation circuit

Abstract

A voltage regulator includes a voltage conversion circuit, a voltage divider, a reference voltage generator, an error amplifier, and a control circuit. The voltage conversion circuit is configured to convert an input voltage to an output voltage according to a first control signal. The voltage divider performs a voltage dividing operation on the output voltage to generate a first feedback voltage and a second feedback voltage. The reference voltage generator is configured to generate a reference voltage according to a second control signal. The error amplifier is configured to generate the first control signal according to a difference between the reference voltage and the first feedback voltage. The control circuit is configured to generate the second control signal according to the second feedback voltage and the reference voltage. In response to a gradual decrease in the second feedback voltage, the reference voltage is adjusted to track the second feedback voltage.

Description

[Technical Field]

[0001] The present invention relates to a voltage regulator, and more particularly, to a voltage regulator and a reference voltage generation circuit. [Background Technology]

[0002] Typically, a voltage regulator provides a range of output voltages. Upon receiving a command to reduce the output voltage, the regulator can operate in dynamic voltages scaling (DVS) buck mode, for example, by reducing the output voltage through negative current flowing to ground via inductors and pull-down transistors; however, this results in wasted power. Alternatively, the regulator can operate in free-running mode, reducing the output voltage to a target level by discharging the regulator's output capacitor through the load. However, in free-running mode, there may be a delay between receiving the command associated with DVS boost operation and the point at which the output voltage begins to increase. This delay can cause the output voltage to not immediately respond to the command, leading to degraded system performance. [Summary of the Invention]

[0003] In a first aspect, the present invention provides a voltage regulator comprising a voltage conversion circuit, a voltage divider, a reference voltage generator, an error amplifier, and a control circuit. The voltage conversion circuit is configured to convert an input voltage into an output voltage according to a first control signal; the voltage divider is configured to divide the output voltage to generate a first feedback voltage and a second feedback voltage; the reference voltage generator is configured to generate a reference voltage according to a second control signal; the error amplifier is configured to generate the first control signal based on the difference between the reference voltage and the first feedback voltage; and the control circuit is configured to generate the second control signal based on the second feedback voltage and the reference voltage; wherein, in response to a gradual decrease in the second feedback voltage (e.g., in a buck mode), the reference voltage is adjusted to track the second feedback voltage.

[0004] In some embodiments, the second feedback voltage is less than the first feedback voltage.

[0005] In some embodiments, the control circuit includes: a comparator configured to perform a comparison operation on the second feedback voltage and the reference voltage to generate a comparison result signal; and a control unit configured to generate the second control signal based on the comparison result signal; wherein, in buck mode, the second feedback voltage gradually decreases, and when the reference voltage is greater than the second feedback voltage, the comparator enables the comparison result signal, and, in response to the enabled comparison result signal, the second control signal is controlled to enable the reference voltage generator to reduce the reference voltage by a preset decrease step size.

[0006] In some embodiments, the control unit is further configured to receive a buck signal, and, in response to the buck signal being enabled, the voltage regulator enters the buck mode.

[0007] In some embodiments, the control unit is further configured to receive a boost signal; wherein, in response to the boost signal being enabled, the voltage regulator enters a boost mode, the second control signal is controlled to enable the reference voltage generator to increase the reference voltage; and, in response to the increase in the reference voltage, the output voltage is increased.

[0008] In some embodiments, in the boost mode, according to the second control signal, the reference voltage generator increases the reference voltage by a preset increment step at predetermined intervals.

[0009] In some embodiments, the control circuit further includes a latching circuit configured to receive and latch the comparison result signal to generate a latched comparison result signal.

[0010] In some embodiments, the latching circuit includes an SR flip-flop and a delay circuit. The SR flip-flop includes a reset terminal, a setting terminal for receiving the comparison result signal, and an output terminal for outputting the latched comparison result signal. The delay circuit is coupled between the reset terminal and the output terminal of the SR flip-flop.

[0011] In some embodiments, in the buck mode, when the reference voltage is greater than the second feedback voltage, the pulse width of the latched comparison result signal is greater than the pulse width of the comparison result signal before latching.

[0012] In some embodiments, the comparator is controlled by a buck signal, and in response to the buck signal being enabled, the voltage regulator enters the buck mode and the comparator is enabled.

[0013] In some embodiments, the voltage conversion circuit includes a capacitor, and the capacitor discharges in buck mode through a load coupled to the voltage regulator.

[0014] In some embodiments, the voltage divider includes: a first resistor including a first end for receiving the output voltage and a second end coupled to a first node, wherein the first feedback voltage is generated at the first node; a second resistor including a first end coupled to the first node and a second end coupled to a second node, wherein the second feedback voltage is generated at the second node; and a third resistor including a first end coupled to the second node and a second end coupled to a ground terminal.

[0015] In some embodiments, the voltage conversion circuit includes: a pulse width modulation (PWM) controller configured to generate a PWM signal according to the first control signal; a driver configured to generate a first drive signal and a second drive signal according to the PWM signal; a P-type transistor including: a first terminal for receiving the input voltage, a second terminal coupled to a first node, and a control terminal for receiving the first drive signal; an N-type transistor including: a first terminal coupled to the first node, a second terminal coupled to a ground terminal, and a control terminal for receiving the second drive signal; an inductor including: a first terminal coupled to the first node, and a second terminal coupled to the output terminal of the voltage regulator; and a capacitor coupled between the output terminal and the ground terminal.

[0016] In some embodiments, the PWM controller includes a comparator, wherein the non-inverting input of the comparator is used to receive the first control signal, and the inverting input of the comparator is used to receive a ramp signal.

[0017] In a second aspect, the present invention provides a reference voltage generating circuit, comprising: a reference voltage generator configured to be controlled by a control signal to generate a reference voltage; and a control circuit configured to generate the control signal based on a feedback voltage and the reference voltage, wherein the reference voltage is configured to track the feedback voltage as the feedback voltage gradually decreases.

[0018] In some embodiments, the control circuit includes: a comparator configured to perform a comparison operation on the feedback voltage and the reference voltage to generate a comparison result signal; and a control unit configured to generate the control signal based on the comparison result signal; wherein, in buck mode, the feedback voltage gradually decreases, and when the reference voltage is greater than the feedback voltage, the comparator enables the comparison result signal, and, in response to the enabled comparison result signal, the control signal is controlled to enable the reference voltage generator to decrease the reference voltage by a preset decrease step size.

[0019] In some embodiments, the reference voltage generation circuit is adapted to a voltage regulator, the control unit is further configured to receive a buck signal, and, in response to the buck signal being enabled, the voltage regulator enters a buck mode.

[0020] In some embodiments, the control unit is further configured to receive a boost signal; wherein, in response to the boost signal being enabled, the voltage regulator enters the boost mode, and the control unit generates the control signal to control the reference voltage generator to increase the reference voltage; and, in response to the increase in the reference voltage, the output voltage is increased.

[0021] In some embodiments, the reference voltage generation circuit is adapted to a voltage regulator, the comparator is controlled by a buck signal, and in response to the buck signal being enabled, the voltage regulator enters a buck mode, and the comparator is enabled.

[0022] Thirdly, the present invention also provides a voltage regulator comprising: a voltage conversion circuit configured to convert an input voltage into an output voltage at an output terminal of the voltage regulator according to a control signal; a voltage divider coupled to the output terminal and configured to generate a first feedback voltage at a first node and a second feedback voltage at a second node, wherein the first feedback voltage and the second feedback voltage are positively correlated with the output voltage, and the second feedback voltage is less than the first feedback voltage; an error amplifier including an inverting input terminal coupled to the first node, a non-inverting input terminal for receiving a reference voltage, and an output terminal for outputting the control signal; and a reference voltage generation circuit configured to generate the reference voltage, wherein, during a buck mode of the voltage regulator, the reference voltage decreases in response to a decrease in the second feedback voltage to track the second feedback voltage.

[0023] In this invention, through the operation of the reference voltage generation circuit and the error amplifier, in buck mode, the reference voltage can dynamically and adaptively track or follow the decrease of the output voltage or the second feedback voltage, thereby improving performance and response speed.

[0024] These and other objects of the invention will be readily understood by those skilled in the art upon reading the following detailed description of the preferred embodiments illustrated in the accompanying drawings. A detailed description will be given in the following embodiments with reference to the accompanying drawings. [Attached Image Description]

[0025] A more complete understanding of the invention can be obtained by reading the following detailed description and referring to the examples given in the accompanying drawings.

[0026] Figure 1 An exemplary embodiment of a voltage regulator is shown.

[0027] Figure 2 It shows Figure 1 An exemplary embodiment of the control circuit for a medium voltage regulator.

[0028] Figure 3 An exemplary embodiment is shown. Figure 2 The timing diagram of the main signals and main voltages of the control circuit.

[0029] Figure 4 It shows Figure 1 An exemplary embodiment of the control circuit for a medium voltage regulator.

[0030] Figure 5 It shows Figure 1 An exemplary embodiment of the control circuit for a medium voltage regulator.

[0031] Figure 6 An exemplary embodiment is shown. Figure 5 The timing diagram of the main signals and voltages of the control circuit.

[0032] Figure 7 An exemplary embodiment of an electronic device is shown. 【Detailed Implementation Methods】

[0033] The following description illustrates preferred embodiments of the present invention and is intended only to exemplify the technical features of the invention, not to limit the scope of the invention. Throughout this specification and claims, certain terms are used to refer to specific elements. Those skilled in the art should understand that manufacturers may use different names for the same element. Therefore, this specification and claims do not distinguish elements by differences in name, but rather by differences in function. The terms "element," "system," and "device" used in this invention can refer to computer-related entities, where the computer can be hardware, software, or a combination of hardware and software. The terms "comprising" and "including" as used in the following description and claims are open-ended terms and should be interpreted as "comprising, but not limited to...". Furthermore, the term "coupled" refers to an indirect or direct electrical connection. Therefore, if a device is described as coupled to another device, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0034] Figure 1 An exemplary embodiment of a voltage regulator 1 is shown. For example, in this embodiment, the voltage regulator 1 is a buck regulator. (See reference...) Figure 1 The voltage regulator 1 includes a voltage conversion circuit 10, a reference voltage generation circuit 13, a voltage divider 14, and an error amplifier (EA) 15. Figure 1In the illustrated embodiment, the voltage conversion circuit 10 is shown to include a pulse-width-modulation (PWM) controller 11, a driver stage 12, an inductor 122, and a capacitor 123, but the invention is not limited thereto. The voltage conversion circuit 10 is configured to convert the input voltage VIN into an output voltage VOUT located at the output terminal T10 according to a first control signal Vc (i.e., control signal S15). It should be noted that the focus of the invention is on the generation of the reference voltage Vref, and the structure of the voltage conversion circuit 10 is not the focus of the invention; therefore, the voltage conversion circuit 10 should not be limited to the exemplary embodiment shown in the figures.

[0035] exist Figure 1 In this embodiment, the drive stage 12 includes a driver 124, a P-type transistor 120, and an N-type transistor 121. The driver 124 is configured to generate drive signals S11A and S11B according to a PWM signal S10. The P-type transistor 120 includes a first terminal for receiving the input voltage VIN, a second terminal coupled to node N10, and a control terminal for receiving the drive signal S11A. The N-type transistor 121 includes a first terminal coupled to node N10, a second terminal coupled to ground GND, and a control terminal for receiving the drive signal S11B. The first terminal of the inductor 122 is coupled to node N10, and the second terminal of the inductor 122 is coupled to the output terminal T10. A capacitor 123 is coupled between the output terminal T10 and the ground GND. The on / off states of the P-type transistor 120 and the N-type transistor 121 are controlled by the drive signals S11A and S11B, respectively, thereby charging and discharging the capacitor 123. Therefore, in voltage regulator 1, output voltage VOUT is generated at output terminal T10, and charge is stored in capacitor 123.

[0036] In one embodiment, the P-type transistor 120 and the N-type transistor 121 are implemented using a P-type metal-oxide-semiconductor (PMOS) transistor and an N-type metal-oxide-semiconductor (NMOS) transistor, respectively. The first terminal, the second terminal, and the control terminal of the P-type transistor 120 correspond to the source, drain, and gate of the PMOS transistor, respectively. The first terminal, the second terminal, and the control terminal of the N-type transistor 121 correspond to the drain, source, and gate of the NMOS transistor, respectively.

[0037] Voltage divider 14 is coupled to output terminal T10 to receive output voltage VOUT and is configured to generate a first feedback voltage and a second feedback voltage that are positively correlated with output voltage VOUT. In one example, the second feedback voltage may be the same as the first feedback voltage. In another example, the second feedback voltage is less than the first feedback voltage. Specifically, voltage divider 14 is configured to divide the output voltage VOUT to generate a voltage such that... Figure 1 The feedback voltages Vfb1 and Vfb2 are shown. In this embodiment, the voltage divider 14 includes resistors 140-142. For example, in a preferred embodiment, the resistance value of resistor 141 is much smaller than that of each of resistors 140 and 142, for example, by orders of magnitude more than a predetermined multiple. Based on the circuit structure of the voltage divider 14, the feedback voltage Vfb2 is less than (e.g., slightly less than) the feedback voltage Vfb1. The first terminal of resistor 140 receives the output voltage VOUT (i.e., coupled to the output terminal T10), and its second terminal is coupled to the first node N11. The first terminal of resistor 141 is connected to the first node N11, and its second terminal is connected to the second node N12. The first terminal of resistor 142 is connected to the second node N12, and its second terminal is connected to the ground terminal GND. The feedback voltage Vfb1 is generated at the first node N11, and the feedback voltage Vfb2 is generated at the second node N12. According to the circuit structure of voltage divider 14, each of the feedback voltages Vfb1 and Vfb2 is positively correlated with or proportional to the output voltage VOUT, but voltage divider 14 is not limited to... Figure 1 The structure shown. For example, any structure that can ensure that the feedback voltages Vfb1 and Vfb2 are both positively correlated with the output voltage VOUT can be used as voltage divider 14. Figure 1 In the embodiment shown, since the feedback voltage Vfb2 is less than Vfb1, the voltage regulator 1 will adjust the reference voltage in advance, which enables the voltage regulator 1 to respond quickly when the output voltage VOUT gradually decreases (i.e., when the voltage regulator 1 is in buck mode).

[0038] The reference voltage generator 130 is configured to generate a reference voltage Vref according to a second control signal S131, and the reference voltage Vref can be used to indicate a target level of the output voltage VOUT (e.g., the reference voltage Vref has a proportional relationship or a preset relationship with the target output level). Figure 1 The non-inverting input (+) of error amplifier 15 receives the reference voltage Vref, and its inverting input (-) receives the feedback voltage Vfb1. Error amplifier 15 generates a control signal S15 at its output based on the difference between the reference voltage Vref and the feedback voltage Vfb1.

[0039] The PWM controller 11 is configured to generate a PWM signal S10 based on a control signal S15 and a ramp signal Vramp. In this embodiment, the PWM controller 11 includes a comparator 100. The non-inverting input (+) of the comparator 100 receives the control signal S15, and its inverting input (-) receives the ramp signal Vramp. The comparator 100 is configured to generate the PWM signal S10 at its output based on the comparison result between the control signal S15 and the ramp signal Vramp. As described above, the driver 124 generates drive signals S11A and S11B based on the PWM signal S10, thereby controlling the P-type transistor 120 and the N-type transistor 121 to convert the input voltage VIN into the output voltage VOUT.

[0040] Based on the above operations, the target level of the output voltage VOUT is determined according to the reference voltage Vref. Therefore, a change in the reference voltage Vref will cause a change in the output voltage VOUT. In this embodiment, the reference voltage generation circuit 13 includes a reference voltage generator 130 and a control circuit 131. The control circuit 131 receives the reference voltage Vref and the feedback voltage Vfb2, and is configured to generate a control signal S131 based on the reference voltage Vref and the feedback voltage Vfb2. Furthermore, the control circuit 131 may also receive a scaling-down signal SDN to indicate a buck mode (e.g., Dynamic Voltage Scaling (DVS) buck (down, DN) mode) and a boost signal SUP to indicate a boost mode (e.g., DVS boost (up, UP) mode). For example, once the buck signal SDN is enabled, it indicates that the voltage regulator 1 expects to reduce from the current level to the desired target level; for example, the output voltage VOUT will gradually decrease to the desired target level. For example, once the boost signal SUP is enabled, it means that voltage regulator 1 expects to increase from the current level to another desired target level.

[0041] In buck mode (SDN signal enabled), load 16 draws current from output terminal T10, causing capacitor 123 to discharge through load 16. Therefore, the output voltage VOUT gradually decreases towards the desired target level. In buck mode, control circuit 131 generates control signal S131 to control reference voltage generator 130 to generate a reference voltage that decreases in response to a decrease in output voltage VOUT or feedback voltage Vfb2 (or alternatively, a decrease or reduction, etc.).

[0042] The following will be based on reference Figure 2 and Figure 3 To describe the operation and structure of control circuit 131.

[0043] Figure 2An exemplary embodiment of the control circuit 131 is shown. Figure 3 A timing diagram of the buck signal SDN, the boost signal SUP, and the comparison result signal S20 is shown according to an exemplary embodiment, and the changes in the feedback voltage Vfb2 and the reference voltage Vref are further shown. To clearly illustrate the operation of the control circuit 131, Figure 2 Voltage divider 14 and reference voltage generator 130 are also shown.

[0044] refer to Figure 2 The control circuit 131 includes a comparator 20 and a control unit 21 (e.g., a digital control unit). The inverting input of the comparator 20 is coupled to a second node N12 (specifically, directly connected) to receive a feedback voltage Vfb2, and the non-inverting input of the comparator 20 is coupled to a reference voltage generator 130 to receive a reference voltage Vref. The comparator 20 is configured to generate a comparison result signal S20 based on the comparison result between the reference voltage Vref and the feedback voltage Vfb2.

[0045] Control unit 21 is coupled to the output of comparator 20 to receive the comparison result signal S20, and is further configured to generate a control signal S131 (e.g., a digital control code) based on the comparison result signal S20. Control unit 21 is also configured to receive a buck signal SDN and a boost signal SUP (which in... Figure 2 (Not shown in the image). In this embodiment, the buck signal SDN and the boost signal SUP will not be enabled simultaneously.

[0046] refer to Figure 3 Before time point T30, the level of feedback voltage Vfb2 is the same as the level of reference voltage Vref. When the buck signal SDN is enabled, for example, during the example period P30 from time point T30 to time point T31, voltage regulator 1 enters buck mode. In buck mode, as load 16 draws current from output terminal T10, capacitor 123 discharges through load 16, thereby gradually decreasing the output voltage VOUT. In response to the gradual decrease of output voltage VOUT, the feedback voltage Vfb2, which is positively correlated with output voltage VOUT, also gradually decreases, moving towards the target level L30 (which is related to the target output level of buck mode, such as if there is a proportional relationship between the two). At time point T30, in response to the decrease of feedback voltage Vfb2, reference voltage Vref is greater than feedback signal Vfb2, thus comparator 20 switches the comparison result signal S20 from a low voltage level to a high voltage level, thereby giving the comparison result signal S20 a rising edge.

[0047] In this embodiment, the control unit 21 receives a buck signal SDN and a comparison result signal S20. The control unit 21 can pre-determine the decreasing amount of the control signal S131 in buck mode, and further pre-determine the increasing amount of the control signal S131 in boost mode. When the control unit 21 receives the enabled buck signal SDN, it generates the control signal S131 based on the decreasing amount. When the control unit 21 receives the enabled boost signal SDN, it generates the control signal S131 based on the increasing amount.

[0048] In buck mode, when the comparison result signal S20 has a rising edge (e.g., at time point T30), the control unit 21 is triggered to reduce the value of the control signal S131 by a predetermined decrease. The reference voltage generator 130 is controlled by the control signal S131, which has already been reduced by the predetermined decrease, to reduce the reference voltage Vref by a predetermined / preset decreasing step. In this embodiment, the preset decreasing step of the reference voltage Vref corresponds to the predetermined decrease of the control signal S131; specifically, the preset decreasing step of the reference voltage Vref is determined by the predetermined decrease of the control signal S131. Figure 3 As shown, in response to the reference voltage Vref decreasing by a preset decreasing step size, the reference voltage Vref will become no greater than the feedback signal Vfb2. Therefore, comparator 20 switches the comparison result signal S20 from a high voltage level back to a low voltage level, giving the comparison result signal S20 a falling edge. Thus, a short pulse 30 appears on the comparison result signal S20, which can be considered as the comparison result signal being enabled. Consequently, control unit 21 generates a control signal S131 in response to the enabled comparison result signal S20.

[0049] refer to Figure 3 Starting at time point T30, the feedback voltage Vfb2 gradually decreases towards the target level L30. At time point T300, in response to the continued decrease of the feedback voltage Vfb2, the reference voltage Vref again becomes greater than the feedback signal Vfb2. Therefore, comparator 20 switches the comparison result signal S20 from a low voltage level to a high voltage level again, giving the comparison result signal S20 another rising edge. When the comparison result signal S20 has a rising edge at time point T300, the control unit 21 is triggered again to decrease the value of the control signal S131 by a predetermined decrease amount. The reference voltage generator 130, controlled by the decreased control signal S131, decreases the reference voltage Vref again by a predetermined decrease step size. Figure 3As shown, in response to the reference voltage Vref decreasing by a preset decreasing step size, the reference voltage Vref becomes no greater than the feedback signal Vfb2. Therefore, comparator 20 switches the comparison result signal S20 back from a high voltage level to a low voltage level, giving the comparison result signal S20 another falling edge. At this time, a short pulse 31 appears on the comparison result signal S20.

[0050] During the period P30 corresponding to the buck mode, once the reference voltage Vref is greater than the feedback signal Vfb2, the comparator 20 enables the comparison result signal S20, causing the comparison result signal S20 to have a rising edge. Each time a rising edge appears on the comparison result signal S20, the control unit 21 decreases the value of the control signal S131 by a predetermined decrement amount. The reference voltage generator 130 is controlled by the decreased control signal S131, thereby decreasing the reference voltage Vref by a predetermined decrement step size.

[0051] According to the above operation, as the feedback voltage Vfb2 gradually decreases, the reference voltage Vref decreases by a predetermined decreasing step size each time the value of the control signal S131 decreases by a predetermined amount. Therefore, in buck mode, as the feedback voltage Vfb2 gradually decreases, the reference voltage Vref is adjusted or controlled to track the feedback voltage Vfb2. Figure 3 During time period P30, the reference voltage Vref approaches (closes) the feedback voltage Vfb2.

[0052] refer to Figure 3 Before the feedback signal Vfb2 reaches the target level L30 of the buck mode, for example, at time point T31, the buck signal SDN is disabled while the boost signal SUP is enabled, and the voltage regulator 1 exits the buck mode and enters the boost mode. In the boost mode, the operation of the comparator 20 does not affect the operation of the control unit 21, and the control unit 21 automatically increases the value of the control signal S131 at predetermined intervals. Figure 3 As shown, the reference voltage generator 130 is controlled by the increased control signal S131 so that the reference voltage Vref is increased by a predetermined increment step at predetermined intervals.

[0053] In boost mode, the voltage conversion circuit 10 and the error amplifier 15 operate based on an increased reference voltage Vref, and the output voltage VOUT gradually increases toward the desired target level. Figure 3 The feedback voltage Vfb2 also gradually increases because it is positively correlated with the output voltage VOUT. In other words, in boost mode, the reference voltage Vref is proactively raised to increase the output voltage VOUT.

[0054] According to the above embodiment, in buck mode, the reference voltage generation circuit 13 (specifically, the reference voltage generator 130) generates a reference voltage Vref that tracks the feedback voltage Vfb2. Therefore, in buck mode, the reference voltage Vref is close to the feedback voltage Vfb2. That is, in buck mode, in response to a decrease in the output voltage VOUT, the reference voltage Vref passively decreases to track or follow the decrease in the output voltage VOUT or the feedback voltage Vfb2.

[0055] If boost mode is enabled (i.e., boost signal is enabled) before the feedback voltage Vfb2 reaches the target level L30 of buck mode, the reference voltage Vref can increase from the current level (e.g., the current level above the target level L30) instead of from the target level L30 because the reference voltage Vref is close to the feedback voltage Vfb2. In response to the reference voltage Vref approaching the feedback voltage Vfb2, the output voltage VOUT can be increased immediately and can be increased from... Figure 3 It can be seen that when the boost signal SUP is enabled, the feedback voltage Vfb2 immediately increases toward the target voltage L31. Therefore, the time delay between the time when the boost signal SUP is enabled and the time when the output voltage VOUT begins to increase is shortened or even eliminated.

[0056] In the above embodiment, the comparison result signal S20 is only meaningful for the buck mode. Therefore, during the time period outside the period P30 when the buck signal SDN is enabled, a portion of the comparison result signal S20 is shown as a dashed line.

[0057] In another embodiment, such as Figure 4 As shown, comparator 20 can be configured to receive a buck signal SDN. When the buck signal SDN is enabled to indicate that the voltage regulator 1 has entered buck mode, comparator 20 is enabled according to the enabled buck signal SDN. In response to the enable of comparator 20, the comparison result signal S20 changes according to the comparison result between the reference voltage Vref and the feedback voltage Vfb2. When the buck signal SDN is disabled to indicate that the voltage regulator 1 is not operating in buck mode, comparator 20 is disabled according to the disabled buck signal SDN. In response to the disable of comparator 20, the comparison result signal S20 is at a predetermined level, for example, a low voltage level.

[0058] In other embodiments, the sampling time for the control unit 21 to sample its input signal is taken into account. To ensure that the control unit 21 can correctly sample the enabled comparison result signal S20, the control circuit 131 may further include, for example, Figure 5The latch circuit 5 is shown. Latch circuit 5 is coupled to comparator 20. Latch circuit 5 receives the comparison result signal S20 and is configured to latch the comparison result signal S20, thereby extending the width of each pulse on the comparison result signal S20. (Reference) Figure 5 The latch circuit 5 includes an SR flip-flop 50 and a delay circuit (in Figure 5 The SR flip-flop 50 (referred to as "DLY") 51 receives the comparison result signal S20 at its setting terminal (S), and its output terminal (Q) outputs the latched comparison result signal S20'. A delay circuit 51 is coupled between the reset terminal (R) and the output terminal (Q) of the SR flip-flop 50. The delay circuit 51 is configured to provide a preset delay Tdelay. Based on the operation of the SR flip-flop 50 and the delay circuit 51, the pulse on the latched comparison result signal S20' (e.g., as shown in the image)... Figure 6 The widths of the pulses 60 and 61 shown are wider than the corresponding pulses on the comparison result signal S20 (e.g., as shown). Figure 3 The widths of the pulses 30 and 31 shown are, for example, width / multiple Tdelay, respectively.

[0059] In buck mode (e.g., at time T30), in response to the reference voltage Vref being greater than the feedback signal Vfb2, comparator 20 switches the comparison result signal S20 from a low voltage level to a high voltage level. In response to the high voltage level of the comparison result signal S20, the latched comparison result signal S20' output from the output (Q) of SR flip-flop 50 is enabled to switch from a low voltage level to a high voltage level, thereby causing a rising edge to appear on the latched comparison result signal S20'. In response to the rising edge on the latched comparison result signal S20', control unit 21 reduces the value of control signal S131 by a predetermined decrease, thereby controlling the reference voltage generator 130 to reduce the reference voltage Vref by a preset decrease step size. In response to the reference voltage Vref being reduced by the preset decrease step size, such as... Figure 6As shown, the reference voltage Vref becomes no greater than the feedback signal Vfb2, and thus, comparator 20 switches the comparison result signal S20 from a high voltage level back to a low voltage level. At this time, the set terminal (S) of SR flip-flop 50 receives the comparison result signal S20 with a low voltage level. The delay circuit 51 delays and latches the comparison result signal S20'. Through the delay circuit 51 delaying and latching the comparison result signal S20', the reset terminal (R) of SR flip-flop 50 will also receive a signal with a high voltage level within an additional preset delay Tdelay following the enabled comparison result signal S20. Therefore, the latched comparison result signal S20' output by the output terminal (Q) of SR flip-flop 50 cannot switch from a high level to a low level before the additional preset delay Tdelay introduced by the delay circuit 51 ends. Figure 6 As shown, pulse 60 appears on the latched comparison result signal S20', which corresponds to pulse 30 on the comparison result signal S20. Based on the operation of the latch circuit 5, the width of pulse 60 is greater than the width of pulse 30.

[0060] Other pulses on the latched comparison result signal S20' are generated according to a similar operation, and the relevant description is omitted here.

[0061] Figure 7 An exemplary embodiment of an electronic device is shown. (Reference) Figure 7 The electronic device 7 includes a power management integrated circuit (PMIC) 70 and a processor 71. The PMIC 70 includes a voltage regulator 1. For example, the processor 71 generates a buck signal SDN and a boost signal SUP based on the operating frequency, number of tasks, and ambient temperature of the electronic device 7. The processor 71 provides the buck signal SDN and the boost signal SUP to the voltage regulator 1 of the PMIC 70. The output voltage VOUT generated by the voltage regulator 1 is provided to the processor 71 as its supply voltage. In this embodiment, the processor 71 can function as a load 16.

[0062] In this invention, through the operation of the reference voltage generation circuit and the error amplifier, in buck mode, the reference voltage dynamically and adaptively tracks or follows the decrease of the output voltage or the second feedback voltage. When the voltage regulator exits buck mode and enters boost mode, the reference voltage can start increasing from the current level instead of from the target level, thereby enabling an immediate increase in the output voltage in response to the increase in the reference voltage. Therefore, the delay time between the point at which the voltage regulator enters boost mode and the point at which the output voltage begins to increase is greatly shortened or even eliminated.

[0063] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various variations and similar structures (as will be apparent to those skilled in the art), such as combinations or substitutions of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such variations and similar structures.

Claims

1. A voltage regulator, comprising: A voltage conversion circuit is configured to convert an input voltage into an output voltage according to a first control signal; A voltage divider is configured to divide the output voltage to generate a first feedback voltage and a second feedback voltage. A reference voltage generator is configured to generate a reference voltage according to a second control signal; An error amplifier is configured to generate the first control signal based on the difference between the reference voltage and the first feedback voltage; as well as The control circuit is configured to generate the second control signal based on the second feedback voltage and the reference voltage. In response to the gradual decrease of the second feedback voltage, the reference voltage is adjusted to track the second feedback voltage.

2. The voltage regulator as claimed in claim 1, wherein, The second feedback voltage is less than the first feedback voltage.

3. The voltage regulator as claimed in claim 1, wherein, The control circuit includes: A comparator is configured to perform a comparison operation between the second feedback voltage and the reference voltage to generate a comparison result signal; and The control unit is configured to generate the second control signal based on the comparison result signal; In buck mode, the second feedback voltage gradually decreases. When the reference voltage is greater than the second feedback voltage, the comparator enables the comparison result signal. In response to the enabled comparison result signal, the second control signal is controlled to enable the reference voltage generator to reduce the reference voltage by a preset decrease step.

4. The voltage regulator as described in claim 3, wherein, The control unit is further configured to receive a buck signal, and, in response to the buck signal being enabled, the voltage regulator enters the buck mode.

5. The voltage regulator as described in claim 3, wherein, The control unit is further configured to receive a boost signal; In response to the boost signal being enabled, the voltage regulator enters boost mode, the second control signal is controlled to enable the reference voltage generator to increase the reference voltage; and in response to the increase in the reference voltage, the output voltage is increased.

6. The voltage regulator as claimed in claim 5, wherein, In this boost mode, according to the second control signal, the reference voltage generator increases the reference voltage by a preset increment step at predetermined intervals.

7. The voltage regulator as claimed in claim 3, wherein, The control circuit also includes: The latch circuit is configured to receive and latch the comparison result signal to generate the latched comparison result signal.

8. The voltage regulator as claimed in claim 7, wherein, The latching circuit includes an SR flip-flop and a delay circuit. The SR flip-flop includes: a reset terminal, a setting terminal for receiving the comparison result signal, and an output terminal for outputting the latched comparison result signal; and The delay circuit is coupled between the reset terminal and the output terminal of the SR flip-flop.

9. The voltage regulator as claimed in claim 7, wherein, In this buck mode, when the reference voltage is greater than the second feedback voltage, the pulse width of the latched comparison result signal is greater than the pulse width of the comparison result signal before latching.

10. The voltage regulator as claimed in claim 3, wherein, The comparator is controlled by a buck signal, and in response to the buck signal being enabled, the voltage regulator enters the buck mode and the comparator is enabled.

11. The voltage regulator as claimed in claim 1, wherein, The voltage conversion circuit includes a capacitor, and the capacitor discharges in buck mode through a load coupled to the voltage regulator.

12. The voltage regulator as claimed in claim 1, wherein, This voltage divider includes: The first resistor includes a first terminal for receiving the output voltage and a second terminal coupled to the first node, wherein the first feedback voltage is generated at the first node; The second resistor includes a first terminal coupled to the first node and a second terminal coupled to the second node, wherein the second feedback voltage is generated at the second node; and The third resistor includes a first end coupled to the second node and a second end coupled to the ground terminal.

13. The voltage regulator as claimed in claim 1, wherein, The voltage conversion circuit includes: A pulse width modulation (PWM) controller is configured to generate a PWM signal according to the first control signal; The driver is configured to generate a first drive signal and a second drive signal based on the PWM signal; The P-type transistor includes: a first terminal for receiving the input voltage, a second terminal coupled to a first node, and a control terminal for receiving the first drive signal. The N-type transistor includes: a first terminal coupled to the first node, a second terminal coupled to ground, and a control terminal for receiving the second drive signal; An inductor includes: a first terminal coupled to the first node, and a second terminal coupled to the output of the voltage regulator; and A capacitor is coupled between the output terminal and the ground terminal.

14. The voltage regulator of claim 13, wherein, The PWM controller includes: A comparator, wherein the non-inverting input of the comparator is used to receive the first control signal, and the inverting input of the comparator is used to receive the ramp signal.

15. A reference voltage generating circuit, comprising: A reference voltage generator is configured to be controlled by a control signal to generate a reference voltage; as well as The control circuit is configured to generate the control signal based on the feedback voltage and the reference voltage. The reference voltage is configured to track the feedback voltage as the feedback voltage gradually decreases; The control circuit includes: A comparator is configured to perform a comparison operation between the feedback voltage and the reference voltage to generate a comparison result signal; and The control unit is configured to generate the control signal based on the comparison result signal; In buck mode, the feedback voltage gradually decreases. When the reference voltage exceeds the feedback voltage, the comparator enables the comparison result signal. In response to the enabled comparison result signal, the control signal is controlled to enable the reference voltage generator to reduce the reference voltage by a preset decrease step size.

16. The reference voltage generating circuit as described in claim 15, wherein, The reference voltage generation circuit is adapted to the voltage regulator, and the control unit is further configured to receive a buck signal, and, in response to the buck signal being enabled, the voltage regulator enters buck mode.

17. The reference voltage generating circuit as described in claim 16, wherein, The control unit is further configured to receive a boost signal; In response to the boost signal being enabled, the voltage regulator enters boost mode, and the control unit generates the control signal to control the reference voltage generator to increase the reference voltage; and in response to the increase in the reference voltage, the output voltage is increased.

18. The reference voltage generating circuit as described in claim 15, wherein, The reference voltage generation circuit is suitable for a voltage regulator. The comparator is controlled by a buck signal, and in response to the buck signal being enabled, the voltage regulator enters buck mode, and the comparator is enabled.

19. A voltage regulator, comprising: A voltage conversion circuit is configured to convert an input voltage into an output voltage at the output terminal of the voltage regulator according to a control signal. A voltage divider, coupled to the output terminal and configured to generate a first feedback voltage at a first node and a second feedback voltage at a second node, wherein the first feedback voltage and the second feedback voltage are positively correlated with the output voltage, and the second feedback voltage is less than the first feedback voltage; and An error amplifier includes an inverting input coupled to the first node, a non-inverting input for receiving a reference voltage, and an output for outputting the control signal; and A reference voltage generation circuit is configured to generate the reference voltage, wherein, during the period when the voltage regulator is in buck mode, the reference voltage decreases in response to a decrease in the second feedback voltage to track the second feedback voltage.

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