Switching circuit and power supply circuit

Abstract

The present switching circuit is provided with a first switching element in which a connection state between a power generating element and an electric storage device is controlled in accordance with a voltage applied to a first control terminal, and a control circuit which outputs a first voltage for keeping the first switching element on to the first control terminal from when a voltage difference between both ends of the electric storage device is in an initial state until the voltage difference increases with time to a first predetermined value larger than the initial state, and outputs a second voltage for keeping the first switching element off to the first control terminal from when the voltage difference exceeds the first predetermined value until the voltage difference drops below a second predetermined value smaller than the first predetermined value.

Description

Technical Field

[0001] This invention relates to switching circuits and power supply circuits. Background Technology

[0002] In order to use the electricity generated by the vibratory power generation element itself as power for operating the control circuit in the power conversion circuit that converts the electricity generated by the vibratory power generation element, it is known to store the electricity generated by the vibratory power generation element or other power generation elements in an energy storage device such as a capacitor and supply the stored electricity to the control circuit. In this case, a cold start switch is provided that has the function of directly connecting the output of the power generation element to the energy storage device, and the control of the circuit is started using the electricity stored in the energy storage device. Subsequently, when the voltage from the power generation element increases, the connection between the output of the power generation element and the energy storage device is disconnected to reduce the power consumption in the cold start switch (Patent Document 1). Figure 5 ).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2014-33494 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] Ideally, the cold start switch should supply the required power as stably as possible. However, in cases where the output varies greatly, as in vibrating generators, it is difficult to turn the cold start switch on or off at the appropriate timing. In such situations, the utilization efficiency of the power generated by the generator decreases.

[0008] The present invention was made in view of the above-mentioned problems. One object of the present invention is to provide a switching circuit and a power supply circuit that can control the on / off state of a cold start switch at appropriate timing and improve the utilization efficiency of the power generated from the power generation element.

[0009] Technical solutions to the problem

[0010] The present invention is a switching circuit comprising: a first switching element that controls the connection state between a power generation element and a power storage device based on a voltage applied to a first control terminal; and a control circuit configured to output a first voltage to the first control terminal as the voltage difference between the two ends of the power storage device increases over time from an initial state until the voltage difference becomes greater than a first predetermined value of the initial state, and to output a second voltage to the first control terminal as the voltage difference exceeds the first predetermined value until the voltage difference becomes lower than a second predetermined value smaller than the first predetermined value, wherein the first voltage is a voltage that keeps the first switching element on and the second voltage is a voltage that keeps the first switching element off.

[0011] In the above configuration, one configuration can be adopted in which the power generation element includes: a power generation unit configured to output alternating current; and a rectifier circuit configured to rectify the alternating current.

[0012] In the above configuration, one configuration can be adopted in which one end of the energy storage device is connected to a reference potential, and the connection state of the other end of the energy storage device to the power generation element is controlled by a first switching element, and the first switching element is an enhancement-mode FET, and the control circuit outputs the voltage of the terminal of the first switching element on the power generation element side as a first voltage, and outputs the reference potential as a second voltage.

[0013] In the above configuration, one configuration can be adopted in which the rectifier circuit generates a positive voltage relative to the reference potential, and the first switching element is an enhancement-mode NFET.

[0014] In the above configuration, one configuration can be adopted in which the rectifier circuit generates a negative voltage relative to the reference potential, and the first switching element is an enhancement-mode PFET.

[0015] In the above configuration, one configuration can be adopted in which one end of the energy storage device is connected to a reference potential, and the connection state of the other end of the energy storage device to the power generation element is controlled by a first switching element, and the first switching element is an enhancement-mode FET, and the control circuit outputs the reference potential as a first voltage, and outputs the voltage of the terminal of the first switching element on the power generation element side as a second voltage.

[0016] In the above configuration, one configuration can be adopted in which the rectifier circuit generates a positive voltage relative to the reference potential, and the first switching element is an enhancement-mode PFET.

[0017] In the above configuration, one configuration can be adopted in which the rectifier circuit generates a negative voltage relative to the reference potential, and the first switching element is an enhancement-mode NFET.

[0018] In the above configuration, one configuration can be adopted in which the switching circuit is further provided with a second switching element. The second switching element is an enhancement-type FET and controls the connection state between the first switching element and the energy storage device according to the voltage applied to the second control terminal. The control circuit outputs a reference potential to the second control terminal as the voltage difference between the two ends of the energy storage device increases over time from the initial state until the voltage difference becomes a first predetermined value. When the voltage difference exceeds the first predetermined value, the control circuit outputs the voltage of the terminal of the second switching element on the energy storage device side to the second control terminal until the voltage difference becomes lower than the second predetermined value.

[0019] In the above configuration, a configuration can be provided in which the switching circuit is further provided with a third switching element. The third switching element controls the connection state between the first control terminal and the reference potential according to the voltage applied to the third control terminal. One end of the energy storage device is connected to the reference potential, and the connection state between the other end of the energy storage device and the power generation element is controlled by the first switching element. The first control terminal is capacitively coupled to the power generation element. The first switching element is an enhancement-mode FET. The control circuit continuously inputs the reference potential to the third control terminal until the voltage difference reaches a first predetermined value, and when the voltage difference exceeds the first predetermined value, it outputs the voltage of the other end of the energy storage device to the third control terminal until the voltage difference becomes lower than a second predetermined value.

[0020] In the above configuration, one configuration may be adopted in which the switching circuit further includes: a fourth switching element, the fourth switching element having a withstand voltage lower than that of the first switching element, the fourth switching element controlling the connection state between the first switching element and the energy storage device according to the voltage applied to the first control terminal; and a limiting element configured to limit the voltage between the first switching element and the fourth switching element to no more than a third predetermined value.

[0021] In the above configuration, one configuration can be adopted in which the control circuit includes a latching circuit, which is configured to output a first voltage to the first control terminal when the voltage difference between the two ends of the energy storage device increases over time from an initial state until the voltage difference becomes a first predetermined value, and to output a second voltage to the first control terminal when the voltage difference exceeds the first predetermined value until the voltage difference becomes lower than a second predetermined value.

[0022] In the above configuration, one configuration can be adopted in which the control circuit resets the latching state of the latching circuit when the voltage difference becomes lower than a second predetermined value, so as to output a first voltage to the control terminal of the first switching element to turn on the first switching element.

[0023] In the above configuration, one configuration can be adopted in which, in the initial state, the voltage difference between the two ends of the energy storage device is 0V.

[0024] The present invention is a power supply circuit, which includes: the aforementioned switching circuit; and a power conversion circuit configured to convert the output power of a power generation element, wherein the switching circuit outputs a signal to the power conversion circuit for activating the power conversion circuit when the voltage difference exceeds a first predetermined value.

[0025] In the above configuration, one option is to keep the switching circuit off when the voltage difference exceeds a first predetermined value until the voltage difference becomes lower than a second predetermined value.

[0026] In the above configuration, one option is to use a configuration in which, when the voltage difference exceeds a first predetermined value, the switching circuit turns off and outputs a signal to the power conversion circuit to activate the power conversion circuit.

[0027] In the above configuration, one configuration can be adopted in which the power conversion circuit is a voltage conversion circuit that includes an inductor and converts the third voltage input from the power generation element into a fourth voltage.

[0028] In the above configuration, one configuration may be adopted in which the switching circuit includes: a determination circuit configured to determine whether the voltage difference exceeds a first predetermined value; and a generation circuit configured to generate a signal for activating the power conversion circuit when the determination circuit determines that the voltage difference exceeds the first predetermined value.

[0029] The effects of the invention

[0030] The present invention provides a switching circuit and a power supply circuit that can control the on / off state of a cold start switch at appropriate timing. Attached Figure Description

[0031] [ Figure 1 ] Figure 1 This is a circuit diagram showing a power supply circuit using a switching circuit according to an embodiment.

[0032] [ Figure 2 ] Figure 2 This is a diagram showing the ON and OFF states of the switch relative to time and the current IL flowing through the inductor in a voltage conversion circuit using a switching circuit according to an embodiment.

[0033] [ Figure 3 ] Figure 3 (a) and Figure 3 (b) is a circuit diagram of the switching circuit according to the first embodiment.

[0034] [ Figure 4 ] Figure 4 This is a circuit diagram of the switching circuit according to the first embodiment.

[0035] [ Figure 5 ] Figure 5 This is a circuit diagram of the control circuit in the first embodiment.

[0036] [ Figure 6 ] Figure 6 This is a circuit diagram of the determination circuit in the first embodiment.

[0037] [ Figure 7 ] Figure 7 It is a graph showing the voltage in the switching circuit according to the first embodiment and the time variation of the FET's on / off state.

[0038] [ Figure 8 ] Figure 8 (a) and Figure 8 (b) is a circuit diagram of the latch circuit in the first embodiment.

[0039] [ Figure 9 ] Figure 9 (a) and Figure 9 (b) is a circuit diagram of a switching circuit according to a first variation of the first embodiment.

[0040] [ Figure 10 ] Figure 10 This is a circuit diagram of a switching circuit according to a first variation of the first embodiment.

[0041] [ Figure 11 ] Figure 11 It is a graph showing the voltage and the time variation of the FET's on / off state in the switching circuit of a first variation of the first embodiment.

[0042] [ Figure 12 ] Figure 12 (a) and Figure 12 (b) is a circuit diagram of a switching circuit according to a second variation of the first embodiment.

[0043] [ Figure 13 ] Figure 13 It is a graph showing the voltage in the switching circuit according to the second embodiment and the time variation of the FET's on / off state.

[0044] [ Figure 14 ] Figure 14 It is a graph showing the voltage and the time variation of the FET's on / off state in the switching circuit of the first variant according to the second embodiment.

[0045] [ Figure 15 ] Figure 15 This is a circuit diagram of the switching circuit according to the third embodiment.

[0046] [ Figure 16 ] Figure 16 This is a circuit diagram of the switching circuit according to the fourth embodiment.

[0047] [ Figure 17 ] Figure 17 This is a circuit diagram of a switching circuit according to a first variation of the fourth embodiment.

[0048] [ Figure 18 ] Figure 18 This is a block diagram showing a system using a switching circuit according to the first to fourth embodiments and their variations. Detailed Implementation

[0049] The embodiments will now be described with reference to the accompanying drawings.

[0050] First Implementation Method

[0051] Figure 1 This is a circuit diagram showing a power supply circuit using a switching circuit according to an embodiment. (e.g.) Figure 1 As shown, the power supply circuit includes a voltage conversion circuit 12 and a switching circuit 20. The switching circuit 20 includes a cold start switch CSW and a control circuit 16. The cold start switch CSW is a switch that turns on and off to connect and disconnect between the input terminal Tin and the output terminal Tout. The control circuit 16 controls the on / off state of the cold start switch CSW. Additionally, the control circuit 16 outputs an enable signal Ven to the voltage conversion circuit 12 to activate it. The output of the power generation element 10 is input to the input terminal Tin of the switching circuit 20 and the input terminal T1 of the voltage conversion circuit 12. The power generation element 10 consists of a power generation unit 10a, such as a vibration power generation element, which serves as an energy harvesting element, and a rectifier circuit 10b. When the power generation unit (power generation section) 10a outputs alternating current, the alternating current output by the power generation unit 10a is rectified by the rectifier circuit 10b and input to the input terminal Tin.

[0052] Vibration-generating elements are, for example, piezoelectric elements using piezoelectric materials or microelectromechanical systems (MEMS) elements using MEMS. These elements are installed on roads, bridges, etc., and generate electricity, for example, through vibrations caused by passing pedestrians or vehicles. The electricity generated by the generating element 10 is micro-electricity and varies over time. A first embodiment is an example where the generating element 10 includes a rectifier circuit 10b in which the output of the generating element 10 is positive relative to ground. In this case, the voltage V2 of capacitor C2 is positive. As described above, the generating element 10 is an element that generates a voltage with one polarity relative to ground (reference potential).

[0053] The output terminal Tout of the switching circuit 20 is connected to one end of the capacitor C2. The capacitor C2 is an energy storage device. The output terminal T2 of the voltage conversion circuit 12 is connected to one end of the capacitor C2. Both the voltage Vout at the output terminal Tout of the switching circuit 20 and the voltage V2 at the output terminal T2 of the voltage conversion circuit 12 are voltages of the capacitor C2 relative to ground. In the following description, when describing the operation of the voltage conversion circuit 12, voltage V2 is used as the voltage of the capacitor C2, while in other descriptions, voltage Vout is used as the voltage of the capacitor C2.

[0054] Voltage conversion circuit 12 converts the voltage V1 at input terminal T1 into voltage V2 at capacitor C2 and outputs it to output terminal T2. The value obtained by dividing voltage V1 by the current input to input terminal T1 corresponds to the input impedance of voltage conversion circuit 12. The values ​​of each element in voltage conversion circuit 12 are preset such that the input impedance of voltage conversion circuit 12 matches the output impedance of power generation element 10. Each unit in voltage conversion circuit 12, including control unit 14, operates using power stored in capacitor C2 from power generation element 10.

[0055] Nodes N01 to N03 are positioned between input terminal T1 and output terminal T2 of voltage conversion circuit 12. One end of switch SW1 is connected to node N01, and the other end is connected to node N02. One end of inductor L1 is connected to node N02, and the other end is connected to node N03. One end of switch SW4 is connected to node N03, and the other end is connected to output terminal T2. One end of primary-side capacitor C1 is connected to node N01, and the other end is connected to ground (reference potential). One end of switch SW2 is connected to node N02, and the other end is connected to ground. One end of switch SW3 is connected to node N03, and the other end is connected to ground. One end of secondary-side capacitor C2 is connected to output terminal T2, and the other end is connected to ground. Switches SW1 to SW4 are turned on or off based on control signals S1 to S4, respectively. Enable signal Ven and voltage Vout are input to control unit 14 of voltage conversion circuit 12, and control unit 14 outputs control signals S1 to S4. The control unit 14 and the control circuit 16 may be, for example, dedicated circuits or processors.

[0056] Figure 2 This is a diagram showing the ON and OFF states of the switch relative to time and the current IL flowing through the inductor in a voltage conversion circuit using a switching circuit according to an embodiment.

[0057] Before the power generation element 10 starts generating electricity, the voltage Vout of capacitor C2 is low, for example, 0V. When the voltage Vout is low, the cold start switch CSW is turned on to connect the output of the power generation element 10 to capacitor C2 without passing through the voltage conversion circuit 12. Since no power is supplied to the voltage conversion circuit 12 to allow it to operate, the voltage conversion circuit 12 does not operate. For example, control signals S1 to S4 are 0V, and at this time, switches SW1 to SW4 are off. When the voltage Vout of capacitor C2 becomes large enough to allow the voltage conversion circuit 12 to operate, the control circuit 16 turns off the cold start switch CSW and outputs an enable signal Ven to the voltage conversion circuit 12. As a result, the voltage conversion circuit 12 is activated and starts operating. The control unit 14 of the voltage conversion circuit 12 is activated to control switches SW1 to SW4.

[0058] At time t00, the value of voltage V2 is V21. Control unit 14 keeps switches SW1 to SW4 in the OFF state. The charge stored in capacitor C1 increases through the current generated by generator element 10, and voltage V1 gradually increases. When the value of voltage V1 exceeds the threshold voltage V11, at time t01, control unit 14 turns on switches SW1 and SW3 and keeps switches SW2 and SW4 in the OFF state. As a result, current IL begins to flow from capacitor C1 through node N01, switch SW1, inductor L1, and switch SW3 to ground. Between time t01 and time t02, current IL gradually increases and the charge in capacitor C1 is released, and thus, voltage V1 gradually decreases. Magnetic field energy is stored in inductor L1.

[0059] At time t02, the value of voltage V1 becomes V12. The value of voltage V2 is V21. Current IL is at its maximum at IL1. Control unit 14 turns off switches SW1 and SW3 and turns on switches SW2 and SW4. Between time t02 and time t03, the magnetic field energy stored in inductor L1 causes current IL to flow from ground through switch SW2, inductor L1, and switch SW4, and capacitor C2 is charged. Voltage V2 increases.

[0060] At time t03, control unit 14 turns off switches SW2 and SW4 and maintains switches SW1 and SW3 in the OFF state. After time t03, the current IL is 0, the voltage V1 is V12, and the voltage V2 is V22. Voltage values ​​V21 and V22 can be lower or higher than voltage values ​​V11 and V12. As described above, when current is input from the generator element 10 to the input terminal T1 during the period when switches SW1 to SW4 are turned off, capacitor C1 is charged. When the voltage relative to ground at node N01 of capacitor C1, i.e., the voltage V1 at input terminal T1, reaches the threshold voltage V11, and voltage conversion circuit 12 operates, the charge in capacitor C1 moves to capacitor C2. The voltage relative to ground at the output terminal T2 of capacitor C2 is the voltage V2 at output terminal T2.

[0061] Figure 3 (a) and Figure 3 (b) is a circuit diagram of the switching circuit according to the first embodiment. Figure 3 As shown in (a), in the first embodiment, the enhancement-mode (normally off mode) NFET M11 is used as a cold-start switch CSW. The threshold voltage of NFET M11 is positive. The source of NFET M11 is connected to the output terminal Tout and the drain is connected to the input terminal Tin. The terminal connected to the output terminal Tout is the first terminal, and the terminal connected to the input terminal Tin is the second terminal. The gate is the control terminal. The cold-start switch CSW is controlled to turn on when the voltage Vout is equal to or lower than a predetermined reference voltage Vref, and to turn off when the voltage Vout is higher than the reference voltage Vref. Therefore, when the voltage Vout is equal to or lower than the reference voltage Vref, the gate of NFET M11 is connected to the drain and no power supply is required. Therefore, when the voltage Vin becomes equal to or greater than the threshold voltage of NFET M11 relative to the voltage Vout, NFET M11 turns on. Figure 3 As shown in (b), when the voltage Vout is higher than the reference voltage Vref, ground potential is applied to the gate of NFET M11. Therefore, NFET M11 is turned off.

[0062] As described above, when the voltage Vout of capacitor C2 is lower than the reference voltage Vref, the cold start switch CSW is not controlled by the control circuit and conducts without power. When the voltage Vout is higher than the reference voltage Vref, the cold start switch CSW is turned off.

[0063] Figure 4 This is a circuit diagram of the switching circuit according to the first embodiment. For example... Figure 4 As shown, the switching circuit 20 includes an NFET M11 and circuit 17. Circuit 17 is as follows: Figure 3As shown in (a), when the voltage Vout is equal to or lower than the reference voltage Vref, a voltage VG is applied to the gate to turn on the NFET M11, and as... Figure 3 As shown in (b), when the voltage Vout is higher than the reference voltage Vref, a voltage VG is applied to the gate to turn off the NFET M11.

[0064] The NFET M11 is in enhancement mode, with its source connected to the output terminal Tout and its drain connected to the input terminal Tin. The power supply terminal Tp of the latch circuit 18 is connected to the drain of the NFET M11. The reference potential terminal Tg is connected to ground. The output terminal Tq1 is connected to the gate of the NFET M11. Based on the voltage Vout, the control circuit 16 outputs voltages Vset and Vrst to the set terminal Tset and reset terminal Trst of the latch circuit 18, respectively. When a high level is input as voltage Vset to terminal Tset, the latch circuit 18 outputs the voltage Vin of the power supply terminal Tp to the output terminal Tq1 until a high level is input to terminal Trst. When a high level is input to terminal Trst as voltage Vrst, the latch circuit 18 outputs the 0V voltage at the reference potential terminal Tg to the output terminal Tq1 until a high level is input to terminal Tset.

[0065] Figure 5 This is a circuit diagram of the control circuit 16 in the first embodiment. (Example) Figure 5 As shown, voltage Vout is input to decision circuits 22 and 24. When voltage Vout is equal to or higher than reference voltages Vref1 and Vref2, decision circuits 22 and 24 output voltage Vout as voltages V01 and V02, respectively. When voltage Vout is lower than reference voltages Vref1 and Vref2, they output ground potential 0V as voltages V01 and V02, respectively.

[0066] When both voltages V01 and V02 go high, spike generation circuit 26 outputs a spike signal as the reset voltage Vrst. When both voltages V01 and V02 go low, spike generation circuit 28 outputs a spike signal as the set voltage Vset. Spike generation circuits 26 and 28 do not require a clock signal, are composed of FETs, and consume power only when generating the output pulse width; therefore, power consumption is low. Thus, they are optimal as circuits for controlling micro-electromotive force elements, such as piezoelectric elements that generate electricity from vibration, which function as power generation elements. The spike signal is a single signal, and the interval between spike signals is sufficiently wide relative to the pulse width of the spike signal.

[0067] Figure 6 This is a circuit diagram of the determination circuit in the first embodiment. For example... Figure 6As shown, in decision circuits 22 and 24, diodes D1 and D2 are connected in series between the input terminal to which voltage Vout is input and ground. Diode D1 is connected in the forward direction, and diode D2 is connected in the reverse direction. Although the connection states of the circuit elements are the same in decision circuits 22 and 24, the values ​​of diodes D1 and D2 are set separately as described below. Node N1 between diodes D1 and D2 outputs voltages V01 and V02 via inverters Iv1 and Iv2. Inverters Iv1 and Iv2 use voltage Vout as the power supply voltage. Regardless of the voltage at its terminals, the reverse current flowing through diode D2 is essentially constant. The forward current flowing through diode D1 depends on the voltage at its terminals. In the low voltage range of Vout, the voltage at node N1 is difficult to increase even as voltage Vout increases, but in the high voltage range of Vout, the voltage at node N1 increases rapidly as voltage Vout increases. When voltage Vout is low, the voltage at node N1 is low, inverter Iv1 outputs voltage Vout, and inverter Iv2 outputs a ground potential of 0V. When the voltage at node N1 increases rapidly due to the increase in voltage Vout, the voltage at node N1 becomes equal to or greater than the threshold voltage of inverter Iv1. Inverter Iv1 outputs a ground potential of 0V, and inverter Iv2 outputs voltage Vout.

[0068] By appropriately setting the values ​​of diodes D1 and D2, a freely selectable reference voltage can be set, such that inverter Iv2 outputs voltage Vout when voltage Vout is equal to or higher than the reference voltage, and outputs ground potential 0V when voltage Vout is lower than the reference voltage. For example, setting diode D1 to be greater than diode D2 allows for a higher reference voltage, and setting diode D1 to be less than diode D2 allows for a lower reference voltage. The values ​​of diodes D1 and D2 in decision circuits 22 and 24 are set such that the reference voltage in decision circuit 22 is Vref1, and in decision circuit 24 it is Vref2, which is higher than Vref1. As a result, when voltage Vout is higher than the reference voltages Vref1 and Vref2, respectively, decision circuits 22 and 24 output voltage Vout as voltages V01 and V02, and when voltage Vout is lower than the reference voltages Vref1 and Vref2, they output ground potential 0V as voltages V01 and V02.

[0069] Figure 7 This is a graph showing the voltage variations in the switching circuit according to the first embodiment, as well as the on / off time variations of the FET. Voltage Vout is indicated by dashed lines for voltages V01 and V02, reset voltage Vrst, and set voltage Vset. Figure 7As shown, at time t11, voltage Vin is approximately 0V, the voltage Vout of capacitor C2 is approximately 0V, the voltage V01 and V02, the reset voltage Vrst and the set voltage Vset are all at ground potential 0V. The voltage VG at the gate of NFET M11 is Vin. NFET M11 is turned off. After time t11, voltage Vin increases. Latch circuit 18 is asymmetrical, and the voltage VG at output terminal Tq1 becomes Vin and increases.

[0070] At time t12, when the voltage VG reaches the threshold voltage Vth of NFET M11, NFET M11 turns on. After time t12, because NFET M11 is on, capacitor C2 begins to charge. As a result, voltage Vout increases. The rates of increase of voltages Vin and Vout may not necessarily be the same.

[0071] When the voltage Vout becomes equal to or greater than the reference voltage Vref1 at time t13, the determination circuit 22 outputs voltage Vout as voltage V01. When the voltage Vout becomes equal to or greater than the reference voltage Vref2 at time t14, the determination circuit 24 outputs voltage Vout as voltage V02. When both voltages V01 and V02 become high, the spike generation circuit 26 outputs spike signal 30 as reset voltage Vrst. The height of spike signal 30 is the same as the height of voltage Vout. The latch circuit 18 outputs the ground potential 0V at the reference potential terminal Tg as voltage VG to the output terminal Tq1. NFET M11 is turned off. When spike signal 30 is output, the control circuit 16 outputs activation to the control unit 14 as an enable signal Ven. As a result, the voltage conversion circuit 12 is activated and starts operating. After time t14, the voltage Vout of capacitor C2 increases due to the output voltage V2 of voltage conversion circuit 12.

[0072] At time t15, voltage Vin begins to decrease, and voltage Vout also begins to decrease. When voltage Vout becomes lower than reference voltage Vref2 at time t16, determination circuit 22 outputs ground potential 0V as voltage V02. When voltage Vout becomes lower than reference voltage Vref1 at time t17, determination circuit 24 outputs ground potential 0V as voltage V01. When both voltages V01 and V02 become ground potential 0V, spike generation circuit 28 outputs spike signal 32 as set voltage Vset. The height of spike signal 32 is the same as the height of voltage Vout. Latch circuit 18 outputs voltage Vin, which is the voltage at power supply terminal Tp, to output terminal Tq1 as voltage VG. NFET M11 is turned on. When spike signal 32 is output, control circuit 16 outputs an enable signal Ven to control unit 14 indicating inactivity. As a result, voltage conversion circuit 12 stops operating. At time t18, voltage Vout becomes essentially 0.

[0073] According to the first embodiment, such as Figure 4 As shown, the NFET M11 (first switching element) has a gate (first control terminal), and the connection state between the power generation element 10 and the capacitor C2 is controlled according to the voltage applied to the gate. Then, as... Figure 7 From time t11 to time t14, as the voltage difference Vout-0V across capacitor C2 increases from its initial state (e.g., 0V) over time, circuit 17 outputs a first voltage to keep NFET M11 on until the voltage difference Vout-0V becomes greater than the initial reference voltage Vref2 (a first predetermined value). When the voltage difference Vout-0V exceeds the reference voltage Vref2, circuit 17 outputs a second voltage to the gate to keep NFET M11 off until the voltage difference Vout-0V becomes lower than the reference voltage Vref1 (a second predetermined value).

[0074] As a result, NFET M11 in the cold start switch CSW is turned on without power. When the reset voltage Vrst is input at time t14, the latch circuit 18 outputs ground potential to the output terminal Tq1 (see...). Figure 7 This allows the NFET M11 to be turned off. Therefore, the cold start switch CSW can be reliably controlled.

[0075] When the voltage difference between voltage Vout and ground potential increases over time and becomes equal to or greater than the reference voltage Vref2 (first reference voltage), control circuit 16 outputs a reset voltage Vrst. Control circuit 16 also outputs an enable signal Ven to activate voltage conversion circuit 12. As a result, voltage Vout increases, and when the power stored in capacitor C2 is used as a power source for, for example, voltage conversion circuit 12, the cold start switch CSW can be turned off. Figure 5The determination circuits 22 and 24 shown function as determination circuits to determine whether the voltage difference between voltage Vout and ground potential exceeds the reference voltage Vref2. The spike generation circuit 26 and control circuit 16 function as generation circuits to generate an enable signal Ven when the determined voltage difference exceeds the reference voltage Vref2.

[0076] When the voltage difference between voltage Vout and ground potential 0V decreases over time and becomes equal to or less than the reference voltage Vref1 (second reference voltage), control circuit 16 outputs set voltage Vset. The output of latch circuit 18 is converted from the second voltage to the first voltage. That is, the latching state of the latch circuit is reset. As a result, for example, when voltage Vout decreases and the power stored in capacitor C2 is no longer used as a power source for voltage conversion circuit 12, cold start switch CSW can be turned on.

[0077] Figure 8 (a) and Figure 8 (b) is a circuit diagram of the latch circuit 18 in the first embodiment. Figure 8 In (a), a NOR-type latch circuit will be described as an example of latch circuit 18. PFETs M7, M10, M2 and NFET M1 are connected in series between the power supply terminal Tp and the reference potential terminal Tg. PFETs M8, M9, M4 and NFET M3 are connected in series between the power supply terminal Tp and the reference potential terminal Tg, and are connected in parallel with these FETs. The gates of PFETs M8 and M7 are connected to the set terminal Tset and the reset terminal Trst, respectively. The gates of PFETs M9 and M10 are connected to the reference potential terminal Tg.

[0078] The drains of PFET M2 and NFET M1 are connected to node Q1, and the gates of PFET M2 and NFET M1 are connected to node Q2. The drains of PFET M4 and NFET M3 are connected to node Q2, and the gates of PFET M4 and NFET M3 are connected to node Q1. PFET M4 and NFET M3 form an inverter, as do PFET M2 and NFET M1. Nodes Q1 and Q2 are memory nodes and maintain complementary voltages.

[0079] Node Q1 is connected to output terminal Tq1, and node Q2 is connected to output terminal Tq2. Nodes Q1 and Q2 are connected to reference potential terminal Tg via NFETs M5 and M6, respectively. The gates of NFETs M5 and M6 are connected to reset terminal Trst and set terminal Tset, respectively.

[0080] When voltage Vrst is low while node Q1 is high and node Q2 is low, NFETs M1 and M5 are off, PFETs M2, M10, and M7 are on, NFETs M3 and M6 are on, and PFETs M4, M9, and M8 are off. When voltage Vrst goes high, NFET M5 turns on and node Q1 goes low. Additionally, PFET M7 turns off. As a result, node Q1 is switched low and node Q2 is switched high. Similarly, when voltage Vset goes high while node Q1 is low and node Q2 is high, node Q1 is switched high and node Q2 is switched low.

[0081] As described above, when a high-level voltage Vset is input to the set terminal Tset, the latch circuit 18 outputs the voltage at the power supply terminal Tp to the output terminal Tq1 and the voltage at the reference potential terminal Tg to the output terminal Tq2 until the high-level voltage Vrst is input to the reset terminal Trst again. When a high-level voltage Vrst is input to the reset terminal Trst, the latch circuit 18 outputs the voltage at the reference potential terminal Tg to the output terminal Tq1 and the voltage at the power supply terminal Tp to the output terminal Tq2 until the high-level voltage Vset is input to the set terminal Tset again.

[0082] The drains of PFETs M7 and M8 can be directly connected to the sources of PFETs M2 and M4 without configuring PFETs M9 and M10. When the voltage levels of nodes Q1 and Q2 are reversed, current flows from the power supply terminal Tp to the reference potential terminal Tg. PFETs M9 and M10 are configured such that no large current flows when the voltage at the power supply terminal Tp is high.

[0083] In the symmetrical latch circuit with nodes Q1 and Q2, when the supply voltage (the voltage at power supply terminal Tp relative to the reference potential terminal Tg) increases from 0V, it is uncertain which of nodes Q1 and Q2 will become the voltage (high level) at power supply terminal Tp. In latch circuit 18, nodes Q1 and Q2 are asymmetrical, and when the supply voltage of latch circuit 18 increases from 0V, the voltage at node Q1 becomes high. Therefore, to achieve asymmetry, the gate width of NFET M5 is adjusted to be narrower than the gate width of NFET M6. For example, the gate length of NFET is 0.8μm, the gate length of PFET is 5μm, the gate width of PFET is 0.6μm, and the gate widths of NFETs M1 and M3 are 0.8μm. In this case, the gate widths of NFETs M5 and M6 are 15μm and 60μm, respectively. Therefore, when the supply voltage increases from 0V, the current I6 flowing through NFET M6 is greater than the current I5 flowing through NFET M5, and the voltage at node Q2 becomes lower than the voltage at node Q1. Consequently, the latch circuit 18 increases, causing node Q1 to become the voltage at the power supply terminal Tp. Other parameters can be changed as long as nodes Q1 and Q2 increase asymmetrically. For example, the gate width of NFET M1 is adjusted to be narrower than the gate width of NFET M3. The gate widths of PFETs M2, M10, and M7 are adjusted to be wider than the gate widths of PFETs M4, M9, and M8, respectively. Therefore, when the supply voltage increases from 0V, the voltage at node Q2 becomes lower than the voltage at node Q1. To, for example, switch the levels of nodes Q1 and Q2 with voltages Vset and Vrst of approximately 1V even when the voltage at the power supply terminal Tp increases to approximately 5V, the gate widths of NFETs M5 and M6 are larger than the gate widths of the other FETs.

[0084] Figure 8 (b) shows an example of a NAND-type latch circuit. Latch circuit 18 includes PFETs M20a to M20c and M21a to M21c, and NFETs M22a to M22d and M23a to M23d. The operation of latch circuit 18 is similar to that in... Figure 8 The operation shown in (a) is the same, and its description is omitted. Whenever the above operation is performed, latch circuit 18 can have... Figure 8 (a) and Figure 8 The circuit configuration other than the circuit configuration shown in (b).

[0085] Figure 8 (a) and Figure 8 The latch circuit 18 shown in (b) is used for... Figure 4The circuit shown applies a voltage VG to the gate of the NFET M11. When the input reset voltage Vrst (first control signal) is applied, the latch circuit 18 continuously inputs a second voltage to the gate of the NFET M11 to turn it off. By using this latch circuit 18, the latch circuit 18 can output a first voltage to the output terminal Tq1 before the input reset voltage Vrst, and can output a second voltage to the output terminal Tq1 when the input reset voltage Vrst is applied. A circuit for generating the second voltage to turn off the NFET M11 can be easily implemented.

[0086] When the set voltage Vset (second control signal) is input, the latch circuit 18 outputs a first voltage to the gate of NFET M11 to turn on NFET M11 until the reset voltage Vrst is input. Therefore, when the set voltage Vset is input to the latch circuit 18, the voltage VG at the gate of NFET M11 becomes the first voltage, and NFET M11 can be turned on.

[0087] [First Variation of the First Embodiment]

[0088] In a first variation of the first embodiment, the PFET is used as a cold start switch (CSW). In this case, the first terminal and the second terminal are the drain and source of the PFET, respectively.

[0089] Figure 9 (a) and Figure 9 (b) is a circuit diagram of a switching circuit according to a first variation of the first embodiment. Figure 9 As shown in (a), in a first variation of the first embodiment, the enhancement-mode PFET M11a is used as a cold-start switch CSW. The threshold voltage of PFET M11a is negative. The source of PFET M11a is connected to the input terminal Tin and the drain is connected to the output terminal Tout. When the voltage Vout is equal to or lower than the reference voltage Vref, the gate of PFET M11a is connected to ground without power. Therefore, when the local potential becomes equal to or lower than the threshold voltage of PFET M11a relative to the voltage Vin, PFET M11a turns on. Figure 9 As shown in (b), when the voltage Vout is higher than the reference voltage Vref, the input terminal Tin is connected to the gate of PFET M11a. Therefore, PFET M11a is turned on.

[0090] Figure 10 This is a circuit diagram of a switching circuit according to a first variation of the first embodiment. For example... Figure 10 As shown, in a first variation of the first embodiment, the first embodiment is... Figure 4In contrast, NFET M11 is replaced with an enhancement-mode PFET M11a. The source of PFET M11a is connected to the input terminal Tin, the drain is connected to the output terminal Tout, and the gate is connected to the output terminal Tq2 of latch circuit 18a. Except for the output terminal Tq2 being connected to the gate of PFET M11a, the configuration of latch circuit 18a is the same as that of latch circuit 18 in the first embodiment. Other circuit configurations are the same as in the first embodiment. Figure 4 The circuit configuration is the same as that in the previous example, so its description has been omitted.

[0091] Figure 11 This is a graph showing the voltage variations in the switching circuit according to a first variation of the first embodiment, as well as the on / off time variations of the FET. The gate voltage of PFET M11a relative to the source voltage is shown as voltage VG-Vin. The threshold voltage of PFET M11a is negative. Figure 11 As shown, the change of voltage Vin with respect to time is... Figure 7 The changes are the same. At time t11, the voltage VG at the gate of PFET M11a is ground potential 0V. PFET M11a is turned off. After time t11, the voltage Vin increases. Voltage VG-Vin is -Vin. Latch circuit 18 is asymmetrical, and when the supply voltage of latch circuit 18 increases from 0V, the voltage at output terminal Tq2 becomes low (that is, ground potential). Even when voltage Vin increases, the voltage at output terminal Tq2 remains at ground potential 0V.

[0092] When the voltage VG-Vin reaches the threshold voltage Vth of PFET M11a at time t12, PFET M11a turns on. After time t12, the voltage Vout increases. When the voltage Vout becomes equal to or greater than the reference voltage Vref2 at time t14, the control circuit 16 outputs a spike signal 30 as the reset voltage Vrst to the reset terminal Trst of the latch circuit 18. The latch circuit 18 outputs the voltage Vin, which is the voltage at the power supply terminal Tp, as the voltage VG to the output terminal Tq2. As a result, the voltage VG-Vin essentially becomes 0V. Therefore, PFET M11a turns off.

[0093] When the voltage Vout becomes lower than the reference voltage Vref1 at time t17, the control circuit 16 outputs a spike signal 32 to the set terminal Tset of the latch circuit 18 as the set voltage Vset. The latch circuit 18 outputs a ground potential of 0V, which is the voltage at the reference potential terminal Tg, to the output terminal Tq2 as the voltage VG. As a result, the voltage VG-Vin becomes -Vin and the PFET M11a turns on. Other configurations and operations are the same as those in the first embodiment, and their description will be omitted.

[0094] In the first embodiment and its first variation, the input voltage Vin is higher than ground potential. In this case, when NFET M11 is used as a cold start switch CSW as in the first embodiment, the first voltage to turn on NFET M11 is the input voltage Vin. When PFET M11a is used as a cold start switch CSW as in the first variation of the first embodiment, the first voltage to turn on PFET M11a is the voltage at ground potential. This configuration allows NFET M11 and PFET M11a to be stably turned on.

[0095] When NFET M11 is used as in the first embodiment for the cold start switch CSW, the second voltage to turn off NFET M11 is the voltage at ground potential. When PFET M11a is used as in the first variation of the first embodiment for the cold start switch CSW, the second voltage to turn off PFET M11a is the voltage Vin. This eliminates the need for additional circuitry to generate the -α or +α used in the second and third variations of the first embodiment.

[0096] In the first embodiment, when the voltage Vout is Figure 7 When the voltage VG becomes higher than the voltage Vin between times t14 and t17, the voltage VG is at ground potential 0V and lower than both voltages Vout and Vin. Therefore, the gate voltage of NFET M11 is lower than the source voltage. Therefore, NFET M11 is turned off. In a first variation of the first embodiment, when the voltage Vout is at... Figure 11 When the voltage VG becomes higher than the voltage Vin between time t14 and time t17, the voltage VG is the voltage Vin and lower than the voltage Vout. Therefore, when the voltage Vin-Vout becomes lower than the threshold voltage of PFET M11a, PFET M11a turns on, and current flows from terminal Tout back to terminal Tin. Therefore, the cold start switch CSW is preferably an NFET M11 as in the first embodiment.

[0097] [Second variation of the first embodiment]

[0098] A second variation of the first embodiment is an example of using the depletion mode (normally on mode) as a cold start switch. Figure 12 (a) and Figure 12 (b) is a circuit diagram of a switching circuit according to a second variation of the first embodiment. Figure 12As shown in (a), in a second variation of the first embodiment, the depletion-mode NFET M11b is used as a cold-start switch CSW. The threshold voltage of the NFET M11b is negative. The source of the NFET M11b is connected to the output terminal Tout and the drain is connected to the input terminal Tin. When the voltage Vout is equal to or lower than the reference voltage Vref, the gate of the NFET M11b is connected to ground without power. As a result, the NFET M11b is turned on. Figure 12 As shown in (b), when the voltage Vout is higher than the reference voltage Vref, a voltage Vout-α (α is positive) is applied to the gate of the NFET M11b. When -α is equal to or less than the threshold voltage of the NFET M11b, the NFET M11b is turned off.

[0099] In a second variation of the first implementation where a depletion-mode NFET is used as a cold-start switch (CSW), the leakage current of the NFET M11b increases unless -α is sufficiently lower than... Figure 12 The reference voltage in (b). When the depletion-mode PFET is used as a cold-start switch (CSW), the threshold voltage of the PFET is positive. To reduce the leakage current of the PFET when it is turned off, a voltage +α sufficiently greater than the threshold voltage is applied to the gate of the PFET. However, additional circuitry is required to generate a sufficiently low -α or a sufficiently high +α, which also consumes additional power. In the first embodiment and its first variation, the use of an enhancement-mode transistor eliminates the need for additional circuitry to generate -α or +α. As a result, the additional power consumption can be reduced.

[0100] The voltage Vin output from the latch circuit 18 to the gates of NFET M11 and PFET M11a can be the voltage Vin at the output terminal Tout that decreases due to the parasitic resistance of the latch circuit 18. Additionally, the ground potential 0V output from the latch circuit 18 to the gates of NFET M11 and PFET M11a can be the voltage at ground potential that increases due to the parasitic resistance of the latch circuit 18.

[0101] Second Implementation Method

[0102] The second embodiment and its variations are examples where the input voltage Vin is lower than ground, the output of the generator element 10 is negative relative to ground, and the voltage V2 of capacitor C2 is negative. In the second embodiment, the enhancement-mode PFET M11a is used as the cold-start switch CSW. The circuit configuration is the same as the first variation of the first embodiment. Figure 9 The circuit configurations are the same, and their descriptions will be omitted.

[0103] Figure 13 This is a graph showing the voltage and the on / off state of the FET in the switching circuit according to the second embodiment over time. Figure 13 As shown, voltages Vin, Vout, V01, V02, reset voltage Vrst, set voltage Vset, and voltage VG are negative. The threshold voltage Vth of PFET M11a is negative. Reference voltages Vref1 and Vref2 are negative. Between times t12 and t14, and between times t17 and t18, voltage VG becomes equal to or lower than the threshold voltage Vth, therefore, PFET M11a turns on. Since voltage VG is higher than the threshold voltage Vth between times t14 and t17, PFET M11a turns off. Other configurations are the same as in the first embodiment. Figure 7 The other configurations are the same, and their descriptions are omitted.

[0104] [First variation of the second embodiment]

[0105] In a first variation of the second embodiment, the enhancement-mode NFET M11 is used as the cold-start switch CSW. The circuit configuration is the same as in the first embodiment. Figure 4 The circuit configuration shown is the same, and its description is omitted. Figure 14 This is a graph showing the voltage and the on / off state of the FET in the switching circuit according to the first variation of the second embodiment over time. Figure 14 As shown, the threshold voltage Vth of NFET M11 is positive. Reference voltages Vref1 and Vref2 are negative. Between times t12 and t14, and between times t17 and t18, the voltage VG-Vin becomes equal to or greater than the threshold voltage Vth, therefore, NFET M11 turns on. Between times t14 and t17, the voltage VG-Vin is essentially 0V and below the threshold voltage Vth, therefore, NFET M11 turns off. Other configurations are similar. Figure 13 The other configurations of the second embodiment shown are the same, and their description is omitted.

[0106] In the second embodiment and its first variation, the input voltage Vin is lower than ground potential. In this case, when PFET M11a is used as in the second embodiment for the cold start switch CSW, the first voltage to turn on PFET M11a is ground potential. When NFET M11 is used as in the first variation of the second embodiment for the cold start switch CSW, the first voltage to turn on NFET M11 is voltage Vin. Therefore, NFET M11 and PFET M11a can be stably turned on.

[0107] When PFET M11a is used as in the second embodiment for the cold start switch CSW, the second voltage to turn off PFET M11a is voltage Vin. When NFET M11 is used as in the first variation of the second embodiment for the cold start switch CSW, the second voltage to turn off NFET M11 is ground potential. Therefore, the need for additional circuitry for generating -α or +α is eliminated.

[0108] In the second embodiment, when the voltage Vout is Figure 13 When the voltage VG becomes higher than the voltage Vin between time t14 and time t17, the voltage VG is higher than the ground potential of both voltage Vout and Vin (0V). Therefore, the gate voltage of PFET M11a is higher than the source voltage. Therefore, PFET M11a is turned off. In the first variation of the second embodiment, when the voltage Vout is... Figure 14 When the voltage VG becomes lower than the voltage Vin between time t14 and time t17, the voltage VG is higher than the voltage Vout of Vin. For this reason, when the voltage Vin-Vout becomes higher than the threshold voltage of NFET M11, NFET M11 turns on and current flows from terminal Tin back to terminal Tout. Therefore, the cold start switch CSW is preferably a PFET M11a as in the second embodiment.

[0109] Third Implementation Method

[0110] In the first embodiment, a voltage drop occurs when NFET M11 is turned on because NFET M11 is diode-connected. Therefore, as in the first variation of the first embodiment, PFET M11a can be used instead of NFET M11. However, in the first variation of the first embodiment, when voltage Vout becomes higher than voltage Vin, current flows from terminal Tout back to terminal Tin. This can cause power loss. The third embodiment is an example of a switching circuit that suppresses the return current from terminal Tout to terminal Tin even when voltage Vout becomes higher than voltage Vin.

[0111] Figure 15 This is a circuit diagram of the switching circuit according to the third embodiment. It differs from the first variation of the first embodiment. Figure 10In contrast, the switching circuit 20 also includes a PFET M2 and a latch circuit 18c. The source of PFET M2 is connected to the drain of PFET M11a, and the drain is connected to the output terminal Tout. The power supply terminal Tp of the latch circuit 18c is connected to the drain of PFET M2. The reference potential terminal Tg of the latch circuit 18c is connected to ground. The output terminal Tq2 of the latch circuit 18c is connected to the gate of PFET M2. Voltages Vset and Vrst are input from the control circuit 16 to the set terminal Tset and reset terminal Trst of the latch circuit 18c, respectively. Other circuit configurations are the same as those in the first variation of the first embodiment. Figure 10 The other circuit configurations are the same, and their descriptions are omitted.

[0112] Reference Figure 11 The operation of the switching circuit in the third embodiment is described. For simplicity, it is assumed that the threshold voltages of PFETs M11a and M2 are substantially 0V and that times t11 and t12 are substantially the same. Figure 11 During the transitions from time t11 to time t14 and from time t17 to time t18, the voltage VG applied to the gate of PFET M11a and the voltage VG2 applied to the gate of PFET M2 are both 0V, and from time t14 to time t17, both voltages VG and VG2 are Vout. Therefore, PFET M2 is turned on when PFET M11a is turned on and turned off when PFET M11a is turned off. Thus, the switching circuit of the third embodiment performs the same operation as the switching circuit 20 of the first variation of the first embodiment (i.e., Figure 11 The operations shown are basically the same.

[0113] As described above, in the third embodiment, the connection state between PFET M2 (the second switching element) and PFET M11a (the first switching element), and the connection state between PFET M2 and capacitor C2, are controlled based on the voltage applied to the gate (the second control terminal). Circuit 17 outputs 0V (the first voltage) to the gate of PFET M2 to keep PFET M2 on until the voltage difference Vout-0V across capacitor C2 becomes the reference voltage Vref2. When the voltage difference Vout-0V exceeds the reference voltage Vref2, circuit 17 outputs Vout (the second voltage) to the gate of PFET M2 to keep PFET M2 off until the voltage difference Vout-0V becomes lower than the reference voltage Vref1. As a result, even when the voltage Vout becomes higher than the voltage Vin during the period between the turn-off of PFET M11a and PFET M2, the gate voltage VG2 of PFET M2 remains Vout and PFET M2 remains off. Therefore, reverse current flow from terminal Tout to terminal Tin can be suppressed. Therefore, power loss can be prevented and power efficiency degradation can be reduced.

[0114] Although the third embodiment has described an example of using an enhancement-type PFET as PFET M11a and PFET M2 when the input voltage Vin is above ground potential, an enhancement-type NFET can be used instead of PFET M11a and PFET M2 when the input voltage Vin is below ground potential.

[0115] Fourth Implementation Method

[0116] The fourth embodiment is an example of a high output voltage (i.e., input voltage Vin) for the power generation element 10. For example, when a device with a small capacitive component, such as an organic piezoelectric element or a microelectromechanical system (MEMS) device using an electret, is used as the power generation element, the output voltage of the power generation element 10 is high, for example, 35V. In this case, a high-voltage FET is used as the NFET M11 of the first embodiment. A high-voltage FET is a FET with a high drain withstand voltage (the withstand voltage between the drain and the source), and a FET with a drain withstand voltage of 35V or higher is used as the NFET M11. However, in the first embodiment, a high voltage is applied to the power supply terminal Tp of the latch circuit 18. The withstand voltage of a typical MOSFET is approximately 5V, and when a voltage higher than 5V is applied to the power supply terminal Tp, the latch circuit 18 is damaged. The fourth embodiment is an example of suppressing damage to the latch circuit 18 even when the voltage Vin becomes high.

[0117] Figure 16 This is a circuit diagram of the switching circuit according to the fourth embodiment. For example... Figure 16 As shown, the gate of NFET M11 is connected to node NG. Capacitor C3 is connected between node NG and input terminal Tin. NFET M11 and capacitor C3 are high-voltage withstand devices, withstanding voltages equal to or greater than 35V. The source and drain of NFET M3 are connected to ground and node NG, respectively. NFET M3 is an enhancement-mode FET. The power supply terminal Tp of latch circuit 18b is connected to the output terminal Tout. The reference potential terminal Tg is connected to ground. The output terminal Tq2 is connected to the gate of NFET M3. Voltages Vset and Vrst are input from control circuit 16 to the set terminal Tset and reset terminal Trst of latch circuit 18b, respectively.

[0118] exist Figure 7During the transition from time t11 to time t14 and from time t17 to time t18, the voltage VG3 applied to the gate of NFET M3 is 0V, and from time t14 to time t17, the voltage VG3 is Vout. If the capacitance of capacitor C3 is made sufficiently large relative to the gate capacitance of NFET M11 and the drain capacitance of NFET M3, then when the voltage Vin increases after time t11, the voltage VG at the gate of NFET M11, which is capacitively coupled to the input terminal Tin, increases to a voltage substantially the same as the voltage Vin. When the voltage VG3 becomes Vout and NFET M3 turns on at time t14, the voltage VG becomes 0V and NFET M11 turns on. When the voltage VG3 becomes 0V and NFET M3 turns on at time t17, the voltage VG becomes substantially Vin and NFET M11 turns on. Other operations of the switching circuit 20 are the same as in the first embodiment. Figure 7 The other operations are the same, and their descriptions will be omitted.

[0119] In the fourth embodiment, the NFET M3 (third switching element) controls the connection state between node NG and the reference potential based on the voltage VG3 applied to its gate (third control terminal). The latch circuit 18b continuously inputs the reference potential to the gate of the NFET M3 until the voltage difference Vout-0V across capacitor C2 reaches the reference voltage Vref1. Furthermore, when the voltage difference Vout-0V exceeds the reference voltage Vref1, it outputs Vout to the gate of the NFET M3 until the voltage difference Vout-0V becomes lower than the reference voltage Vref2. As described above, since the power supply terminal Tp of the latch circuit 18b is connected to the output terminal Tout, damage to the latch circuit 18b can be prevented even when the voltage Vin becomes high.

[0120] [First variation of the fourth embodiment]

[0121] In the fourth embodiment, when the input voltage Vin increases during the turn-off period of NFET M11, leakage current can flow through NFET M11 and current can flow from the input terminal Tin to the output terminal Tout. Specifically, when NFET M11 is a high-voltage FET, the turn-off resistance can be low, and the leakage current can be increased. A first variation of the fourth embodiment is an example of reducing the leakage current of NFET M11.

[0122] Figure 17 This is a circuit diagram of the switching circuit according to the first variation of the fourth embodiment. For example... Figure 17 As shown, compared with the fourth embodiment Figure 16In contrast, the switching circuit 20 also includes an NFET M4 and a Zener diode Zd. The source of the NFET M4 is connected to the output terminal Tout, the drain is connected to the source of the NFET M11, and the gate is connected to node NG. The NFET M4 is an enhancement-mode FET, and the threshold voltage of the NFET M4 is substantially the same as that of the NFET M11. By using a FET with a drain withstand voltage lower than that of the NFET M4 instead of a high-voltage FET for the NFET M4, the turn-off resistance of the NFET M4 can be higher than that of the NFET M11. The anode of the Zener diode Zd is connected to ground, and its cathode is connected to node N4 between the NFETs M11 and M4. The breakdown voltage of the Zener diode Zd is, for example, 5.5V. Other aspects are similar to those in the fourth embodiment. Figure 16 The circuit configuration is the same, and its description is omitted.

[0123] exist Figure 7 In this configuration, when NFET M11 is turned on or off, PFET M2 is turned on or off, respectively. Since NFETs M11 and M4 are connected in series between the input terminal Tin and the output terminal Tout, the leakage current flowing from the input terminal Tin to the output terminal Tout can be reduced when NFETs M11 and M4 are turned off. However, when the turn-off resistance of NFET M4 is high, the voltage at node N4 becomes high. When the voltage at node N4 relative to the output voltage Vout exceeds the drain withstand voltage of NFET M4, NFET M4 can break down. Therefore, the breakdown voltage of the Zener diode Zd is set to be equal to or less than (the drain withstand voltage of NFET M4 - the maximum value of Vout). This configuration prevents the voltage at node N4 - Vout from becoming higher than the drain withstand voltage of NFET M4. Therefore, NFET M4 can be prevented from breaking down.

[0124] In a first variation of the fourth embodiment, the drain withstand voltage of NFET M4 (the fourth switching element) is lower than that of NFET M11, and the connection state between NFET M11 and the output terminal Tout is controlled according to the voltage applied to node N0. A Zener diode Zd (limiting element) limits the voltage at node N4 to ensure it does not exceed the breakdown voltage (a third predetermined value). Therefore, the arrangement of NFET M4 reduces the leakage current flowing from the input terminal Tin to the output terminal Tout. Because a high voltage is applied to NFET M4, the arrangement of Zener diode Zd suppresses the breakdown of NFET M4.

[0125] By positioning the Zener diode Zd closer to the input terminal Tin than the NFET M11, it is possible to prevent the input voltage Vin applied to the NFET M11 from becoming too high. However, when the cold start switch CSW is turned off, the output power of the generator unit 10a can be compared with... Figure 1 The rectifier circuit 10b shown is a different rectifier circuit (e.g., described later). Figure 18 The voltage is rectified in the rectifier circuit 62 shown. In this case, if the voltage Vin at the input terminal Tin is limited, a high voltage will not be applied to the different rectifier circuits. Therefore, as in the first variation of the fourth embodiment, the Zener diode Zd is preferably provided in node N4.

[0126] In the fourth embodiment and its first variation, examples have been described in which an enhancement-type NFET is used as NFET M11 and M4 when the input voltage Vin is higher than the ground potential, but when the input voltage Vin is lower than the ground potential, an enhancement-type PFET is used instead of NFET M11 and M4.

[0127] In the first to fourth embodiments and their variations, when the transistor is enhancement-mode, NFETs M11, M11b, M3, and M4 are turned off when the gate voltage is ground potential 0V and turned on when the gate voltage becomes higher than the positive threshold voltage. PFETs M11a, M11c, and M2 are turned off when the gate voltage (the voltage between the gate and the source) is ground potential 0V and turned on when the gate voltage becomes lower than the negative threshold voltage. For example, NFETs M11, M11b, M3, and M4, as well as PFETs M11a, M11c, and M2, use silicon MOS (metal-oxide-semiconductor) FETs.

[0128] The switching circuit of the first to fourth embodiments and their variations is used as Figure 1 The cold start switch CSW of the voltage conversion circuit 12. When the output reset voltage Vrst is reached, the voltage conversion circuit 12 (power conversion circuit) initiates the conversion of the output power of the generator element 10. In other words, when the output reset voltage Vrst is reached, circuit 17 activates the voltage conversion circuit 12. Although Figure 1 An example of a buck / boost voltage converter circuit as a power supply circuit is shown, but the power supply circuit can be a buck voltage converter circuit, a boost voltage converter circuit, or an inverting voltage converter circuit. The power conversion circuit can be a voltage conversion circuit (e.g., a DC-DC converter) that includes an inductor and converts a third voltage (e.g., DC voltage) input from the generator element 10 to a fourth voltage (e.g., DC voltage). The power supply circuit can also be a power conversion circuit that converts alternating current to direct current, etc.

[0129] Figure 18This is a block diagram illustrating a system using a switching circuit according to any of the first to fourth embodiments and their variations. For example... Figure 18 As shown, the system includes a power generation element 60, rectifier circuits 61 and 62, a matching circuit 63, a voltage conversion circuit 64, a charging management circuit 65, an energy storage device 66, a cold start circuit 67, and a boost circuit 68.

[0130] For example, the power generation element 60 is Figure 1 The generator element 10 generates a small current of alternating current. Rectifier circuit 61 is, for example, a diode bridge, and rectifier circuit 62 is, for example, a synchronous rectifier circuit. Matching circuit 63 matches the output impedance of rectifier circuits 61 and 62 with the input impedance of voltage conversion circuit 64. Voltage conversion circuit 64 is, for example, a... Figure 1 The voltage conversion circuit 12 is a DC-DC converter. The charging management circuit 65 charges one of the plurality of energy storage devices 66. The energy storage device 66 is, for example, a capacitor. The charging management circuit 65 monitors the voltage at the terminals of the plurality of energy storage devices and charges the energy storage device appropriately with the generated power. The cold start circuit 67 is the switching circuit 20 shown in any of the first to fourth embodiments and their variations, and charges the energy storage device 66 with the output current of the rectifier circuit 61 when the energy storage device 66 is almost not charged. The boost circuit 68 is, for example, a charge pump, and generates voltage for the rectifier circuit 62, the voltage conversion circuit 64, etc.

[0131] The operation of the system will now be described. When the power generation element 60 generates a small amount of power in a state where the energy storage device 66 is almost not charged, the rectifier circuit 61 rectifies the small amount of power. The rectifier circuit 61 is preferably a circuit such as a diode bridge that can perform rectification without an external power supply. The rectifier circuit is not limited to a diode bridge, and can also be a rectifier circuit formed by combining FETs with their gates, sources, or drains shorted. A rectifier circuit configured by combining such FETs is suitable for generating small amounts of power in terms of reducing voltage drop compared to a diode bridge. The current rectified by the rectifier circuit 61 reaches the charging management circuit 65 via the cold start circuit 67 and is stored in the energy storage device 66. When the energy storage device 66 is charged to a sufficient voltage, the boost circuit 68 boosts the voltage of the energy storage device 66 to the voltage used by the rectifier circuit 62 and the voltage conversion circuit 64. The voltage of the energy storage device 66 is, for example, 1V, and the voltage output from the boost circuit 68 is, for example, 2V. When the rectifier circuit 62 and the voltage conversion circuit 64 operate using the voltage of the energy storage device 66, the boost circuit 68 can be omitted.

[0132] Matching circuit 63 adjusts the input voltage of rectifier circuits 61 and 62 based on the power output of generator element 60. The input impedance of rectifier circuits 61 and 62 is obtained by dividing the input voltage by the output current of generator element 60. Therefore, matching circuit 63 increases the input voltage when the output current of generator element 60 is high and decreases the input voltage when the output current of generator element 60 is low. Thus, the output impedance of generator element 60 matches the input impedance of rectifier circuits 61 and 62. Matching circuit 63 switches between rectifier circuits 61 and 62 based on the input voltage. For example, if rectifier circuits 61 and 62 are a diode bridge and a synchronous rectifier circuit, respectively, the losses caused by the diode's forward voltage increase when the input voltage becomes equal to or lower than 1V. Therefore, rectifier circuit 62 is used. When the input voltage is equal to or higher than 1V, rectifier circuit 61 is used.

[0133] Voltage conversion circuit 64 converts the input voltage set by matching circuit 63 into a voltage for charging energy storage device 66. The voltage of energy storage device 66 is, for example, 1V or 3.3V. Charging management circuit 65 monitors the voltage of energy storage device 66 and uses the generated power to charge the appropriate energy storage device 66.

[0134] In a system using a power generation element 60 that generates this micro-power, the cold start circuit 67 is powered on without power when no power is stored in the energy storage device 66, and is turned off after power is stored in the energy storage device 66. The cold start switch can be stably controlled by using a switching circuit 20 according to any of the first to fourth embodiments and their variations for the cold start circuit 67.

[0135] In the above-described embodiment, for example, Figure 1 The cold-start switch CSW shown is used as a switching element with a control terminal, and the connection state between the power generation element and the energy storage device is controlled according to the voltage applied to the control terminal according to the invention. A FET is used as such a switching element. Although FETs are preferred due to their low power consumption, the switching element of the invention is not limited to the FET, but can be other switching elements such as bipolar transistor elements or IGBTs (insulated-gate bipolar transistors). In a bipolar transistor element, the first and second terminals are the emitter and collector, and the control terminal is the base. In an IGBT, the first and second terminals are the emitter and collector, and the control terminal is the gate.

[0136] include Figure 4The circuit 17 of the latching circuit 18 shown is used as follows: as the voltage difference between the two ends of the energy storage device increases over time from an initial state, a first voltage is output to the control terminal to keep the transistor on until the voltage difference becomes greater than a first predetermined value of the initial state; and when the voltage difference exceeds the first predetermined value, a second voltage is output to the control terminal to keep the switching element off until the voltage difference becomes less than a second predetermined value smaller than the first predetermined value. Figure 4 In the circuit shown, the normal initial voltage difference between the two ends of the energy storage device is zero volts, but the present invention is not limited to this zero volt. For example, the initial state is based on the amount of charge in the energy storage device with a small amount of charge remaining and the voltage of the capacitor of the energy storage device, and the present invention can be configured with a circuit that does not include a latching circuit and has hysteresis characteristics. The present invention is not limited to this configuration. For example, the present invention also includes a combination of an element whose output voltage has hysteresis characteristics relative to the input voltage and a control circuit that controls the on / off of the switch CSW based on the output voltage of the element.

[0137] Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the spirit of the present invention as described in the claims.

[0138] Explanation of reference numerals in the attached figures

[0139] 10 power generation components

[0140] 12 Voltage Conversion Circuit

[0141] 14 control units

[0142] 16 control circuits

[0143] 17 circuits

[0144] 18 latch circuits

[0145] 20. Switching circuit.

Claims

1. A switching circuit, the switching circuit comprising: A first switching element controls the connection state between the power generation element and the energy storage device based on the voltage applied to the first control terminal. The control circuit controls the voltage of the first control terminal to turn the first switching element on or off. The control circuit includes a latching circuit. The latching circuit is configured to output a first voltage to the first control terminal as the voltage difference between the two ends of the energy storage device increases over time from an initial state until the voltage difference becomes greater than a first predetermined value of the initial state, and to output a second voltage to the first control terminal when the voltage difference exceeds the first predetermined value until the voltage difference becomes lower than a second predetermined value smaller than the first predetermined value, wherein the first voltage is a voltage that keeps the first switching element on and the second voltage is a voltage that keeps the first switching element off.

2. The switching circuit according to claim 1, wherein, The power generation element includes: a power generation unit configured to output alternating current; and a rectifier circuit configured to rectify the alternating current.

3. The switching circuit according to claim 2, in, One end of the energy storage device is connected to a reference potential, and the connection state between the other end of the energy storage device and the power generation element is controlled by the first switching element. Wherein, the first switching element is an enhancement-mode FET, and the control circuit outputs the voltage of the terminal of the first switching element on the power generation element side as the first voltage, and outputs the reference potential as the second voltage.

4. The switching circuit according to claim 3, in, The rectifier circuit generates a positive voltage relative to the reference potential, and The first switching element is an enhancement-mode NFET.

5. The switching circuit according to claim 3, in, The rectifier circuit generates a negative voltage relative to the reference potential, and The first switching element is an enhancement-type PFET.

6. The switching circuit according to claim 2, in, One end of the energy storage device is connected to a reference potential, and the connection state between the other end of the energy storage device and the power generation element is controlled by the first switching element. Wherein, the first switching element is an enhancement-mode FET, and the control circuit outputs the reference potential as the first voltage, and outputs the voltage of the terminal of the first switching element on the power generation element side as the second voltage.

7. The switching circuit according to claim 6, in, The rectifier circuit generates a positive voltage relative to the reference potential, and The first switching element is an enhancement-type PFET.

8. The switching circuit according to claim 6, in, The rectifier circuit generates a negative voltage relative to the reference potential, and The first switching element is an enhancement-mode NFET.

9. The switching circuit according to any one of claims 6 to 8, wherein the switching circuit further comprises: A second switching element, which is an enhancement-mode FET, controls the connection state between the first switching element and the energy storage device based on the voltage applied to the second control terminal. The control circuit outputs the reference potential to the second control terminal when the voltage difference increases from the initial state over time until the voltage difference becomes the first predetermined value, and outputs the voltage of the terminal of the second switching element on the energy storage device side to the second control terminal when the voltage difference exceeds the first predetermined value until the voltage difference becomes lower than the second predetermined value.

10. The switching circuit according to claim 6, further comprising: A third switching element controls the connection state between the first control terminal and the reference potential based on the voltage applied to the third control terminal. One end of the energy storage device is connected to the reference potential, and the connection state between the other end of the energy storage device and the power generation element is controlled by the first switching element. The first control terminal is capacitively coupled to the power generation element. Wherein, the first switching element is an enhancement-mode FET, and The control circuit continuously inputs the reference potential to the third control terminal until the voltage difference reaches the first predetermined value, and when the voltage difference exceeds the first predetermined value, it outputs the voltage of the other end of the energy storage device to the third control terminal until the voltage difference becomes lower than the second predetermined value.

11. The switching circuit according to claim 10, further comprising: A fourth switching element, wherein the withstand voltage of the fourth switching element is lower than that of the first switching element, and the fourth switching element controls the connection state between the first switching element and the energy storage device according to the voltage applied to the first control terminal; as well as A limiting element configured to limit the voltage between the first switching element and the fourth switching element to no more than a third predetermined value.

12. The switching circuit according to claim 1, wherein, When the voltage difference becomes lower than the second predetermined value, the control circuit resets the latching state of the latching circuit to output the first voltage to the control terminal of the first switching element to turn on the first switching element.

13. The switching circuit according to any one of claims 1 to 8, wherein, In the initial state, the voltage difference between the two ends of the energy storage device is 0 V.

14. A power supply circuit, the power supply circuit comprising: The switching circuit according to any one of claims 1 to 8; as well as A power conversion circuit configured to convert the output power of the power generation element. When the voltage difference exceeds the first predetermined value, the switching circuit outputs a signal to the power conversion circuit to activate the power conversion circuit.

15. A power supply circuit, the power supply circuit comprising: A switching circuit includes a first switching element and a control circuit. The first switching element controls the connection state between a power generation element and an energy storage device based on the voltage applied to a first control terminal. The control circuit controls the voltage of the first control terminal to turn the first switching element on or off. as well as A power conversion circuit configured to convert the output power of the power generation element. Wherein, when the voltage difference between the two ends of the energy storage device increases from the initial state over time, the control circuit outputs a first voltage to the first control terminal until the voltage difference becomes greater than a first predetermined value of the initial state. When the voltage difference exceeds the first predetermined value, the control circuit outputs a signal to the power conversion circuit to activate the power conversion circuit and outputs a second voltage to the first control terminal until the voltage difference becomes lower than a second predetermined value smaller than the first predetermined value. The first voltage is the voltage that keeps the first switching element on, and the second voltage is the voltage that keeps the first switching element off.

16. The power supply circuit according to claim 15, wherein, When the voltage difference exceeds the first predetermined value, the control circuit keeps the first switching element off until the voltage difference becomes lower than the second predetermined value.

17. The power supply circuit according to claim 15, wherein, When the voltage difference exceeds the first predetermined value, the control circuit turns off the first switching element and outputs a signal to the power conversion circuit to activate the power conversion circuit.

18. The power supply circuit according to claim 15, wherein, The power conversion circuit is a voltage conversion circuit that includes an inductor and converts the third voltage input from the power generation element into a fourth voltage.

19. The power supply circuit according to claim 15, wherein, The control circuit includes: a determination circuit configured to determine whether the voltage difference exceeds a first predetermined value; and a generation circuit configured to generate the signal for activating the power conversion circuit when the determination circuit determines that the voltage difference exceeds the first predetermined value.

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