Ultrasound sensing panel and signal reading method thereof, ultrasound sensing system

Abstract

The embodiments of the present disclosure provide an ultrasonic sensing panel, a signal reading method thereof and an ultrasonic sensing system. The ultrasonic sensing panel comprises: a plurality of rows and columns of ultrasonic sensing circuits; a plurality of signal reading lines corresponding to the plurality of columns of ultrasonic sensing circuits one by one, the signal reading lines being coupled to the ultrasonic sensing circuits to receive sensing signals; a signal reading pin, the number of which is less than the number of the signal reading lines; a switch module corresponding to the signal reading lines one by one, the switch module being used to provide the signal reading pin with the sensing signals on the signal reading lines under the control of a control signal line; at least two switch modules being coupled to the same signal reading pin, the plurality of switch modules coupled to the same signal reading pin being coupled to different control signal lines, and the different control signal lines being used to control the corresponding switch modules in time, so that the signal reading pin receives the sensing signals on the plurality of signal reading lines in time. The present scheme reduces the number of signal reading pins and reduces the binding process difficulty.

Description

Technical Field

[0001] This disclosure relates to the field of ultrasonic imaging technology, and in particular to an ultrasonic sensing panel and its signal reading method, and an ultrasonic sensing system. Background Technology

[0002] In related technologies, the ultrasonic sensing panels used in ultrasonic imaging systems typically employ a 200*200 array, meaning that multiple ultrasonic sensing circuits within the panel are arranged in a 200*200 array. Each column of ultrasonic sensing circuits corresponds to a signal readout line, which is used to read the sensing signal from that column of ultrasonic sensing circuits. The ultrasonic sensing panel also includes bonding pins, to which the signal readout lines are directly coupled. The ultrasonic sensing panel is bonded to the signal processing circuit via these bonding pins, allowing the signal processing circuit to receive the sensing signals from the signal readout lines.

[0003] As demand changes, the size of ultrasonic sensing panels is gradually increasing, and the number of ultrasonic sensing circuits on these panels is also growing, reaching arrays as large as 1400*1400. This increase in the number of ultrasonic sensing circuit arrays and signal readout lines leads to a greater number of bonding pins on the ultrasonic sensing panel. This increased number of bonding pins increases the difficulty of the bonding process, which is detrimental to the development of ultrasonic imaging systems. Summary of the Invention

[0004] This disclosure provides an ultrasonic sensing panel and its signal reading method, as well as an ultrasonic sensing system, to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of the present disclosure, the present disclosure provides an ultrasonic sensing panel, including:

[0006] Base;

[0007] An ultrasonic sensing circuit is located on one side of the substrate. Multiple ultrasonic sensing circuits are arranged in multiple rows and columns. The ultrasonic sensing circuit is used to emit ultrasonic waves toward the target object and generate sensing signals based on the received echo signals.

[0008] Signal reading lines, multiple signal reading lines correspond one-to-one with multiple columns of ultrasonic sensing circuits, and the signal reading lines are coupled to the ultrasonic sensing circuits in the corresponding columns to receive sensing signals;

[0009] The signal readout pins are located on one side of the substrate, and the number of signal readout pins is less than the number of signal readout lines;

[0010] The switch module corresponds one-to-one with the signal reading line. The switch module is coupled to the control signal line, the signal reading line and the signal reading pin respectively. The switch module is used to provide the sensing signal on the signal reading line to the signal reading pin under the control of the control signal line.

[0011] In this configuration, at least two switch modules are coupled to the same signal readout pin, and multiple switch modules coupled to the same signal readout pin are coupled to different control signal lines. The different control signal lines control the corresponding switch modules in a time-division manner, so that the signal readout pin receives sensing signals from multiple signal readout lines in a time-division manner.

[0012] In some embodiments, the ultrasonic sensing panel further includes a plurality of control signal pins located on one side of the substrate. The control signal pins are coupled to control signal lines and are used to couple to a control signal driving module. The control signal driving module is used to provide control signals to the plurality of control signal lines in a time-division manner.

[0013] In some embodiments, the ultrasonic sensing panel further includes a shift register located on one side of the substrate, with multiple control signal lines coupled to the shift register, which is used to provide control signals to the multiple control signal lines in a time-division manner.

[0014] In some embodiments, the ultrasonic sensing panel further includes timing signal pins, and a shift register is also coupled to the timing signal pins. The timing signal pins are used to couple with a timing drive module, and the shift register is used to provide control signals to multiple control signal lines in a time-division manner under the timing signal drive of the timing drive module.

[0015] In some embodiments, the shift register includes a plurality of cascaded shift units, each shift unit comprising:

[0016] The pull-up submodule is coupled to the signal input terminal and the pull-up node respectively, and is used to provide the signal input terminal signal to the pull-up node under the control of the signal input terminal signal;

[0017] The reset submodule is coupled to the reset signal terminal, the first power supply terminal and the pull-up node respectively, and is used to provide the first power supply terminal signal to the pull-up node under the control of the reset signal terminal signal.

[0018] The first output submodule is coupled to the pull-up node, the first clock signal terminal and the signal output terminal respectively, and is used to provide the signal of the first clock signal terminal to the signal output terminal under the control of the pull-up node;

[0019] The second output submodule is coupled to the reset signal terminal, the first power supply terminal and the signal output terminal respectively, and is used to provide the signal from the first power supply terminal to the signal output terminal under the control of the reset signal terminal.

[0020] The first storage capacitor has two plates that are coupled to the pull-up node and the signal output terminal, respectively.

[0021] Specifically, the signal output terminal of the shift unit is coupled to the control signal line; the signal output terminal of the (i-1)th shift unit is coupled to the signal input terminal of the ith shift unit; the signal output terminal of the ith shift unit is coupled to the reset signal terminal of the (i-1)th shift unit; the signal output terminal of the ith shift unit is coupled to the signal input terminal of the (i+1)th shift unit; and the signal output terminal of the (i+1)th shift unit is coupled to the reset signal terminal of the ith shift unit.

[0022] In some embodiments,

[0023] The reset submodule includes a second transistor and a seventh transistor. The first terminals of the second transistor and the seventh transistor are both coupled to a pull-up node. The second terminals of the second transistor and the seventh transistor are both coupled to a first power supply terminal. The gate of the second transistor is coupled to a reset signal terminal, and the gate of the seventh transistor is coupled to a pull-down node.

[0024] The second output submodule includes a fourth transistor and an eighth transistor. The first terminal of the fourth transistor and the first terminal of the eighth transistor are both coupled to the signal output terminal. The second terminal of the fourth transistor and the second terminal of the eighth transistor are both coupled to the first power supply terminal. The gate of the eighth transistor is coupled to the pull-down node. The gate of the fourth transistor is coupled to the reset signal terminal.

[0025] The shift unit also includes:

[0026] The fifth transistor has its first terminal and gate both coupled to the second clock signal terminal, and its second terminal coupled to the pull-down node.

[0027] The sixth transistor has its gate coupled to the pull-up node, and its first and second terminals coupled to the pull-down node and the first power supply terminal, respectively.

[0028] In some embodiments, the ultrasonic sensing panel includes N groups of ultrasonic sensing circuits, each group of ultrasonic sensing circuits includes M columns of ultrasonic sensing circuits, the number of signal reading pins is N, the N signal reading pins correspond one-to-one with the N groups of ultrasonic sensing circuits, and the M switching modules corresponding to the M columns of ultrasonic sensing circuits in each group of ultrasonic sensing circuits are all coupled to the same signal reading pin.

[0029] There are M control signal lines, and each of the M control signal lines is coupled to one of the M switching modules corresponding to each group of ultrasonic sensing circuits.

[0030] In some embodiments, the ultrasonic sensing circuit includes:

[0031] An ultrasonic sensor is coupled to a second power supply terminal and a first node, respectively. The ultrasonic sensor is used to emit ultrasonic waves toward the target object and receive the echo signal reflected back by the target object.

[0032] The first submodule is coupled to the first control terminal, the bias voltage terminal, and the first node, respectively. It is used to provide the first signal of the bias voltage terminal to the first node under the control of the first control terminal signal during the transmission phase; and to provide the second signal of the bias voltage terminal to the first node under the control of the first control terminal signal during the sampling phase.

[0033] The second submodule is coupled to the second control terminal, the first node, and the second node respectively, and is used to provide the first node's signal to the second node under the control of the second control terminal signal.

[0034] The second storage capacitor is coupled to the second power supply terminal and the second node at its two ends, respectively, and is used to store the signal of the second node.

[0035] The third submodule is coupled to the second node, the third power supply terminal, the gate signal terminal, and the second output terminal, respectively, and is used to provide a sensing signal to the second output terminal based on the signal from the second node and under the control of the gate signal terminal.

[0036] In some embodiments, the ultrasonic sensing panel further includes a gate driving circuit, which is coupled to the gate signal terminal in a row of ultrasonic sensing circuits.

[0037] As a second aspect of this disclosure, this disclosure provides a signal reading method for an ultrasonic sensing panel, applied to the ultrasonic sensing panel in this disclosure, the method comprising:

[0038] When a gate signal is provided to a row of ultrasonic sensing circuits, control signals are provided to multiple control signal lines in a time-division manner so that the signal readout pins can receive sensing signals from multiple signal readout lines in a time-division manner.

[0039] In some embodiments, the ultrasonic sensing panel includes N groups of ultrasonic sensing circuits, each group of ultrasonic sensing circuits includes M columns of ultrasonic sensing circuits, the number of signal reading pins is N, the N signal reading pins correspond one-to-one with the N groups of ultrasonic sensing circuits, and the M switching modules corresponding to the M columns of ultrasonic sensing circuits in each group of ultrasonic sensing circuits are all coupled to the same signal reading pin; the number of control signal lines is M, and the M control signal lines are coupled one-to-one with the M switching modules corresponding to each group of ultrasonic sensing circuits;

[0040] The methods include:

[0041] When a grid signal is provided to a row of ultrasonic sensing circuits, control signals are provided to N control signal lines in a time-division manner, so that each signal readout pin receives the sensing signals from the N signal readout lines in the corresponding group in a time-division manner.

[0042] As a third aspect of the present disclosure, the present disclosure provides an ultrasonic sensing system, including the ultrasonic sensing panel of the present disclosure, and further including a signal processing module. The signal processing module includes multiple signal conversion circuits, which are coupled one-to-one with multiple signal reading pins. The signal conversion circuits are used to receive sensing signals on the signal reading pins and convert the sensing signals into voltage signals for processing by the signal processing module.

[0043] In some embodiments, a control signal driving module is also included. The control signal driving module is coupled to the control signal line through the control signal pin on the ultrasonic sensing panel. The control signal driving module is used to provide control signals to multiple control signal lines in a time-division manner.

[0044] In some embodiments, the ultrasonic sensing panel further includes a timing drive module. The ultrasonic sensing panel also includes a shift register located on one side of the substrate. Multiple control signal lines are coupled to the shift register. The ultrasonic sensing panel also includes timing signal pins. The timing drive module is coupled to the shift register through the timing signal pins. The timing drive module is used to provide timing signals to the shift register to drive the shift register to provide control signals to the multiple control signal lines in a time-division manner.

[0045] In the technical solution of this disclosure, the switch modules correspond one-to-one with the signal reading lines. At least two switch modules are coupled to the same signal reading pin, and multiple switch modules coupled to the same signal reading pin are coupled to different control signal lines. Different control signal lines control their corresponding switch modules in a time-division manner, allowing the signal reading pin to receive sensing signals from multiple signal reading lines in a time-division manner. This achieves a situation where the number of signal reading pins is less than the number of signal reading lines. Furthermore, by setting different control signal lines to control the corresponding switch modules in a time-division manner, the signal reading pin can receive sensing signals from multiple signal reading lines in a time-division manner. This approach allows the signal reading pin to not only read the sensing signals from each signal reading line separately but also reduces the number of signal reading pins, thereby reducing the area of ​​the bonding region and lowering the difficulty of bonding the ultrasonic sensing panel and the signal processing module, which is beneficial for the commercialization of high-resolution ultrasonic sensing panels.

[0046] The above overview is for illustrative purposes only and is not intended to be limiting in any way. Further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Attached Figure Description

[0047] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this disclosure and should not be construed as limiting the scope of this disclosure.

[0048] Figure 1 This is a schematic diagram of the structure of an ultrasonic sensing system;

[0049] Figure 2A This is a schematic diagram of an ultrasonic sensing circuit;

[0050] Figure 2B for Figure 2A A timing diagram of the ultrasonic sensing circuit shown.

[0051] Figure 3 This is a schematic diagram of the internal structure of a signal processing module in a related technology;

[0052] Figure 4 This is a schematic diagram of the structure of an ultrasonic sensing system in one embodiment of the present disclosure;

[0053] Figure 5 This is a schematic diagram of the structure of an ultrasonic sensing system in another embodiment of the present disclosure;

[0054] Figure 6 This is a structural block diagram of a shifting unit in one embodiment of the present disclosure;

[0055] Figure 7 This is a schematic diagram of the structure of a shift register in one embodiment of the present disclosure;

[0056] Figure 8 This is a schematic diagram of the structure of a shift unit in one embodiment of the present disclosure;

[0057] Figure 9A This is a schematic diagram of a shifting unit.

[0058] Figure 9B for Figure 9A A timing diagram of the shift unit shown;

[0059] Figure 10A This is a schematic diagram of another type of shift unit;

[0060] Figure 10B for Figure 10A A timing diagram of the shift unit shown;

[0061] Figure 11 This is a schematic diagram of the signal processing module in one embodiment of the present disclosure;

[0062] Figure 12 This is a timing diagram of an ultrasonic sensing system according to an embodiment of the present disclosure. Detailed Implementation

[0063] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure, and different embodiments can be combined arbitrarily without conflict. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0064] Figure 1 This is a schematic diagram of the structure of an ultrasonic sensing system. Figure 1 As shown, the ultrasonic sensing system includes an ultrasonic sensing panel 11 and a signal processing module 12. The ultrasonic sensing panel 11 includes a substrate and multiple ultrasonic sensing circuits 111 disposed on one side of the substrate. The multiple ultrasonic sensing circuits 111 are arranged in multiple rows and columns. The ultrasonic sensing circuits 111 are used to emit ultrasonic waves toward the target object and generate sensing signals based on the received echo signals. It should be noted that this article... Figure 1 , Figure 4 and Figure 5 In order to facilitate the arrangement of the diagram, the horizontal direction is taken as the column direction and the vertical direction as the row direction.

[0065] like Figure 1 As shown, the ultrasonic sensing panel 11 also includes multiple signal reading lines (Read) located on one side of the substrate. The number of signal reading lines (Read) is the same as the number of columns of the ultrasonic sensing circuit 111, and the multiple signal reading lines (Read) correspond one-to-one with the multiple columns of ultrasonic sensing circuits 111. The signal reading lines (Read) are coupled to the ultrasonic sensing circuits 111 in the corresponding columns so that the signal reading lines (Read) can receive the sensing signals of the ultrasonic sensing circuits 111.

[0066] In related technologies, the signal read line Read is directly connected to the signal processing module 12, such as... Figure 1 As shown, the signal processing module 12 includes a Mux (multiplexed) analog switch circuit. One Mux analog switch circuit can be connected to multiple signal readout lines (Read). For example, the signal processing module 12 may include N Mux analog switch circuits, namely Mux 1, Mux 2, ..., Mux N. One Mux analog switch circuit can be connected to 16 signal readout lines (Read). The Mux analog switch circuit uses time-division multiplexing to switch the readout channels, which can greatly reduce the number of physical acquisition channels in the signal processing module 12.

[0067] Figure 2A This is a schematic diagram of an ultrasonic sensing circuit. Figure 2AAs shown, the ultrasonic sensing circuit 111 includes an ultrasonic sensor 31, a first submodule 32, a second submodule 33, a second storage capacitor C2, and a third submodule 34. The ultrasonic sensor 31 is coupled to a second power supply terminal GND and a first node N1, respectively. The ultrasonic sensor 31 is used to emit ultrasonic waves towards the target and receive the echo signals reflected back from the target.

[0068] The first submodule 32 is coupled to the first control terminal, the bias voltage terminal, and the first node N1, respectively. It is used to provide the first signal Vbias1 of the bias voltage terminal to the first node N1 under the control of the signal Vrst of the first control terminal during the transmission phase, and to provide the second signal Vbias2 of the bias voltage terminal to the first node N1 under the control of the signal Vrst of the first control terminal during the sampling phase. The second signal Vbias2 is different from the first signal Vbias1.

[0069] The second submodule 33 is coupled to the second control terminal, the first node N1 and the second node N2 respectively, and is used to provide the signal of the first node N1 to the second node N2 under the control of the second control terminal signal Vclose.

[0070] The second storage capacitor C2 is coupled to the second power supply terminal GND and the second node N2 respectively, and is used to store the charge of the second node N2.

[0071] The third submodule 34 is coupled to the second node N2, the third power supply terminal VDD, the gate signal terminal Gate, and the second output terminal OUT2, respectively, and is used to provide a sensing signal to the second output terminal OUT2 based on the signal of the second node N2 and under the control of the gate signal terminal Gate.

[0072] For example, the ultrasonic sensor 31 includes at least one of a PVDF (polyvinylidene fluoride) sensor, a CMUT (capacitive micromechanical ultrasonic transducer), and a PMUT (piezoelectric micromechanical ultrasonic transducer). In practical applications, the material of the ultrasonic sensor 31 can be designed and determined according to the actual application environment, and is not limited here.

[0073] The first submodule 32 may include a first transistor T1, the gate of the first transistor T1 being coupled to a first control terminal, the first electrode of the first transistor T1 being coupled to a bias voltage terminal, and the second electrode of the first transistor T1 being coupled to a first node N1.

[0074] The second submodule 33 may include a second transistor T2, the gate of which is coupled to a second control terminal, and the first and second terminals of the second transistor T2 are coupled to a first node N1 and a second node N2, respectively.

[0075] The third submodule 34 includes a third transistor T3 and a fourth transistor T4. The gate of the third transistor T3 is coupled to the second node N2, and the first terminal of the third transistor T3 is coupled to the third power supply terminal VDD. The gate of the fourth transistor T4 is coupled to the gate signal terminal Gate, the second terminal of the third transistor T3 is coupled to the first terminal of the fourth transistor T4, and the second terminal of the fourth transistor T4 is coupled to the second output terminal OUT2.

[0076] The bias voltage terminal provides a bias voltage for the conduction of the third transistor T3; the first control terminal provides a reset signal after each frame of data is read, and the signal of the first control terminal can control the conduction of the first transistor T1 and the acquisition of echo signals; the signal of the second control terminal provides a circuit for the sensing voltage of the ultrasonic sensor 31, and can latch the voltage of the second storage capacitor C2 after the second control terminal controls the second transistor T2 to turn off; the second storage capacitor C2 can be a parasitic capacitor used to store the echo signal sensing voltage; the third power supply terminal VDD provides a DC voltage for the third transistor T3; the signal of the gate signal terminal Gate is a row scan strobe signal.

[0077] Figure 2B for Figure 2A The diagram shows a timing sequence of the ultrasonic sensing circuit. The following section combines... Figure 2B illustrate Figure 2A The working process of the ultrasonic sensing circuit 111 shown.

[0078] During the transmission phase (t0-t1), the signal Vrst at the first control terminal is high, the signal Vclose at the second control terminal is high, the gate signal terminal is low, and the bias voltage signal Vbias is low. The first transistor T1 and the second transistor T2 are both turned on, while the fourth transistor T4 is turned off. The first node N1 and the second node N2 are the first signals at the bias voltage terminals, i.e., low-level signals. The drive signal Tx drives the ultrasonic sensor 31 to emit ultrasonic waves.

[0079] During the sampling phase (t1-t2), the signal Vrst at the first control terminal is high, the signal Vclose at the second control terminal is high, and the signal Vbias at the bias voltage terminal is high. Both the first transistor T1 and the second transistor T2 are turned on. The second node N2 receives the second signal (high) from the bias voltage terminal, charging itself. This charging voltage is stored in the second storage capacitor C2, which performs the sampling. After sampling, the signal Vrst at the first control terminal goes low, the first transistor T1 is turned off, and the final potential of the second node N2 is affected by the echo signal.

[0080] During the hold phase (t2-t3), and the phase preceding the hold phase (t2-t3'), the first control terminal signal Vrst is low, the second control terminal signal Vclose is high, the gate signal terminal Gate is low, the first transistor T1 and the fourth transistor T4 are both off, the second transistor T2 is on, and the first node N1 and the second node N2 are at the same potential. After the echo ends, i.e., during the t3'-t3 phase, the first control terminal is low, the second control terminal is low, and the first transistor T1, the second transistor T2, and the fourth transistor T4 are all off to reduce leakage current.

[0081] During the readout phase (t3-t4), the first control terminal signal Vrst is low, the second control terminal signal Vclose is low, the gate signal terminal Gate is high, the first transistor T1 and the second transistor T2 are both off, the fourth transistor T4 is on, and the potential of the second node N2 is converted into a current signal (i.e., an induced signal) through the third transistor T3 and output from the second output terminal OUT2.

[0082] In one embodiment, the ultrasonic sensing panel 11 may further include a gate driving circuit, i.e., a GOA circuit, which may be coupled to the gate signal terminal Gate in a row of ultrasonic sensing circuits 111, and the gate driving circuit may provide a gate signal to the ultrasonic sensing circuits 111.

[0083] Figure 3 This is a schematic diagram of the internal structure of a signal processing module in a related technology. For example... Figure 3 As shown, the signal processing module 12 also includes multi-stage amplifier circuits, such as an IV converter circuit, a differential amplifier circuit, a VGA amplifier circuit, an 8th-order Bessel filter, and an analog-to-digital converter circuit.

[0084] The Mux analog switch circuit is connected in a time-division multiplexing manner to one of the multiple Read signal read lines to read the sensing signal on that Read line. The first stage amplifier circuit is an IV converter circuit, which converts current into voltage; the second stage amplifier circuit is a differential amplifier circuit; the third stage is a VGA variable gain amplifier circuit; the fourth stage is an 8th order Bessel filter; and the last stage is an analog-to-digital converter (ADC) circuit, which acquires the amplified voltage signal and transmits it to the host computer software. Vref1 and Vref2 are bias voltages, whose values ​​can be adjusted according to the output current to ensure operation in the amplification region.

[0085] Among them, the Mux analog switch circuit uses time-division multiplexing to switch the sensor signal readout channels, which can greatly reduce the number of physical acquisition channels.

[0086] Figure 3In this circuit, the IV converter, also known as the current-to-voltage converter, converts the current signal output from the ultrasonic sensor circuit 111 into a voltage signal. The differential amplifier circuit increases the driving capability and provides impedance matching with the back-end. The variable gain amplifier (VGA) circuit allows programmable amplification. A DAC chip (e.g., AD5724) provides precise reference voltages to the first and second stage amplifier circuits and the AD8336. Vref1 is connected to a pin in the IV converter circuit, and Vref2 is connected to a pin in the differential amplifier circuit, thereby adjusting the bias voltage of the amplifier output. An 8th-order Bessel filter with a cutoff frequency of 1MHz filters out high-frequency noise. The analog-to-digital converter converts the analog signal into a digital signal and transmits it to the back-end FPGA (Field-Programmable Gate Array) for data signal processing.

[0087] Vref1 and Vref2 can adjust the static operating points of the first two amplifier stages, respectively; Vgain can adjust the amplification factor of the VGA variable gain amplifier circuit; Vref1, Vref2, and Vgain can be provided by a DAC chip (e.g., AD5724), with a voltage range of -5V to +5V; the output voltage of the DAC chip can be controlled by the FPGA program.

[0088] In related technologies, the ultrasonic sensing panel 11 includes a first binding area, which is provided with multiple binding pins. Multiple signal reading lines Read are connected to the multiple binding pins one by one. The first binding area is bound to the signal processing module 12 to realize the connection between the signal reading lines Read and the MUX analog switch circuit in the signal processing module 12.

[0089] The ultrasonic sensing panel 11 of the related technology has a low resolution, that is, the number of ultrasonic sensing circuits 111 in the ultrasonic sensing panel 11 is small. For example, a 200*200 ultrasonic sensing circuit 111 array is usually used. Such an ultrasonic sensing panel 11 has a small number of signal reading lines (Read). Correspondingly, the number of bonding pins in the first bonding area is also small, making it easy to achieve bonding connection between the first bonding area and the signal processing module 12.

[0090] With technological advancements and changing demands, the size and resolution of the ultrasonic sensing panel 11 have gradually increased. For example, the number of ultrasonic sensing circuits 111 in the ultrasonic sensing panel 11 has reached 1400*1400. This has led to an increase in the number of signal reading lines (Read), the number of bonding pins, and the area of ​​the first bonding region. This not only exceeds the frame size of the ultrasonic sensing panel 11 but also increases the difficulty of bonding and connecting the ultrasonic sensing panel 11 with the signal processing module 12, which is not conducive to the commercialization of high-resolution ultrasonic sensing panels 11.

[0091] To address some problems in related technologies, this disclosure provides an ultrasonic sensing panel.

[0092] Figure 4 This is a schematic diagram of the structure of an ultrasonic sensing system according to an embodiment of the present disclosure. Figure 5 This is a schematic diagram of the structure of an ultrasonic sensing system according to another embodiment of this disclosure. Figure 4 and Figure 5 As shown, the ultrasonic sensing system may include an ultrasonic sensing panel 11 and a signal processing module 12. The ultrasonic sensing panel 11 includes a substrate and a plurality of ultrasonic sensing circuits 111 disposed on one side of the substrate. The plurality of ultrasonic sensing circuits 111 are arranged in multiple rows and columns. The ultrasonic sensing circuits 111 are used to emit ultrasonic waves toward the target and generate sensing signals based on the received echo signals.

[0093] The ultrasonic sensing panel 11 also includes multiple signal reading lines (Read) located on one side of the substrate, each of which corresponds to a column of ultrasonic sensing circuits 111. The signal reading lines (Read) are coupled to the ultrasonic sensing circuits 111 in the corresponding column to receive the sensing signals generated by the ultrasonic sensing circuits 111.

[0094] like Figure 4 and Figure 5 As shown, the ultrasonic sensing panel 11 also includes a signal reading pin, Read_out, located on one side of the substrate. For example, the signal reading pin Read_out may be located on the side of the substrate facing the signal reading line Read. Exemplarily, the ultrasonic sensing panel 11 may include a first bonding region, and the signal reading pin Read_out may be located in the first bonding region. The number of signal reading pins Read_out is less than the number of signal reading lines Read.

[0095] The ultrasonic sensing panel 11 may further include a switch module 112, and multiple switch modules 112 may correspond one-to-one with multiple signal readout lines Read. The switch module 112 is coupled to the control signal line CtrL, the signal readout line Read, and the signal readout pin Read_out, respectively. The switch module 112 is used to provide the sensing signal on the signal readout line Read to the signal readout pin Read_out under the control of the control signal line CtrL.

[0096] like Figure 4 and Figure 5As shown, at least two switch modules 112 are coupled to the same signal read pin Read_out, meaning that one signal read pin Read_out is coupled to at least two switch modules 112. For example, the signal read pin Read_out1 is coupled to at least switch modules 112a and 112b. Multiple switch modules 112 coupled to the same signal read pin Read_out are coupled to different control signal lines CtrL. For example, switch modules 112a, 112b, and 112c are coupled to the same signal read pin Read_out1. Switch module 112a is coupled to control signal line CtrL1, switch module 112b is coupled to control signal line CtrL2, and switch module 112c is coupled to control signal line CtrL3. Control signal lines CtrL1, CtrL2, and CtrL3 are different control signal lines CtrL.

[0097] Different control signal lines CtrL control the corresponding switch modules 112 in a time-division manner, enabling the signal reading pin Read_out to receive sensing signals from multiple signal reading lines Read in a time-division manner. For example, control signal lines CtrL1, CtrL2, and CtrL3 control the corresponding switch modules 112a, 112b, and 112c in a time-division manner. When control signal line CtrL1 controls switch module 112a to conduct during the first time period, the signal reading pin Read_out1 receives the sensor signal on signal reading line Read1, which corresponds to switch module 112a. When control signal line CtrL2 controls switch module 112b to conduct during the second time period, the signal reading pin Read_out1 receives the sensor signal on signal reading line Read2, which corresponds to switch module 112b. When control signal line CtrL3 controls switch module 112c to conduct during the third time period, the signal reading pin Read_out1 receives the sensor signal on signal reading line Read3, which corresponds to switch module 112c. Therefore, the signal reading pin Read_out can receive sensor signals from multiple signal reading lines Read in a time-division multiplexing manner.

[0098] In this embodiment, each switch module 112 corresponds one-to-one with a signal reading line Read. At least two switch modules 112 are coupled to the same signal reading pin Read_out. Multiple switch modules 112 coupled to the same signal reading pin Read_out are coupled to different control signal lines CtrL. The different control signal lines CtrL control the corresponding switch modules 112 in a time-division manner, so that the signal reading pin Read_out receives the sensing signals from multiple signal reading lines Read in a time-division manner, thus realizing that the number of signal reading pins Read_out is less than the number of signal reading lines Read. Furthermore, by setting different control signal lines CtrL to control the corresponding switch modules 112 in a time-division manner, the signal reading pin Read_out receives the sensing signals from multiple signal reading lines Read in a time-division manner. In this way, the signal reading pin Read_out can not only read the sensing signals from each signal reading line Read separately, but also reduce the number of signal reading pins Read_out, thereby reducing the area of ​​the first binding region, reducing the difficulty of binding and connecting the ultrasonic sensing panel 11 and the signal processing module 12, and facilitating the commercialization of the high-resolution ultrasonic sensing panel 11.

[0099] For example, the material of the substrate can be set as needed. For instance, the substrate material can be glass, or the substrate can be a flexible substrate.

[0100] like Figure 4 and Figure 5 As shown, the ultrasonic sensing circuits 111 in the ultrasonic sensing panel 11 can be divided into N groups of ultrasonic sensing circuits 111 according to columns. Each group of ultrasonic sensing circuits 111 can include M columns of ultrasonic sensing circuits 111. The number of signal reading pins (Read_out) can be N, and the N signal reading pins (Read_out) correspond one-to-one with the N groups of ultrasonic sensing circuits 111. One column of ultrasonic sensing circuits 111 corresponds to one switch module 112, and the M columns of ultrasonic sensing circuits 111 in each group of ultrasonic sensing circuits 111 correspond to M switch modules 112. The M switch modules 112 corresponding to the M columns of ultrasonic sensing circuits 111 in each group of ultrasonic sensing circuits 111 are all coupled to the same signal reading pin (Read_out). For example, in Figure 4 and Figure 5 In this circuit, the signal reading pin Read_out1 corresponds to the first group of ultrasonic sensing circuits 111, and all M switching modules 112 corresponding to the first group of ultrasonic sensing circuits 111 are coupled to the signal reading pin Read_out1; the signal reading pin Read_out2 corresponds to the second group of ultrasonic sensing circuits 111, and all M switching modules 112 corresponding to the second group of ultrasonic sensing circuits 111 are coupled to the signal reading pin Read_out2. For example, M can be 16.

[0101] The number of control signal lines CtrL can be M, and each of the M control signal lines CtrL is coupled one-to-one with one of the M switch modules 112 corresponding to each group of ultrasonic sensing circuits 111. For example, each group of ultrasonic sensing circuits 111 may include M columns of ultrasonic sensing circuits 111, and each group of ultrasonic sensing circuits 111 may correspond to M switch modules 112. The M control signal lines CtrL can be sequentially connected one-to-one with each of the M switch modules 112 corresponding to each group of ultrasonic sensing circuits 111. Figure 4 and Figure 5 In this circuit, 16 control signal lines CtrL are connected one-to-one with the 16 switch modules 112 corresponding to the first group of ultrasonic sensing circuits 111; 16 control signal lines CtrL are connected one-to-one with the 16 switch modules 112 corresponding to the second group of ultrasonic sensing circuits 111; ...; 16 control signal lines CtrL are connected one-to-one with the 16 switch modules 112 corresponding to the Nth group of ultrasonic sensing circuits 111.

[0102] In this embodiment of the present disclosure, the M switching modules 112 corresponding to the M columns of ultrasonic sensing circuits 111 in each group of ultrasonic sensing circuits 111 are all coupled to the same signal reading pin Read_out; the number of control signal lines CtrL is M, and the M control signal lines CtrL are coupled one-to-one with the M switching modules 112 corresponding to each group of ultrasonic sensing circuits 111. In this way, by providing control signals to the M control signal lines CtrL in a time-division manner, the signal reading pin Read_out can receive the sensing signals on the M signal reading lines Read in the same group in a time-division manner. Furthermore, different signal reading pins Read_out can simultaneously read the sensing signals on the signal reading lines Read in different groups, thereby improving the efficiency of sensing signal reading.

[0103] By dividing the ultrasonic sensing panel 11 into N groups, each group of ultrasonic sensing circuits 111 has M switch modules 112 corresponding to M control signal lines CtrL, so that M control signal lines CtrL can meet the needs of each group of ultrasonic sensing circuits 111, reducing the number of control signal lines CtrL and facilitating the wiring of the ultrasonic sensing panel 11.

[0104] Understandably, the specific values ​​of M and N can be set as needed.

[0105] It is understood that in some embodiments, the number of columns of the ultrasonic sensing circuits 111 in the last group of ultrasonic sensing circuits 111 may be less than M. For example, M is 16, N is 5, and the 5th group includes 15 columns of ultrasonic sensing circuits 111. Then, when the signal reading pin Read_out corresponding to the 1st to 4th groups receives the sensing signal from the corresponding 16th column of ultrasonic sensing circuits 111, the signal reading pin Read_out corresponding to the 5th group no longer receives the sensing signal.

[0106] In one embodiment, the switching module 112 may include a switching transistor, which may be a thin-film transistor. The control terminal of the switching transistor may be coupled to a control signal line CtrL, and the first and second terminals of the switching transistor may be coupled to a signal readout line Read and a signal readout pin Read_out, respectively. The control signal line CtrL can control the switching transistor to be turned on or off. When the control signal line CtrL controls the switching transistor to be turned on, the sensing signal on the signal readout line Read can be provided to the signal readout pin Read_out.

[0107] It should be noted that, Figure 4 and Figure 5 The diagram only schematically illustrates the specific structure of the switch module 112. The switch module 112 is not limited to a switching transistor; other modules with switching functions can also be used.

[0108] In one embodiment, such as Figure 4 As shown, the ultrasonic sensing panel 11 may further include a plurality of control signal pins 114 located on one side of the substrate, and control signal lines CtrL may be coupled to the control signal pins 114. For example, multiple control signal lines CtrL are coupled to multiple control signal pins 114 in a one-to-one correspondence. Exemplarily, the ultrasonic sensing panel 11 may further include a second bonding region, in which the multiple control signal pins 114 are located.

[0109] like Figure 4 As shown, control signal pin 114 is used to couple with control signal drive module 13. Exemplarily, control signal pin 114 is connected to control signal drive module 13 via a bonding process. Control signal drive module 13 provides control signals to multiple control signal lines CtrL in a time-division manner through control signal pin 114.

[0110] In this embodiment, the control signal drive module 13 outside the ultrasonic sensing panel 11 provides control signals to multiple control signal lines CtrL in a time-division manner, which can simplify the components on the ultrasonic sensing panel 11 and reduce the layout difficulty.

[0111] For example, such as Figure 4As shown, the control signal driving module 13 may include a MUX driving circuit. The MUX circuit can provide control signals to multiple control signal lines CtrL in a time-division manner, thereby controlling multiple switching modules 112 to turn on in a time-division manner, so that the signal reading pin Read_out can receive the sensing signals on multiple signal reading lines Read in a time-division manner. For example, the multiple control signal lines CtrL may be CtrL1, CtrL2, ..., CtrL16. The MUX driving circuit can provide control signals to 16 control signal lines CtrL sequentially by switching the time-division manner. The 16 control signal lines CtrL sequentially control the corresponding switching modules 112 to turn on, and the signal reading pin Read_out sequentially receives the sensing signals on the signal reading lines Read in a time-division manner.

[0112] It should be noted that the control signal drive module 13 can also use other types of drive circuits, as long as they can provide control signals to multiple control signal lines CtrL in a time-division manner.

[0113] exist Figure 4 In this configuration, the number of signal read lines (Read) is 16*N, meaning the number of signal read channels is 16*N. One control signal line (CtrL) simultaneously controls N switch modules 112, and N signal read pins (Read_out) simultaneously receive the sensing signals from the corresponding column of signal read lines (Read). Correspondingly, the signal processing module 12 may include N receiving channels, each of which is coupled one-to-one with one of the N signal read pins (Read_out). Each receiving channel receives the sensing signal from one signal read pin (Read_out).

[0114] exist Figure 4 In this circuit, the MUX driver circuit can provide control signals to 16 control signal lines CtrL sequentially by switching time-division multiplexing, and the switching ratio of the MUX driver circuit is 16:1.

[0115] As the number of columns of ultrasonic sensing circuits 111 in the ultrasonic sensing panel 11 increases, the number of receiving channels in the signal processing module 12 cannot be increased indefinitely due to limitations in cost and size. In other words, the number of receiving channels in the signal processing module 12 is limited. Therefore, when the number of columns of ultrasonic sensing circuits 111 in the ultrasonic sensing panel 11 increases, given the limited number of receiving channels in the signal processing module 12, in order to ensure that the sensing signals in each column of ultrasonic sensing circuits 111 are read, it is necessary to increase the number of control signal lines (CtrL), thereby increasing the switching frequency of the MUX drive circuit, which leads to increased computational resources. Furthermore, the increased number of control signal lines (CtrL) leads to an increase in the number of control signal pins in the second bonding area, increasing the difficulty of the bonding process.

[0116] In one embodiment, such as Figure 5As shown, the ultrasonic sensing panel 11 may further include a shift register located on one side of the substrate, with multiple control signal lines CtrL coupled to the shift register. The shift register is used to provide control signals to the multiple control signal lines CtrL in a time-division manner. For example, the shift register can provide control signals to the multiple control signal lines CtrL sequentially.

[0117] exist Figure 5 In the illustrated embodiment, N can be less than or equal to 32, meaning the number of signal readout pins (Read_out) can be limited to less than or equal to 32, thus the number of receiving channels in the signal processing module 12 is less than or equal to 32. When the number of columns of ultrasonic sensing circuits 111 in the ultrasonic sensing panel 11 increases, the number of control signal lines (CtrL) can be increased, allowing the shift register to connect to more control signal lines (CtrL).

[0118] By placing a shift register on one side of the base, control signals can be sequentially provided to multiple control signal lines CtrL. The shift register can include multiple cascaded shift units, and the output of each shift unit can be coupled to a control signal line CtrL. The number of shift units in the shift register can be set as needed and is no longer limited to a specific number; for each additional control signal line CtrL, a cascaded shift unit can be added to the shift register. For example... Figure 5 In this configuration, the number of control signal lines CtrL can be M, and the shift register can be configured to include M shift units. The output of each shift unit is coupled to the corresponding control signal line CtrL, so that the shift register can provide control signals to the M control signal lines CtrL in a time-division manner.

[0119] By setting a shift register on the substrate to provide control signals to multiple control signal lines CtrL in a time-division manner, the number of columns of the ultrasonic sensing circuit 111 can be increased as needed, no longer affected by the number of receiving channels in the signal processing module 12, thus expanding the application size and range of the ultrasonic sensing panel 11.

[0120] In one embodiment, such as Figure 5 As shown, the ultrasonic sensing panel 11 may further include timing signal pins, and a shift register is coupled to the timing signal pins. The timing signal pins are used to couple with the timing drive module 14, thereby the shift register is coupled to the timing drive module 14 through the timing signal pins. The shift register is used to provide control signals to multiple control signal lines CtrL in a time-division manner under the timing signal drive of the timing drive module 14.

[0121] For example, the ultrasonic sensing panel 11 may include a second bonding area, where timing signal pins may be located. The timing signal pins may be bonded to the timing drive module 14. The timing drive module 14 may include timing drive circuitry.

[0122] Figure 6 This is a structural block diagram of a shift unit in one embodiment of the present disclosure. Figure 7 This is a schematic diagram of the structure of a shift register according to an embodiment of this disclosure. Figure 6 As shown, a shift unit may include a first clock signal terminal CLK, a second clock signal terminal CLKB, a reset signal terminal Reset, a signal input terminal Input, a first output terminal Output, and a first power supply terminal VSS. A shift register includes multiple cascaded shift units.

[0123] like Figure 7 As shown, the first output terminal of the shift unit is coupled to the control signal line CtrL; the first output terminal of the (i-1)th shift unit is coupled to the signal input terminal of the ith shift unit; the first output terminal of the ith shift unit is coupled to the reset signal terminal of the (i-1)th shift unit; the first output terminal of the ith shift unit is coupled to the signal input terminal of the (i+1)th shift unit; and the first output terminal of the (i+1)th shift unit is coupled to the reset signal terminal of the ith shift unit. The timing driver module 14 can provide timing signals to the shift register. The timing signals may include a first clock signal and a second clock signal. The first clock signal is provided to the first clock signal terminal CLK, and the second clock signal is provided to the second clock signal terminal CLKB.

[0124] Figure 8 This is a schematic diagram of the structure of a shift unit in one embodiment of this disclosure. Figure 8 As shown, the shift unit may include a pull-up submodule 21, a reset submodule 22, a first output submodule 23, a second output submodule 24, and a first storage capacitor C1.

[0125] The pull-up submodule 21 is coupled to the signal input terminal Input and the pull-up node PU respectively, and is used to provide the signal input terminal Input to the pull-up node PU under the control of the signal input terminal Input signal.

[0126] The reset submodule 22 is coupled to the reset signal terminal Reset, the first power supply terminal VSS and the pull-up node PU respectively. It is used to provide the first power supply terminal VSS signal to the pull-up node PU under the control of the reset signal terminal Reset signal, so as to reset the pull-up node PU.

[0127] The first output submodule 23 is coupled to the pull-up node PU, the first clock signal terminal CLK, and the first output terminal Output, respectively, and is used to provide the signal of the first clock signal terminal CLK to the first output terminal Output under the control of the pull-up node PU.

[0128] The second output submodule 24 is coupled to the reset signal terminal Reset, the first power supply terminal VSS, and the first output terminal Output, respectively, and is used to provide the signal of the first power supply terminal VSS to the first output terminal Output under the control of the reset signal terminal Reset.

[0129] The two plates of the first storage capacitor C1 are coupled to the pull-up node PU and the first output terminal Output, respectively, and are used to store the charge of the pull-up node PU.

[0130] Figure 9A This is a schematic diagram of a shifting unit. (Example) Figure 9A As shown, the pull-up submodule 21 may include a first transistor M1, the gate of the first transistor M1 is coupled to the signal input terminal Input, and the first stage and the second stage of the first transistor M1 are coupled to the signal input terminal Input and the pull-up node PU, respectively.

[0131] The first output submodule 23 may include a third transistor M3. The gate of the third transistor M3 is coupled to the pull-up node PU. The first and second terminals of the third transistor M3 are coupled to the first clock signal terminal CLK and the first output terminal Output, respectively. A parasitic capacitance Cgd is formed between the gate and drain of the third transistor M3.

[0132] like Figure 9A As shown, the reset submodule 22 includes a second transistor M2, the gate of which is coupled to the pull-down node PD, and the first and second terminals of which are coupled to the pull-up node PU and the first power supply terminal VSS, respectively. The second output submodule 24 includes a fourth transistor M4, the gate of which is coupled to the pull-down node PD, and the first and second terminals of which are coupled to the first output terminal Output and the first power supply terminal VSS, respectively.

[0133] Figure 9B for Figure 9A The diagram shows a timing diagram of a shift unit. The following is in conjunction with... Figure 9B illustrate Figure 9A The working process of the shift unit shown.

[0134] Before the output signal of the previous shift unit arrives, although the first clock signal terminal CLK provides a high level to the first pole (source) of the third transistor M3, the third transistor M3 is in the off state because the pull-up node PU is low. At this time, the first output terminal Output will not output a high level, and the first output terminal Output will remain at a low level.

[0135] In the first stage (I), the output signal from the previous shift unit arrives, providing an input signal to the input terminal (Input) of the current shift unit. The first transistor M1 turns on, the pull-up node PU's potential rises, and the third transistor M3 is turned on. However, since the first clock signal terminal CLK is low, the first output terminal (Output) will still not output a high level, but rather a low level. Figure 9B Phase I of the process.

[0136] In the second stage (II), the first clock signal terminal CLK outputs a high level. Due to the coupling effect of the gate and source parasitic capacitance Cgd of the third transistor M3, the potential of the pull-up node PU is pulled high again, enhancing the conduction capability of the third transistor M3. The first output terminal Output of the current stage shift unit then outputs a high level, such as... Figure 9B Phase II of the process.

[0137] In the third stage (III), the output signal of the current stage shift unit becomes the input signal of the next stage shift unit. Therefore, while the first output terminal (Output) of the current stage shift unit is high, the next stage shift unit is pre-charging. As the level of the first clock signal terminal (CLK) changes from high to low, the output signal of the next stage shift unit is input to the reset signal terminal (Reset) of the current stage, serving as the reset signal for the current stage shift unit. This causes the gates of the second transistor M2 and the fourth transistor M4 to be high, and both transistors M2 and M4 are simultaneously turned on. Both ends of the first storage capacitor C1 are connected to the first power supply terminal (VSS) for discharge. The first output terminal (Output) is also connected to the first power supply terminal (VSS), causing the first output terminal (Output) of the current stage shift unit to output a low level. Figure 9B Phase III of the process.

[0138] Figure 10A This is a schematic diagram of another type of shifting unit. For example... Figure 10A As shown, the pull-up submodule 21 may include a first transistor M1. The gate and first electrode of the first transistor M1 are both coupled to the signal input terminal Input, and the second electrode of the first transistor M1 is coupled to the pull-up node PU.

[0139] The first output submodule 23 may include a third transistor M3. The gate of the third transistor M3 is coupled to the pull-up node PU. The first and second terminals of the third transistor M3 are coupled to the first clock signal terminal CLK and the first output terminal Output, respectively. A parasitic capacitance Cgd may be formed between the gate and drain of the third transistor M3.

[0140] like Figure 10AAs shown, the reset submodule 22 includes a second transistor M2 and a seventh transistor M7. The first terminal of the second transistor M2 and the first terminal of the seventh transistor M7 are both coupled to the pull-up node PU. The second terminal of the second transistor M2 and the second terminal of the seventh transistor M7 are both coupled to the first power supply terminal VSS. The gate of the second transistor M2 is coupled to the reset signal terminal Reset, and the gate of the seventh transistor M7 is coupled to the pull-down node PD.

[0141] The second output submodule 24 includes a fourth transistor M4 and an eighth transistor M8. The first terminal of the fourth transistor M4 and the first terminal of the eighth transistor M8 are both coupled to the first output terminal Output. The second terminal of the fourth transistor M4 and the second terminal of the eighth transistor M8 are both coupled to the first power supply terminal VSS. The gate of the eighth transistor M8 is coupled to the pull-down node PD. The gate of the fourth transistor M4 is coupled to the reset signal terminal Reset.

[0142] The shift unit also includes a fifth transistor M5 and a sixth transistor M6. The first terminal and gate of the fifth transistor M5 are both coupled to the second clock signal terminal CLKB, and the second terminal of the fifth transistor M5 is coupled to the pull-down node PD. The gate of the sixth transistor M6 is coupled to the pull-up node PU, and the first terminal and the second terminal of the sixth transistor M6 are coupled to the pull-down node PD and the first power supply terminal VSS, respectively.

[0143] Figure 10B for Figure 10A The diagram shows a timing diagram of a shift unit. The following is in conjunction with... Figure 10B illustrate Figure 10A The working process of the shift unit shown.

[0144] Before the output signal of the previous shift unit arrives, although the first clock signal terminal CLK provides a high level to the first pole (source) of the third transistor M3, the third transistor M3 is in the off state because the pull-up node PU is low. At this time, the first output terminal Output will not output a high level, and the first output terminal Output will remain at a low level.

[0145] In the first stage (I), the output signal from the previous shift unit arrives, providing an input signal to the input terminal (Input) of the current shift unit. The first transistor M1 turns on, the pull-up node PU's potential rises, and the third transistor M3 is turned on. However, since the first clock signal terminal CLK is low, the first output terminal (Output) will still not output a high level, but rather a low level. Figure 10BPhase I of the process. In this phase, the second clock signal terminal CLKB is high, and the high level signal of the second clock signal terminal CLKB controls the fifth transistor M5; the pull-up node PU is high, and the high level of the pull-up node PU controls the sixth transistor M6. By setting the on-resistance of the fifth transistor M5 and the sixth transistor M6, the sixth transistor M6 can be turned on, so that the potential of the pull-down node PD is determined by the sixth transistor M6. Therefore, the pull-down node PD is a low-level signal (i.e., the signal of the first power supply terminal VSS). Consequently, the seventh transistor M7 and the eighth transistor M8 are both in the off state.

[0146] In the second stage (II), the first clock signal terminal CLK outputs a high level. Under the coupling effect of the gate and source parasitic capacitance Cgd of the third transistor M3, the potential of the pull-up node PU is pulled high again. The second clock signal terminal CLKB outputs a low level, the fifth transistor M5 is cut off, and the pull-up node PU controls the sixth transistor M6 to conduct, providing the first power supply terminal VSS signal to the pull-down node PD. The pull-down node PD is low, and both the seventh transistor M7 and the eighth transistor M8 are cut off. After the potential of the pull-up node PU is pulled high again, the conduction capability of the third transistor M3 is enhanced, providing the first clock signal terminal CLK with a high level signal to the first output terminal Output. The first output terminal Output of the current stage shift unit outputs a high level, such as... Figure 10B Phase II of the process.

[0147] In the third stage (III), the output signal of the current stage shift unit becomes the input signal of the next stage shift unit. Therefore, while the first output terminal (Output) of the current stage shift unit is high, the next stage shift unit is pre-charging. As the level of the first clock signal terminal (CLK) changes from high to low, the output signal of the next stage shift unit is input to the reset signal terminal (Reset) of the current stage, serving as the reset signal for the current stage shift unit. This causes the gates of the second transistor M2 and the fourth transistor M4 to be high, and both transistors M2 and M4 are simultaneously turned on. Both ends of the first storage capacitor C1 are connected to the first power supply terminal (VSS) for discharge. The first output terminal (Output) is also connected to the first power supply terminal (VSS), causing the first output terminal (Output) of the current stage shift unit to output a low level. Figure 9B Phase III. In this phase, the second clock signal terminal CLKB is high, the fifth transistor M5 is turned on, making the pull-down node PD high, the seventh transistor M7 and the eighth transistor M8 are turned on, making both ends of the first storage capacitor C1 and the first output terminal Output connected to the first power supply terminal VSS, further ensuring that the first output terminal Output outputs a low level and reducing the noise of the first output terminal Output.

[0148] Therefore, the shift unit circuit in this embodiment has better stability and lower noise. When the second clock signal terminal CLKB is high, the first output terminal Output outputs a low level. The duty cycle of the second clock signal terminal CLKB is 50%, so the first output terminal Output is pulled down to a low level for half of the time in a frame.

[0149] Figure 9A and Figure 10A The specific circuit structure of the shift unit is illustrated exemplarily. It should be understood that the shift unit is not limited to... Figure 9A and Figure 10A The circuit structure shown can be replaced with other circuit forms, as long as they can achieve the desired function.

[0150] In this embodiment of the present disclosure, by setting a shift register on the ultrasonic sensing panel 11, it can be applied to ultrasonic sensing panels 11 with larger size and more columns of ultrasonic sensing circuits 111. Even if the number of columns of ultrasonic sensing circuits 111 on the ultrasonic sensing panel 11 increases, the sensing signal of each column can still be read out in time division. Furthermore, it greatly reduces the number of pins in the first bonding area and the number of pins in the second bonding area, which is beneficial to the commercialization and mass production of the ultrasonic sensing system.

[0151] This disclosure also provides a signal reading method for an ultrasonic sensing panel, which can be applied to the ultrasonic sensing panel 11 in this disclosure embodiment.

[0152] The signal reading method of the ultrasonic sensing panel 11 may include: providing a gate signal to a row of ultrasonic sensing circuits 111, and providing control signals to multiple control signal lines CtrL in a time-division manner, so that the signal reading pin Read_out receives the sensing signals on multiple signal reading lines Read in a time-division manner.

[0153] For example, in Figure 4 In the process, when a grid signal is provided to a row of ultrasonic sensing circuits 111, the row of ultrasonic sensing circuits 111 all output sensing signals; control signals are provided to control signal lines CtrL1, CtrL2, ..., CtrL15, and CtrL16 in a time-division manner so that the signal reading pin Read_out1 receives the sensing signals on the signal reading lines Read1, Read2, ..., Read15, and Read16 in a time-division manner.

[0154] In one embodiment, such as Figure 4 and Figure 5As shown, the ultrasonic sensing panel 11 includes N groups of ultrasonic sensing circuits 111, each group of ultrasonic sensing circuits 111 includes M columns of ultrasonic sensing circuits 111, and the number of signal reading pins Read_out is N. Each of the N signal reading pins Read_out corresponds one-to-one with one of the N groups of ultrasonic sensing circuits 111. The M switching modules 112 corresponding to the M columns of ultrasonic sensing circuits 111 in each group of ultrasonic sensing circuits 111 are all coupled to the same signal reading pin Read_out. The number of control signal lines CtrL is M, and each of the M control signal lines CtrL is coupled one-to-one with one of the M switching modules 112 corresponding to each group of ultrasonic sensing circuits 111. The signal reading method may include: when providing a gate signal to one row of ultrasonic sensing circuits 111, providing control signals to the N control signal lines CtrL in a time-division manner, so that each signal reading pin Read_out receives the sensing signals on the N signal reading lines Read in the corresponding group in a time-division manner.

[0155] For example, in Figure 5 In this process, when a grid signal is provided to a row of ultrasonic sensing circuits 111, the row of ultrasonic sensing circuits 111 all output sensing signals; control signals are provided to control signal lines CtrL1, CtrL2, ..., CtrL(M-1), and CtrLM in a time-sharing manner; the signal reading pin Read_outRead_out1 receives the sensing signals on the signal reading lines Read1, Read2, ..., Read(M-1), and ReadM in a time-sharing manner; the signal reading pin Read_out2 receives the sensing signals on the signal reading lines Read(M+1), Read(M+2), ..., Read(2M-1), and Read(2M) in a time-sharing manner; ...; the signal reading pin Read_outN receives the sensing signals on the signal reading lines Read(M*(N-1)+1), Read(M*(N-1)+2), ..., Read(M*N-1), and Read(M*N) in a time-sharing manner.

[0156] It should be noted that the signal reading pin Read_out receives the sensing signals of the ultrasonic sensing circuit 111 line by line through the signal reading line Read.

[0157] This disclosure also provides an ultrasonic sensing system, which can be an ultrasonic sensing imaging device. The ultrasonic sensing system includes the ultrasonic sensing panel 11 described in this disclosure, and also includes a signal processing module 12. The signal processing module 12 includes multiple signal conversion circuits. These signal conversion circuits can be IV conversion circuits (i.e., current-to-voltage conversion circuits). Each of the multiple signal conversion circuits is coupled to a corresponding multiple signal readout pins (Read_out). The signal conversion circuits receive the sensing signals on the Read_out pins and convert the sensing signals into voltage signals for processing by the signal processing module 12.

[0158] Figure 11 This is a schematic diagram of the signal processing module in one embodiment of the present disclosure. Figure 11 Only one signal conversion circuit and its related circuits are shown. For example... Figure 11 As shown, the signal processing module 12 may further include a differential amplifier circuit, a variable gain amplifier circuit (VGA), an 8th-order Bessel filter, and an analog-to-digital converter circuit. The signal conversion circuit may include an IV converter circuit (current-to-voltage converter circuit), which converts the current signal output from the ultrasonic sensing circuit 111 into a voltage signal. The differential amplifier circuit can increase the driving capability and perform impedance matching with the back-end. The variable gain amplifier circuit (VGA) can control the amplification factor through a program. The DAC (AD5724) provides a precise reference voltage for the first and second stage amplifier circuits and the AD8336. Vref1 is connected to a pin in the IV converter circuit, and Vref2 is connected to a pin in the differential amplifier circuit, thereby adjusting the bias voltage of the amplifier circuit output. The 8th-order Bessel filter, with a cutoff frequency of 1MHz, can filter out high-frequency noise. The analog-to-digital converter circuit can convert the analog signal into a digital signal and transmit it to the back-end FPGA for data signal processing.

[0159] Figure 11 In the circuit, Vref1 and Vref2 can adjust the static operating points of the first two amplifier stages respectively; Vgain can adjust the amplification factor of the VGA variable gain amplifier circuit; Vref1, Vref2, and Vgain can be provided by a DAC chip (AD5724) with a voltage range of -5V to +5V; the output voltage of the DAC chip can be controlled by the FPGA program.

[0160] In one embodiment, such as Figure 4 As shown, the ultrasonic sensing system may also include a control signal driving module 13. The control signal driving module 13 is coupled to the control signal line CtrL through the control signal pin on the ultrasonic sensing panel 11. The control signal driving module 13 is used to provide control signals to multiple control signal lines CtrL in a time-division manner.

[0161] For example, the ultrasonic sensing panel 11 includes a first binding region and a second binding region, the signal reading pin Read_out can be located in the first binding region, and the control signal pin is located in the second binding region.

[0162] For example, the control signal driving module 13 may include a MUX driving circuit, which may include multiple output terminals, each corresponding to a multiple control signal line CtrL via control signal pins. The MUX circuit can provide control signals to the multiple output terminals in a time-division manner, thereby providing control signals to the multiple control signal lines CtrL in a time-division manner.

[0163] In one embodiment, such as Figure 5 As shown, the ultrasonic sensing system also includes a timing drive module 14, and the ultrasonic sensing panel 11 also includes a shift register located on one side of the substrate. Multiple control signal lines CtrL are coupled to the shift register. The ultrasonic sensing panel 11 also includes timing signal pins. The timing drive module 14 is coupled to the shift register through the timing signal pins. The timing drive module 14 is used to provide timing signals to the shift register to drive the shift register to provide control signals to the multiple control signal lines CtrL in a time-division manner.

[0164] For example, the ultrasonic sensing panel 11 includes a first binding region and a second binding region, the signal reading pin Read_out can be located in the first binding region, and the timing signal pin is located in the second binding region.

[0165] Figure 12 This is a timing diagram of an ultrasonic sensing system according to an embodiment of this disclosure. (Reference) Figure 5 and Figure 12 The shift register sequentially provides control signals (high-level signals) to the M control signal lines CtrL, and the sensing signals of the M columns of ultrasonic sensing circuits 111 in each group of ultrasonic sensing circuits 111 are read out sequentially.

[0166] For example, the ultrasonic sensing system can be an ultrasonic sensing imaging device, which may further include an imaging circuit that can be connected to the signal processing module 12. The imaging circuit is used to reconstruct an image of the target object based on the signal output by the signal processing module 12, thereby achieving ultrasonic imaging.

[0167] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0168] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0169] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0170] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0171] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0172] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure, and these should all be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An ultrasonic sensing panel, characterized by, include: Base; An ultrasonic sensing circuit is located on one side of the substrate. Multiple ultrasonic sensing circuits are arranged in multiple rows and columns. The ultrasonic sensing circuit is used to emit ultrasonic waves toward the target object and generate a sensing signal based on the received echo signal. Signal reading lines, multiple signal reading lines correspond one-to-one with multiple columns of ultrasonic sensing circuits, and the signal reading lines are coupled to the ultrasonic sensing circuits in the corresponding columns to receive the sensing signals; Signal readout pins are located on one side of the substrate, and the number of signal readout pins is less than the number of signal readout lines; A switch module corresponds one-to-one with the signal reading line. The switch module is coupled to the control signal line, the signal reading line and the signal reading pin respectively. The switch module is used to provide the sensing signal on the signal reading line to the signal reading pin under the control of the control signal line. In this configuration, at least two of the switch modules are coupled to the same signal reading pin, and multiple switch modules coupled to the same signal reading pin are coupled to different control signal lines. The different control signal lines control the corresponding switch modules in a time-division manner, so that the signal reading pin receives the sensing signals from multiple signal reading lines in a time-division manner. The ultrasonic sensing panel also includes a shift register located on one side of the substrate, and multiple control signal lines are coupled to the shift register. The shift register is used to provide control signals to the multiple control signal lines in a time-division manner.

2. The ultrasonic sensing panel of claim 1, wherein, The ultrasonic sensing panel also includes a plurality of control signal pins located on one side of the substrate. The control signal pins are coupled to the control signal lines and are used to be coupled to a control signal driving module. The control signal driving module is used to provide control signals to the plurality of control signal lines in a time-division manner.

3. The ultrasonic sensing panel of claim 1, wherein, The ultrasonic sensing panel also includes timing signal pins, and the shift register is coupled to the timing signal pins. The timing signal pins are used to couple with the timing drive module, and the shift register is used to provide control signals to multiple control signal lines in a time-division manner under the timing signal drive of the timing drive module.

4. The ultrasonic sensing panel of claim 1, wherein, The shift register includes multiple cascaded shift units, each shift unit comprising: The pull-up submodule is coupled to the signal input terminal and the pull-up node respectively, and is used to provide the signal from the signal input terminal to the pull-up node under the control of the signal from the signal input terminal; The reset submodule is coupled to the reset signal terminal, the first power supply terminal and the pull-up node respectively, and is used to provide the first power supply terminal signal to the pull-up node under the control of the reset signal terminal signal; The first output submodule is coupled to the pull-up node, the first clock signal terminal and the signal output terminal respectively, and is used to provide the signal of the first clock signal terminal to the signal output terminal under the control of the pull-up node; The second output submodule is coupled to the reset signal terminal, the first power supply terminal and the signal output terminal respectively, and is used to provide the signal from the first power supply terminal to the signal output terminal under the control of the reset signal terminal. The first storage capacitor has two plates that are respectively coupled to the pull-up node and the signal output terminal; The signal output terminal of the shift unit is coupled to the control signal line; the signal output terminal of the (i-1)th shift unit is coupled to the signal input terminal of the ith shift unit; the signal output terminal of the ith shift unit is coupled to the reset signal terminal of the (i-1)th shift unit; the signal output terminal of the ith shift unit is coupled to the signal input terminal of the (i+1)th shift unit; and the signal output terminal of the (i+1)th shift unit is coupled to the reset signal terminal of the ith shift unit.

5. The ultrasonic sensing panel according to claim 4, characterized in that, The reset submodule includes a second transistor and a seventh transistor. The first terminals of the second transistor and the seventh transistor are both coupled to the pull-up node. The second terminals of the second transistor and the seventh transistor are both coupled to the first power supply terminal. The gate of the second transistor is coupled to the reset signal terminal, and the gate of the seventh transistor is coupled to the pull-down node. The second output submodule includes a fourth transistor and an eighth transistor. The first terminals of the fourth transistor and the eighth transistor are both coupled to the signal output terminal. The second terminals of the fourth transistor and the eighth transistor are both coupled to the first power supply terminal. The gate of the eighth transistor is coupled to the pull-down node. The gate of the fourth transistor is coupled to the reset signal terminal. The shifting unit further includes: The fifth transistor has its first terminal and gate both coupled to the second clock signal terminal, and its second terminal coupled to the pull-down node; The sixth transistor has its gate coupled to the pull-up node, and its first and second terminals are coupled to the pull-down node and the first power supply terminal, respectively.

6. The ultrasonic sensing panel of any one of claims 1-5, wherein, The ultrasonic sensing panel includes N sets of ultrasonic sensing circuits, each set of ultrasonic sensing circuits includes M columns of ultrasonic sensing circuits, the number of signal reading pins is N, the N signal reading pins correspond one-to-one with the N sets of ultrasonic sensing circuits, and the M switching modules corresponding to the M columns of ultrasonic sensing circuits in each set of ultrasonic sensing circuits are all coupled to the same signal reading pin. The number of control signal lines is M, and each of the M control signal lines is coupled to one of the M switching modules corresponding to each group of ultrasonic sensing circuits.

7. The ultrasonic sensing panel according to claim 1, characterized in that, The ultrasonic sensing circuit includes: An ultrasonic sensor is coupled to a second power supply terminal and a first node, respectively. The ultrasonic sensor is used to emit ultrasonic waves toward a target object and receive the echo signal reflected back by the target object. The first submodule is coupled to the first control terminal, the bias voltage terminal, and the first node, respectively. It is used to provide the first signal of the bias voltage terminal to the first node under the control of the first control terminal signal during the transmission phase; and to provide the second signal of the bias voltage terminal to the first node under the control of the first control terminal signal during the sampling phase. The second submodule is coupled to the second control terminal, the first node, and the second node respectively, and is used to provide the first node's signal to the second node under the control of the second control terminal signal. The second storage capacitor is coupled to the second power supply terminal and the second node at its two ends, respectively, and is used to store the signal of the second node. The third submodule is coupled to the second node, the third power supply terminal, the gate signal terminal, and the second output terminal, respectively, and is used to provide the sensing signal to the second output terminal based on the signal of the second node and under the control of the gate signal terminal.

8. The ultrasonic sensing panel according to claim 7, characterized in that, The ultrasonic sensing panel also includes a grid driving circuit, which is coupled to the grid signal terminal in a row of ultrasonic sensing circuits.

9. A method for reading signals from an ultrasonic sensing panel, characterized in that, The method, applied to the ultrasonic sensing panel of any one of claims 1-8, comprises: When a gate signal is provided to a row of ultrasonic sensing circuits, control signals are provided to multiple control signal lines in a time-division manner so that the signal readout pins can receive sensing signals from multiple signal readout lines in a time-division manner.

10. The method according to claim 9, characterized in that, The ultrasonic sensing panel includes N groups of ultrasonic sensing circuits, each group of ultrasonic sensing circuits includes M columns of ultrasonic sensing circuits, the number of signal reading pins is N, and the N signal reading pins correspond one-to-one with the N groups of ultrasonic sensing circuits. The M switching modules corresponding to the M columns of ultrasonic sensing circuits in each group of ultrasonic sensing circuits are all coupled to the same signal reading pin; the number of control signal lines is M, and the M control signal lines are coupled one-to-one with the M switching modules corresponding to each group of ultrasonic sensing circuits. The method includes: When a grid signal is provided to a row of ultrasonic sensing circuits, control signals are provided to N control signal lines in a time-division manner, so that each signal readout pin receives the sensing signals from the N signal readout lines in the corresponding group in a time-division manner.

11. An ultrasonic sensing system, characterized in that, The ultrasonic sensing panel according to any one of claims 1-8 further includes a signal processing module, the signal processing module including a plurality of signal conversion circuits, the plurality of signal conversion circuits being coupled one-to-one with a plurality of the signal reading pins, the signal conversion circuits being used to receive the sensing signals on the signal reading pins and convert the sensing signals into voltage signals for processing by the signal processing module.

12. The ultrasonic sensing system according to claim 11, characterized in that, It also includes a control signal driving module, which is coupled to the control signal lines through the control signal pins on the ultrasonic sensing panel. The control signal driving module is used to provide control signals to multiple control signal lines in a time-division manner.

13. The ultrasonic sensing system according to claim 11, characterized in that, The ultrasonic sensing panel also includes a timing drive module. The ultrasonic sensing panel further includes a shift register located on one side of the substrate. Multiple control signal lines are coupled to the shift register. The ultrasonic sensing panel also includes timing signal pins. The timing drive module is coupled to the shift register through the timing signal pins. The timing drive module is used to provide timing signals to the shift register to drive the shift register to provide control signals to the multiple control signal lines in a time-division manner.

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