LDO circuit

Abstract

The application discloses a kind of LDO circuits, including operational amplifier, voltage division sampling circuit and power tube that are electrically connected with each other, wherein, it further includes an overshoot adjusting circuit, which is connected with operational amplifier, including capacitor, first MOS tube, second MOS tube and first mirror unit, one end of capacitor is connected with power supply, the other end is connected with the grid of first MOS tube, first mirror unit is commonly connected, the source and drain of first MOS tube are connected with operational amplifier, the source of second MOS tube is connected with power supply, an external voltage is input to the grid of second MOS tube, the drain of second MOS tube is connected with first mirror unit, and first mirror unit mirrors the current on the circuit of second MOS tube to the circuit on capacitor.The LDO circuit of the application smoothly solves the problem of overshoot of output voltage during power-on process, prevents the damage of circuit device due to voltage overshoot during operation, and improves the reliability of the entire circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically to an LDO circuit. Background Technology

[0002] Typically, LDO (Low Dropout Linear Regulator) circuits consist of four main components, such as... Figure 1 As shown, the existing LDO circuit includes a reference generation circuit, a voltage divider sampling circuit, an operational amplifier EA (Error Amplifier), and a power transistor Mp. The reference generation circuit generates a reference voltage VREF and bias voltages or currents used by other circuits. The reference voltage VREF is input to the inverting input of the operational amplifier EA. The voltage divider sampling circuit samples the output voltage Vout through resistors R1 and R2 and sends the sampled voltage to the non-inverting input of the operational amplifier EA. The operational amplifier EA compares the sampled voltage with the reference voltage VREF at the inverting input, amplifies the comparison result, and then outputs this amplified signal to the control electrode (gate of the PMOS transistor MP) of the power transistor Mp. Thus, this amplified signal can control the turn-on voltage of the power transistor Mp, thereby forming a negative feedback regulation loop. The output voltage Vout is the input voltage Vin minus the turn-on voltage of the power transistor Mp. Therefore, controlling the turn-on voltage of the power transistor Mp is equivalent to controlling the output voltage of the LDO circuit. Because of the negative feedback adjustment circuit, the voltage at the non-inverting input terminal and the inverting input terminal of the operational amplifier are the same, that is, the voltage FB is the same as the reference voltage VREF. Therefore, the output voltage Vout is determined by the resistance ratio of the two resistors R1 and R2, and its magnitude is: Vout=[(R1+ R2) / R2] *VREF.

[0003] In the aforementioned existing LDO circuit, during the power-on process, the LDO circuit is not started in the initial state, and both the output voltage Vout and the reference voltage VREF are 0. After the LDO circuit starts, the reference voltage VREF begins to rise, and the negative feedback loop of the LDO circuit begins to be established. In order to make the reference VREF consistent with the voltage FB, the operational amplifier EA will cause the gate voltage VGate of the power transistor Mp to drop rapidly, causing the power transistor Mp to turn on. This leads to a large current flowing into the output terminal, causing the output voltage Vout to overshoot. Since the devices connected to the output voltage Vout are generally low-voltage devices, the risk of low-voltage devices being broken down under these circumstances is very high, which can easily damage the low-voltage devices and greatly reduce the reliability of the entire LDO circuit.

[0004] Therefore, it is necessary to provide an improved LDO circuit to overcome the above-mentioned defects. Summary of the Invention

[0005] The application aims to provide an LDO circuit, which solves the problem of overshoot of output voltage during power-on process, prevents the damage of circuit devices due to voltage overshoot during operation, and improves the reliability of the whole circuit.

[0006] To achieve the above-mentioned purpose, the application provides an LDO circuit, which comprises an operational amplifier, a voltage division sampling circuit and a power tube. The power tube generates an output voltage through an output terminal in the on state. The voltage division sampling circuit divides the output voltage and inputs the divided voltage into the operational amplifier. The operational amplifier compares and amplifies the reference voltage input from outside with the divided voltage, and inputs the amplified signal into the power tube to control the on state of the power tube. The LDO circuit further comprises an overshoot adjusting circuit connected with the operational amplifier, which comprises a capacitor, a first MOS tube, a second MOS tube and a first mirror unit. One end of the capacitor is connected with a power supply, and the other end is connected with the gate of the first MOS tube and the first mirror unit. The source and drain of the first MOS tube are connected with the operational amplifier. The source of the second MOS tube is connected with the power supply, and an external voltage is input into the gate of the second MOS tube to generate a bias current on the second MOS tube during the power-on process of the circuit. The drain of the second MOS tube is connected with the first mirror unit, and the first mirror unit mirrors the current on the second MOS tube to the circuit line where the capacitor is located.

[0007] Preferably, the first mirror unit comprises a third MOS tube and a fourth MOS tube. The gate and source of the third MOS tube are commonly connected with the drain of the second MOS tube. The drain of the fourth MOS tube is connected with the gate of the first MOS tube, and the gate of the fourth MOS tube is connected with the gate of the third MOS tube. The sources of the third MOS tube and the fourth MOS tube are grounded.

[0008] Preferably, the operational amplifier comprises a second mirror unit, a fifth MOS tube, a sixth MOS tube and a seventh MOS tube. The gate of the fifth MOS tube is connected with the voltage division sampling circuit, and the source of the fifth MOS tube is commonly connected with the drain of the first MOS tube and the second mirror unit. The gate of the sixth MOS tube is input with an external reference voltage VREF. The source of the sixth MOS tube is connected with the gate of the power tube. The drains of the first MOS tube, the fifth MOS tube, the sixth MOS tube and the seventh MOS tube are commonly connected. Another external voltage is input into the gate of the seventh MOS tube to generate another bias current on the seventh MOS tube. The source of the seventh MOS tube is grounded.

[0009] Preferably, the second mirror unit comprises an eighth MOS transistor and a ninth MOS transistor, the gate of the eighth MOS transistor is connected with the drain of the fifth MOS transistor, the drain of the ninth MOS transistor is connected with the drain of the sixth MOS transistor, the gate of the ninth MOS transistor is connected with the gate of the eighth MOS transistor, and the source of the eighth MOS transistor and the source of the ninth MOS transistor are connected with the power supply.

[0010] Preferably, the width-length ratio and the capacitance value of the third MOS transistor and the fourth MOS transistor are adjusted, and the external reference voltage is less than the gate voltage of the first MOS transistor.

[0011] Preferably, the first MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor and the seventh MOS transistor are N-type MOS transistors.

[0012] Preferably, the second MOS transistor, the eighth MOS transistor and the ninth MOS transistor are P-type MOS transistors.

[0013] Compared with the prior art, the LDO circuit of the present application has an overshoot adjusting circuit, so that the power transistor is always in the off state before the negative feedback loop is established during power-on; during power-on, the gate voltage of the first MOS transistor slowly decreases from the power supply voltage to the reference voltage value due to the effect of the capacitor and the fourth MOS transistor (mirror current), and the feedback loop is always in an open loop state, and the operational amplifier works in a comparator state, so that the gate voltage of the power transistor is stabilized at the power supply voltage; during the whole process, the gate voltage of the power transistor is stabilized at the power supply voltage, so that the power transistor is cut off, resulting in no large current flowing to the output end of the LDO circuit, thus solving the problem of overshoot of the output voltage Vout of the LDO circuit during power-on, preventing the circuit device from being damaged due to voltage overshoot during operation, and improving the reliability of the whole circuit.

[0014] The present application will become more clear from the following description and in conjunction with the drawings, which are used to explain the embodiments of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 It is a structural schematic diagram of the LDO circuit of the prior art.

[0016] Figure 2 It is a structural schematic diagram of the LDO circuit of the present application.

[0017] Figure 3 It is Figure 2 a partial voltage change schematic diagram of the structure shown. DETAILED DESCRIPTION

[0018] Embodiments of the present application will now be described with reference to the accompanying drawings, in which like reference numerals represent like elements. As described above, the present application provides an LDO circuit, and the LDO circuit of the present application smoothly solves the problem of overshoot of output voltage during power-on process of the circuit, prevents damage of circuit devices due to voltage overshoot during operation, and improves reliability of the entire circuit.

[0019] Please refer to Figure 2 , Figure 2The application discloses a structure diagram of an LDO circuit. As shown in the figure, the LDO circuit comprises an operational amplifier, a voltage dividing and sampling circuit and a power tube Mp, the power tube Mp generates an output voltage Vout through an output terminal in a conducting state, the voltage dividing and sampling circuit divides the output voltage Vout and inputs a divided voltage VFB into the operational amplifier; wherein the voltage dividing and sampling circuit is composed of a resistor R1 and a resistor R2, the resistor R1 and the resistor R2 divide the voltage Vout to generate the voltage VFB, so that the size relationship between the voltage VFB and the output voltage Vout can be adjusted by selecting appropriate resistance values of the resistor R1 and the resistor R2 to meet the setting requirements; the operational amplifier compares and amplifies an external input reference voltage VREF and the divided voltage VFB, and inputs the amplified signal into a gate of the power tube Mp, so that the output signal of the operational amplifier controls the conduction of the power tube Mp. In the application, the LDO circuit further comprises an overshoot adjusting circuit connected with the operational amplifier, which is used for adjusting the gate voltage of the power tube Mp to prevent the output voltage Vout from overshooting; specifically, the overshoot adjusting circuit comprises a capacitor C1, a first MOS tube M1, a second MOS tube M2 and a first mirror unit, one end of the capacitor C1 is connected with a power supply Vin, and the other end is connected with the gate of the first MOS tube M1 and the first mirror unit, so as to couple the power supply voltage Vin to the gate of the first MOS tube M1 and the first mirror unit; the source and the drain of the first MOS tube M1 are connected with the operational amplifier, the source of the second MOS tube M2 is connected with the power supply Vin, an external voltage VP is input into the gate of the second MOS tube M2, and the drain of the second MOS tube M2 is connected with the first mirror unit; in the power-on process, the second MOS tube M2 generates a bias current IB1 through the external voltage VP and inputs the current IB1 into the first mirror unit; the first mirror unit mirrors the current (IB1) on the second MOS tube M2 line to the capacitor C1 line. Specifically, the first mirror unit comprises a third MOS tube M3 and a fourth MOS tube M4, the gate and the drain of the third MOS tube M3 are connected together and connected with the drain of the second MOS tube M2, the drain of the fourth MOS tube M4 is connected with the gate of the first MOS tube M1, the gate of the fourth MOS tube M4 is connected with the gate of the third MOS tube M3, and the sources of the third MOS tube M3 and the fourth MOS tube M4 are grounded; so that the third MOS tube M3 and the fourth MOS tube M4 mirror the current IB1 to the capacitor C1 and the line where the fourth MOS tube M4 is located.

[0020] Further, as a preferred embodiment of the present application, the operational amplifier comprises a second mirror unit, a fifth MOS transistor M5, a sixth MOS transistor M6 and a seventh MOS transistor M7, the base of the fifth MOS transistor M5 is connected with the voltage division sampling circuit, the drain of the fifth MOS transistor M5 is commonly connected with the drain of the first MOS transistor M1 and the second mirror unit, the gate of the sixth MOS transistor M6 is inputted with an external reference voltage VREF, the drain of the sixth MOS transistor M6 is connected with the gate of the power transistor Mp, the source of the first MOS transistor M1, the fifth MOS transistor M5 and the sixth MOS transistor M6 is commonly connected with the drain of the seventh MOS transistor M7, the gate of the seventh MOS transistor M7 is inputted with another external voltage VN, and the source of the seventh MOS transistor M7 is grounded, so as to generate a bias current IB2 on the seventh MOS transistor M7; wherein the second mirror unit comprises an eighth MOS transistor M8 and a ninth MOS transistor M9, the gate of the eighth MOS transistor M8 is commonly connected with the drain and is connected with the drain of the fifth MOS transistor M5, the drain of the ninth MOS transistor M9 is connected with the drain of the sixth MOS transistor M6, and the gate of the ninth MOS transistor M9 is connected with the gate of the eighth MOS transistor M8, the source of the eighth MOS transistor M8 and the ninth MOS transistor M9 is connected with the power supply Vin; and the second mirror unit has the same function as the first mirror unit, which will not be described here.

[0021] As a preferred embodiment of the present application, in order to better cooperate with the overshoot adjusting circuit to control the gate voltage of the power transistor Mp, the first MOS transistor M1, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6 and the seventh MOS transistor M7 are all N-type MOS transistors; and the second MOS transistor M2, the eighth MOS transistor M8 and the ninth MOS transistor M9 are all P-type MOS transistors.

[0022] Further, in combination with the reference Figure 3 , the working principle of the LDO circuit of the present application is described. During the power-on process of the power supply, that is Figure 3As shown in the T1 stage of the circuit operation, because of the function of the capacitor C1, the power supply voltage Vin is coupled to the node NA, so that the voltage VNA of the node NA (also the gate voltage of the first MOS tube M1) rises in the T1 (power-on stage) stage following the power supply voltage Vin. Similarly, because of the parasitic capacitance of the power tube Mp, the gate voltage VGate of the power tube Mp rises following the input power supply voltage Vin. At the same time, in the T1 stage, the external reference voltage VREF starts to slowly build up and rise. Before the reference voltage VREF rises to the point where the sixth MOS tube M6 is turned on, the negative feedback loop has not yet been established. Therefore, at this time, the output voltage Vout is basically 0 because of the existence of the voltage dividing sampling circuit. With the rise of the reference voltage VREF, if there is no overshoot adjustment circuit of the present application, the negative feedback loop starts to establish. In order to make the reference voltage VREF consistent with the feedback point FB voltage VFB, the operational amplifier will make the power tube Mp gate voltage VGate drop rapidly, causing the power tube Mp to open rapidly, and then causing a large current to flow into the output terminal, so that the output voltage Vout overshoots. However, in the present application, by adding the overshoot adjustment circuit, in the T2 (processing overshoot stage) stage of the circuit operation as shown in 3, during the rise of the reference voltage VREF, the bias current IB1 (the first bias current generated by the second MOS tube M2) and the bias current IB2 (the second bias current generated by the seventh MOS tube M7) generated by the voltage VREF also start to establish. Due to the action of the first mirror unit, the current IM4 flowing through the fourth MOS tube M4 of the N-type MOS tube at this time is IM4 = 1 / N*IB1 (where N is the width-length ratio coefficient of the third MOS tube M3 and the fourth MOS tube M4). However, because of the capacitor C1, the voltage VNA of the node NA cannot immediately drop to 0. The drop speed of the voltage VNA is determined by the current IM4 of the fourth MOS tube M4 and the capacitance value of the capacitor C1, and the drop slope is equal to IM4 / C1.In the process of the voltage VNA of the node NA falling, because the voltage VNA is basically slowly falling from the power supply voltage Vin, the falling voltage can also completely enable the first MOS Ml of the N-type MOS to be turned on, and the bias current IB2 is also established at this time; and the voltage VNA of the node NA needs to be always higher than the reference voltage VREF in the T2 stage, because only when the voltage VNA of the node NA is higher than the reference voltage VREF can the negative feedback loop be in an open loop state, so as to enable the operational amplifier to be in a comparator state; specifically, in the whole T2 stage, the voltage VNA can be set to be greater than the reference voltage VREF by setting the falling speed IM4 / C1 of the voltage VNA of the node NA (that is, adjusting the values of the bias current IM4 and the capacitor C1, because the greater the slope IM4 / C1, the smaller the voltage VNA of the node NA, and vice versa), so that the current on the line flows from the eighth MOS M8 adopting a diode connection, through the first MOS Ml, and then through the bias MOS (the seventh MOS M7) to the ground, so as to ensure that the negative feedback loop is in an open loop state, and the fifth MOS M5 and the sixth MOS M6 are also both cut off; at this time, the combination of the overshoot adjusting circuit and the operational amplifier can only be regarded as a comparator composed of the eighth MOS M8, the ninth MOS M9, the first MOS Ml and the sixth MOS M6, so that the gate voltage VGate of the power tube Mp is maintained at the power supply voltage Vin, which leads to the power tube Mp being always in an off state in the T2 stage, and the output voltage Vout is still 0 in the T2 stage because the voltage sampling circuit still maintains 0. With the voltage VNA of the node NA continuously falling, when it falls below the reference voltage VREF, the current no longer flows through the first MOS Ml, that is, the first MOS Ml is cut off, and the fifth MOS M5 and the sixth MOS M6 are both turned on and work in the saturation region, the negative feedback loop starts to work, the currents flowing through the fifth MOS M5 and the sixth MOS M6 are equal, and the gate voltage VGate of the power tube Mp starts to fall and stabilizes at a certain value (the value is determined according to the output current, the greater the output current, the smaller the value, and the smaller the output current, the greater the value). At this time, the power-on process of the whole LDO circuit is completed, and in the power-on process, the output voltage Vout realizes power-on without overshoot, which ensures the reliability of the circuit.

[0023] In summary, the LDO circuit of the present application, due to the additional overshoot adjustment circuit, the power tube Mp is always in the off state before the negative feedback loop is established during power-on. During power-on, because of the capacitor C1, the fourth MOS tube (mirror current) makes the first MOS tube M1 gate voltage slowly drop from the power supply voltage, until the negative feedback loop is always in an open loop state before the value of the reference voltage VREF is dropped, and the operational amplifier works in the comparator state, so that the gate voltage VGate of the power tube Mp is stabilized at the power supply voltage. In this process, the gate voltage of the power tube Mp is stabilized at the power supply voltage, so that the power tube Mp is cut off, resulting in no large current flowing to the output end of the LDO circuit, thus solving the problem of overshoot of the output voltage Vout of the LDO circuit during power-on, preventing the damage of the circuit device due to voltage overshoot during operation, and improving the reliability of the entire circuit.

[0024] The present application has been described in conjunction with the preferred embodiments thereof, but it will be understood that the present application is not limited to the embodiments disclosed, but is intended to cover any modifications, equivalent combinations, and equivalents thereof according to the spirit of the present application.

Claims

1. An LDO circuit, comprising an operational amplifier, a voltage divider sampling circuit, and a power transistor, wherein the power transistor generates an output voltage through its output terminal when it is turned on; the voltage divider sampling circuit divides the output voltage and inputs the divided voltage to the operational amplifier; the operational amplifier compares and amplifies an externally input reference voltage with the divided voltage, and inputs the amplified signal to the power transistor to control its conduction; characterized in that, It also includes an overshoot adjustment circuit connected to the operational amplifier. The overshoot adjustment circuit includes a capacitor, a first MOSFET, a second MOSFET, and a first mirror unit. One end of the capacitor is connected to a power supply, and the other end is connected to the gate of the first MOSFET and the first mirror unit. The source and drain of the first MOSFET are both connected to the operational amplifier. The source of the second MOSFET is connected to the power supply. An external voltage is input to the gate of the second MOSFET to generate a bias current on the second MOSFET during power-up. The drain of the second MOSFET is connected to the first mirror unit, which mirrors the current on the second MOSFET line to the line containing the capacitor. The operational amplifier includes a second mirror unit. The system includes a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor. The gate of the fifth MOS transistor is connected to a voltage divider sampling circuit, and its drain is connected to the drain of the first MOS transistor and the second mirror unit. An external reference voltage is input to the gate of the sixth MOS transistor. The drain of the sixth MOS transistor is connected to the second mirror unit and the gate of the power transistor. The second mirror unit mirrors the current on the line of the fifth MOS transistor to the line of the sixth MOS transistor. The sources of the first, fifth, and sixth MOS transistors are connected to the drain of the seventh MOS transistor. Another external voltage is input to the gate of the seventh MOS transistor to generate another bias current in the seventh MOS transistor. The source of the seventh MOS transistor is grounded.

2. The LDO circuit as described in claim 1, characterized in that, The first mirror unit includes a third MOS transistor and a fourth MOS transistor. The gate and source gate of the third MOS transistor are connected together and connected to the drain of the second MOS transistor. The drain of the fourth MOS transistor is connected to the gate of the first MOS transistor, and its gate is connected to the gate of the third MOS transistor. The sources of both the third MOS transistor and the fourth MOS transistor are grounded.

3. The LDO circuit as described in claim 2, characterized in that, The second mirror unit includes an eighth MOS transistor and a ninth MOS transistor. The gate and drain of the eighth MOS transistor are connected together and connected to the drain of the fifth MOS transistor. The drain of the ninth MOS transistor is connected to the drain of the sixth MOS transistor, and its gate is connected to the gate of the eighth MOS transistor. The sources of both the eighth and ninth MOS transistors are connected to the power supply.

4. The LDO circuit as described in claim 3, characterized in that, Adjust the width-to-length ratio of the third MOS transistor and the fourth MOS transistor, as well as the capacitance value of the capacitor, to control the external reference voltage to be less than the gate voltage of the first MOS transistor.

5. The LDO circuit as described in claim 4, characterized in that, The first, third, fourth, fifth, sixth, and seventh MOSFETs are all N-type MOSFETs.

6. The LDO circuit as described in claim 5, characterized in that, The second, eighth, and ninth MOSFETs are all P-type MOSFETs.

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