Wide voltage pci resistive load card

Abstract

The application provides a wide voltage PCI resistance load card, which comprises a PCI interface control chip, a D / A chip module and an FPGA chip; the PCI interface control chip is used for receiving read / write signals sent by a PCI bus interface and forwarding the read / write signals to a local bus according to a preset mode; the D / A chip module comprises a plurality of groups of D / A chip sets arranged in an array, and each group of D / A chip sets constitutes a resistance channel; the FPGA chip is used for receiving read / write signals from the local bus, determining chip control signals and chip read / write data corresponding to a target D / A chip set in the plurality of groups of D / A chip sets based on the read / write signals, and transmitting the chip read / write data to the target D / A chip set based on the chip control signals, so that the target D / A chip set changes with the air speed and outputs corresponding resistance values. The application can solve the technical problem that the working voltage of the PCI resistance load card in the prior art cannot meet the joint test requirement of a certain type of aircraft lever force automatic adjustment system.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and more specifically to a wide-voltage PCI resistive load card. Background Technology

[0002] With the development of automatic measurement and control technology, the demand for automated testing in the aviation maintenance industry is increasing. The design and application of various test computer boards have become common, but there are still some aircraft airborne equipment with special technical requirements that are different from general measurement and control instruments and equipment.

[0003] For example, the integration testing of an aircraft stick force automatic adjustment system requires the use of a multi-resistance box to build a bridge circuit. The performance of this type of automatic stick force adjustment system is then tested by manually adjusting the resistance values ​​of the bridge arms. The operating voltage range of this bridge is 0V to 28.5VDC. However, the resistive analog channels of commercially available industrial measurement and automation control PCI (Peripheral Component Interconnect, a standard defining local buses) resistive load cards typically have voltages of ±1.25V, ±2.5V, ±5V, and ±10V. This incompatibility between the two limits the application of automated testing methods in the integration testing of this system. In other words, existing technology suffers from a problem where the operating voltage of industrial measurement and automation control PCI resistive load cards cannot meet the integration testing requirements of aircraft stick force automatic adjustment systems. Summary of the Invention

[0004] In view of this, it is necessary to provide a wide-voltage PCI resistive load card to solve the technical problem that the operating voltage of the existing PCI resistive load card cannot meet the commissioning and testing requirements of the automatic stick force adjustment system of a certain type of aircraft.

[0005] To achieve the above objectives, the present invention provides a wide-voltage PCI resistive load card, comprising:

[0006] The PCI interface control chip is used to receive read and write signals sent by the PCI bus interface and forward the read and write signals to the local bus according to a preset mode.

[0007] The D / A chip module includes multiple D / A chip groups distributed in an array, with each D / A chip group forming a resistance channel.

[0008] An FPGA chip is used to receive read / write signals from the local bus, determine the chip control signal and chip read / write data corresponding to the target D / A chip group among the multiple D / A chip groups based on the read / write signals, and transmit the chip read / write data to the target D / A chip group based on the chip control signals, so that the target D / A chip group simulates the fine channel potentiometer and coarse channel potentiometer of the speed pressure sensor as the air speed changes, and outputs the corresponding resistance value.

[0009] Furthermore, the FPGA chip includes:

[0010] Multiple SPI master controllers;

[0011] A data register is used to store the read and write data of the chip;

[0012] The address determination logic module is used to determine, based on the read / write signal, the target SPI master controller corresponding to the target D / A chip group among the multiple SPI master controllers, and control the target SPI master controller to transmit the chip read / write data to the target D / A chip group.

[0013] Furthermore, the target SPI master controller is used to transmit the chip read / write data bit by bit to the target D / A chipset according to the clock cycle of the target SPI master controller.

[0014] Furthermore, the multiple D / A chip sets consist of 4 D / A chip sets, each of which is composed of at least 8 D / A chips arranged in an array and connected in parallel.

[0015] Furthermore, the operating voltage of the D / A chip is -0.3V to +35VDC.

[0016] Furthermore, the maximum total resistance of each D / A chipset is 2.5kΩ.

[0017] Furthermore, the maximum continuous operating current of each D / A chipset is 24mA.

[0018] Furthermore, the resistive load card also includes a power supply chip, and the FPGA chip is connected to the local bus through the power supply chip.

[0019] Furthermore, the resistive load card also includes a level conversion circuit, wherein the PCI interface control chip is connected to the FPGA chip through the level conversion circuit, and the level conversion circuit is used to convert the level of the read / write signal output by the PCI interface control chip and send it to the FPGA chip.

[0020] Furthermore, the resistive load card also includes an EEPROM configuration chip, which is connected to the PCI interface control chip and is used to erase and reprogram the PCI interface control chip.

[0021] The beneficial effects of the above implementation method are as follows: The wide-voltage PCI resistive load card provided by the present invention receives read / write signals from the local bus through an FPGA chip. Based on the read / write signals, it determines the chip control signal and chip read / write data corresponding to the target D / A chip group among multiple D / A chip groups. Based on the chip control signal, it transmits the chip read / write data to the target D / A chip group, so that the target D / A chip group simulates the fine channel potentiometer and coarse channel potentiometer of the speed pressure sensor as the airspeed changes and outputs the corresponding resistance value. The whole process is completed automatically. In the joint debugging and testing of the aircraft stick force automatic adjustment system, the joint debugging and testing of the aircraft stick force automatic adjustment system can be achieved by outputting the corresponding resistance value through the target D / A chip group. Moreover, the D / A chip group can withstand a wide voltage range based on its own characteristics. The power supply of the D / A chip group can be directly taken from an external wide-voltage power supply, thus realizing the compatibility of the PCI resistive load card with the external wide-voltage working environment. This solves the technical problem that the working voltage of the PCI resistive load card in the prior art cannot meet the joint debugging and testing requirements of the aircraft stick force automatic adjustment system. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A schematic diagram of the wide voltage PCI resistive load card provided by the present invention;

[0024] Figure 2 This is a hardware layout diagram of the wide-voltage PCI resistive load card provided by the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0026] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0027] In this embodiment of the invention, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, apparatus, product or device that includes a series of steps or modules is not necessarily limited to those steps or modules that are explicitly listed, but may include other steps or modules that are not explicitly listed or that are inherent to such process, method, product or device.

[0028] The naming or numbering of steps in the embodiments of the present invention does not mean that the steps in the method flow must be executed in the time / logical order indicated by the naming or numbering. The execution order of the named or numbered process steps can be changed according to the technical purpose to be achieved, as long as the same or similar technical effect can be achieved.

[0029] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0030] like Figure 1 As shown, the present invention provides a wide-voltage PCI resistive load card, which includes:

[0031] PCI (Peripheral Component Interconnect, a standard for defining local buses) interface control chip 111 is used to receive read and write signals sent by PCI bus interface 114 and forward the read and write signals to the local bus according to a preset mode.

[0032] D / A chip module 113 includes multiple D / A chip groups distributed in an array, each D / A chip group forming a resistance channel;

[0033] The FPGA (Field Programmable Gate Array) chip 112 is used to receive read / write signals from the local bus, determine the chip control signal and chip read / write data corresponding to the target D / A chip group among the multiple D / A chip groups based on the read / write signals, and transmit the chip read / write data to the target D / A chip group based on the chip control signals, so that the target D / A chip group simulates the fine channel potentiometer and coarse channel potentiometer of the speed pressure sensor as the air speed changes, and outputs the corresponding resistance value.

[0034] Furthermore, the multiple D / A chipsets consist of four D / A chipsets, each composed of at least eight D / A chips arranged in an array in parallel. The D / A chips are digital-to-analog converter chips. The hardware layout diagram of the wide-voltage PCI resistive load card is shown below. Figure 2 As shown.

[0035] It is understood that the wide-voltage PCI resistive load card provided by the present invention mainly consists of a MAXII series FPGA chip 112, a 9052 model PCI interface control chip 111 (PCI9052 interface control chip), 32 D / A chips AD5293 with SPI interface (Serial Peripheral Interface), and other peripheral circuit chips such as EEPROM chip. Every 8 D / A chips are connected in parallel to form a resistive load channel, and there are a total of four resistive load channels.

[0036] The PCI interface control chip 111PCI9052 can forward the instructions and data sent from the PCI bus interface 114 to the local data bus and local address bus according to the configured mode, so as to realize the data communication and control between the PCI interface on the board and the FPGA chip 112.

[0037] In some embodiments, the FPGA chip 112 includes:

[0038] Multiple SPI master controllers;

[0039] A data register is used to store the read and write data of the chip;

[0040] The address determination logic module is used to determine, based on the read / write signal, the target SPI master controller corresponding to the target D / A chip group among the multiple SPI master controllers, and control the target SPI master controller to transmit the chip read / write data to the target D / A chip group.

[0041] Furthermore, the target SPI master controller is used to transmit the chip read / write data bit by bit to the target D / A chipset according to the clock cycle of the target SPI master controller.

[0042] Understandably, the resistive load card is mainly composed of the MAXII series FPGA chip 112, the PCI9052 interface control chip, the D / A chip with the SPI interface, and other peripheral circuit chips such as the EEPROM chip.

[0043] FPGA chip 112 is the communication bridge between PCI interface control chip 111 and D / A chip. The logic functions in FPGA chip 112 are designed using hardware description language. The functions implemented include: (1) reading data and address on the PCI9052 local bus; (2) performing local bus data parallel / serial conversion under the control of PCI9052 read / write signals; (3) determining which D / A chip group the data is used to control; (4) generating SPI master controller circuit according to logic design and outputting a series of control signals and read / write signals that meet SPI timing requirements; (5) transmitting the data received by FPGA to the D / A chip group in the agreed SPI serial communication mode.

[0044] The PCI interface control chip 111 can forward the instructions and data sent from the PCI bus interface 114 to the local data bus and local address bus according to the configured mode, so as to realize the data communication and control between the PCI interface on the board and the FPGA chip 112.

[0045] Each of the four D / A chipsets consists of eight D / A chips connected in parallel. Under the control of the test program, the SPI master controller designed inside the FPGA can convert the local bus data from parallel to serial and send the data bit by bit to the D / A chipset according to the SPI SCLK clock, so that the D / A chipset outputs different resistance values.

[0046] In some embodiments, the operating voltage of the D / A chip is -0.3V to +35VDC, the maximum total resistance of each D / A chip group is 2.5kΩ, and the maximum continuous operating current of each D / A chip group is 24mA.

[0047] Understandably, the board uses 32 AD5293 (20kΩ) chips with a working voltage range of -0.3V to +35VDC to form four resistance channels. Each channel consists of 8 chips connected in parallel. The maximum total resistance of a single channel is 2.5kΩ, and the maximum continuous working current is 24mA, which meets the external working conditions of the automatic stick force adjustment system of a certain type of aircraft.

[0048] In some embodiments, the resistive load card further includes a power supply chip 115, and the FPGA chip 112 is connected to the local bus through the power supply chip 115.

[0049] It is understandable that power chip 115 can supply power to FPGA chip 112.

[0050] In some embodiments, the resistive load card further includes a level conversion circuit 116, wherein the PCI interface control chip 111 is connected to the FPGA chip 112 through the level conversion circuit 116, and the level conversion circuit 116 is used to convert the read / write signals output by the PCI interface control chip 111 and send them to the FPGA chip 112.

[0051] Understandably, the read / write signals output by the PCI interface control chip 111 are in electrical signal form, and the level of the read / write signals needs to be converted to meet the requirements of the FPGA chip 112.

[0052] In some embodiments, the resistive load card further includes an EEPROM (Electrically Erasable Programmable Read Only Memory) configuration chip 117, which is connected to the PCI interface control chip 111 and is used to erase and reprogram the PCI interface control chip 111.

[0053] It is understood that by using the EEPROM configuration chip 117 to erase and reprogram the PCI interface control chip 111, the PCI interface control chip 111 can be controlled to forward data according to a preset mode.

[0054] The wide-voltage PCI resistive load card provided by this invention includes: a PCI interface control chip 111, used to receive read / write signals sent by a PCI bus interface 114, and forward the read / write signals to a local bus according to a preset mode; a D / A chip module 113, including multiple D / A chip groups distributed in an array; and an FPGA chip 112, used to receive read / write signals from the local bus, determine the chip control signal and chip read / write data corresponding to a target D / A chip group among the multiple D / A chip groups based on the read / write signals, and transmit the chip read / write data to the target D / A chip group based on the chip control signal, so that the target D / A chip group simulates the fine channel potentiometer and coarse channel potentiometer of a speed pressure sensor as the air speed changes, and outputs the corresponding resistance value.

[0055] To meet the wide voltage range operating characteristics of PCI resistive load cards, a D / A chip capable of withstanding a wide voltage range should be selected to build the resistive load channel. The power supply of the D / A chip can be directly taken from an external wide voltage power supply, thus achieving compatibility between the PCI resistive load card and the external wide voltage operating environment.

[0056] The wide-voltage PCI resistive load card provided by this invention receives read / write signals from the local bus via an FPGA chip 112. Based on these signals, it determines the chip control signal and chip read / write data corresponding to the target D / A chip group among multiple D / A chip groups. Based on the chip control signal, it transmits the chip read / write data to the target D / A chip group, enabling the target D / A chip group to simulate the fine-channel and coarse-channel potentiometers of the velocity pressure sensor as airspeed changes, and outputs the corresponding resistance value. The entire process is automated. During the joint debugging and testing of the aircraft stick force automatic adjustment system, the corresponding resistance value output by the target D / A chip group can be used to achieve the joint debugging and testing of the aircraft stick force automatic adjustment system. Furthermore, the D / A chip group, based on its own characteristics, can withstand a wide voltage range, and its power supply can be directly taken from an external wide-voltage power supply. This achieves compatibility between the PCI resistive load card and the external wide-voltage operating environment, solving the technical problem that the operating voltage of the PCI resistive load card in the prior art cannot meet the joint debugging and testing requirements of the aircraft stick force automatic adjustment system.

[0057] The wide-voltage PCI resistive load card provided by this invention differs from existing PCI resistive load cards. This invention utilizes all general-purpose chips, such as the PCI interface control chip 111, FPGA chip 112, and D / A chip, eliminating the need for specialized chips. This design approach simplifies the process, and the FPGA functionality can be customized through online programming. The wide voltage range of the board is determined solely by the operating voltage that the selected chip can withstand. For resistive load card requirements with different voltage ranges, this design can be implemented by replacing the D / A chip, demonstrating its universal applicability.

[0058] The wide-voltage PCI resistive load card provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A wide-voltage PCI resistive load card, characterized in that, include: The PCI interface control chip is used to receive read and write signals sent by the PCI bus interface and forward the read and write signals to the local bus according to a preset mode. The D / A chip module includes multiple D / A chip groups distributed in an array, with each D / A chip group forming a resistance channel. An FPGA chip is used to receive read / write signals from the local bus, determine the chip control signal and chip read / write data corresponding to the target D / A chip group among the multiple D / A chip groups based on the read / write signals, and transmit the chip read / write data to the target D / A chip group based on the chip control signals, so that the target D / A chip group simulates the fine channel potentiometer and coarse channel potentiometer of the speed pressure sensor as the air speed changes, and outputs the corresponding resistance value; The FPGA chip includes: Multiple SPI master controllers; A data register is used to store the read and write data of the chip; The address determination logic module is used to determine, based on the read / write signal, the target SPI master controller corresponding to the target D / A chip group among the multiple SPI master controllers, and control the target SPI master controller to transmit the chip read / write data to the target D / A chip group.

2. The wide-voltage PCI resistive load card according to claim 1, characterized in that, The target SPI master controller is used to transmit the chip read / write data bit by bit to the target D / A chipset according to the clock cycle of the target SPI master controller.

3. The wide-voltage PCI resistive load card according to claim 1, characterized in that, The multiple D / A chip sets consist of 4 D / A chip sets, each of which is composed of at least 8 D / A chips arranged in an array and connected in parallel.

4. The wide-voltage PCI resistive load card according to claim 3, characterized in that, The D / A chip operates at a voltage of -0.3V to +35VDC.

5. The wide-voltage PCI resistive load card according to claim 3, characterized in that, The maximum total resistance of each D / A chipset is 2.5kΩ.

6. The wide-voltage PCI resistive load card according to claim 3, characterized in that, The maximum continuous operating current of each D / A chipset is 24mA.

7. The wide-voltage PCI resistive load card according to claim 1, characterized in that, The resistive load card further includes a power supply chip, and the FPGA chip is connected to the local bus through the power supply chip.

8. The wide-voltage PCI resistive load card according to claim 1, characterized in that, The resistive load card further includes a level conversion circuit. The PCI interface control chip is connected to the FPGA chip through the level conversion circuit. The level conversion circuit is used to convert the read / write signals output by the PCI interface control chip and then send them to the FPGA chip.

9. The wide-voltage PCI resistive load card according to any one of claims 1-8, characterized in that, The resistive load card further includes an EEPROM configuration chip, which is connected to the PCI interface control chip and is used to erase and reprogram the PCI interface control chip.

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