Low-dropout voltage regulator and control method thereof

Abstract

The present disclosure relates to a low-dropout voltage regulator and a control method thereof. The low-dropout voltage regulator includes a reference circuit, an amplification circuit, a power switch circuit, a feedback circuit, and a control circuit. The reference circuit is configured to generate a reference voltage. The amplification circuit is configured to generate an amplified voltage based on the reference voltage and a feedback voltage. The power switch circuit is configured to receive the amplified voltage and generate an output voltage at an output terminal based on an input voltage. The feedback circuit is configured to generate the feedback voltage based on the output voltage. The control circuit is configured to control the power switch circuit based on the input voltage and a signal from the reference circuit.

Description

Technical Field

[0001] This disclosure relates to a low-dropout voltage regulator circuit and its control method. Specifically, it relates to a low-dropout voltage regulator circuit and its control method that can prevent large inrush currents from flowing through the power switching circuit during the initial power-on process. Background Technology

[0002] With the development of technology, various integrated circuits have been developed. However, there is still room for improvement in the performance of many integrated circuits.

[0003] For example, in some existing technologies, during the initial power-up process of a low-dropout regulator (the initial input voltage ramp-up process), a large inrush current flows through the power switching circuit in the low-dropout regulator. This large inrush current may burn out components or metal wires. Summary of the Invention

[0004] Some embodiments of this disclosure relate to a low-dropout voltage regulator circuit. The low-dropout voltage regulator circuit includes a reference circuit, an amplifier circuit, a power switch circuit, a feedback circuit, and a control circuit. The reference circuit generates a reference voltage. The amplifier circuit generates an amplified voltage based on the reference voltage and a feedback voltage. The power switch circuit receives the amplified voltage and generates an output voltage at an output terminal based on an input voltage. The feedback circuit generates a feedback voltage based on the output voltage. The control circuit controls the power switch circuit based on the input voltage and a signal from the reference circuit.

[0005] Some embodiments of this disclosure relate to a control method for a low-dropout voltage regulator circuit. The control method includes the following operations: generating a reference voltage via a reference circuit; generating an amplified voltage via an amplifier circuit based on the reference voltage and a feedback voltage; receiving the amplified voltage via a power switching circuit and generating an output voltage at an output terminal based on an input voltage; generating a feedback voltage via a feedback circuit based on the output voltage; and controlling the power switching circuit via a control circuit based on the input voltage and a signal from the reference circuit.

[0006] In summary, in the low-dropout voltage regulator circuit disclosed herein, the control circuit can control the power switching circuit based on the input voltage and the signal from the reference circuit, so that the current flowing through the power switching circuit during the initial power-on process of the low-dropout voltage regulator circuit is relatively small, thereby avoiding large inrush current. Attached Figure Description

[0007] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described below:

[0008] Figure 1This is a schematic diagram of a low-dropout voltage regulator circuit illustrated according to some embodiments of the present disclosure;

[0009] Figure 2 This is a circuit diagram of a low-dropout voltage regulator circuit illustrated according to some embodiments of the present disclosure;

[0010] Figure 3 This is a circuit diagram of a low-dropout voltage regulator circuit illustrated according to some embodiments of the present disclosure;

[0011] Figure 4 This is a circuit diagram of a low-dropout regulator circuit illustrated according to some embodiments of the present disclosure; and

[0012] Figure 5 This is a flowchart illustrating a control method according to some embodiments of the present disclosure. Detailed Implementation

[0013] The term "coupled" as used in this article can also refer to "electrical coupling," and the term "connected" can also refer to "electrical connection." "Coupled" and "connected" can also refer to the cooperation or interaction of two or more components.

[0014] refer to Figure 1 . Figure 1 This is a schematic diagram of a low-dropout voltage regulator circuit 100 illustrated in accordance with some embodiments of the present disclosure.

[0015] As illustrated in the figure, the low-dropout regulator circuit 100 includes a reference circuit 102, an amplifier circuit 104, a power switch circuit 106, a feedback circuit 108, and a control circuit 110.

[0016] Reference circuit 102 is coupled to amplifier circuit 104. Amplifier circuit 104 is coupled to power switch circuit 106 and feedback circuit 108. Power switch circuit 106 is coupled to feedback circuit 108 and control circuit 110. Load L is coupled between output terminal OUT and ground terminal GND. An external capacitor CEX can be mounted on a printed circuit board. The first terminal of capacitor CEX is coupled to the pin of output terminal OUT through the parasitic resistance RS of a component or metal trace, and the second terminal of capacitor CEX can be coupled to ground terminal GND. The external capacitor CEX is used to make the output voltage VO more stable.

[0017] Reference circuit 102 operates based on input voltage AVDD and is used to generate reference voltage VBG. Figure 1 In the example, during the power-on process of the low-dropout regulator circuit 100, the input voltage AVDD will rise from 0 volts to 5 volts, but this disclosure is not limited to this voltage value. Other suitable voltage values ​​are also within the scope of this disclosure.

[0018] Amplifier circuit 104 operates based on input voltage AVDD and includes a positive input terminal and a negative input terminal. The negative input terminal of amplifier circuit 104 receives a reference voltage VBG from reference circuit 102, and the positive input terminal of amplifier circuit 104 receives a feedback voltage VFB from feedback circuit 108. Amplifier circuit 104 is used to compare the reference voltage VBG and the feedback voltage VFB to generate an amplified voltage VGATE. In some embodiments, amplifier circuit 104 may be an analog amplifier.

[0019] The power switch circuit 106 receives the amplified voltage VGATE and generates an output voltage VO at the output terminal OUT based on the input voltage AVDD. The power switch circuit 106 may include at least one power switch, which can be turned on by the amplified voltage VGATE, and the current flowing through the power switch can charge the output terminal OUT to generate the output voltage VO.

[0020] Feedback circuit 108 is used to generate a feedback voltage VFB based on the output voltage VO and send it to the positive input terminal of amplifier circuit 104. Figure 1 For example, the feedback circuit 108 includes resistors R1 and R2, and capacitor CFB. Resistor R1 is coupled between the output terminal OUT and the feedback node N1. Resistor R2 is coupled between the feedback node N1 and ground GND. Capacitor CFB is coupled between the output terminal OUT and the feedback node N1. Based on the resistance ratio of resistors R1 and R2, the feedback voltage VFB responds to the output voltage VO generated at the feedback node N1 and transmitted to the positive input terminal of the amplifier circuit 104.

[0021] Control circuit 110 controls power switch circuit 106 based on input voltage AVDD and signal SS from reference circuit 102. Details of how control circuit 110 controls power switch circuit 106 based on input voltage AVDD and signal SS will be provided later. Figures 2 to 4 Describe it.

[0022] refer to Figure 2 . Figure 2 This is a circuit diagram of a low-dropout voltage regulator circuit 200 illustrated in accordance with some embodiments of the present disclosure.

[0023] exist Figure 2 In the example, control circuit 210 can be used to implement Figure 1 The control circuit 110 is located in the reference circuit 102. Specifically, the control circuit 210 controls the power switch circuit 206 based on the input voltage AVDD and the reference voltage VBG from the reference circuit 102. That is, in... Figure 2 In this example, the reference voltage VBG from reference circuit 102 is used to achieve Figure 1 The signal SS in the middle.

[0024] by Figure 2 For example, the control circuit 210 includes a voltage divider circuit 212, a monitoring circuit 214, and a counting circuit 216.

[0025] Voltage divider circuit 212 is used to generate a divided voltage VX based on the input voltage AVDD. For example, voltage divider circuit 212 includes resistors R3 and R4, and capacitor CX. The first terminal of resistor R3 receives the input voltage AVDD, and the second terminal of resistor R3 is coupled to the first terminal of resistor R4, which is also coupled to ground GND. The first terminal of capacitor CX is coupled to the connection node N2 between resistors R3 and R4, and the second terminal of capacitor CX is coupled to ground GND. The divided voltage VX is generated at connection node N2. In this architecture, the divided voltage VX is positively correlated with the input voltage AVDD. That is, the higher the input voltage AVDD, the higher the divided voltage VX will be.

[0026] Detection circuit 214 generates detection signal DS based on reference voltage VBG and voltage divider voltage VX. In some embodiments, detection circuit 214 may be implemented using a comparator. For example, the comparator compares the reference voltage VBG with the voltage divider voltage VX. When the voltage divider voltage VX is less than the reference voltage VBG, the comparator outputs detection signal DS with a first logic value (e.g., logic 0). Conversely, when the voltage divider voltage VX is equal to or greater than the reference voltage VBG, the comparator outputs detection signal DS with a second logic value (e.g., logic 1). Detection signal DS with a second logic value (e.g., logic 1) enables counting circuit 216 to start counting.

[0027] The counting circuit 216 is used to generate a counting signal CN based on the detection signal DS. As described above, when the voltage divider voltage VX is equal to or greater than the reference voltage VBG, the detection signal DS, which has a second logic value (e.g., logic value 1), enables the counting circuit 216 to start counting to generate the counting signal CN, thereby controlling the power switch circuit 206.

[0028] by Figure 2 For example, power switch circuit 206 includes power switch MP1 and power switches MP2-MP4. Power switches MP1-MP4 can be implemented using P-type transistors. Power switches MP1-MP4 are coupled in parallel. The first terminal of power switches MP1-MP4 is used to receive the input voltage AVDD, and the second terminal of power switches MP1-MP4 is coupled to the output terminal OUT. The control terminal of power switch MP1 is used to receive the amplified voltage VGATE, while the counting signal CN is used to control power switches MP2-MP4.

[0029] During the initial power-on process of the low-dropout regulator circuit 200, the amplified voltage VGATE can first turn on the power switch MP1, allowing the input voltage AVDD to charge the output terminal OUT to a small extent. At this time, because the input voltage AVDD is not large enough and the reference circuit 102 is not yet stable (the voltage divider voltage VX is less than the reference voltage VBG), the detection circuit 214 has not yet output a detection signal DS with the second logic value, and the counting circuit 216 is still disabled. At this time, the power switches MP2-MP4 are still open.

[0030] After a period of time, when the input voltage AVDD is sufficiently large (making the voltage divider voltage VX equal to or greater than the reference voltage VBG), that is, the output voltage VO has been charged to a certain voltage level and is relatively stable. Since the voltage divider voltage VX is equal to or greater than the reference voltage VBG, the detection circuit 214 can output a detection signal DS with a second logic value to enable the counting circuit 216 to start counting. For example, the value of the counting signal CN can increase from 0. In some embodiments, a power switch control circuit (not shown) can be coupled to the counting circuit 216. When the value of the counting signal CN increases to a first value (equivalent to after a first delay time), this power switch control circuit can output a control signal to turn on the power switch MP2. When the value of the counting signal CN increases to a second value (equivalent to after a second delay time), the power switch control circuit can output a control signal to turn on the power switch MP3. When the value of the counting signal CN increases to a third value (equivalent to after a third delay time), the power switch control circuit can output a control signal to turn on the power switch MP4. In other words, when the input voltage AVDD is sufficiently large (the output voltage VO has been charged to a certain voltage level and is relatively stable), more power switches will be turned on, causing the current flowing through the power switch circuit 206 to gradually increase and the low-dropout regulator circuit 200 to be able to provide a large current to the load L for normal operation. In some other embodiments, power switches MP2-MP4 can also be turned on simultaneously.

[0031] In some embodiments, the power switches MP1-MP4 have the same gate length but different gate widths. For example, the ratio of the gate widths of power switches MP1-MP4 may be 1:2:4:8, but this disclosure is not limited thereto. In the example above, power switch MP1 is the smallest, resulting in a very small initial current flowing through power switch circuit 206. In some other embodiments, the gate widths of power switches MP1-MP4 may all be the same.

[0032] Furthermore, the number of transistors in the power switching circuit 206 is merely illustrative and is not limited to this number. Various other suitable numbers are within the scope of this disclosure.

[0033] by Figure 2For example, in some embodiments, the low-dropout regulator circuit 200 further includes an overcurrent protection circuit OCP1. A first terminal of the overcurrent protection circuit OCP1 receives the input voltage AVDD, and a second terminal of the overcurrent protection circuit OCP1 is coupled to the control terminal of the power switch MP1. Generally, the control circuit 210 can control the current flowing through the power switch circuit 206 during the initial power-on process of the low-dropout regulator circuit 200. The overcurrent protection circuit OCP1, however, only begins normal operation to control the current flowing through the power switch circuit 206 after the input voltage AVDD reaches its maximum input voltage (e.g., 5 volts).

[0034] In some existing technologies, low-dropout regulator circuits only include overcurrent protection. However, as mentioned above, the overcurrent protection circuit can only begin normal operation after the input voltage exceeds a threshold voltage. If there are multiple transistors connected in series in the overcurrent protection circuit, this threshold voltage will be even higher. Based on this threshold voltage, the overcurrent protection circuit may not have started normal operation even after the power switching circuit in the low-dropout regulator circuit has been turned on. Therefore, the overcurrent protection circuit cannot prevent large inrush currents from flowing through the power switching circuit during the initial power-on process of the low-dropout regulator circuit (the initial input voltage ramp-up process).

[0035] In some other existing technologies, an additional low-pass filter circuit (e.g., a resistor-capacitor circuit) is coupled to the output of the reference circuit in a low-dropout regulator circuit. This additional low-pass filter circuit allows the reference voltage output by the reference circuit to rise more slowly, thereby allowing the power switching circuit to charge the output slowly until the output voltage stabilizes. However, the additional low-pass filter circuit may occupy a large circuit area.

[0036] Compared to the aforementioned prior art, in this disclosure, the control circuit 210 can control the current flowing through the power switching circuit 206 to be relatively small during the initial power-on process of the low-dropout regulator circuit 200. This avoids large inrush currents flowing through the power switching circuit 206 during the initial power-on process. Furthermore, this disclosure does not require an additional low-pass filter circuit, thus avoiding excessive increases in circuit area.

[0037] refer to Figure 3 . Figure 3 This is a circuit diagram of a low-dropout regulator circuit 300 illustrated in accordance with some embodiments of the present disclosure.

[0038] Figure 3 The low dropout voltage regulator circuit 300 in the middle and Figure 2One of the main differences between the low-dropout regulator circuits 200 is that the power switch circuit 306 includes a power switch MP5. The power switch MP5 can be implemented using a P-type transistor. The power switch MP5 includes a first terminal, a second terminal, and a control terminal. The first terminal of the power switch MP5 is used to receive the input voltage AVDD, the second terminal of the power switch MP5 is coupled to the output terminal OUT, and the control terminal of the power switch MP5 is coupled to the output terminal of the amplifier circuit 104.

[0039] Figure 3 The low dropout voltage regulator circuit 300 in the middle and Figure 2 Another key difference between the low-dropout regulator circuits 200 and those in the control circuit 310 is that the control circuit 310 is used to achieve... Figure 1 The control circuit 110 is included. The control circuit 310 includes... Figure 2 The circuit includes a control circuit 210, an additional switch SW, and a transistor MD. The switch SW has a first terminal and a second terminal. The transistor MD has a first terminal, a second terminal, and a control terminal. The first terminal of the switch SW receives the input voltage AVDD, and the second terminal of the switch SW is coupled to the first terminal of the transistor MD. The control terminal of the transistor MD is coupled to the second terminal of the transistor MD to form a diode connection. The second terminal of the transistor MD is coupled to the control terminal of the power switch MP5.

[0040] In some embodiments, Figure 3 The implementation method of the control circuit 210 is the same as that of... Figure 2 Control circuit 210. In Figure 3 In the middle, the counting signal CN output by the control circuit 210 is used to control the switch SW.

[0041] During the initial power-on process of the low-dropout regulator circuit 300, the switch SW can be turned on to limit the gate-source voltage of the power switch MP5, so that the current flowing through the power switch circuit 306 is not too large.

[0042] Similar to Figure 2After a period of time, the input voltage AVDD becomes sufficiently large (the voltage divider voltage VX is equal to or greater than the reference voltage VBG). That is, the output voltage VO has been charged to a certain voltage level and is relatively stable. The detection circuit 214 can output a detection signal DS with a second logic value to enable the counting circuit 216 to start counting. For example, the value of the counting signal CN can increase from 0. In some embodiments, a switch control circuit (not shown) can be coupled to the counting circuit 216. When the value of the counting signal CN increases to a specific value (equivalent to a delay time), this switch control circuit can output a control signal to open the switch SW. When the switch SW is open, the current flowing through the power switch circuit 306 will increase, enabling the low-dropout regulator circuit 300 to provide a large current to the load L for normal operation.

[0043] by Figure 3 For example, in some embodiments, the low-dropout regulator circuit 300 further includes an overcurrent protection circuit OCP2. A first terminal of the overcurrent protection circuit OCP2 receives the input voltage AVDD, and a second terminal of the overcurrent protection circuit OCP2 is coupled to the control terminal of the power switch MP5. Generally, the control circuit 310 can control the current flowing through the power switch circuit 306 during the initial power-on process of the low-dropout regulator circuit 300. The overcurrent protection circuit OCP2 can begin normal operation after the input voltage AVDD reaches the maximum input voltage (e.g., 5 volts) to control the current flowing through the power switch circuit 306.

[0044] Similarly, during the initial power-on process of the low-dropout regulator circuit 300, the current flowing through the power switch circuit 306 is relatively small. This avoids large inrush currents flowing through the power switch circuit 306 during the initial power-on process. Furthermore, this disclosure eliminates the need for an additional low-pass filter circuit, thus avoiding excessive increases in circuit area.

[0045] refer to Figure 4 . Figure 4 This is a circuit diagram of a low-dropout regulator circuit 400 illustrated in accordance with some embodiments of the present disclosure.

[0046] The following description focuses on the differences between the low-dropout voltage regulator circuit 400 and the aforementioned embodiments. Other parts of the low-dropout voltage regulator circuit 400 that are similar to those in the aforementioned embodiments will not be described in detail here.

[0047] by Figure 4 For example, reference circuit 402 includes a current mirror. The current mirror in reference circuit 402 can provide a reference current IX. In some embodiments, reference circuit 402 can also be used to implement Figure 2 and Figure 3 Reference circuit 102 in the middle.

[0048] exist Figure 4 In the example, control circuit 410 is used to achieve Figure 1 The control circuit 110 is located in the middle. The control circuit 410 can control the power switch circuit 406 based on the input voltage AVDD and the reference current IX from the reference circuit 402. That is to say, in Figure 4 In the example, the reference current IX from reference circuit 402 is used to achieve Figure 1 The signal SS in the middle.

[0049] The power switch circuit 406 includes a power switch MP6. The power switch MP6 can be implemented using a P-type transistor. The power switch MP6 includes a first terminal, a second terminal, and a control terminal. The first terminal of the power switch MP6 is used to receive the input voltage AVDD, the second terminal of the power switch MP6 is coupled to the output terminal OUT, and the control terminal of the power switch MP6 is coupled to the output terminal of the amplifier circuit 104.

[0050] Control circuit 410 includes transistor MR and capacitor CR. Transistor MR includes a first terminal, a second terminal, and a control terminal. The first terminal of transistor MR is used to receive the input voltage AVDD. The second terminal of transistor MR is coupled to the control terminal of power switch MP6. Reference circuit 402, the control terminal of transistor MR, and the first terminal of capacitor CR are coupled to node N3. The second terminal of capacitor CR is coupled to ground GND. The node voltage VR at node N3 initially has a first logic value (e.g., logic value 0), and the reference current IX from reference circuit 402 can be used to charge node N3.

[0051] During the initial power-up of the low-dropout regulator circuit 400, the input voltage AVDD rises from 0 volts to the threshold voltage of transistor MR. Since the node voltage VR at node N3 initially has a first logic value (e.g., logic 0), transistor MR is turned on. At this time, power switch MP6 is turned off. Once reference circuit 402 stabilizes, it generates a small reference current IX to slowly charge node N3. During charging, the gate-source voltage of transistor MR gradually decreases. Consequently, the equivalent resistance RR of transistor MR gradually increases. This increases the difference between the input voltage AVDD and the amplified voltage VGATE, thus gradually increasing the conduction level of power switch MP6. Therefore, the input voltage AVDD charges the output terminal OUT. When the node voltage VR at node N3 is charged to a sufficiently high level (e.g., the difference between the input voltage AVDD and the node voltage VR is less than the absolute value of the threshold voltage of transistor MR), power switch MP6 can provide a large current to the load L.

[0052] by Figure 4For example, in some embodiments, the low-dropout regulator circuit 400 further includes an overcurrent protection circuit OCP3. A first terminal of the overcurrent protection circuit OCP3 receives the input voltage AVDD, and a second terminal of the overcurrent protection circuit OCP3 is coupled to the control terminal of the power switch MP6. Generally, the control circuit 410 can control the current flowing through the power switch circuit 406 during the initial power-on process of the low-dropout regulator circuit 400. The overcurrent protection circuit OCP3 can only begin normal operation after the input voltage AVDD reaches the maximum input voltage (e.g., 5 volts) to control the current flowing through the power switch circuit 406.

[0053] Similarly, during the initial power-on process of the low-dropout regulator circuit 400, the current flowing through the power switch circuit 406 is relatively small. This avoids large inrush currents flowing through the power switch circuit 406 during the initial power-on process. Furthermore, this disclosure does not require an additional low-pass filter circuit, thus avoiding excessive increases in circuit area.

[0054] refer to Figure 5 . Figure 5 This is a flowchart illustrating a control method 500 according to some embodiments of the present disclosure. Figure 5 For example, control method 500 includes operation S510, operation S520, operation S530, operation S540 and operation S550.

[0055] In some embodiments, the control method 500 may be applied to Figure 1 The low-dropout regulator circuit 100 is included, but this disclosure is not limited thereto. For ease of understanding, the control method 500 will be combined with... Figure 1 The low-dropout voltage regulator circuit 100 is described in the text.

[0056] In operation S510, a reference voltage VBG is generated by the reference circuit 102. In some embodiments, the reference circuit 102 may be... Figure 4 The reference circuit 402 is implemented in the example.

[0057] In operation S520, the amplifier circuit 104 generates an amplified voltage VGATE based on the reference voltage VBG and the feedback voltage VFB. In some embodiments, the negative input terminal of the amplifier circuit 104 receives the reference voltage VBG, and the positive input terminal of the amplifier circuit 104 receives the feedback voltage VFB.

[0058] In operation S530, the power switch circuit 106 receives the amplified voltage VGATE and generates an output voltage VO at the output terminal OUT based on the input voltage AVDD. In some embodiments, when the power switch circuit 106 is turned on, the input voltage AVDD can charge the output terminal OUT through the power switch circuit 106.

[0059] In operation S540, the feedback circuit 108 generates a feedback voltage VFB based on the output voltage VO. In some embodiments, the relationship between the feedback voltage VFB and the output voltage VO is related to the ratio of the resistance values ​​of resistor R1 and resistor R2.

[0060] In operation S550, the control circuit 110 controls the power switch circuit 106 based on the input voltage AVDD and the signal SS from the reference circuit 102. In some embodiments (e.g.: Figure 2 as well as Figure 3 The signal SS is the reference voltage VBG of the reference circuit 102. In some embodiments (e.g.: Figure 4 The signal SS is the reference current IX of the reference circuit 102.

[0061] In summary, in the low-dropout voltage regulator circuit disclosed herein, the control circuit can control the power switching circuit based on the input voltage and the signal from the reference circuit, so that the current flowing through the power switching circuit during the initial power-on process of the low-dropout voltage regulator circuit is relatively small, thereby avoiding large inrush current.

[0062] Although this disclosure has been described above with reference to embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the scope of the appended claims.

[0063] [Symbol Explanation]

[0064] 100, 200, 300, 400: Low dropout voltage regulator circuit

[0065] 102,402: Reference Circuit

[0066] 104: Amplifier Circuit

[0067] 106, 206, 306, 406: Power switching circuits

[0068] 108: Feedback Circuit

[0069] 110, 210, 310, 410: Control circuit

[0070] 212: Voltage divider circuit

[0071] 214: Detection Circuit

[0072] 216: Counting Circuit

[0073] 500: Control Method

[0074] AVDD: Input voltage

[0075] VBG: Reference Voltage

[0076] VFB: Feedback Voltage

[0077] VGATE: Amplifying voltage

[0078] VO: Output voltage

[0079] OUT: Output terminal

[0080] R1, R2, RS, R3, R4, RR: Resistors

[0081] CFB, CEX, CX, CR: Capacitors

[0082] GND: ground terminal

[0083] N1, N2, N3: Nodes

[0084] SS: Signal

[0085] L: Load

[0086] VX: Voltage divider

[0087] DS: Detection signal

[0088] CN: Counting signal

[0089] MP1, MP2, MP3, MP4, MP5, MP6: Power Switch

[0090] MD, MR: Transistor

[0091] OCP1, OCP2, OCP3: Overcurrent protection circuit

[0092] SW: Switch

[0093] IX: Reference current

[0094] VR: Node Voltage

[0095] S510, S520, S530, S540, S550: Operation.

Claims

1. A low-dropout voltage regulator, comprising: a reference circuit configured to generate a reference voltage; an amplification circuit configured to generate an amplified voltage based on the reference voltage and a feedback voltage; a power switch circuit configured to receive the amplified voltage and generate an output voltage at an output terminal based on an input voltage; a feedback circuit configured to generate the feedback voltage based on the output voltage; and a control circuit configured to control the power switch circuit based on the input voltage and a signal from the reference circuit; wherein the signal from the reference circuit is the reference voltage; wherein the control circuit comprises a voltage divider circuit configured to generate a divided voltage based on the input voltage, a detection circuit configured to generate a detection signal based on the reference voltage and the divided voltage, and a counting circuit configured to generate a counting signal based on the detection signal, wherein the counting signal is configured to control the power switch circuit.

2. The low-dropout voltage regulator of claim 1, wherein the power switch circuit comprises a first power switch and a plurality of second power switches, a control terminal of the first power switch is configured to receive the amplified voltage, and the counting signal is configured to control the plurality of second power switches.

3. The low-dropout voltage regulator of claim 1, wherein the power switch circuit comprises a first power switch, and the control circuit further comprises: a switch comprising a first terminal and a second terminal, wherein the first terminal of the switch is configured to receive the input voltage, wherein the counting signal is configured to control the switch; and a transistor comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the transistor is coupled to the second terminal of the switch, the control terminal of the transistor is coupled to the second terminal of the transistor, and the second terminal of the transistor is coupled to a control terminal of the first power switch.

4. The low-dropout voltage regulator of claim 2 or 3, further comprising: an overcurrent protection circuit comprising a first terminal and a second terminal, wherein the first terminal of the overcurrent protection circuit is configured to receive the input voltage, and the second terminal of the overcurrent protection circuit is coupled to the control terminal of the first power switch.

5. The low-dropout voltage regulator of claim 1, wherein the signal is a reference current from a current mirror in the reference circuit.

6. The low-dropout voltage regulator of claim 5, wherein the power switch circuit comprises a power switch, and the control circuit further comprises: a transistor comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the transistor is configured to receive the input voltage, and the second terminal of the transistor is coupled to a control terminal of the power switch, the reference circuit and the control terminal of the transistor are coupled to a node; and a capacitor coupled between the node and a ground terminal, wherein the reference current is configured to charge the node.

7. The low-dropout voltage regulator of claim 6, further comprising: an overcurrent protection circuit comprising a first terminal and a second terminal, wherein the first terminal of the overcurrent protection circuit is configured to receive the input voltage, and the second terminal of the overcurrent protection circuit is coupled to the control terminal of the power switch. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 8. A control method of a low-dropout voltage regulator, the control method comprising: generating a reference voltage by a reference circuit; generating an amplified voltage by an amplification circuit according to the reference voltage and a feedback voltage; receiving the amplified voltage by a power switch circuit and generating an output voltage at an output terminal according to an input voltage; generating the feedback voltage by a feedback circuit according to the output voltage; and controlling the power switch circuit by a control circuit according to the input voltage and a signal from the reference circuit; wherein the signal from the reference circuit is the reference voltage; wherein the control circuit comprises a voltage dividing circuit for generating a divided voltage according to the input voltage, a detection circuit for generating a detection signal according to the reference voltage and the divided voltage, and a counting circuit for generating a counting signal according to the detection signal, wherein the counting signal is used to control the power switch circuit.

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